java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_true-valid-memsafety.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-a74eeac-m [2018-02-02 20:36:26,047 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-02 20:36:26,049 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-02 20:36:26,062 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-02 20:36:26,062 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-02 20:36:26,063 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-02 20:36:26,064 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-02 20:36:26,066 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-02 20:36:26,068 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-02 20:36:26,068 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-02 20:36:26,069 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-02 20:36:26,069 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-02 20:36:26,070 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-02 20:36:26,071 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-02 20:36:26,072 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-02 20:36:26,074 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-02 20:36:26,075 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-02 20:36:26,077 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-02 20:36:26,078 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-02 20:36:26,078 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-02 20:36:26,080 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-02 20:36:26,080 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-02 20:36:26,080 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-02 20:36:26,081 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-02 20:36:26,082 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-02 20:36:26,083 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-02 20:36:26,083 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-02 20:36:26,084 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-02 20:36:26,084 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-02 20:36:26,084 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-02 20:36:26,084 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-02 20:36:26,085 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-02 20:36:26,094 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-02 20:36:26,095 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-02 20:36:26,096 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-02 20:36:26,096 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-02 20:36:26,096 INFO L133 SettingsManager]: * Use SBE=true [2018-02-02 20:36:26,096 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-02 20:36:26,096 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-02 20:36:26,096 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-02 20:36:26,097 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-02 20:36:26,098 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-02 20:36:26,098 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-02 20:36:26,098 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-02 20:36:26,098 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-02 20:36:26,098 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-02 20:36:26,098 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 20:36:26,098 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-02 20:36:26,099 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-02 20:36:26,129 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-02 20:36:26,141 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-02 20:36:26,144 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-02 20:36:26,146 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-02 20:36:26,146 INFO L276 PluginConnector]: CDTParser initialized [2018-02-02 20:36:26,147 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_true-valid-memsafety.i [2018-02-02 20:36:26,306 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-02 20:36:26,307 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-02 20:36:26,308 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-02 20:36:26,308 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-02 20:36:26,313 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-02 20:36:26,314 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,317 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@e7890ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26, skipping insertion in model container [2018-02-02 20:36:26,317 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,330 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 20:36:26,367 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-02 20:36:26,474 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 20:36:26,510 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-02 20:36:26,523 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26 WrapperNode [2018-02-02 20:36:26,523 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-02 20:36:26,524 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-02 20:36:26,524 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-02 20:36:26,524 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-02 20:36:26,534 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,535 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,546 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,546 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,558 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,562 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,564 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... [2018-02-02 20:36:26,567 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-02 20:36:26,567 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-02 20:36:26,567 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-02 20:36:26,568 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-02 20:36:26,568 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-02 20:36:26,603 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-02 20:36:26,603 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-02 20:36:26,603 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-02-02 20:36:26,604 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_get_clientdata [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_set_clientdata [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure master_xfer [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_transfer [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_m88ts2022_rd_reg [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure alloc_fix_12 [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure free_12 [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-02 20:36:26,605 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-02 20:36:26,605 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-02-02 20:36:26,606 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-02 20:36:26,606 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure memcpy [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-02 20:36:26,607 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_get_clientdata [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_set_clientdata [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure master_xfer [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_transfer [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_m88ts2022_rd_reg [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure alloc_fix_12 [2018-02-02 20:36:26,608 INFO L128 BoogieDeclarations]: Found specification of procedure free_12 [2018-02-02 20:36:26,609 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-02 20:36:26,609 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-02 20:36:26,609 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-02 20:36:26,609 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-02 20:36:27,224 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-02 20:36:27,305 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-02 20:36:27,306 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 08:36:27 BoogieIcfgContainer [2018-02-02 20:36:27,306 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-02 20:36:27,306 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-02 20:36:27,306 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-02 20:36:27,308 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-02 20:36:27,308 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 02.02 08:36:26" (1/3) ... [2018-02-02 20:36:27,309 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4dc6220 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 08:36:27, skipping insertion in model container [2018-02-02 20:36:27,309 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 02.02 08:36:26" (2/3) ... [2018-02-02 20:36:27,309 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4dc6220 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 02.02 08:36:27, skipping insertion in model container [2018-02-02 20:36:27,309 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 02.02 08:36:27" (3/3) ... [2018-02-02 20:36:27,310 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test12_true-valid-memsafety.i [2018-02-02 20:36:27,316 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-02 20:36:27,321 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 141 error locations. [2018-02-02 20:36:27,343 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-02 20:36:27,344 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-02 20:36:27,344 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-02 20:36:27,344 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-02 20:36:27,344 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-02 20:36:27,344 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-02 20:36:27,344 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-02 20:36:27,344 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-02 20:36:27,344 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-02 20:36:27,361 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states. [2018-02-02 20:36:27,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-02 20:36:27,368 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:27,369 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-02 20:36:27,369 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:27,372 INFO L82 PathProgramCache]: Analyzing trace with hash 18685926, now seen corresponding path program 1 times [2018-02-02 20:36:27,412 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:27,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:27,523 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:27,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:27,560 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:27,560 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 20:36:27,561 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:27,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:27,562 INFO L182 omatonBuilderFactory]: Interpolants [401#true, 402#false, 403#(= 1 (select |#valid| |~#ldv_global_msg_list.base|))] [2018-02-02 20:36:27,562 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:27,563 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 20:36:27,572 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 20:36:27,573 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:36:27,574 INFO L87 Difference]: Start difference. First operand 398 states. Second operand 3 states. [2018-02-02 20:36:27,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:27,917 INFO L93 Difference]: Finished difference Result 487 states and 527 transitions. [2018-02-02 20:36:27,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 20:36:27,918 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-02 20:36:27,919 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:27,935 INFO L225 Difference]: With dead ends: 487 [2018-02-02 20:36:27,935 INFO L226 Difference]: Without dead ends: 481 [2018-02-02 20:36:27,937 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:36:27,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-02 20:36:27,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 436. [2018-02-02 20:36:27,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-02-02 20:36:27,986 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 491 transitions. [2018-02-02 20:36:27,986 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 491 transitions. Word has length 4 [2018-02-02 20:36:27,987 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:27,987 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 491 transitions. [2018-02-02 20:36:27,987 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 20:36:27,987 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 491 transitions. [2018-02-02 20:36:27,987 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-02 20:36:27,987 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:27,987 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-02 20:36:27,987 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:27,988 INFO L82 PathProgramCache]: Analyzing trace with hash 18685927, now seen corresponding path program 1 times [2018-02-02 20:36:27,989 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:28,000 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:28,001 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:28,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,031 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:28,031 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 20:36:28,031 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:28,031 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,031 INFO L182 omatonBuilderFactory]: Interpolants [1328#false, 1329#(and (= |~#ldv_global_msg_list.offset| 0) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 1327#true] [2018-02-02 20:36:28,032 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,032 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 20:36:28,033 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 20:36:28,033 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:36:28,033 INFO L87 Difference]: Start difference. First operand 436 states and 491 transitions. Second operand 3 states. [2018-02-02 20:36:28,244 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:28,244 INFO L93 Difference]: Finished difference Result 567 states and 652 transitions. [2018-02-02 20:36:28,244 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 20:36:28,245 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-02 20:36:28,245 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:28,247 INFO L225 Difference]: With dead ends: 567 [2018-02-02 20:36:28,247 INFO L226 Difference]: Without dead ends: 567 [2018-02-02 20:36:28,247 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:36:28,248 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-02-02 20:36:28,260 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 497. [2018-02-02 20:36:28,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 497 states. [2018-02-02 20:36:28,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 497 states to 497 states and 602 transitions. [2018-02-02 20:36:28,262 INFO L78 Accepts]: Start accepts. Automaton has 497 states and 602 transitions. Word has length 4 [2018-02-02 20:36:28,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:28,262 INFO L432 AbstractCegarLoop]: Abstraction has 497 states and 602 transitions. [2018-02-02 20:36:28,262 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 20:36:28,262 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 602 transitions. [2018-02-02 20:36:28,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 20:36:28,262 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:28,262 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:28,263 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:28,263 INFO L82 PathProgramCache]: Analyzing trace with hash -769194584, now seen corresponding path program 1 times [2018-02-02 20:36:28,264 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:28,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:28,280 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:28,330 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,331 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:28,331 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:28,331 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:28,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,332 INFO L182 omatonBuilderFactory]: Interpolants [2394#true, 2395#false, 2396#(not (= |ldv_malloc_#t~malloc4.base| 0)), 2397#(not (= |ldv_malloc_#res.base| 0)), 2398#(not (= |entry_point_#t~ret59.base| 0)), 2399#(not (= entry_point_~client~0.base 0))] [2018-02-02 20:36:28,332 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,332 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:28,332 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:28,332 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:28,333 INFO L87 Difference]: Start difference. First operand 497 states and 602 transitions. Second operand 6 states. [2018-02-02 20:36:28,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:28,390 INFO L93 Difference]: Finished difference Result 543 states and 666 transitions. [2018-02-02 20:36:28,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:28,391 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-02 20:36:28,391 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:28,394 INFO L225 Difference]: With dead ends: 543 [2018-02-02 20:36:28,394 INFO L226 Difference]: Without dead ends: 543 [2018-02-02 20:36:28,395 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:28,396 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-02-02 20:36:28,411 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 496. [2018-02-02 20:36:28,411 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 496 states. [2018-02-02 20:36:28,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 604 transitions. [2018-02-02 20:36:28,414 INFO L78 Accepts]: Start accepts. Automaton has 496 states and 604 transitions. Word has length 21 [2018-02-02 20:36:28,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:28,414 INFO L432 AbstractCegarLoop]: Abstraction has 496 states and 604 transitions. [2018-02-02 20:36:28,414 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:28,414 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 604 transitions. [2018-02-02 20:36:28,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 20:36:28,415 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:28,415 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:28,415 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:28,416 INFO L82 PathProgramCache]: Analyzing trace with hash 976272294, now seen corresponding path program 1 times [2018-02-02 20:36:28,417 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:28,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:28,440 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:28,506 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,507 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:28,507 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 20:36:28,507 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:28,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,507 INFO L182 omatonBuilderFactory]: Interpolants [3441#true, 3442#false, 3443#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 3444#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 3445#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-02 20:36:28,507 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,507 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:28,508 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:28,508 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:28,508 INFO L87 Difference]: Start difference. First operand 496 states and 604 transitions. Second operand 5 states. [2018-02-02 20:36:28,735 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:28,736 INFO L93 Difference]: Finished difference Result 571 states and 703 transitions. [2018-02-02 20:36:28,736 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:28,736 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2018-02-02 20:36:28,736 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:28,738 INFO L225 Difference]: With dead ends: 571 [2018-02-02 20:36:28,738 INFO L226 Difference]: Without dead ends: 571 [2018-02-02 20:36:28,739 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:28,739 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-02 20:36:28,750 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 538. [2018-02-02 20:36:28,750 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-02 20:36:28,752 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 661 transitions. [2018-02-02 20:36:28,753 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 661 transitions. Word has length 21 [2018-02-02 20:36:28,753 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:28,753 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 661 transitions. [2018-02-02 20:36:28,753 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:28,753 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 661 transitions. [2018-02-02 20:36:28,754 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-02 20:36:28,754 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:28,754 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:28,754 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:28,754 INFO L82 PathProgramCache]: Analyzing trace with hash 976272295, now seen corresponding path program 1 times [2018-02-02 20:36:28,756 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:28,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:28,771 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:28,882 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,882 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:28,882 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:28,882 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:28,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,883 INFO L182 omatonBuilderFactory]: Interpolants [4560#false, 4561#(and (= 0 |~#ldv_global_msg_list.offset|) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 4562#(and (= 8 (select |#length| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 4563#(= |old(#length)| |#length|), 4564#(and (= 0 |ldv_destroy_msgs_#t~mem23.offset|) (= 8 (select |#length| |ldv_destroy_msgs_#t~mem23.base|))), 4565#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 4) 0) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4)) (= (select |#length| ldv_destroy_msgs_~msg~1.base) 8)), 4559#true] [2018-02-02 20:36:28,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:28,884 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:28,884 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:28,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:28,884 INFO L87 Difference]: Start difference. First operand 538 states and 661 transitions. Second operand 7 states. [2018-02-02 20:36:29,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:29,766 INFO L93 Difference]: Finished difference Result 668 states and 771 transitions. [2018-02-02 20:36:29,766 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 20:36:29,766 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-02-02 20:36:29,766 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:29,768 INFO L225 Difference]: With dead ends: 668 [2018-02-02 20:36:29,768 INFO L226 Difference]: Without dead ends: 668 [2018-02-02 20:36:29,768 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:36:29,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states. [2018-02-02 20:36:29,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 538. [2018-02-02 20:36:29,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-02 20:36:29,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 660 transitions. [2018-02-02 20:36:29,778 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 660 transitions. Word has length 21 [2018-02-02 20:36:29,778 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:29,778 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 660 transitions. [2018-02-02 20:36:29,778 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:29,778 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 660 transitions. [2018-02-02 20:36:29,779 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-02 20:36:29,779 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:29,779 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:29,779 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:29,779 INFO L82 PathProgramCache]: Analyzing trace with hash 886332479, now seen corresponding path program 1 times [2018-02-02 20:36:29,780 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:29,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:29,789 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:29,851 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:29,852 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:29,852 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:36:29,852 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:29,853 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:29,853 INFO L182 omatonBuilderFactory]: Interpolants [5784#true, 5785#false, 5786#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 5787#(and (= 0 |entry_point_#t~ret59.base|) (= 0 |entry_point_#t~ret59.offset|)), 5788#(and (= 0 entry_point_~client~0.offset) (= entry_point_~client~0.base 0))] [2018-02-02 20:36:29,853 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:29,853 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:29,854 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:29,854 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:29,854 INFO L87 Difference]: Start difference. First operand 538 states and 660 transitions. Second operand 5 states. [2018-02-02 20:36:29,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:29,886 INFO L93 Difference]: Finished difference Result 503 states and 588 transitions. [2018-02-02 20:36:29,886 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:36:29,886 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-02-02 20:36:29,894 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:29,896 INFO L225 Difference]: With dead ends: 503 [2018-02-02 20:36:29,896 INFO L226 Difference]: Without dead ends: 503 [2018-02-02 20:36:29,897 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:29,898 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-02 20:36:29,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 495. [2018-02-02 20:36:29,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-02-02 20:36:29,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 574 transitions. [2018-02-02 20:36:29,917 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 574 transitions. Word has length 24 [2018-02-02 20:36:29,917 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:29,917 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 574 transitions. [2018-02-02 20:36:29,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:29,918 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 574 transitions. [2018-02-02 20:36:29,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 20:36:29,918 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:29,919 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:29,919 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:29,919 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343331, now seen corresponding path program 1 times [2018-02-02 20:36:29,920 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:29,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:29,931 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:29,962 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:29,962 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:29,963 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:36:29,963 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:29,963 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:29,963 INFO L182 omatonBuilderFactory]: Interpolants [6787#true, 6788#false, 6789#(= 0 |ldv_malloc_#t~malloc4.offset|), 6790#(= 0 |ldv_malloc_#res.offset|), 6791#(= 0 |entry_point_#t~ret59.offset|), 6792#(= 0 entry_point_~client~0.offset)] [2018-02-02 20:36:29,964 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:29,964 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:29,964 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:29,964 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:29,964 INFO L87 Difference]: Start difference. First operand 495 states and 574 transitions. Second operand 6 states. [2018-02-02 20:36:30,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:30,005 INFO L93 Difference]: Finished difference Result 496 states and 579 transitions. [2018-02-02 20:36:30,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:30,006 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-02-02 20:36:30,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:30,008 INFO L225 Difference]: With dead ends: 496 [2018-02-02 20:36:30,008 INFO L226 Difference]: Without dead ends: 496 [2018-02-02 20:36:30,008 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:30,009 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-02-02 20:36:30,016 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 494. [2018-02-02 20:36:30,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 494 states. [2018-02-02 20:36:30,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 494 states to 494 states and 572 transitions. [2018-02-02 20:36:30,018 INFO L78 Accepts]: Start accepts. Automaton has 494 states and 572 transitions. Word has length 26 [2018-02-02 20:36:30,018 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:30,018 INFO L432 AbstractCegarLoop]: Abstraction has 494 states and 572 transitions. [2018-02-02 20:36:30,018 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:30,019 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 572 transitions. [2018-02-02 20:36:30,019 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 20:36:30,019 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:30,019 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:30,020 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:30,020 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343330, now seen corresponding path program 1 times [2018-02-02 20:36:30,021 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:30,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:30,030 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:30,072 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,072 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:30,072 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 20:36:30,073 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:30,073 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,073 INFO L182 omatonBuilderFactory]: Interpolants [7792#(= |#valid| |old(#valid)|), 7786#true, 7787#false, 7788#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 7789#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 7790#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 7791#(= 1 (select |#valid| entry_point_~client~0.base))] [2018-02-02 20:36:30,073 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,074 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:30,074 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:30,074 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:30,074 INFO L87 Difference]: Start difference. First operand 494 states and 572 transitions. Second operand 7 states. [2018-02-02 20:36:30,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:30,831 INFO L93 Difference]: Finished difference Result 597 states and 705 transitions. [2018-02-02 20:36:30,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:30,832 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-02-02 20:36:30,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:30,836 INFO L225 Difference]: With dead ends: 597 [2018-02-02 20:36:30,836 INFO L226 Difference]: Without dead ends: 592 [2018-02-02 20:36:30,837 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:30,838 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2018-02-02 20:36:30,849 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 521. [2018-02-02 20:36:30,849 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-02-02 20:36:30,851 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 620 transitions. [2018-02-02 20:36:30,851 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 620 transitions. Word has length 26 [2018-02-02 20:36:30,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:30,852 INFO L432 AbstractCegarLoop]: Abstraction has 521 states and 620 transitions. [2018-02-02 20:36:30,852 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:30,852 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 620 transitions. [2018-02-02 20:36:30,852 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-02 20:36:30,853 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:30,853 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:30,853 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:30,853 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343329, now seen corresponding path program 1 times [2018-02-02 20:36:30,854 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:30,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:30,863 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:30,902 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:30,903 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:30,903 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:36:30,903 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:30,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,903 INFO L182 omatonBuilderFactory]: Interpolants [8913#true, 8914#false, 8915#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 8916#(and (= 0 |entry_point_#t~ret60.base|) (= 0 |entry_point_#t~ret60.offset|)), 8917#(and (= 0 entry_point_~cfg~2.offset) (= 0 entry_point_~cfg~2.base))] [2018-02-02 20:36:30,904 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:30,904 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:30,904 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:30,904 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:30,904 INFO L87 Difference]: Start difference. First operand 521 states and 620 transitions. Second operand 5 states. [2018-02-02 20:36:30,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:30,922 INFO L93 Difference]: Finished difference Result 523 states and 619 transitions. [2018-02-02 20:36:30,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:36:30,922 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-02-02 20:36:30,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:30,924 INFO L225 Difference]: With dead ends: 523 [2018-02-02 20:36:30,925 INFO L226 Difference]: Without dead ends: 523 [2018-02-02 20:36:30,925 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:30,925 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-02-02 20:36:30,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 520. [2018-02-02 20:36:30,935 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-02-02 20:36:30,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 617 transitions. [2018-02-02 20:36:30,937 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 617 transitions. Word has length 26 [2018-02-02 20:36:30,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:30,938 INFO L432 AbstractCegarLoop]: Abstraction has 520 states and 617 transitions. [2018-02-02 20:36:30,938 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:30,938 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 617 transitions. [2018-02-02 20:36:30,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-02 20:36:30,938 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:30,938 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:30,943 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:30,943 INFO L82 PathProgramCache]: Analyzing trace with hash -1082862565, now seen corresponding path program 1 times [2018-02-02 20:36:30,944 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:30,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:30,954 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:30,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,994 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:30,994 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 20:36:30,994 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:30,994 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,995 INFO L182 omatonBuilderFactory]: Interpolants [9961#true, 9962#false, 9963#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base)), 9964#(= 1 (select |#valid| |ldv_list_del_#in~entry.base|)), 9965#(= 1 (select |#valid| ldv_list_del_~entry.base))] [2018-02-02 20:36:30,995 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:30,995 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:30,995 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:30,995 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:30,995 INFO L87 Difference]: Start difference. First operand 520 states and 617 transitions. Second operand 5 states. [2018-02-02 20:36:31,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:31,272 INFO L93 Difference]: Finished difference Result 541 states and 644 transitions. [2018-02-02 20:36:31,272 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:31,272 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-02-02 20:36:31,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:31,274 INFO L225 Difference]: With dead ends: 541 [2018-02-02 20:36:31,274 INFO L226 Difference]: Without dead ends: 541 [2018-02-02 20:36:31,274 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:31,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-02-02 20:36:31,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 537. [2018-02-02 20:36:31,284 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-02-02 20:36:31,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 638 transitions. [2018-02-02 20:36:31,286 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 638 transitions. Word has length 27 [2018-02-02 20:36:31,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:31,286 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 638 transitions. [2018-02-02 20:36:31,286 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:31,286 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 638 transitions. [2018-02-02 20:36:31,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-02 20:36:31,287 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:31,287 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:31,287 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:31,287 INFO L82 PathProgramCache]: Analyzing trace with hash -1082862564, now seen corresponding path program 1 times [2018-02-02 20:36:31,289 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:31,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:31,299 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:31,471 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:31,471 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:31,471 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-02 20:36:31,471 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:31,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:31,472 INFO L182 omatonBuilderFactory]: Interpolants [11046#true, 11047#false, 11048#(and (= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11049#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11050#(and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= (+ |~#ldv_global_msg_list.offset| 8) (select |#length| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11051#(and (<= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 11052#(and (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|) (<= |~#ldv_global_msg_list.offset| 0) (<= 0 |~#ldv_global_msg_list.offset|)), 11053#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|))] [2018-02-02 20:36:31,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:31,472 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 20:36:31,472 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 20:36:31,472 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:31,472 INFO L87 Difference]: Start difference. First operand 537 states and 638 transitions. Second operand 8 states. [2018-02-02 20:36:31,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:31,809 INFO L93 Difference]: Finished difference Result 500 states and 568 transitions. [2018-02-02 20:36:31,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 20:36:31,810 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-02-02 20:36:31,810 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:31,812 INFO L225 Difference]: With dead ends: 500 [2018-02-02 20:36:31,812 INFO L226 Difference]: Without dead ends: 488 [2018-02-02 20:36:31,812 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-02-02 20:36:31,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2018-02-02 20:36:31,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 477. [2018-02-02 20:36:31,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 477 states. [2018-02-02 20:36:31,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 550 transitions. [2018-02-02 20:36:31,823 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 550 transitions. Word has length 27 [2018-02-02 20:36:31,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:31,824 INFO L432 AbstractCegarLoop]: Abstraction has 477 states and 550 transitions. [2018-02-02 20:36:31,824 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 20:36:31,824 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 550 transitions. [2018-02-02 20:36:31,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 20:36:31,824 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:31,825 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:31,825 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:31,825 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671872, now seen corresponding path program 1 times [2018-02-02 20:36:31,826 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:31,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:31,837 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:31,867 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:31,867 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:31,867 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:31,867 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:31,868 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 20:36:31,868 INFO L182 omatonBuilderFactory]: Interpolants [12039#true, 12040#false, 12041#(not (= |ldv_malloc_#t~malloc4.base| 0)), 12042#(not (= |ldv_malloc_#res.base| 0)), 12043#(not (= |entry_point_#t~ret60.base| 0)), 12044#(not (= entry_point_~cfg~2.base 0))] [2018-02-02 20:36:31,868 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:31,868 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:31,868 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:31,868 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:31,869 INFO L87 Difference]: Start difference. First operand 477 states and 550 transitions. Second operand 6 states. [2018-02-02 20:36:31,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:31,904 INFO L93 Difference]: Finished difference Result 478 states and 549 transitions. [2018-02-02 20:36:31,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:31,905 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-02 20:36:31,905 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:31,906 INFO L225 Difference]: With dead ends: 478 [2018-02-02 20:36:31,906 INFO L226 Difference]: Without dead ends: 478 [2018-02-02 20:36:31,907 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:31,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-02 20:36:31,914 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 476. [2018-02-02 20:36:31,914 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 476 states. [2018-02-02 20:36:31,916 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 476 states to 476 states and 547 transitions. [2018-02-02 20:36:31,916 INFO L78 Accepts]: Start accepts. Automaton has 476 states and 547 transitions. Word has length 28 [2018-02-02 20:36:31,916 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:31,916 INFO L432 AbstractCegarLoop]: Abstraction has 476 states and 547 transitions. [2018-02-02 20:36:31,916 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:31,916 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 547 transitions. [2018-02-02 20:36:31,917 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 20:36:31,917 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:31,917 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:31,917 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:31,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671871, now seen corresponding path program 1 times [2018-02-02 20:36:31,918 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:31,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:31,938 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:32,138 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:32,139 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:32,139 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 20:36:32,139 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:32,139 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:32,139 INFO L182 omatonBuilderFactory]: Interpolants [13008#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 13009#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 13010#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 13011#(and (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 13001#true, 13002#false, 13003#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 13004#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 13005#(and (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 13006#(and (<= 20 (select |#length| |entry_point_#t~ret59.base|)) (= 0 |entry_point_#t~ret59.offset|) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 13007#(and (= (select |#valid| entry_point_~client~0.base) 1) (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base)))] [2018-02-02 20:36:32,140 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:32,140 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 20:36:32,140 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 20:36:32,140 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:36:32,140 INFO L87 Difference]: Start difference. First operand 476 states and 547 transitions. Second operand 11 states. [2018-02-02 20:36:33,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:33,627 INFO L93 Difference]: Finished difference Result 640 states and 746 transitions. [2018-02-02 20:36:33,628 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 20:36:33,628 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 28 [2018-02-02 20:36:33,628 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:33,629 INFO L225 Difference]: With dead ends: 640 [2018-02-02 20:36:33,630 INFO L226 Difference]: Without dead ends: 640 [2018-02-02 20:36:33,630 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=217, Unknown=0, NotChecked=0, Total=272 [2018-02-02 20:36:33,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 640 states. [2018-02-02 20:36:33,639 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 640 to 485. [2018-02-02 20:36:33,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 485 states. [2018-02-02 20:36:33,640 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 562 transitions. [2018-02-02 20:36:33,641 INFO L78 Accepts]: Start accepts. Automaton has 485 states and 562 transitions. Word has length 28 [2018-02-02 20:36:33,641 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:33,641 INFO L432 AbstractCegarLoop]: Abstraction has 485 states and 562 transitions. [2018-02-02 20:36:33,641 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 20:36:33,641 INFO L276 IsEmpty]: Start isEmpty. Operand 485 states and 562 transitions. [2018-02-02 20:36:33,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-02 20:36:33,641 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:33,642 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:33,642 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:33,642 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671872, now seen corresponding path program 1 times [2018-02-02 20:36:33,643 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:33,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:33,652 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:33,723 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:33,723 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:33,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 20:36:33,724 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:33,724 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:33,724 INFO L182 omatonBuilderFactory]: Interpolants [14149#true, 14150#false, 14151#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 14152#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 14153#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 14154#(= 1 (select |#valid| entry_point_~client~0.base)), 14155#(= |#valid| |old(#valid)|), 14156#(and (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 14157#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 20:36:33,724 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:33,725 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 20:36:33,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 20:36:33,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-02 20:36:33,725 INFO L87 Difference]: Start difference. First operand 485 states and 562 transitions. Second operand 9 states. [2018-02-02 20:36:34,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:34,436 INFO L93 Difference]: Finished difference Result 591 states and 693 transitions. [2018-02-02 20:36:34,436 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 20:36:34,436 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-02-02 20:36:34,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:34,439 INFO L225 Difference]: With dead ends: 591 [2018-02-02 20:36:34,439 INFO L226 Difference]: Without dead ends: 591 [2018-02-02 20:36:34,439 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-02-02 20:36:34,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 591 states. [2018-02-02 20:36:34,448 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 591 to 473. [2018-02-02 20:36:34,448 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-02 20:36:34,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 544 transitions. [2018-02-02 20:36:34,449 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 544 transitions. Word has length 28 [2018-02-02 20:36:34,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:34,450 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 544 transitions. [2018-02-02 20:36:34,450 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 20:36:34,450 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 544 transitions. [2018-02-02 20:36:34,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 20:36:34,450 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:34,450 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:34,451 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:34,451 INFO L82 PathProgramCache]: Analyzing trace with hash 1049980534, now seen corresponding path program 1 times [2018-02-02 20:36:34,452 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:34,462 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:34,462 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:34,611 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:34,612 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:34,612 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 20:36:34,612 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:34,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:34,613 INFO L182 omatonBuilderFactory]: Interpolants [15232#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 15233#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15234#(and (not (= |entry_point_#t~ret59.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 15235#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= entry_point_~client~0.base 0))), 15228#true, 15229#false, 15230#(= 1 (select |#valid| |~#ldv_global_msg_list.base|)), 15231#(= |#valid| |old(#valid)|)] [2018-02-02 20:36:34,613 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:34,613 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 20:36:34,613 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 20:36:34,613 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:34,614 INFO L87 Difference]: Start difference. First operand 473 states and 544 transitions. Second operand 8 states. [2018-02-02 20:36:35,434 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:35,434 INFO L93 Difference]: Finished difference Result 569 states and 639 transitions. [2018-02-02 20:36:35,434 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 20:36:35,434 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-02-02 20:36:35,434 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:35,435 INFO L225 Difference]: With dead ends: 569 [2018-02-02 20:36:35,435 INFO L226 Difference]: Without dead ends: 569 [2018-02-02 20:36:35,435 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:36:35,436 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states. [2018-02-02 20:36:35,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 473. [2018-02-02 20:36:35,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-02 20:36:35,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 543 transitions. [2018-02-02 20:36:35,446 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 543 transitions. Word has length 29 [2018-02-02 20:36:35,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:35,446 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 543 transitions. [2018-02-02 20:36:35,446 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 20:36:35,446 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 543 transitions. [2018-02-02 20:36:35,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-02 20:36:35,447 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:35,447 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:35,447 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:35,447 INFO L82 PathProgramCache]: Analyzing trace with hash 1049980535, now seen corresponding path program 1 times [2018-02-02 20:36:35,448 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:35,453 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:35,453 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:35,507 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:35,507 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:35,507 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 20:36:35,507 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:35,508 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:35,508 INFO L182 omatonBuilderFactory]: Interpolants [16288#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16289#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 16290#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16291#(= |old(#length)| |#length|), 16284#true, 16285#false, 16286#(and (= |~#ldv_global_msg_list.offset| 0) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 16287#(and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 8 (select |#length| |~#ldv_global_msg_list.base|)))] [2018-02-02 20:36:35,508 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:35,508 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 20:36:35,508 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 20:36:35,508 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:35,509 INFO L87 Difference]: Start difference. First operand 473 states and 543 transitions. Second operand 8 states. [2018-02-02 20:36:36,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:36,337 INFO L93 Difference]: Finished difference Result 635 states and 718 transitions. [2018-02-02 20:36:36,337 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 20:36:36,337 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-02-02 20:36:36,337 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:36,338 INFO L225 Difference]: With dead ends: 635 [2018-02-02 20:36:36,339 INFO L226 Difference]: Without dead ends: 635 [2018-02-02 20:36:36,339 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-02-02 20:36:36,339 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states. [2018-02-02 20:36:36,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 472. [2018-02-02 20:36:36,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 20:36:36,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 541 transitions. [2018-02-02 20:36:36,348 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 541 transitions. Word has length 29 [2018-02-02 20:36:36,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:36,349 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 541 transitions. [2018-02-02 20:36:36,349 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 20:36:36,349 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 541 transitions. [2018-02-02 20:36:36,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-02-02 20:36:36,349 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:36,349 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:36,350 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:36,350 INFO L82 PathProgramCache]: Analyzing trace with hash -286010216, now seen corresponding path program 1 times [2018-02-02 20:36:36,351 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:36,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:36,358 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:36,417 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 20:36:36,417 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:36,417 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:36:36,417 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:36,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:36,418 INFO L182 omatonBuilderFactory]: Interpolants [17411#true, 17412#false, 17413#(= 0 |~#ldv_global_msg_list.offset|), 17414#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 17415#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 17416#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4)))] [2018-02-02 20:36:36,418 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 20:36:36,418 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:36,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:36,418 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:36,418 INFO L87 Difference]: Start difference. First operand 472 states and 541 transitions. Second operand 6 states. [2018-02-02 20:36:36,787 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:36,787 INFO L93 Difference]: Finished difference Result 481 states and 550 transitions. [2018-02-02 20:36:36,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:36,788 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-02-02 20:36:36,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:36,789 INFO L225 Difference]: With dead ends: 481 [2018-02-02 20:36:36,789 INFO L226 Difference]: Without dead ends: 481 [2018-02-02 20:36:36,789 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:36:36,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-02 20:36:36,805 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 472. [2018-02-02 20:36:36,805 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 20:36:36,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 540 transitions. [2018-02-02 20:36:36,807 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 540 transitions. Word has length 31 [2018-02-02 20:36:36,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:36,807 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 540 transitions. [2018-02-02 20:36:36,808 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:36,808 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 540 transitions. [2018-02-02 20:36:36,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 20:36:36,808 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:36,808 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:36,808 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:36,809 INFO L82 PathProgramCache]: Analyzing trace with hash 974304967, now seen corresponding path program 1 times [2018-02-02 20:36:36,810 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:36,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:36,819 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:36,850 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:36,851 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:36,851 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:36:36,851 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:36,851 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 20:36:36,852 INFO L182 omatonBuilderFactory]: Interpolants [18384#(= 0 entry_point_~cfg~2.offset), 18379#true, 18380#false, 18381#(= 0 |ldv_malloc_#t~malloc4.offset|), 18382#(= 0 |ldv_malloc_#res.offset|), 18383#(= 0 |entry_point_#t~ret60.offset|)] [2018-02-02 20:36:36,852 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:36,852 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:36,852 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:36,852 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:36,852 INFO L87 Difference]: Start difference. First operand 472 states and 540 transitions. Second operand 6 states. [2018-02-02 20:36:36,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:36,878 INFO L93 Difference]: Finished difference Result 471 states and 539 transitions. [2018-02-02 20:36:36,879 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:36,879 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-02-02 20:36:36,879 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:36,881 INFO L225 Difference]: With dead ends: 471 [2018-02-02 20:36:36,881 INFO L226 Difference]: Without dead ends: 471 [2018-02-02 20:36:36,881 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:36,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 471 states. [2018-02-02 20:36:36,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 471 to 471. [2018-02-02 20:36:36,885 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-02 20:36:36,886 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 539 transitions. [2018-02-02 20:36:36,886 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 539 transitions. Word has length 36 [2018-02-02 20:36:36,886 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:36,886 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 539 transitions. [2018-02-02 20:36:36,886 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:36,886 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 539 transitions. [2018-02-02 20:36:36,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 20:36:36,887 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:36,887 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:36,887 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:36,887 INFO L82 PathProgramCache]: Analyzing trace with hash 974304968, now seen corresponding path program 1 times [2018-02-02 20:36:36,888 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:36,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:36,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:36,916 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:36,916 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:36,916 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 20:36:36,916 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:36,917 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 20:36:36,917 INFO L182 omatonBuilderFactory]: Interpolants [19329#true, 19330#false, 19331#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 19332#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 19333#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 19334#(= 1 (select |#valid| entry_point_~cfg~2.base)), 19335#(= |#valid| |old(#valid)|)] [2018-02-02 20:36:36,917 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:36,917 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:36,917 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:36,917 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:36,917 INFO L87 Difference]: Start difference. First operand 471 states and 539 transitions. Second operand 7 states. [2018-02-02 20:36:37,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:37,470 INFO L93 Difference]: Finished difference Result 547 states and 631 transitions. [2018-02-02 20:36:37,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:37,470 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-02-02 20:36:37,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:37,471 INFO L225 Difference]: With dead ends: 547 [2018-02-02 20:36:37,472 INFO L226 Difference]: Without dead ends: 547 [2018-02-02 20:36:37,472 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:37,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-02-02 20:36:37,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 472. [2018-02-02 20:36:37,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 20:36:37,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 539 transitions. [2018-02-02 20:36:37,477 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 539 transitions. Word has length 36 [2018-02-02 20:36:37,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:37,477 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 539 transitions. [2018-02-02 20:36:37,477 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:37,478 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 539 transitions. [2018-02-02 20:36:37,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-02 20:36:37,478 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:37,478 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:37,478 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:37,478 INFO L82 PathProgramCache]: Analyzing trace with hash 974304983, now seen corresponding path program 1 times [2018-02-02 20:36:37,479 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:37,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:37,484 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:37,508 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:37,508 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:37,508 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:36:37,508 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:37,509 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 20:36:37,509 INFO L182 omatonBuilderFactory]: Interpolants [20357#true, 20358#false, 20359#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 20360#(and (= 0 |entry_point_#t~ret62.base|) (= 0 |entry_point_#t~ret62.offset|)), 20361#(and (= 0 entry_point_~fe~2.base) (= 0 entry_point_~fe~2.offset))] [2018-02-02 20:36:37,509 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:37,509 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:37,509 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:37,509 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:37,509 INFO L87 Difference]: Start difference. First operand 472 states and 539 transitions. Second operand 5 states. [2018-02-02 20:36:37,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:37,519 INFO L93 Difference]: Finished difference Result 477 states and 541 transitions. [2018-02-02 20:36:37,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:36:37,520 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 36 [2018-02-02 20:36:37,520 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:37,521 INFO L225 Difference]: With dead ends: 477 [2018-02-02 20:36:37,521 INFO L226 Difference]: Without dead ends: 477 [2018-02-02 20:36:37,521 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:37,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 477 states. [2018-02-02 20:36:37,524 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 477 to 470. [2018-02-02 20:36:37,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-02 20:36:37,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-02 20:36:37,526 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-02 20:36:37,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:37,526 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-02 20:36:37,526 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:37,526 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-02 20:36:37,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-02-02 20:36:37,526 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:37,526 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:37,526 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:37,527 INFO L82 PathProgramCache]: Analyzing trace with hash 138683223, now seen corresponding path program 1 times [2018-02-02 20:36:37,527 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:37,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:37,533 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:37,656 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:37,657 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:37,657 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 20:36:37,657 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:37,657 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:37,657 INFO L182 omatonBuilderFactory]: Interpolants [21312#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 21313#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 21314#(= 1 (select |#valid| entry_point_~client~0.base)), 21315#(= |#valid| |old(#valid)|), 21316#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 21317#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 21318#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 21319#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 21320#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 21309#true, 21310#false, 21311#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))] [2018-02-02 20:36:37,657 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:37,657 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 20:36:37,657 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 20:36:37,657 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-02-02 20:36:37,658 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 12 states. [2018-02-02 20:36:38,367 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:38,368 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-02 20:36:38,368 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 20:36:38,368 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 37 [2018-02-02 20:36:38,368 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:38,369 INFO L225 Difference]: With dead ends: 540 [2018-02-02 20:36:38,369 INFO L226 Difference]: Without dead ends: 540 [2018-02-02 20:36:38,369 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2018-02-02 20:36:38,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-02 20:36:38,374 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 471. [2018-02-02 20:36:38,374 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-02 20:36:38,375 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-02 20:36:38,376 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 37 [2018-02-02 20:36:38,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:38,376 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-02 20:36:38,376 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 20:36:38,376 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-02 20:36:38,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 20:36:38,377 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:38,377 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:38,377 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:38,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1026304086, now seen corresponding path program 1 times [2018-02-02 20:36:38,378 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:38,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:38,386 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:38,419 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:38,420 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:38,420 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:38,420 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:38,420 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 20:36:38,420 INFO L182 omatonBuilderFactory]: Interpolants [22336#true, 22337#false, 22338#(not (= |ldv_malloc_#t~malloc4.base| 0)), 22339#(not (= |ldv_malloc_#res.base| 0)), 22340#(not (= |entry_point_#t~ret62.base| 0)), 22341#(not (= entry_point_~fe~2.base 0))] [2018-02-02 20:36:38,421 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:38,421 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:38,421 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:38,421 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:38,421 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 6 states. [2018-02-02 20:36:38,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:38,457 INFO L93 Difference]: Finished difference Result 474 states and 537 transitions. [2018-02-02 20:36:38,457 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:38,457 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2018-02-02 20:36:38,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:38,458 INFO L225 Difference]: With dead ends: 474 [2018-02-02 20:36:38,459 INFO L226 Difference]: Without dead ends: 474 [2018-02-02 20:36:38,459 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:38,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states. [2018-02-02 20:36:38,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 471. [2018-02-02 20:36:38,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-02 20:36:38,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 533 transitions. [2018-02-02 20:36:38,463 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 533 transitions. Word has length 38 [2018-02-02 20:36:38,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:38,464 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 533 transitions. [2018-02-02 20:36:38,464 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:38,464 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 533 transitions. [2018-02-02 20:36:38,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 20:36:38,464 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:38,464 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:38,464 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:38,464 INFO L82 PathProgramCache]: Analyzing trace with hash -1026304072, now seen corresponding path program 1 times [2018-02-02 20:36:38,465 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:38,471 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:38,471 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:38,521 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:38,521 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:38,521 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-02 20:36:38,521 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:38,521 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 20:36:38,521 INFO L182 omatonBuilderFactory]: Interpolants [23296#(and (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 23297#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 23289#true, 23290#false, 23291#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 23292#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 23293#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 23294#(= 1 (select |#valid| entry_point_~cfg~2.base)), 23295#(= |#valid| |old(#valid)|)] [2018-02-02 20:36:38,522 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:38,522 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-02 20:36:38,522 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-02 20:36:38,522 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-02 20:36:38,522 INFO L87 Difference]: Start difference. First operand 471 states and 533 transitions. Second operand 9 states. [2018-02-02 20:36:39,328 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:39,328 INFO L93 Difference]: Finished difference Result 576 states and 665 transitions. [2018-02-02 20:36:39,328 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 20:36:39,328 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-02-02 20:36:39,328 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:39,329 INFO L225 Difference]: With dead ends: 576 [2018-02-02 20:36:39,329 INFO L226 Difference]: Without dead ends: 576 [2018-02-02 20:36:39,330 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:36:39,330 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 576 states. [2018-02-02 20:36:39,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 576 to 470. [2018-02-02 20:36:39,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-02 20:36:39,334 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 532 transitions. [2018-02-02 20:36:39,335 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 532 transitions. Word has length 38 [2018-02-02 20:36:39,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:39,335 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 532 transitions. [2018-02-02 20:36:39,335 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-02 20:36:39,335 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 532 transitions. [2018-02-02 20:36:39,335 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-02 20:36:39,335 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:39,335 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:39,335 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:39,335 INFO L82 PathProgramCache]: Analyzing trace with hash -1026304071, now seen corresponding path program 1 times [2018-02-02 20:36:39,336 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:39,342 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:39,343 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:39,516 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 20:36:39,516 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:39,516 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 20:36:39,516 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:39,516 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:39,517 INFO L182 omatonBuilderFactory]: Interpolants [24352#(and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (= 0 entry_point_~cfg~2.offset)), 24353#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 24354#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 24355#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 24356#(and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= entry_point_~cfg~2.offset 0)), 24346#true, 24347#false, 24348#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 24349#(and (= 0 |ldv_malloc_#t~malloc4.offset|) (or (and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|))) (<= (+ |ldv_malloc_#in~size| 1) 0) (<= 2147483648 |ldv_malloc_#in~size|))), 24350#(and (= 0 |ldv_malloc_#res.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (= (select |#valid| |ldv_malloc_#res.base|) 1)) (<= 2147483648 |ldv_malloc_#in~size|))), 24351#(and (= 0 |entry_point_#t~ret60.offset|) (= (select |#valid| |entry_point_#t~ret60.base|) 1) (<= 4 (select |#length| |entry_point_#t~ret60.base|)))] [2018-02-02 20:36:39,517 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-02 20:36:39,517 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 20:36:39,517 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 20:36:39,517 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:36:39,517 INFO L87 Difference]: Start difference. First operand 470 states and 532 transitions. Second operand 11 states. [2018-02-02 20:36:40,788 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:40,788 INFO L93 Difference]: Finished difference Result 619 states and 715 transitions. [2018-02-02 20:36:40,788 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 20:36:40,788 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-02-02 20:36:40,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:40,790 INFO L225 Difference]: With dead ends: 619 [2018-02-02 20:36:40,790 INFO L226 Difference]: Without dead ends: 619 [2018-02-02 20:36:40,791 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=141, Unknown=0, NotChecked=0, Total=182 [2018-02-02 20:36:40,791 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 619 states. [2018-02-02 20:36:40,796 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 619 to 469. [2018-02-02 20:36:40,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-02 20:36:40,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 531 transitions. [2018-02-02 20:36:40,798 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 531 transitions. Word has length 38 [2018-02-02 20:36:40,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:40,798 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 531 transitions. [2018-02-02 20:36:40,798 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 20:36:40,798 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 531 transitions. [2018-02-02 20:36:40,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-02 20:36:40,799 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:40,799 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:40,799 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:40,799 INFO L82 PathProgramCache]: Analyzing trace with hash -246151779, now seen corresponding path program 1 times [2018-02-02 20:36:40,800 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:40,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:40,810 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:40,975 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:40,975 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:40,975 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 20:36:40,975 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:40,975 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:40,975 INFO L182 omatonBuilderFactory]: Interpolants [25456#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 25457#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 25458#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 25459#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 25460#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 25461#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |entry_point_#t~ret60.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 25462#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 25452#true, 25453#false, 25454#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 25455#(= |#valid| |old(#valid)|)] [2018-02-02 20:36:40,976 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:40,976 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 20:36:40,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 20:36:40,976 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:36:40,976 INFO L87 Difference]: Start difference. First operand 469 states and 531 transitions. Second operand 11 states. [2018-02-02 20:36:41,943 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:41,943 INFO L93 Difference]: Finished difference Result 566 states and 631 transitions. [2018-02-02 20:36:41,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 20:36:41,943 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 40 [2018-02-02 20:36:41,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:41,945 INFO L225 Difference]: With dead ends: 566 [2018-02-02 20:36:41,945 INFO L226 Difference]: Without dead ends: 566 [2018-02-02 20:36:41,945 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 6 SyntacticMatches, 5 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=41, Invalid=141, Unknown=0, NotChecked=0, Total=182 [2018-02-02 20:36:41,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 566 states. [2018-02-02 20:36:41,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 566 to 472. [2018-02-02 20:36:41,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-02 20:36:41,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 535 transitions. [2018-02-02 20:36:41,950 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 535 transitions. Word has length 40 [2018-02-02 20:36:41,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:41,950 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 535 transitions. [2018-02-02 20:36:41,950 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 20:36:41,950 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 535 transitions. [2018-02-02 20:36:41,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-02 20:36:41,951 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:41,951 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:41,951 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:41,951 INFO L82 PathProgramCache]: Analyzing trace with hash -357951082, now seen corresponding path program 1 times [2018-02-02 20:36:41,952 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:41,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:41,959 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:42,035 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:42,036 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:42,036 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 20:36:42,036 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:42,036 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-02 20:36:42,036 INFO L182 omatonBuilderFactory]: Interpolants [26512#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (= |#valid| (store |old(#valid)| |entry_point_#t~ret59.base| (select |#valid| |entry_point_#t~ret59.base|)))), 26513#(and (= |#valid| (store |old(#valid)| entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0))), 26507#true, 26508#false, 26509#(= |#valid| |old(#valid)|), 26510#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 26511#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0)))] [2018-02-02 20:36:42,036 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:42,036 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:42,037 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:42,037 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:42,037 INFO L87 Difference]: Start difference. First operand 472 states and 535 transitions. Second operand 7 states. [2018-02-02 20:36:42,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:42,587 INFO L93 Difference]: Finished difference Result 532 states and 608 transitions. [2018-02-02 20:36:42,588 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 20:36:42,588 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 39 [2018-02-02 20:36:42,588 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:42,589 INFO L225 Difference]: With dead ends: 532 [2018-02-02 20:36:42,590 INFO L226 Difference]: Without dead ends: 514 [2018-02-02 20:36:42,590 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-02 20:36:42,590 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 514 states. [2018-02-02 20:36:42,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 514 to 455. [2018-02-02 20:36:42,593 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 455 states. [2018-02-02 20:36:42,594 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 517 transitions. [2018-02-02 20:36:42,595 INFO L78 Accepts]: Start accepts. Automaton has 455 states and 517 transitions. Word has length 39 [2018-02-02 20:36:42,595 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:42,595 INFO L432 AbstractCegarLoop]: Abstraction has 455 states and 517 transitions. [2018-02-02 20:36:42,595 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:42,595 INFO L276 IsEmpty]: Start isEmpty. Operand 455 states and 517 transitions. [2018-02-02 20:36:42,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 20:36:42,595 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:42,595 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:42,595 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:42,596 INFO L82 PathProgramCache]: Analyzing trace with hash -328647170, now seen corresponding path program 1 times [2018-02-02 20:36:42,596 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:42,607 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:42,608 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:42,727 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:42,727 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:42,727 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 20:36:42,727 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:42,728 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:42,728 INFO L182 omatonBuilderFactory]: Interpolants [27505#true, 27506#false, 27507#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 27508#(not (= |ldv_malloc_#t~malloc4.base| 0)), 27509#(not (= |ldv_malloc_#res.base| 0)), 27510#(and (not (= |entry_point_#t~ret59.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 27511#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 27512#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 27513#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 27514#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-02 20:36:42,728 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:42,728 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 20:36:42,728 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 20:36:42,729 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:36:42,729 INFO L87 Difference]: Start difference. First operand 455 states and 517 transitions. Second operand 10 states. [2018-02-02 20:36:43,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:43,200 INFO L93 Difference]: Finished difference Result 481 states and 547 transitions. [2018-02-02 20:36:43,200 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 20:36:43,200 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-02 20:36:43,200 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:43,201 INFO L225 Difference]: With dead ends: 481 [2018-02-02 20:36:43,201 INFO L226 Difference]: Without dead ends: 481 [2018-02-02 20:36:43,201 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=215, Unknown=0, NotChecked=0, Total=272 [2018-02-02 20:36:43,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-02 20:36:43,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 464. [2018-02-02 20:36:43,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:36:43,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 528 transitions. [2018-02-02 20:36:43,205 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 528 transitions. Word has length 42 [2018-02-02 20:36:43,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:43,205 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 528 transitions. [2018-02-02 20:36:43,205 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 20:36:43,205 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 528 transitions. [2018-02-02 20:36:43,205 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-02 20:36:43,206 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:43,206 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:43,206 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:43,206 INFO L82 PathProgramCache]: Analyzing trace with hash -328647169, now seen corresponding path program 1 times [2018-02-02 20:36:43,206 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:43,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:43,212 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:43,386 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:43,386 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:43,386 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 20:36:43,386 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:43,387 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:43,387 INFO L182 omatonBuilderFactory]: Interpolants [28480#(and (or (not (= |entry_point_#t~ret59.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 28481#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 28482#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 28483#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 28484#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 28474#true, 28475#false, 28476#(= 0 |~#ldv_global_msg_list.offset|), 28477#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 28478#(not (= |ldv_malloc_#t~malloc4.base| 0)), 28479#(not (= |ldv_malloc_#res.base| 0))] [2018-02-02 20:36:43,387 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:43,387 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 20:36:43,387 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 20:36:43,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:36:43,388 INFO L87 Difference]: Start difference. First operand 464 states and 528 transitions. Second operand 11 states. [2018-02-02 20:36:44,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:44,064 INFO L93 Difference]: Finished difference Result 482 states and 548 transitions. [2018-02-02 20:36:44,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 20:36:44,065 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 42 [2018-02-02 20:36:44,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:44,066 INFO L225 Difference]: With dead ends: 482 [2018-02-02 20:36:44,066 INFO L226 Difference]: Without dead ends: 482 [2018-02-02 20:36:44,066 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=113, Invalid=439, Unknown=0, NotChecked=0, Total=552 [2018-02-02 20:36:44,067 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 482 states. [2018-02-02 20:36:44,070 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 482 to 464. [2018-02-02 20:36:44,070 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:36:44,071 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-02 20:36:44,071 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 42 [2018-02-02 20:36:44,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:44,072 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-02 20:36:44,072 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 20:36:44,072 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-02 20:36:44,072 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 20:36:44,072 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:44,073 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:44,073 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:44,073 INFO L82 PathProgramCache]: Analyzing trace with hash 94945719, now seen corresponding path program 1 times [2018-02-02 20:36:44,074 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:44,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:44,081 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:44,114 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 20:36:44,114 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:44,114 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:36:44,114 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:44,115 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:44,115 INFO L182 omatonBuilderFactory]: Interpolants [29458#true, 29459#false, 29460#(= 0 |ldv_malloc_#t~malloc4.offset|), 29461#(= 0 |ldv_malloc_#res.offset|), 29462#(= 0 |entry_point_#t~ret62.offset|), 29463#(= 0 entry_point_~fe~2.offset)] [2018-02-02 20:36:44,115 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 20:36:44,115 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:44,115 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:44,116 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:44,116 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 6 states. [2018-02-02 20:36:44,136 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:44,136 INFO L93 Difference]: Finished difference Result 463 states and 526 transitions. [2018-02-02 20:36:44,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:44,137 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-02-02 20:36:44,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:44,138 INFO L225 Difference]: With dead ends: 463 [2018-02-02 20:36:44,138 INFO L226 Difference]: Without dead ends: 463 [2018-02-02 20:36:44,139 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:44,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2018-02-02 20:36:44,145 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 463. [2018-02-02 20:36:44,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 20:36:44,146 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 526 transitions. [2018-02-02 20:36:44,146 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 526 transitions. Word has length 46 [2018-02-02 20:36:44,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:44,147 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 526 transitions. [2018-02-02 20:36:44,147 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:44,147 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 526 transitions. [2018-02-02 20:36:44,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-02 20:36:44,147 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:44,147 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:44,147 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:44,148 INFO L82 PathProgramCache]: Analyzing trace with hash 94945720, now seen corresponding path program 1 times [2018-02-02 20:36:44,148 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:44,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:44,156 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:44,195 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:44,195 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:44,196 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 20:36:44,196 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:44,196 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 20:36:44,196 INFO L182 omatonBuilderFactory]: Interpolants [30392#true, 30393#false, 30394#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 30395#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 30396#(= 1 (select |#valid| |entry_point_#t~ret62.base|)), 30397#(= 1 (select |#valid| entry_point_~fe~2.base)), 30398#(= |#valid| |old(#valid)|)] [2018-02-02 20:36:44,196 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:44,197 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:44,197 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:44,197 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:44,197 INFO L87 Difference]: Start difference. First operand 463 states and 526 transitions. Second operand 7 states. [2018-02-02 20:36:44,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:44,770 INFO L93 Difference]: Finished difference Result 531 states and 610 transitions. [2018-02-02 20:36:44,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:44,770 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 46 [2018-02-02 20:36:44,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:44,771 INFO L225 Difference]: With dead ends: 531 [2018-02-02 20:36:44,771 INFO L226 Difference]: Without dead ends: 531 [2018-02-02 20:36:44,771 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:44,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states. [2018-02-02 20:36:44,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 464. [2018-02-02 20:36:44,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:36:44,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-02 20:36:44,777 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 46 [2018-02-02 20:36:44,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:44,777 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-02 20:36:44,777 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:44,777 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-02 20:36:44,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-02 20:36:44,778 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:44,778 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:44,778 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:44,778 INFO L82 PathProgramCache]: Analyzing trace with hash -1351649693, now seen corresponding path program 1 times [2018-02-02 20:36:44,779 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:44,786 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:44,787 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:44,901 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 20:36:44,901 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:44,901 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-02 20:36:44,901 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:44,902 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 20:36:44,902 INFO L182 omatonBuilderFactory]: Interpolants [31396#true, 31397#false, 31398#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 31399#(= (select |#valid| |ldv_malloc_#res.base|) 1), 31400#(= (select |#valid| |entry_point_#t~ret60.base|) 1), 31401#(= (select |#valid| entry_point_~cfg~2.base) 1), 31402#(= |#valid| |old(#valid)|), 31403#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 31404#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 31405#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 31406#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 31407#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)))] [2018-02-02 20:36:44,902 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 20:36:44,902 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 20:36:44,903 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 20:36:44,903 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-02-02 20:36:44,903 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 12 states. [2018-02-02 20:36:45,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:45,699 INFO L93 Difference]: Finished difference Result 534 states and 613 transitions. [2018-02-02 20:36:45,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 20:36:45,700 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 47 [2018-02-02 20:36:45,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:45,701 INFO L225 Difference]: With dead ends: 534 [2018-02-02 20:36:45,701 INFO L226 Difference]: Without dead ends: 534 [2018-02-02 20:36:45,701 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2018-02-02 20:36:45,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2018-02-02 20:36:45,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 465. [2018-02-02 20:36:45,704 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 465 states. [2018-02-02 20:36:45,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 528 transitions. [2018-02-02 20:36:45,705 INFO L78 Accepts]: Start accepts. Automaton has 465 states and 528 transitions. Word has length 47 [2018-02-02 20:36:45,705 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:45,705 INFO L432 AbstractCegarLoop]: Abstraction has 465 states and 528 transitions. [2018-02-02 20:36:45,705 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 20:36:45,705 INFO L276 IsEmpty]: Start isEmpty. Operand 465 states and 528 transitions. [2018-02-02 20:36:45,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 20:36:45,705 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:45,705 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:45,706 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:45,706 INFO L82 PathProgramCache]: Analyzing trace with hash 15217780, now seen corresponding path program 1 times [2018-02-02 20:36:45,707 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:45,713 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:45,714 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:45,884 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:45,885 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:45,885 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 20:36:45,885 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:45,885 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:45,885 INFO L182 omatonBuilderFactory]: Interpolants [32416#(not (= |ldv_malloc_#res.base| 0)), 32417#(and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 32418#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 32419#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 32420#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 32421#(and (= |~#ldv_global_msg_list.offset| 0) (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 32422#(and (= |~#ldv_global_msg_list.offset| 0) (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 32411#true, 32412#false, 32413#(= 0 |~#ldv_global_msg_list.offset|), 32414#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 32415#(not (= |ldv_malloc_#t~malloc4.base| 0))] [2018-02-02 20:36:45,885 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:45,886 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-02 20:36:45,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-02 20:36:45,886 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=102, Unknown=0, NotChecked=0, Total=132 [2018-02-02 20:36:45,886 INFO L87 Difference]: Start difference. First operand 465 states and 528 transitions. Second operand 12 states. [2018-02-02 20:36:46,324 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:46,324 INFO L93 Difference]: Finished difference Result 469 states and 529 transitions. [2018-02-02 20:36:46,325 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-02 20:36:46,325 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 48 [2018-02-02 20:36:46,325 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:46,326 INFO L225 Difference]: With dead ends: 469 [2018-02-02 20:36:46,326 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 20:36:46,326 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 74 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=100, Invalid=362, Unknown=0, NotChecked=0, Total=462 [2018-02-02 20:36:46,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 20:36:46,329 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 463. [2018-02-02 20:36:46,329 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 20:36:46,329 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 524 transitions. [2018-02-02 20:36:46,329 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 524 transitions. Word has length 48 [2018-02-02 20:36:46,329 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:46,329 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 524 transitions. [2018-02-02 20:36:46,329 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-02 20:36:46,329 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 524 transitions. [2018-02-02 20:36:46,330 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 20:36:46,330 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:46,330 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:46,330 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:46,330 INFO L82 PathProgramCache]: Analyzing trace with hash -48702153, now seen corresponding path program 1 times [2018-02-02 20:36:46,331 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:46,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:46,340 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:46,575 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:46,575 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:46,576 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 20:36:46,576 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:46,576 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:36:46,576 INFO L182 omatonBuilderFactory]: Interpolants [33376#false, 33377#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (and (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0)) (<= |ldv_malloc_#in~size| ldv_malloc_~size))) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (div ldv_malloc_~size 4294967296) 0))), 33378#(or (and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))) (<= 4294967296 |ldv_malloc_#in~size|)), 33379#(or (<= 4294967296 |ldv_malloc_#in~size|) (and (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|)))), 33380#(and (<= 20 (select |#length| |entry_point_#t~ret59.base|)) (= 0 |entry_point_#t~ret59.offset|) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 33381#(and (= (select |#valid| entry_point_~client~0.base) 1) (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 33382#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 33383#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 33384#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 33385#(and (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 33386#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 33387#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 33375#true] [2018-02-02 20:36:46,577 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:46,577 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 20:36:46,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 20:36:46,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:36:46,577 INFO L87 Difference]: Start difference. First operand 463 states and 524 transitions. Second operand 13 states. [2018-02-02 20:36:48,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:48,024 INFO L93 Difference]: Finished difference Result 598 states and 691 transitions. [2018-02-02 20:36:48,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 20:36:48,024 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 48 [2018-02-02 20:36:48,025 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:48,026 INFO L225 Difference]: With dead ends: 598 [2018-02-02 20:36:48,026 INFO L226 Difference]: Without dead ends: 598 [2018-02-02 20:36:48,026 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2018-02-02 20:36:48,027 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 598 states. [2018-02-02 20:36:48,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 598 to 456. [2018-02-02 20:36:48,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 456 states. [2018-02-02 20:36:48,031 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 456 states to 456 states and 514 transitions. [2018-02-02 20:36:48,031 INFO L78 Accepts]: Start accepts. Automaton has 456 states and 514 transitions. Word has length 48 [2018-02-02 20:36:48,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:48,031 INFO L432 AbstractCegarLoop]: Abstraction has 456 states and 514 transitions. [2018-02-02 20:36:48,031 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 20:36:48,031 INFO L276 IsEmpty]: Start isEmpty. Operand 456 states and 514 transitions. [2018-02-02 20:36:48,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 20:36:48,032 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:48,032 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:48,032 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:48,032 INFO L82 PathProgramCache]: Analyzing trace with hash -48702182, now seen corresponding path program 1 times [2018-02-02 20:36:48,032 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:48,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:48,037 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:48,073 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 20:36:48,074 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:48,074 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:48,074 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:48,075 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:48,075 INFO L182 omatonBuilderFactory]: Interpolants [34452#true, 34453#false, 34454#(not (= |ldv_malloc_#t~malloc4.base| 0)), 34455#(not (= |ldv_malloc_#res.base| 0)), 34456#(not (= |entry_point_#t~ret64.base| 0)), 34457#(not (= entry_point_~addr~0.base 0))] [2018-02-02 20:36:48,075 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 20:36:48,075 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:48,075 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:48,075 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:48,075 INFO L87 Difference]: Start difference. First operand 456 states and 514 transitions. Second operand 6 states. [2018-02-02 20:36:48,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:48,106 INFO L93 Difference]: Finished difference Result 482 states and 547 transitions. [2018-02-02 20:36:48,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:48,107 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-02-02 20:36:48,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:48,109 INFO L225 Difference]: With dead ends: 482 [2018-02-02 20:36:48,109 INFO L226 Difference]: Without dead ends: 482 [2018-02-02 20:36:48,109 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:48,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 482 states. [2018-02-02 20:36:48,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 482 to 456. [2018-02-02 20:36:48,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 456 states. [2018-02-02 20:36:48,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 456 states to 456 states and 513 transitions. [2018-02-02 20:36:48,115 INFO L78 Accepts]: Start accepts. Automaton has 456 states and 513 transitions. Word has length 48 [2018-02-02 20:36:48,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:48,115 INFO L432 AbstractCegarLoop]: Abstraction has 456 states and 513 transitions. [2018-02-02 20:36:48,115 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:48,115 INFO L276 IsEmpty]: Start isEmpty. Operand 456 states and 513 transitions. [2018-02-02 20:36:48,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-02 20:36:48,116 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:48,116 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:48,116 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:48,116 INFO L82 PathProgramCache]: Analyzing trace with hash 1048532764, now seen corresponding path program 1 times [2018-02-02 20:36:48,117 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:48,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:48,130 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:48,400 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-02 20:36:48,400 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:48,400 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 20:36:48,400 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:48,401 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:48,401 INFO L182 omatonBuilderFactory]: Interpolants [35398#true, 35399#false, 35400#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 35401#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 35402#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 35403#(= 1 (select |#valid| entry_point_~client~0.base)), 35404#(= |#valid| |old(#valid)|), 35405#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 35406#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 35407#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 35408#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 35409#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35410#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 35411#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 35412#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35413#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base)))] [2018-02-02 20:36:48,401 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-02 20:36:48,401 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 20:36:48,402 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 20:36:48,402 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2018-02-02 20:36:48,402 INFO L87 Difference]: Start difference. First operand 456 states and 513 transitions. Second operand 16 states. [2018-02-02 20:36:49,158 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:49,158 INFO L93 Difference]: Finished difference Result 517 states and 587 transitions. [2018-02-02 20:36:49,158 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 20:36:49,158 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 48 [2018-02-02 20:36:49,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:49,159 INFO L225 Difference]: With dead ends: 517 [2018-02-02 20:36:49,159 INFO L226 Difference]: Without dead ends: 517 [2018-02-02 20:36:49,159 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-02-02 20:36:49,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-02-02 20:36:49,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 457. [2018-02-02 20:36:49,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 457 states. [2018-02-02 20:36:49,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 514 transitions. [2018-02-02 20:36:49,163 INFO L78 Accepts]: Start accepts. Automaton has 457 states and 514 transitions. Word has length 48 [2018-02-02 20:36:49,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:49,163 INFO L432 AbstractCegarLoop]: Abstraction has 457 states and 514 transitions. [2018-02-02 20:36:49,163 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 20:36:49,163 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 514 transitions. [2018-02-02 20:36:49,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-02 20:36:49,163 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:49,163 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:49,163 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:49,163 INFO L82 PathProgramCache]: Analyzing trace with hash -457080904, now seen corresponding path program 1 times [2018-02-02 20:36:49,164 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:49,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:49,170 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:49,459 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 20:36:49,460 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:49,460 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 20:36:49,460 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:49,460 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:49,460 INFO L182 omatonBuilderFactory]: Interpolants [36394#true, 36395#false, 36396#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 36397#(= |#valid| |old(#valid)|), 36398#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 36399#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 36400#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 36401#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 36402#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |entry_point_#t~ret60.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 36403#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 36404#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))), 36405#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 36406#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (= 1 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0)))] [2018-02-02 20:36:49,460 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 20:36:49,461 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 20:36:49,461 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 20:36:49,461 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:36:49,461 INFO L87 Difference]: Start difference. First operand 457 states and 514 transitions. Second operand 13 states. [2018-02-02 20:36:50,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:50,368 INFO L93 Difference]: Finished difference Result 551 states and 611 transitions. [2018-02-02 20:36:50,369 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-02 20:36:50,369 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 51 [2018-02-02 20:36:50,369 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:50,370 INFO L225 Difference]: With dead ends: 551 [2018-02-02 20:36:50,370 INFO L226 Difference]: Without dead ends: 551 [2018-02-02 20:36:50,370 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 11 SyntacticMatches, 6 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=54, Invalid=186, Unknown=0, NotChecked=0, Total=240 [2018-02-02 20:36:50,370 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-02-02 20:36:50,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 460. [2018-02-02 20:36:50,373 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-02 20:36:50,374 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 518 transitions. [2018-02-02 20:36:50,374 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 518 transitions. Word has length 51 [2018-02-02 20:36:50,374 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:50,374 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 518 transitions. [2018-02-02 20:36:50,374 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 20:36:50,374 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 518 transitions. [2018-02-02 20:36:50,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-02 20:36:50,374 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:50,374 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:50,374 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:50,375 INFO L82 PathProgramCache]: Analyzing trace with hash 1546595325, now seen corresponding path program 1 times [2018-02-02 20:36:50,375 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:50,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:50,383 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:50,696 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:50,697 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:50,697 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 20:36:50,697 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:50,697 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 20:36:50,697 INFO L182 omatonBuilderFactory]: Interpolants [37424#true, 37425#false, 37426#(= |#valid| |old(#valid)|), 37427#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 37428#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 37429#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (= |#valid| (store |old(#valid)| |entry_point_#t~ret59.base| (select |#valid| |entry_point_#t~ret59.base|)))), 37430#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 37431#(and (not (= |entry_point_#t~ret60.base| 0)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))))) (not (= entry_point_~client~0.base 0))), 37432#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base 0))), 37433#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0)))] [2018-02-02 20:36:50,697 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:50,697 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 20:36:50,698 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 20:36:50,698 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:36:50,698 INFO L87 Difference]: Start difference. First operand 460 states and 518 transitions. Second operand 10 states. [2018-02-02 20:36:51,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:51,806 INFO L93 Difference]: Finished difference Result 520 states and 591 transitions. [2018-02-02 20:36:51,806 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 20:36:51,806 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 50 [2018-02-02 20:36:51,807 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:51,808 INFO L225 Difference]: With dead ends: 520 [2018-02-02 20:36:51,809 INFO L226 Difference]: Without dead ends: 503 [2018-02-02 20:36:51,809 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 10 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:36:51,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-02 20:36:51,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 446. [2018-02-02 20:36:51,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-02-02 20:36:51,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 503 transitions. [2018-02-02 20:36:51,816 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 503 transitions. Word has length 50 [2018-02-02 20:36:51,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:51,816 INFO L432 AbstractCegarLoop]: Abstraction has 446 states and 503 transitions. [2018-02-02 20:36:51,816 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 20:36:51,816 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 503 transitions. [2018-02-02 20:36:51,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 20:36:51,817 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:51,817 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:51,817 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:51,817 INFO L82 PathProgramCache]: Analyzing trace with hash -1168073383, now seen corresponding path program 1 times [2018-02-02 20:36:51,818 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:51,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:51,828 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:52,021 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 20:36:52,021 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:52,021 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-02 20:36:52,021 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:52,022 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:52,022 INFO L182 omatonBuilderFactory]: Interpolants [38406#true, 38407#false, 38408#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 38409#(not (= |ldv_malloc_#t~malloc4.base| 0)), 38410#(not (= |ldv_malloc_#res.base| 0)), 38411#(and (not (= |entry_point_#t~ret59.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 38412#(and (not (= entry_point_~client~0.base 0)) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 38413#(and (or (and (not (= |entry_point_#t~ret60.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 38414#(and (or (and (or (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 38415#(and (or (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (not (= entry_point_~client~0.base 0))), 38416#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 38417#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 38418#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-02 20:36:52,022 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 20:36:52,022 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-02 20:36:52,022 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-02 20:36:52,023 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:36:52,023 INFO L87 Difference]: Start difference. First operand 446 states and 503 transitions. Second operand 13 states. [2018-02-02 20:36:52,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:52,542 INFO L93 Difference]: Finished difference Result 485 states and 548 transitions. [2018-02-02 20:36:52,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-02 20:36:52,542 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-02-02 20:36:52,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:52,543 INFO L225 Difference]: With dead ends: 485 [2018-02-02 20:36:52,543 INFO L226 Difference]: Without dead ends: 485 [2018-02-02 20:36:52,544 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 4 SyntacticMatches, 7 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=97, Invalid=455, Unknown=0, NotChecked=0, Total=552 [2018-02-02 20:36:52,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 485 states. [2018-02-02 20:36:52,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 485 to 462. [2018-02-02 20:36:52,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-02 20:36:52,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 529 transitions. [2018-02-02 20:36:52,547 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 529 transitions. Word has length 53 [2018-02-02 20:36:52,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:52,548 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 529 transitions. [2018-02-02 20:36:52,548 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-02 20:36:52,548 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 529 transitions. [2018-02-02 20:36:52,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-02 20:36:52,548 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:52,548 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:52,548 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:52,548 INFO L82 PathProgramCache]: Analyzing trace with hash -1168073382, now seen corresponding path program 1 times [2018-02-02 20:36:52,549 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:52,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:52,556 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:52,862 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 20:36:52,862 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:52,862 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-02 20:36:52,863 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:52,863 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:52,863 INFO L182 omatonBuilderFactory]: Interpolants [39392#(not (= |ldv_malloc_#t~malloc4.base| 0)), 39393#(not (= |ldv_malloc_#res.base| 0)), 39394#(and (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 39395#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39396#(and (or (and (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39397#(and (or (and (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (or (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base) (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39398#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0))), 39399#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 39400#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 39401#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 39388#true, 39389#false, 39390#(= 0 |~#ldv_global_msg_list.offset|), 39391#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|))] [2018-02-02 20:36:52,863 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 20:36:52,863 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-02 20:36:52,864 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-02 20:36:52,864 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-02 20:36:52,864 INFO L87 Difference]: Start difference. First operand 462 states and 529 transitions. Second operand 14 states. [2018-02-02 20:36:53,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:53,814 INFO L93 Difference]: Finished difference Result 486 states and 549 transitions. [2018-02-02 20:36:53,815 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 20:36:53,815 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-02-02 20:36:53,815 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:53,816 INFO L225 Difference]: With dead ends: 486 [2018-02-02 20:36:53,816 INFO L226 Difference]: Without dead ends: 486 [2018-02-02 20:36:53,816 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=163, Invalid=767, Unknown=0, NotChecked=0, Total=930 [2018-02-02 20:36:53,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2018-02-02 20:36:53,819 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 462. [2018-02-02 20:36:53,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-02 20:36:53,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 528 transitions. [2018-02-02 20:36:53,820 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 528 transitions. Word has length 53 [2018-02-02 20:36:53,820 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:53,820 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 528 transitions. [2018-02-02 20:36:53,820 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-02 20:36:53,820 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 528 transitions. [2018-02-02 20:36:53,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-02 20:36:53,820 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:53,820 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:53,820 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:53,821 INFO L82 PathProgramCache]: Analyzing trace with hash -919389941, now seen corresponding path program 1 times [2018-02-02 20:36:53,821 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:53,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:53,825 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:53,844 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-02 20:36:53,844 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:53,844 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:36:53,844 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:53,845 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:36:53,845 INFO L182 omatonBuilderFactory]: Interpolants [40385#true, 40386#false, 40387#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 40388#(and (= 0 |entry_point_#t~ret64.offset|) (= 0 |entry_point_#t~ret64.base|)), 40389#(and (= entry_point_~addr~0.offset 0) (= entry_point_~addr~0.base 0))] [2018-02-02 20:36:53,845 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-02 20:36:53,845 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:53,845 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:53,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:53,845 INFO L87 Difference]: Start difference. First operand 462 states and 528 transitions. Second operand 5 states. [2018-02-02 20:36:53,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:53,856 INFO L93 Difference]: Finished difference Result 464 states and 529 transitions. [2018-02-02 20:36:53,856 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:36:53,856 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2018-02-02 20:36:53,856 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:53,857 INFO L225 Difference]: With dead ends: 464 [2018-02-02 20:36:53,857 INFO L226 Difference]: Without dead ends: 464 [2018-02-02 20:36:53,857 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:53,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2018-02-02 20:36:53,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 462. [2018-02-02 20:36:53,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-02 20:36:53,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 527 transitions. [2018-02-02 20:36:53,861 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 527 transitions. Word has length 54 [2018-02-02 20:36:53,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:53,861 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 527 transitions. [2018-02-02 20:36:53,861 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:53,861 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 527 transitions. [2018-02-02 20:36:53,861 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 20:36:53,861 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:53,862 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:53,862 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:53,862 INFO L82 PathProgramCache]: Analyzing trace with hash 1250611821, now seen corresponding path program 2 times [2018-02-02 20:36:53,863 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:53,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:53,868 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:53,886 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-02 20:36:53,886 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:53,887 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:36:53,887 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:53,887 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 20:36:53,887 INFO L182 omatonBuilderFactory]: Interpolants [41316#true, 41317#false, 41318#(= 0 |ldv_malloc_#t~malloc4.offset|), 41319#(= 0 |ldv_malloc_#res.offset|), 41320#(= 0 |entry_point_#t~ret64.offset|), 41321#(= entry_point_~addr~0.offset 0)] [2018-02-02 20:36:53,887 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-02 20:36:53,887 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:53,887 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:53,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:53,888 INFO L87 Difference]: Start difference. First operand 462 states and 527 transitions. Second operand 6 states. [2018-02-02 20:36:53,912 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:53,912 INFO L93 Difference]: Finished difference Result 461 states and 525 transitions. [2018-02-02 20:36:53,912 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:53,912 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2018-02-02 20:36:53,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:53,913 INFO L225 Difference]: With dead ends: 461 [2018-02-02 20:36:53,913 INFO L226 Difference]: Without dead ends: 461 [2018-02-02 20:36:53,914 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:53,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states. [2018-02-02 20:36:53,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 461. [2018-02-02 20:36:53,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-02 20:36:53,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 525 transitions. [2018-02-02 20:36:53,918 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 525 transitions. Word has length 56 [2018-02-02 20:36:53,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:53,918 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 525 transitions. [2018-02-02 20:36:53,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:53,918 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 525 transitions. [2018-02-02 20:36:53,918 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-02 20:36:53,918 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:53,918 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:53,919 INFO L371 AbstractCegarLoop]: === Iteration 42 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:53,919 INFO L82 PathProgramCache]: Analyzing trace with hash 1250611822, now seen corresponding path program 1 times [2018-02-02 20:36:53,919 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:53,925 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:53,925 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:53,948 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 20:36:53,948 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:53,948 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 20:36:53,948 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:53,949 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:36:53,949 INFO L182 omatonBuilderFactory]: Interpolants [42246#true, 42247#false, 42248#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 42249#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 42250#(= 1 (select |#valid| |entry_point_#t~ret64.base|)), 42251#(= 1 (select |#valid| entry_point_~addr~0.base)), 42252#(= |#valid| |old(#valid)|)] [2018-02-02 20:36:53,949 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 20:36:53,949 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:53,949 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:53,949 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:53,949 INFO L87 Difference]: Start difference. First operand 461 states and 525 transitions. Second operand 7 states. [2018-02-02 20:36:54,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:54,464 INFO L93 Difference]: Finished difference Result 526 states and 607 transitions. [2018-02-02 20:36:54,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:54,465 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 56 [2018-02-02 20:36:54,465 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:54,466 INFO L225 Difference]: With dead ends: 526 [2018-02-02 20:36:54,466 INFO L226 Difference]: Without dead ends: 526 [2018-02-02 20:36:54,466 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:36:54,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states. [2018-02-02 20:36:54,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 464. [2018-02-02 20:36:54,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:36:54,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 529 transitions. [2018-02-02 20:36:54,469 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 529 transitions. Word has length 56 [2018-02-02 20:36:54,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:54,470 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 529 transitions. [2018-02-02 20:36:54,470 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:54,470 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 529 transitions. [2018-02-02 20:36:54,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-02 20:36:54,470 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:54,470 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:54,470 INFO L371 AbstractCegarLoop]: === Iteration 43 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:54,470 INFO L82 PathProgramCache]: Analyzing trace with hash 114261097, now seen corresponding path program 1 times [2018-02-02 20:36:54,471 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:54,479 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:54,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:54,570 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 31 proven. 7 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 20:36:54,570 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:54,570 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 20:36:54,571 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:54,571 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:54,571 INFO L182 omatonBuilderFactory]: Interpolants [43248#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 43249#(= 1 (select |#valid| |entry_point_#t~ret62.base|)), 43250#(= 1 (select |#valid| entry_point_~fe~2.base)), 43251#(= |#valid| |old(#valid)|), 43252#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 43253#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 43254#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~fe~2.base |entry_point_#t~ret64.base|)) (= 1 (select |#valid| entry_point_~fe~2.base))), 43255#(and (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 43245#true, 43246#false, 43247#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))] [2018-02-02 20:36:54,571 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 31 proven. 7 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 20:36:54,571 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 20:36:54,571 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 20:36:54,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:36:54,572 INFO L87 Difference]: Start difference. First operand 464 states and 529 transitions. Second operand 11 states. [2018-02-02 20:36:55,409 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:55,409 INFO L93 Difference]: Finished difference Result 522 states and 600 transitions. [2018-02-02 20:36:55,409 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 20:36:55,409 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 57 [2018-02-02 20:36:55,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:55,410 INFO L225 Difference]: With dead ends: 522 [2018-02-02 20:36:55,410 INFO L226 Difference]: Without dead ends: 522 [2018-02-02 20:36:55,411 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:36:55,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-02-02 20:36:55,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 464. [2018-02-02 20:36:55,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:36:55,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 528 transitions. [2018-02-02 20:36:55,417 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 528 transitions. Word has length 57 [2018-02-02 20:36:55,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:55,417 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 528 transitions. [2018-02-02 20:36:55,417 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 20:36:55,417 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 528 transitions. [2018-02-02 20:36:55,418 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-02 20:36:55,418 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:55,418 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:55,418 INFO L371 AbstractCegarLoop]: === Iteration 44 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:55,418 INFO L82 PathProgramCache]: Analyzing trace with hash 114262409, now seen corresponding path program 1 times [2018-02-02 20:36:55,419 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:55,426 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:55,427 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:55,458 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-02 20:36:55,458 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:55,459 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:36:55,459 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:55,459 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-02 20:36:55,459 INFO L182 omatonBuilderFactory]: Interpolants [44246#true, 44247#false, 44248#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 44249#(and (= 0 |entry_point_#t~ret66.base|) (= 0 |entry_point_#t~ret66.offset|)), 44250#(and (= entry_point_~adapter~0.base 0) (= 0 entry_point_~adapter~0.offset))] [2018-02-02 20:36:55,460 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-02 20:36:55,460 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:36:55,460 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:36:55,460 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:55,460 INFO L87 Difference]: Start difference. First operand 464 states and 528 transitions. Second operand 5 states. [2018-02-02 20:36:55,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:55,473 INFO L93 Difference]: Finished difference Result 469 states and 529 transitions. [2018-02-02 20:36:55,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:36:55,474 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-02-02 20:36:55,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:55,475 INFO L225 Difference]: With dead ends: 469 [2018-02-02 20:36:55,476 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 20:36:55,476 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:36:55,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 20:36:55,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 464. [2018-02-02 20:36:55,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:36:55,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-02 20:36:55,481 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 57 [2018-02-02 20:36:55,482 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:55,482 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-02 20:36:55,482 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:36:55,482 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-02 20:36:55,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-02 20:36:55,483 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:55,483 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:55,483 INFO L371 AbstractCegarLoop]: === Iteration 45 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:55,483 INFO L82 PathProgramCache]: Analyzing trace with hash -1916825904, now seen corresponding path program 1 times [2018-02-02 20:36:55,484 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:55,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:55,491 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:55,518 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:36:55,518 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:55,518 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:55,519 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:55,519 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 20:36:55,520 INFO L182 omatonBuilderFactory]: Interpolants [45184#true, 45185#false, 45186#(not (= |ldv_malloc_#t~malloc4.base| 0)), 45187#(not (= |ldv_malloc_#res.base| 0)), 45188#(not (= |entry_point_#t~ret66.base| 0)), 45189#(not (= entry_point_~adapter~0.base 0))] [2018-02-02 20:36:55,520 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:36:55,520 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:55,520 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:55,520 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:55,520 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 6 states. [2018-02-02 20:36:55,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:55,552 INFO L93 Difference]: Finished difference Result 467 states and 526 transitions. [2018-02-02 20:36:55,552 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:55,552 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2018-02-02 20:36:55,552 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:55,554 INFO L225 Difference]: With dead ends: 467 [2018-02-02 20:36:55,554 INFO L226 Difference]: Without dead ends: 467 [2018-02-02 20:36:55,554 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:55,555 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 467 states. [2018-02-02 20:36:55,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 467 to 463. [2018-02-02 20:36:55,559 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 20:36:55,560 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 524 transitions. [2018-02-02 20:36:55,560 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 524 transitions. Word has length 58 [2018-02-02 20:36:55,560 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:55,560 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 524 transitions. [2018-02-02 20:36:55,561 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:55,561 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 524 transitions. [2018-02-02 20:36:55,561 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-02 20:36:55,561 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:55,561 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:55,561 INFO L371 AbstractCegarLoop]: === Iteration 46 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:55,562 INFO L82 PathProgramCache]: Analyzing trace with hash -752873006, now seen corresponding path program 1 times [2018-02-02 20:36:55,562 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:55,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:55,574 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:55,789 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 30 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:55,789 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:55,789 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 20:36:55,789 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:55,790 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:55,790 INFO L182 omatonBuilderFactory]: Interpolants [46122#true, 46123#false, 46124#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 46125#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 46126#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 46127#(= 1 (select |#valid| entry_point_~cfg~2.base)), 46128#(= |#valid| |old(#valid)|), 46129#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 46130#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 46131#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 46132#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 46133#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 46134#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 46135#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 46136#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret64.base|))), 46137#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)))] [2018-02-02 20:36:55,790 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 30 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-02 20:36:55,790 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 20:36:55,790 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 20:36:55,790 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2018-02-02 20:36:55,790 INFO L87 Difference]: Start difference. First operand 463 states and 524 transitions. Second operand 16 states. [2018-02-02 20:36:56,473 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:56,473 INFO L93 Difference]: Finished difference Result 520 states and 595 transitions. [2018-02-02 20:36:56,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 20:36:56,474 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 58 [2018-02-02 20:36:56,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:56,475 INFO L225 Difference]: With dead ends: 520 [2018-02-02 20:36:56,475 INFO L226 Difference]: Without dead ends: 520 [2018-02-02 20:36:56,475 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-02-02 20:36:56,476 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 520 states. [2018-02-02 20:36:56,480 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 520 to 463. [2018-02-02 20:36:56,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-02 20:36:56,481 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 523 transitions. [2018-02-02 20:36:56,481 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 523 transitions. Word has length 58 [2018-02-02 20:36:56,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:56,481 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 523 transitions. [2018-02-02 20:36:56,481 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 20:36:56,481 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 523 transitions. [2018-02-02 20:36:56,482 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 20:36:56,482 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:56,482 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:56,482 INFO L371 AbstractCegarLoop]: === Iteration 47 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:56,482 INFO L82 PathProgramCache]: Analyzing trace with hash 2004050831, now seen corresponding path program 1 times [2018-02-02 20:36:56,483 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:56,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:56,493 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:56,823 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 20:36:56,823 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:56,823 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 20:36:56,823 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:56,824 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-02 20:36:56,824 INFO L182 omatonBuilderFactory]: Interpolants [47136#(and (or (and (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (or (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 47137#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0))), 47138#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 47139#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 47140#(and (or (and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)) (< (+ ldv_destroy_msgs_~msg~1.offset 4) |~#ldv_global_msg_list.offset|)) (or (= |~#ldv_global_msg_list.offset| 0) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)))), 47141#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 47127#true, 47128#false, 47129#(= 0 |~#ldv_global_msg_list.offset|), 47130#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 47131#(not (= |ldv_malloc_#t~malloc4.base| 0)), 47132#(not (= |ldv_malloc_#res.base| 0)), 47133#(and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 47134#(and (not (= entry_point_~client~0.base 0)) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 47135#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 20:36:56,824 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-02 20:36:56,824 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-02 20:36:56,824 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-02 20:36:56,824 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-02-02 20:36:56,824 INFO L87 Difference]: Start difference. First operand 463 states and 523 transitions. Second operand 15 states. [2018-02-02 20:36:57,595 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:57,595 INFO L93 Difference]: Finished difference Result 469 states and 523 transitions. [2018-02-02 20:36:57,595 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 20:36:57,596 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2018-02-02 20:36:57,596 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:57,597 INFO L225 Difference]: With dead ends: 469 [2018-02-02 20:36:57,597 INFO L226 Difference]: Without dead ends: 469 [2018-02-02 20:36:57,597 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=152, Invalid=718, Unknown=0, NotChecked=0, Total=870 [2018-02-02 20:36:57,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-02 20:36:57,600 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 461. [2018-02-02 20:36:57,600 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-02 20:36:57,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-02 20:36:57,600 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 59 [2018-02-02 20:36:57,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:57,600 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-02 20:36:57,601 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-02 20:36:57,601 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-02 20:36:57,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 20:36:57,601 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:57,601 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:57,601 INFO L371 AbstractCegarLoop]: === Iteration 48 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:57,601 INFO L82 PathProgramCache]: Analyzing trace with hash 707940711, now seen corresponding path program 1 times [2018-02-02 20:36:57,602 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:57,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:57,607 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:57,633 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:36:57,633 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:57,633 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:36:57,633 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:57,634 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 20:36:57,634 INFO L182 omatonBuilderFactory]: Interpolants [48102#true, 48103#false, 48104#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 48105#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 48106#(= 1 (select |#valid| |entry_point_#t~ret66.base|)), 48107#(= 1 (select |#valid| entry_point_~adapter~0.base))] [2018-02-02 20:36:57,634 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:36:57,634 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:36:57,634 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:36:57,634 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:36:57,634 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 6 states. [2018-02-02 20:36:57,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:57,998 INFO L93 Difference]: Finished difference Result 460 states and 517 transitions. [2018-02-02 20:36:57,998 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:36:57,998 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2018-02-02 20:36:57,998 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:58,000 INFO L225 Difference]: With dead ends: 460 [2018-02-02 20:36:58,000 INFO L226 Difference]: Without dead ends: 460 [2018-02-02 20:36:58,000 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:58,000 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states. [2018-02-02 20:36:58,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 460. [2018-02-02 20:36:58,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-02 20:36:58,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 517 transitions. [2018-02-02 20:36:58,005 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 517 transitions. Word has length 59 [2018-02-02 20:36:58,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:58,006 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 517 transitions. [2018-02-02 20:36:58,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:36:58,006 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 517 transitions. [2018-02-02 20:36:58,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 20:36:58,006 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:58,006 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:58,006 INFO L371 AbstractCegarLoop]: === Iteration 49 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:58,007 INFO L82 PathProgramCache]: Analyzing trace with hash 707940712, now seen corresponding path program 1 times [2018-02-02 20:36:58,007 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:58,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:58,016 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:58,128 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-02-02 20:36:58,128 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:36:58,129 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:36:58,129 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:58,129 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 20:36:58,129 INFO L182 omatonBuilderFactory]: Interpolants [49030#true, 49031#false, 49032#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 49033#(and (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 49034#(and (= 0 |ldv_malloc_#res.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 49035#(and (<= 4 (select |#length| |entry_point_#t~ret66.base|)) (= 0 |entry_point_#t~ret66.offset|)), 49036#(and (<= 4 (select |#length| entry_point_~adapter~0.base)) (= 0 entry_point_~adapter~0.offset))] [2018-02-02 20:36:58,129 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-02-02 20:36:58,129 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:36:58,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:36:58,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:36:58,130 INFO L87 Difference]: Start difference. First operand 460 states and 517 transitions. Second operand 7 states. [2018-02-02 20:36:58,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:36:58,471 INFO L93 Difference]: Finished difference Result 459 states and 516 transitions. [2018-02-02 20:36:58,471 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:36:58,471 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 59 [2018-02-02 20:36:58,472 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:36:58,472 INFO L225 Difference]: With dead ends: 459 [2018-02-02 20:36:58,472 INFO L226 Difference]: Without dead ends: 459 [2018-02-02 20:36:58,473 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-02 20:36:58,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459 states. [2018-02-02 20:36:58,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459 to 459. [2018-02-02 20:36:58,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-02 20:36:58,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 516 transitions. [2018-02-02 20:36:58,476 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 516 transitions. Word has length 59 [2018-02-02 20:36:58,476 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:36:58,476 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 516 transitions. [2018-02-02 20:36:58,476 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:36:58,476 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 516 transitions. [2018-02-02 20:36:58,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-02 20:36:58,476 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:36:58,477 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:36:58,477 INFO L371 AbstractCegarLoop]: === Iteration 50 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:36:58,477 INFO L82 PathProgramCache]: Analyzing trace with hash -1864226419, now seen corresponding path program 1 times [2018-02-02 20:36:58,477 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:36:58,483 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:36:58,483 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:36:58,903 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 11 proven. 30 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-02-02 20:36:58,903 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:36:58,903 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-02 20:36:58,903 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:36:58,904 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 4 proven. 10 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-02 20:36:58,904 INFO L182 omatonBuilderFactory]: Interpolants [49959#true, 49960#false, 49961#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 49962#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 49963#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 49964#(= 1 (select |#valid| entry_point_~client~0.base)), 49965#(= |#valid| |old(#valid)|), 49966#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 49967#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 49968#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 49969#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 49970#(and (= (select |#valid| entry_point_~client~0.base) 1) (<= 0 entry_point_~client~0.offset) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49971#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (<= 0 entry_point_~client~0.offset) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49972#(and (not (= entry_point_~fe~2.base 0)) (<= 0 entry_point_~client~0.offset) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49973#(and (or (< 0 (+ (div ldv_malloc_~size 4294967296) 1)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 49974#(or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (or (<= (select |#length| |ldv_malloc_#t~malloc4.base|) |ldv_malloc_#in~size|) (<= 2147483648 |ldv_malloc_#in~size|)) (not (= |ldv_malloc_#t~malloc4.base| 0)))), 49975#(or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (or (<= (select |#length| |ldv_malloc_#res.base|) |ldv_malloc_#in~size|) (<= 2147483648 |ldv_malloc_#in~size|)) (not (= |ldv_malloc_#res.base| 0)))), 49976#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (or (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (<= (select |#length| entry_point_~client~0.base) (+ entry_point_~client~0.offset 19)))), 49977#(and (or (and (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= 0 entry_point_~fe~2.base))) (= entry_point_~client~0.base entry_point_~addr~0.base)) (or (<= (select |#length| entry_point_~client~0.base) (+ entry_point_~client~0.offset 19)) (not (= entry_point_~client~0.base entry_point_~addr~0.base))) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49978#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~cfg~2.base))), 49979#(and (= 1 (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49980#(and (= 1 (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base)))] [2018-02-02 20:36:58,904 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 11 proven. 30 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-02-02 20:36:58,904 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-02 20:36:58,904 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-02 20:36:58,904 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=58, Invalid=404, Unknown=0, NotChecked=0, Total=462 [2018-02-02 20:36:58,905 INFO L87 Difference]: Start difference. First operand 459 states and 516 transitions. Second operand 22 states. [2018-02-02 20:37:00,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:00,067 INFO L93 Difference]: Finished difference Result 518 states and 587 transitions. [2018-02-02 20:37:00,067 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 20:37:00,068 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 59 [2018-02-02 20:37:00,068 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:00,069 INFO L225 Difference]: With dead ends: 518 [2018-02-02 20:37:00,069 INFO L226 Difference]: Without dead ends: 518 [2018-02-02 20:37:00,069 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 4 SyntacticMatches, 6 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=110, Invalid=702, Unknown=0, NotChecked=0, Total=812 [2018-02-02 20:37:00,069 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states. [2018-02-02 20:37:00,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 459. [2018-02-02 20:37:00,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-02 20:37:00,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 515 transitions. [2018-02-02 20:37:00,072 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 515 transitions. Word has length 59 [2018-02-02 20:37:00,072 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:00,072 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 515 transitions. [2018-02-02 20:37:00,073 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-02 20:37:00,073 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 515 transitions. [2018-02-02 20:37:00,073 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-02-02 20:37:00,073 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:00,073 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:00,073 INFO L371 AbstractCegarLoop]: === Iteration 51 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:00,073 INFO L82 PathProgramCache]: Analyzing trace with hash 1053346727, now seen corresponding path program 1 times [2018-02-02 20:37:00,074 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:00,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:00,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:00,590 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-02 20:37:00,590 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:00,590 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 20:37:00,590 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:00,590 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-02 20:37:00,590 INFO L182 omatonBuilderFactory]: Interpolants [50976#(= |#valid| |old(#valid)|), 50977#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 50978#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 50979#(and (not (= |entry_point_#t~ret59.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 50980#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= entry_point_~client~0.base 0))), 50981#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |entry_point_#t~ret60.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 50982#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50983#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= 0 entry_point_~cfg~2.base)) (or (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|) (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (not (= entry_point_~client~0.base 0))), 50984#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (= entry_point_~fe~2.base entry_point_~cfg~2.base) (and (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (not (= entry_point_~fe~2.base 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50985#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret64.base| 0)) (or (= entry_point_~fe~2.base |entry_point_#t~ret64.base|) (and (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50986#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (or (= entry_point_~addr~0.base entry_point_~fe~2.base) (= entry_point_~fe~2.base entry_point_~cfg~2.base) (and (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50987#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (and (not (= entry_point_~cfg~2.base |~#ldv_global_msg_list.base|)) (= 1 (select (store |#valid| entry_point_~fe~2.base 0) |~#ldv_global_msg_list.base|))) (= 0 (select |#valid| entry_point_~fe~2.base)) (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50988#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (= 0 (select |#valid| entry_point_~cfg~2.base)) (= 1 (select (store |#valid| entry_point_~cfg~2.base 0) |~#ldv_global_msg_list.base|))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50973#true, 50974#false, 50975#(= 1 (select |#valid| |~#ldv_global_msg_list.base|))] [2018-02-02 20:37:00,591 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-02 20:37:00,591 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 20:37:00,591 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 20:37:00,591 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=203, Unknown=0, NotChecked=0, Total=240 [2018-02-02 20:37:00,591 INFO L87 Difference]: Start difference. First operand 459 states and 515 transitions. Second operand 16 states. [2018-02-02 20:37:02,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:02,380 INFO L93 Difference]: Finished difference Result 547 states and 603 transitions. [2018-02-02 20:37:02,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 20:37:02,381 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-02-02 20:37:02,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:02,382 INFO L225 Difference]: With dead ends: 547 [2018-02-02 20:37:02,382 INFO L226 Difference]: Without dead ends: 547 [2018-02-02 20:37:02,382 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 12 SyntacticMatches, 8 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=100, Invalid=500, Unknown=0, NotChecked=0, Total=600 [2018-02-02 20:37:02,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-02-02 20:37:02,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 453. [2018-02-02 20:37:02,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 453 states. [2018-02-02 20:37:02,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 507 transitions. [2018-02-02 20:37:02,386 INFO L78 Accepts]: Start accepts. Automaton has 453 states and 507 transitions. Word has length 62 [2018-02-02 20:37:02,387 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:02,387 INFO L432 AbstractCegarLoop]: Abstraction has 453 states and 507 transitions. [2018-02-02 20:37:02,387 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 20:37:02,387 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 507 transitions. [2018-02-02 20:37:02,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-02 20:37:02,387 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:02,388 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:02,388 INFO L371 AbstractCegarLoop]: === Iteration 52 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:02,388 INFO L82 PathProgramCache]: Analyzing trace with hash 1554710616, now seen corresponding path program 1 times [2018-02-02 20:37:02,388 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:02,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:02,400 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:03,356 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 20:37:03,356 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:03,356 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 20:37:03,356 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:03,357 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-02 20:37:03,357 INFO L182 omatonBuilderFactory]: Interpolants [52007#true, 52008#false, 52009#(= |#valid| |old(#valid)|), 52010#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 52011#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 52012#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 52013#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 52014#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 52015#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= (select |#valid| |ldv_malloc_#res.base|) 1) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 52016#(and (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (= (select |#valid| |entry_point_#t~ret60.base|) 1))) (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base 0))), 52017#(and (not (= entry_point_~cfg~2.base 0)) (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |#valid| entry_point_~cfg~2.base) 1))) (not (= entry_point_~client~0.base 0))), 52018#(and (= (select |#valid| entry_point_~client~0.base) 1) (or (and (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |#valid| entry_point_~cfg~2.base) 1)) (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 52019#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (store (store (store |old(#valid)| |entry_point_#t~ret62.base| (select |#valid| |entry_point_#t~ret62.base|)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| |entry_point_#t~ret62.base|) 0) (not (= |entry_point_#t~ret62.base| entry_point_~client~0.base)))) (not (= |entry_point_#t~ret62.base| 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 52020#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= entry_point_~fe~2.base 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 52021#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store |#valid| entry_point_~cfg~2.base 0) (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~cfg~2.base) (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 52022#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0)))] [2018-02-02 20:37:03,357 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 20:37:03,357 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 20:37:03,357 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 20:37:03,357 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-02 20:37:03,357 INFO L87 Difference]: Start difference. First operand 453 states and 507 transitions. Second operand 16 states. [2018-02-02 20:37:05,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:05,176 INFO L93 Difference]: Finished difference Result 517 states and 584 transitions. [2018-02-02 20:37:05,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 20:37:05,177 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-02-02 20:37:05,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:05,178 INFO L225 Difference]: With dead ends: 517 [2018-02-02 20:37:05,178 INFO L226 Difference]: Without dead ends: 508 [2018-02-02 20:37:05,178 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 11 SyntacticMatches, 7 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=60, Invalid=320, Unknown=0, NotChecked=0, Total=380 [2018-02-02 20:37:05,179 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states. [2018-02-02 20:37:05,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 451. [2018-02-02 20:37:05,184 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2018-02-02 20:37:05,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 504 transitions. [2018-02-02 20:37:05,185 INFO L78 Accepts]: Start accepts. Automaton has 451 states and 504 transitions. Word has length 61 [2018-02-02 20:37:05,185 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:05,185 INFO L432 AbstractCegarLoop]: Abstraction has 451 states and 504 transitions. [2018-02-02 20:37:05,185 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 20:37:05,185 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 504 transitions. [2018-02-02 20:37:05,186 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-02 20:37:05,186 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:05,186 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:05,186 INFO L371 AbstractCegarLoop]: === Iteration 53 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:05,186 INFO L82 PathProgramCache]: Analyzing trace with hash 1786414281, now seen corresponding path program 1 times [2018-02-02 20:37:05,186 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:05,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:05,193 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:05,259 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-02 20:37:05,259 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:05,259 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 20:37:05,259 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:05,259 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 20:37:05,259 INFO L182 omatonBuilderFactory]: Interpolants [52999#true, 53000#false, 53001#(= (select |#valid| entry_point_~client~0.base) 1), 53002#(= (select |#valid| |alloc_fix_12_#in~client.base|) 1), 53003#(= (select |#valid| alloc_fix_12_~client.base) 1)] [2018-02-02 20:37:05,259 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-02 20:37:05,260 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:37:05,260 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:37:05,260 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:05,260 INFO L87 Difference]: Start difference. First operand 451 states and 504 transitions. Second operand 5 states. [2018-02-02 20:37:05,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:05,456 INFO L93 Difference]: Finished difference Result 450 states and 503 transitions. [2018-02-02 20:37:05,456 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:37:05,456 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 64 [2018-02-02 20:37:05,457 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:05,458 INFO L225 Difference]: With dead ends: 450 [2018-02-02 20:37:05,458 INFO L226 Difference]: Without dead ends: 450 [2018-02-02 20:37:05,458 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:37:05,459 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-02-02 20:37:05,462 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 450. [2018-02-02 20:37:05,462 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 450 states. [2018-02-02 20:37:05,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 503 transitions. [2018-02-02 20:37:05,463 INFO L78 Accepts]: Start accepts. Automaton has 450 states and 503 transitions. Word has length 64 [2018-02-02 20:37:05,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:05,463 INFO L432 AbstractCegarLoop]: Abstraction has 450 states and 503 transitions. [2018-02-02 20:37:05,463 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:37:05,463 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 503 transitions. [2018-02-02 20:37:05,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-02 20:37:05,464 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:05,464 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:05,464 INFO L371 AbstractCegarLoop]: === Iteration 54 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:05,464 INFO L82 PathProgramCache]: Analyzing trace with hash 1786414282, now seen corresponding path program 1 times [2018-02-02 20:37:05,465 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:05,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:05,473 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:05,556 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:37:05,556 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:05,556 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-02 20:37:05,556 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:05,557 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-02 20:37:05,557 INFO L182 omatonBuilderFactory]: Interpolants [53906#true, 53907#false, 53908#(= 0 |ldv_malloc_#t~malloc4.offset|), 53909#(= 0 |ldv_malloc_#res.offset|), 53910#(= 0 |entry_point_#t~ret59.offset|), 53911#(= 0 entry_point_~client~0.offset), 53912#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 0 entry_point_~client~0.offset) (<= 16 (select |#length| entry_point_~client~0.base))), 53913#(and (<= 16 (select |#length| |alloc_fix_12_#in~client.base|)) (= 0 |alloc_fix_12_#in~client.offset|) (= (select |#valid| |alloc_fix_12_#in~client.base|) 1)), 53914#(and (<= 16 (select |#length| alloc_fix_12_~client.base)) (= (select |#valid| alloc_fix_12_~client.base) 1) (= alloc_fix_12_~client.offset 0)), 53915#(and (<= 16 (select |#length| alloc_fix_12_~client.base)) (= alloc_fix_12_~client.offset 0))] [2018-02-02 20:37:05,557 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:37:05,557 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-02 20:37:05,558 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-02 20:37:05,558 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:37:05,558 INFO L87 Difference]: Start difference. First operand 450 states and 503 transitions. Second operand 10 states. [2018-02-02 20:37:05,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:05,879 INFO L93 Difference]: Finished difference Result 449 states and 502 transitions. [2018-02-02 20:37:05,880 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-02 20:37:05,880 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 64 [2018-02-02 20:37:05,880 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:05,881 INFO L225 Difference]: With dead ends: 449 [2018-02-02 20:37:05,881 INFO L226 Difference]: Without dead ends: 449 [2018-02-02 20:37:05,881 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2018-02-02 20:37:05,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states. [2018-02-02 20:37:05,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2018-02-02 20:37:05,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 20:37:05,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 502 transitions. [2018-02-02 20:37:05,885 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 502 transitions. Word has length 64 [2018-02-02 20:37:05,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:05,885 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 502 transitions. [2018-02-02 20:37:05,885 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-02 20:37:05,885 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 502 transitions. [2018-02-02 20:37:05,886 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-02 20:37:05,886 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:05,886 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:05,886 INFO L371 AbstractCegarLoop]: === Iteration 55 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:05,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1242791254, now seen corresponding path program 1 times [2018-02-02 20:37:05,887 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:05,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:05,900 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:06,167 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 27 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 20:37:06,167 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:06,167 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-02 20:37:06,167 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:06,167 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-02 20:37:06,168 INFO L182 omatonBuilderFactory]: Interpolants [54818#true, 54819#false, 54820#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 54821#(= (select |#valid| |ldv_malloc_#res.base|) 1), 54822#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 54823#(= (select |#valid| entry_point_~client~0.base) 1), 54824#(= |#valid| |old(#valid)|), 54825#(= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)), 54826#(= 0 (select |old(#valid)| |ldv_malloc_#res.base|)), 54827#(not (= entry_point_~client~0.base |entry_point_#t~ret60.base|)), 54828#(not (= entry_point_~client~0.base entry_point_~cfg~2.base)), 54829#(and (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54830#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54831#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 54832#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 54833#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)))), 54834#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 54835#(and (or (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= |entry_point_#t~ret66.base| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|))), 54836#(and (or (= entry_point_~adapter~0.base (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) (= 1 (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)))) (not (= entry_point_~client~0.base entry_point_~adapter~0.base))), 54837#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| |alloc_fix_12_#in~client.base|) |alloc_fix_12_#in~client.offset|))), 54838#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| alloc_fix_12_~client.base) alloc_fix_12_~client.offset))), 54839#(= 1 (select |#valid| |alloc_fix_12_#t~mem46.base|)), 54840#(= 1 (select |#valid| alloc_fix_12_~cfg~0.base))] [2018-02-02 20:37:06,168 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 27 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 20:37:06,168 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-02 20:37:06,168 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-02 20:37:06,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=455, Unknown=0, NotChecked=0, Total=506 [2018-02-02 20:37:06,168 INFO L87 Difference]: Start difference. First operand 449 states and 502 transitions. Second operand 23 states. [2018-02-02 20:37:07,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:07,840 INFO L93 Difference]: Finished difference Result 549 states and 629 transitions. [2018-02-02 20:37:07,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 20:37:07,840 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 66 [2018-02-02 20:37:07,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:07,841 INFO L225 Difference]: With dead ends: 549 [2018-02-02 20:37:07,841 INFO L226 Difference]: Without dead ends: 549 [2018-02-02 20:37:07,841 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 7 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 229 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=163, Invalid=1397, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 20:37:07,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states. [2018-02-02 20:37:07,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 447. [2018-02-02 20:37:07,844 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 447 states. [2018-02-02 20:37:07,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 447 states to 447 states and 500 transitions. [2018-02-02 20:37:07,845 INFO L78 Accepts]: Start accepts. Automaton has 447 states and 500 transitions. Word has length 66 [2018-02-02 20:37:07,845 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:07,845 INFO L432 AbstractCegarLoop]: Abstraction has 447 states and 500 transitions. [2018-02-02 20:37:07,845 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-02 20:37:07,845 INFO L276 IsEmpty]: Start isEmpty. Operand 447 states and 500 transitions. [2018-02-02 20:37:07,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-02 20:37:07,845 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:07,846 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:07,846 INFO L371 AbstractCegarLoop]: === Iteration 56 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:07,846 INFO L82 PathProgramCache]: Analyzing trace with hash -1242791253, now seen corresponding path program 1 times [2018-02-02 20:37:07,847 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:07,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:07,864 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:08,517 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 29 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 20:37:08,517 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:08,518 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-02-02 20:37:08,518 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:08,518 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-02 20:37:08,519 INFO L182 omatonBuilderFactory]: Interpolants [55872#false, 55873#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 55874#(= (select |#valid| |ldv_malloc_#res.base|) 1), 55875#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 55876#(= (select |#valid| entry_point_~client~0.base) 1), 55877#(= |#valid| |old(#valid)|), 55878#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|)), 55879#(and (= 0 |ldv_malloc_#res.offset|) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|))), 55880#(and (= 0 |entry_point_#t~ret60.offset|) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|))), 55881#(and (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= 0 entry_point_~cfg~2.offset)), 55882#(and (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (= entry_point_~cfg~2.offset 0) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 55883#(and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset))), 55884#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 55885#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 55886#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 55887#(and (= (select |#valid| entry_point_~client~0.base) 1) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset))), 55888#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 55889#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 55890#(and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|))), 55891#(and (<= 4 (select |#length| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset))) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (= 0 (select (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.offset) entry_point_~client~0.offset)) (= (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) 1)), 55892#(and (= 0 (select (select |#memory_$Pointer$.offset| |alloc_fix_12_#in~client.base|) |alloc_fix_12_#in~client.offset|)) (= (select |#valid| (select (select |#memory_$Pointer$.base| |alloc_fix_12_#in~client.base|) |alloc_fix_12_#in~client.offset|)) 1) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| |alloc_fix_12_#in~client.base|) |alloc_fix_12_#in~client.offset|)))), 55893#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_fix_12_~client.base) alloc_fix_12_~client.offset)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| alloc_fix_12_~client.base) alloc_fix_12_~client.offset))) (= (select |#valid| (select (select |#memory_$Pointer$.base| alloc_fix_12_~client.base) alloc_fix_12_~client.offset)) 1)), 55894#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_fix_12_~client.base) alloc_fix_12_~client.offset)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| alloc_fix_12_~client.base) alloc_fix_12_~client.offset)))), 55895#(and (<= 4 (select |#length| |alloc_fix_12_#t~mem46.base|)) (= 0 |alloc_fix_12_#t~mem46.offset|)), 55896#(and (<= 4 (select |#length| alloc_fix_12_~cfg~0.base)) (= alloc_fix_12_~cfg~0.offset 0)), 55871#true] [2018-02-02 20:37:08,519 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 29 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-02 20:37:08,519 INFO L409 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-02-02 20:37:08,519 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-02-02 20:37:08,519 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=589, Unknown=0, NotChecked=0, Total=650 [2018-02-02 20:37:08,520 INFO L87 Difference]: Start difference. First operand 447 states and 500 transitions. Second operand 26 states. [2018-02-02 20:37:11,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:11,144 INFO L93 Difference]: Finished difference Result 557 states and 637 transitions. [2018-02-02 20:37:11,144 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-02 20:37:11,144 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 66 [2018-02-02 20:37:11,145 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:11,146 INFO L225 Difference]: With dead ends: 557 [2018-02-02 20:37:11,146 INFO L226 Difference]: Without dead ends: 557 [2018-02-02 20:37:11,146 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 305 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=189, Invalid=1703, Unknown=0, NotChecked=0, Total=1892 [2018-02-02 20:37:11,147 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-02-02 20:37:11,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 449. [2018-02-02 20:37:11,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 20:37:11,152 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 506 transitions. [2018-02-02 20:37:11,152 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 506 transitions. Word has length 66 [2018-02-02 20:37:11,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:11,152 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 506 transitions. [2018-02-02 20:37:11,152 INFO L433 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-02-02 20:37:11,152 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 506 transitions. [2018-02-02 20:37:11,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-02-02 20:37:11,153 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:11,153 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:11,153 INFO L371 AbstractCegarLoop]: === Iteration 57 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:11,153 INFO L82 PathProgramCache]: Analyzing trace with hash 466840967, now seen corresponding path program 1 times [2018-02-02 20:37:11,154 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:11,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:11,172 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:14,760 WARN L146 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 71 DAG size of output 38 [2018-02-02 20:37:15,666 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-02 20:37:15,666 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:15,666 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-02 20:37:15,666 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:15,667 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 20:37:15,667 INFO L182 omatonBuilderFactory]: Interpolants [56939#true, 56940#false, 56941#(= |#valid| |old(#valid)|), 56942#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 56943#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56944#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56945#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56946#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 56947#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= 1 (select |#valid| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56948#(and (not (= |entry_point_#t~ret60.base| 0)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= 1 (select |#valid| |entry_point_#t~ret60.base|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))))) (not (= entry_point_~client~0.base 0))), 56949#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= entry_point_~cfg~2.base (@diff |old(#valid)| |#valid|))) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= 1 (select |#valid| entry_point_~cfg~2.base)) (or (= entry_point_~client~0.base (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)) (= entry_point_~cfg~2.base (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))))) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base 0))), 56950#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= 1 (select |#valid| entry_point_~cfg~2.base)))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56951#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (store (store (store |old(#valid)| |entry_point_#t~ret62.base| (select |#valid| |entry_point_#t~ret62.base|)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| |entry_point_#t~ret62.base|) 0) (not (= |entry_point_#t~ret62.base| entry_point_~client~0.base)))) (not (= |entry_point_#t~ret62.base| 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56952#(and (not (= entry_point_~fe~2.base 0)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56953#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56954#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= |entry_point_#t~ret64.base| entry_point_~cfg~2.base)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (or (= entry_point_~fe~2.base |entry_point_#t~ret64.base|) (and (= (select |old(#valid)| |entry_point_#t~ret64.base|) 0) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |old(#valid)| entry_point_~fe~2.base) 0) (= |#valid| (store (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |entry_point_#t~ret64.base| (select |#valid| |entry_point_#t~ret64.base|))))))) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56955#(and (not (= entry_point_~addr~0.base 0)) (or (and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= |#valid| (store (store (store (store |old(#valid)| entry_point_~addr~0.base (select |#valid| entry_point_~addr~0.base)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~addr~0.base) 0) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0) (not (= entry_point_~addr~0.base entry_point_~client~0.base)))) (not (= entry_point_~addr~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))) (= entry_point_~addr~0.base entry_point_~fe~2.base)) (not (= 0 entry_point_~fe~2.base))), 56956#(and (or (= 0 (select |#valid| entry_point_~fe~2.base)) (and (or (and (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~cfg~2.base)) entry_point_~fe~2.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~fe~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~fe~2.base 0)) (= (select |old(#valid)| entry_point_~fe~2.base) (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0)) (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))) (not (= 0 entry_point_~fe~2.base))), 56957#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= (store |#valid| entry_point_~cfg~2.base 0) (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~cfg~2.base) (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56958#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 56959#(and (= |#valid| |old(#valid)|) (= (select |#valid| |~#ldv_global_msg_list.base|) 1))] [2018-02-02 20:37:15,667 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-02 20:37:15,667 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-02 20:37:15,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-02 20:37:15,667 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2018-02-02 20:37:15,668 INFO L87 Difference]: Start difference. First operand 449 states and 506 transitions. Second operand 21 states. [2018-02-02 20:37:18,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:18,371 INFO L93 Difference]: Finished difference Result 526 states and 588 transitions. [2018-02-02 20:37:18,371 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-02 20:37:18,371 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2018-02-02 20:37:18,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:18,372 INFO L225 Difference]: With dead ends: 526 [2018-02-02 20:37:18,373 INFO L226 Difference]: Without dead ends: 507 [2018-02-02 20:37:18,373 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 13 SyntacticMatches, 7 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=97, Invalid=605, Unknown=0, NotChecked=0, Total=702 [2018-02-02 20:37:18,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states. [2018-02-02 20:37:18,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 437. [2018-02-02 20:37:18,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-02-02 20:37:18,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 493 transitions. [2018-02-02 20:37:18,376 INFO L78 Accepts]: Start accepts. Automaton has 437 states and 493 transitions. Word has length 72 [2018-02-02 20:37:18,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:18,376 INFO L432 AbstractCegarLoop]: Abstraction has 437 states and 493 transitions. [2018-02-02 20:37:18,376 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-02 20:37:18,376 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 493 transitions. [2018-02-02 20:37:18,377 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-02 20:37:18,377 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:18,377 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:18,377 INFO L371 AbstractCegarLoop]: === Iteration 58 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:18,377 INFO L82 PathProgramCache]: Analyzing trace with hash -1786339464, now seen corresponding path program 1 times [2018-02-02 20:37:18,378 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:18,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:18,386 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:18,441 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-02 20:37:18,441 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:18,442 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 20:37:18,442 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:18,442 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-02-02 20:37:18,442 INFO L182 omatonBuilderFactory]: Interpolants [57936#false, 57937#(= 0 |ldv_malloc_#res.offset|), 57938#(= 0 |alloc_fix_12_#t~ret48.offset|), 57939#(= alloc_fix_12_~priv~0.offset 0), 57935#true] [2018-02-02 20:37:18,442 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-02 20:37:18,442 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:37:18,442 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:37:18,442 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:18,442 INFO L87 Difference]: Start difference. First operand 437 states and 493 transitions. Second operand 5 states. [2018-02-02 20:37:18,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:18,464 INFO L93 Difference]: Finished difference Result 466 states and 526 transitions. [2018-02-02 20:37:18,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:37:18,464 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 75 [2018-02-02 20:37:18,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:18,465 INFO L225 Difference]: With dead ends: 466 [2018-02-02 20:37:18,465 INFO L226 Difference]: Without dead ends: 466 [2018-02-02 20:37:18,465 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:18,466 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2018-02-02 20:37:18,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 449. [2018-02-02 20:37:18,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 20:37:18,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 515 transitions. [2018-02-02 20:37:18,470 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 515 transitions. Word has length 75 [2018-02-02 20:37:18,470 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:18,470 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 515 transitions. [2018-02-02 20:37:18,470 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:37:18,470 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 515 transitions. [2018-02-02 20:37:18,470 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-02 20:37:18,470 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:18,470 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:18,470 INFO L371 AbstractCegarLoop]: === Iteration 59 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:18,471 INFO L82 PathProgramCache]: Analyzing trace with hash -1786339463, now seen corresponding path program 1 times [2018-02-02 20:37:18,471 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:18,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:18,477 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:18,516 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-02 20:37:18,517 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:18,517 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 20:37:18,517 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:18,518 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-02-02 20:37:18,518 INFO L182 omatonBuilderFactory]: Interpolants [58855#true, 58856#false, 58857#(= 0 |ldv_malloc_#res.base|), 58858#(= 0 |alloc_fix_12_#t~ret48.base|), 58859#(= 0 alloc_fix_12_~priv~0.base)] [2018-02-02 20:37:18,518 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-02 20:37:18,518 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:37:18,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:37:18,519 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:18,519 INFO L87 Difference]: Start difference. First operand 449 states and 515 transitions. Second operand 5 states. [2018-02-02 20:37:18,542 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:18,542 INFO L93 Difference]: Finished difference Result 468 states and 528 transitions. [2018-02-02 20:37:18,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:37:18,542 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 75 [2018-02-02 20:37:18,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:18,543 INFO L225 Difference]: With dead ends: 468 [2018-02-02 20:37:18,543 INFO L226 Difference]: Without dead ends: 468 [2018-02-02 20:37:18,543 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:18,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states. [2018-02-02 20:37:18,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 449. [2018-02-02 20:37:18,547 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 20:37:18,547 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 514 transitions. [2018-02-02 20:37:18,547 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 514 transitions. Word has length 75 [2018-02-02 20:37:18,547 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:18,548 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 514 transitions. [2018-02-02 20:37:18,548 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:37:18,548 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 514 transitions. [2018-02-02 20:37:18,548 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-02 20:37:18,548 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:18,548 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:18,548 INFO L371 AbstractCegarLoop]: === Iteration 60 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:18,548 INFO L82 PathProgramCache]: Analyzing trace with hash -1786339448, now seen corresponding path program 1 times [2018-02-02 20:37:18,549 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:18,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:18,556 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:18,579 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-02 20:37:18,580 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:18,580 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:37:18,580 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:18,580 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-02-02 20:37:18,580 INFO L182 omatonBuilderFactory]: Interpolants [59777#true, 59778#false, 59779#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 59780#(and (= 0 |alloc_fix_12_#t~ret48.offset|) (= 0 |alloc_fix_12_#t~ret48.base|)), 59781#(and (= 0 alloc_fix_12_~priv~0.base) (= alloc_fix_12_~priv~0.offset 0))] [2018-02-02 20:37:18,580 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-02 20:37:18,581 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:37:18,581 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:37:18,581 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:18,581 INFO L87 Difference]: Start difference. First operand 449 states and 514 transitions. Second operand 5 states. [2018-02-02 20:37:18,594 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:18,594 INFO L93 Difference]: Finished difference Result 442 states and 494 transitions. [2018-02-02 20:37:18,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:37:18,594 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 75 [2018-02-02 20:37:18,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:18,595 INFO L225 Difference]: With dead ends: 442 [2018-02-02 20:37:18,595 INFO L226 Difference]: Without dead ends: 442 [2018-02-02 20:37:18,595 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:18,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2018-02-02 20:37:18,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 437. [2018-02-02 20:37:18,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-02-02 20:37:18,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 489 transitions. [2018-02-02 20:37:18,599 INFO L78 Accepts]: Start accepts. Automaton has 437 states and 489 transitions. Word has length 75 [2018-02-02 20:37:18,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:18,599 INFO L432 AbstractCegarLoop]: Abstraction has 437 states and 489 transitions. [2018-02-02 20:37:18,599 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:37:18,599 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 489 transitions. [2018-02-02 20:37:18,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-02-02 20:37:18,599 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:18,600 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:18,600 INFO L371 AbstractCegarLoop]: === Iteration 61 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:18,600 INFO L82 PathProgramCache]: Analyzing trace with hash 1177435946, now seen corresponding path program 1 times [2018-02-02 20:37:18,600 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:18,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:18,606 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:18,645 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-02 20:37:18,646 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:18,646 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:37:18,646 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:18,646 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-02-02 20:37:18,646 INFO L182 omatonBuilderFactory]: Interpolants [60661#true, 60662#false, 60663#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 60664#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 60665#(= 1 (select |#valid| |alloc_fix_12_#t~ret48.base|)), 60666#(= 1 (select |#valid| alloc_fix_12_~priv~0.base))] [2018-02-02 20:37:18,646 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-02 20:37:18,647 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:37:18,647 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:37:18,647 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:37:18,647 INFO L87 Difference]: Start difference. First operand 437 states and 489 transitions. Second operand 6 states. [2018-02-02 20:37:18,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:18,895 INFO L93 Difference]: Finished difference Result 436 states and 488 transitions. [2018-02-02 20:37:18,895 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:37:18,895 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 77 [2018-02-02 20:37:18,895 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:18,896 INFO L225 Difference]: With dead ends: 436 [2018-02-02 20:37:18,896 INFO L226 Difference]: Without dead ends: 436 [2018-02-02 20:37:18,896 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:37:18,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 436 states. [2018-02-02 20:37:18,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 436 to 435. [2018-02-02 20:37:18,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 435 states. [2018-02-02 20:37:18,900 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 487 transitions. [2018-02-02 20:37:18,900 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 487 transitions. Word has length 77 [2018-02-02 20:37:18,901 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:18,901 INFO L432 AbstractCegarLoop]: Abstraction has 435 states and 487 transitions. [2018-02-02 20:37:18,901 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:37:18,901 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 487 transitions. [2018-02-02 20:37:18,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-02-02 20:37:18,901 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:18,902 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:18,902 INFO L371 AbstractCegarLoop]: === Iteration 62 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:18,902 INFO L82 PathProgramCache]: Analyzing trace with hash 1177435948, now seen corresponding path program 1 times [2018-02-02 20:37:18,902 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:18,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:18,915 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:18,999 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-02-02 20:37:19,000 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:19,000 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:37:19,000 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:19,001 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 20:37:19,001 INFO L182 omatonBuilderFactory]: Interpolants [61540#true, 61541#false, 61542#(or (= ldv_malloc_~size 8) (= |ldv_malloc_#in~size| ldv_malloc_~size)), 61543#(or (and (<= 8 (select |#length| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|)) (not (= |ldv_malloc_#in~size| 8))), 61544#(or (and (<= 8 (select |#length| |ldv_malloc_#res.base|)) (= 0 |ldv_malloc_#res.offset|)) (not (= |ldv_malloc_#in~size| 8))), 61545#(and (<= 8 (select |#length| |alloc_fix_12_#t~ret48.base|)) (= 0 |alloc_fix_12_#t~ret48.offset|)), 61546#(and (= alloc_fix_12_~priv~0.offset 0) (<= 8 (select |#length| alloc_fix_12_~priv~0.base)))] [2018-02-02 20:37:19,001 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-02-02 20:37:19,001 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:37:19,002 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:37:19,002 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:37:19,002 INFO L87 Difference]: Start difference. First operand 435 states and 487 transitions. Second operand 7 states. [2018-02-02 20:37:19,299 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:19,300 INFO L93 Difference]: Finished difference Result 445 states and 497 transitions. [2018-02-02 20:37:19,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-02 20:37:19,300 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 77 [2018-02-02 20:37:19,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:19,301 INFO L225 Difference]: With dead ends: 445 [2018-02-02 20:37:19,301 INFO L226 Difference]: Without dead ends: 445 [2018-02-02 20:37:19,301 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:37:19,301 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states. [2018-02-02 20:37:19,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 437. [2018-02-02 20:37:19,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-02-02 20:37:19,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 489 transitions. [2018-02-02 20:37:19,305 INFO L78 Accepts]: Start accepts. Automaton has 437 states and 489 transitions. Word has length 77 [2018-02-02 20:37:19,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:19,305 INFO L432 AbstractCegarLoop]: Abstraction has 437 states and 489 transitions. [2018-02-02 20:37:19,305 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:37:19,305 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 489 transitions. [2018-02-02 20:37:19,305 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-02-02 20:37:19,305 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:19,305 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:19,306 INFO L371 AbstractCegarLoop]: === Iteration 63 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:19,306 INFO L82 PathProgramCache]: Analyzing trace with hash 1177435949, now seen corresponding path program 1 times [2018-02-02 20:37:19,306 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:19,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:19,316 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:19,423 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-02 20:37:19,424 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:19,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-02 20:37:19,424 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:19,425 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 20:37:19,425 INFO L182 omatonBuilderFactory]: Interpolants [62437#true, 62438#false, 62439#(= (select |#valid| entry_point_~client~0.base) 1), 62440#(and (< 0 (+ alloc_fix_12_~cfg~0.offset 1)) (not (= (select |#valid| alloc_fix_12_~cfg~0.base) 0)) (<= (+ alloc_fix_12_~cfg~0.offset 4) (select |#length| alloc_fix_12_~cfg~0.base))), 62441#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 62442#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 62443#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 62444#(and (< 0 (+ alloc_fix_12_~cfg~0.offset 1)) (<= (+ alloc_fix_12_~cfg~0.offset 4) (select |#length| alloc_fix_12_~cfg~0.base)))] [2018-02-02 20:37:19,425 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-02 20:37:19,425 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-02 20:37:19,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-02 20:37:19,426 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-02 20:37:19,426 INFO L87 Difference]: Start difference. First operand 437 states and 489 transitions. Second operand 8 states. [2018-02-02 20:37:20,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:20,161 INFO L93 Difference]: Finished difference Result 541 states and 617 transitions. [2018-02-02 20:37:20,161 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 20:37:20,161 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 77 [2018-02-02 20:37:20,161 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:20,162 INFO L225 Difference]: With dead ends: 541 [2018-02-02 20:37:20,162 INFO L226 Difference]: Without dead ends: 541 [2018-02-02 20:37:20,162 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2018-02-02 20:37:20,163 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-02-02 20:37:20,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 436. [2018-02-02 20:37:20,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-02-02 20:37:20,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 488 transitions. [2018-02-02 20:37:20,166 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 488 transitions. Word has length 77 [2018-02-02 20:37:20,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:20,166 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 488 transitions. [2018-02-02 20:37:20,166 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-02 20:37:20,166 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 488 transitions. [2018-02-02 20:37:20,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-02 20:37:20,166 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:20,166 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:20,166 INFO L371 AbstractCegarLoop]: === Iteration 64 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:20,167 INFO L82 PathProgramCache]: Analyzing trace with hash -1017359662, now seen corresponding path program 1 times [2018-02-02 20:37:20,167 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:20,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:20,173 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:20,209 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 12 proven. 2 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-02-02 20:37:20,209 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:20,209 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:37:20,209 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:20,210 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 20:37:20,210 INFO L182 omatonBuilderFactory]: Interpolants [63426#true, 63427#false, 63428#(= 0 |ldv_malloc_#t~malloc4.offset|), 63429#(= 0 |ldv_malloc_#res.offset|), 63430#(= 0 |entry_point_#t~ret66.offset|), 63431#(= 0 entry_point_~adapter~0.offset)] [2018-02-02 20:37:20,210 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 12 proven. 2 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-02-02 20:37:20,210 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:37:20,210 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:37:20,211 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:37:20,211 INFO L87 Difference]: Start difference. First operand 436 states and 488 transitions. Second operand 6 states. [2018-02-02 20:37:20,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:20,229 INFO L93 Difference]: Finished difference Result 435 states and 487 transitions. [2018-02-02 20:37:20,229 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:37:20,229 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 83 [2018-02-02 20:37:20,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:20,230 INFO L225 Difference]: With dead ends: 435 [2018-02-02 20:37:20,230 INFO L226 Difference]: Without dead ends: 435 [2018-02-02 20:37:20,231 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:37:20,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 435 states. [2018-02-02 20:37:20,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 435 to 435. [2018-02-02 20:37:20,235 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 435 states. [2018-02-02 20:37:20,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 487 transitions. [2018-02-02 20:37:20,236 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 487 transitions. Word has length 83 [2018-02-02 20:37:20,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:20,236 INFO L432 AbstractCegarLoop]: Abstraction has 435 states and 487 transitions. [2018-02-02 20:37:20,236 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:37:20,236 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 487 transitions. [2018-02-02 20:37:20,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-02 20:37:20,237 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:20,237 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:20,237 INFO L371 AbstractCegarLoop]: === Iteration 65 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:20,237 INFO L82 PathProgramCache]: Analyzing trace with hash -1017359661, now seen corresponding path program 1 times [2018-02-02 20:37:20,238 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:20,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:20,248 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:20,338 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 30 proven. 2 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:37:20,338 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:20,338 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-02 20:37:20,339 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:20,339 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-02 20:37:20,339 INFO L182 omatonBuilderFactory]: Interpolants [64304#true, 64305#false, 64306#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 64307#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 64308#(= 1 (select |#valid| |entry_point_#t~ret66.base|)), 64309#(= 1 (select |#valid| entry_point_~adapter~0.base)), 64310#(= |#valid| |old(#valid)|), 64311#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 64312#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 64313#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|))) (= 0 |alloc_fix_12_#t~ret48.base|)), 64314#(and (= 0 alloc_fix_12_~priv~0.base) (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|))))] [2018-02-02 20:37:20,339 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 30 proven. 2 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-02 20:37:20,340 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-02 20:37:20,340 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-02 20:37:20,340 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:37:20,340 INFO L87 Difference]: Start difference. First operand 435 states and 487 transitions. Second operand 11 states. [2018-02-02 20:37:20,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:20,935 INFO L93 Difference]: Finished difference Result 502 states and 570 transitions. [2018-02-02 20:37:20,935 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-02 20:37:20,935 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 83 [2018-02-02 20:37:20,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:20,936 INFO L225 Difference]: With dead ends: 502 [2018-02-02 20:37:20,936 INFO L226 Difference]: Without dead ends: 502 [2018-02-02 20:37:20,936 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-02 20:37:20,937 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states. [2018-02-02 20:37:20,939 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 447. [2018-02-02 20:37:20,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 447 states. [2018-02-02 20:37:20,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 447 states to 447 states and 502 transitions. [2018-02-02 20:37:20,939 INFO L78 Accepts]: Start accepts. Automaton has 447 states and 502 transitions. Word has length 83 [2018-02-02 20:37:20,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:20,940 INFO L432 AbstractCegarLoop]: Abstraction has 447 states and 502 transitions. [2018-02-02 20:37:20,940 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-02 20:37:20,940 INFO L276 IsEmpty]: Start isEmpty. Operand 447 states and 502 transitions. [2018-02-02 20:37:20,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-02 20:37:20,940 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:20,940 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:20,940 INFO L371 AbstractCegarLoop]: === Iteration 66 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:20,940 INFO L82 PathProgramCache]: Analyzing trace with hash 1570043961, now seen corresponding path program 1 times [2018-02-02 20:37:20,941 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:20,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:20,947 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:20,971 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-02-02 20:37:20,972 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:20,972 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-02 20:37:20,972 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:20,972 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-02 20:37:20,972 INFO L182 omatonBuilderFactory]: Interpolants [65268#true, 65269#false, 65270#(<= 3 alloc_fix_12_~ret~2), 65271#(<= 3 |alloc_fix_12_#res|), 65272#(<= 3 |entry_point_#t~ret69|)] [2018-02-02 20:37:20,972 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-02-02 20:37:20,972 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:37:20,972 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:37:20,972 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:20,972 INFO L87 Difference]: Start difference. First operand 447 states and 502 transitions. Second operand 5 states. [2018-02-02 20:37:20,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:20,987 INFO L93 Difference]: Finished difference Result 453 states and 505 transitions. [2018-02-02 20:37:20,987 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-02 20:37:20,987 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 85 [2018-02-02 20:37:20,987 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:20,988 INFO L225 Difference]: With dead ends: 453 [2018-02-02 20:37:20,988 INFO L226 Difference]: Without dead ends: 453 [2018-02-02 20:37:20,988 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:37:20,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453 states. [2018-02-02 20:37:20,991 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453 to 451. [2018-02-02 20:37:20,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2018-02-02 20:37:20,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 503 transitions. [2018-02-02 20:37:20,993 INFO L78 Accepts]: Start accepts. Automaton has 451 states and 503 transitions. Word has length 85 [2018-02-02 20:37:20,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:20,993 INFO L432 AbstractCegarLoop]: Abstraction has 451 states and 503 transitions. [2018-02-02 20:37:20,993 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:37:20,993 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 503 transitions. [2018-02-02 20:37:20,994 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-02-02 20:37:20,994 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:20,994 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:20,994 INFO L371 AbstractCegarLoop]: === Iteration 67 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:20,994 INFO L82 PathProgramCache]: Analyzing trace with hash -1473378144, now seen corresponding path program 1 times [2018-02-02 20:37:20,995 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:21,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:21,008 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:21,182 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 7 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2018-02-02 20:37:21,182 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:21,182 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-02 20:37:21,183 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:21,183 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-02 20:37:21,183 INFO L182 omatonBuilderFactory]: Interpolants [66179#true, 66181#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 66180#false, 66183#(= (select |#valid| |entry_point_#t~ret64.base|) 1), 66182#(= (select |#valid| |ldv_malloc_#res.base|) 1), 66185#(= |#valid| |old(#valid)|), 66184#(= (select |#valid| entry_point_~addr~0.base) 1), 66187#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 66186#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 66189#(and (= (select |#valid| entry_point_~addr~0.base) 1) (not (= entry_point_~adapter~0.base entry_point_~addr~0.base)) (not (= entry_point_~adapter~0.base 0))), 66188#(and (not (= entry_point_~addr~0.base |entry_point_#t~ret66.base|)) (= (select |#valid| entry_point_~addr~0.base) 1) (not (= |entry_point_#t~ret66.base| 0))), 66191#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 66190#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 66193#(and (= 0 alloc_fix_12_~priv~0.base) (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 66192#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|))) (= 0 |alloc_fix_12_#t~ret48.base|)), 66194#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 20:37:21,183 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 7 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2018-02-02 20:37:21,183 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-02 20:37:21,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-02 20:37:21,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=199, Unknown=0, NotChecked=0, Total=240 [2018-02-02 20:37:21,184 INFO L87 Difference]: Start difference. First operand 451 states and 503 transitions. Second operand 16 states. [2018-02-02 20:37:22,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:22,177 INFO L93 Difference]: Finished difference Result 537 states and 613 transitions. [2018-02-02 20:37:22,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-02 20:37:22,177 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 84 [2018-02-02 20:37:22,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:22,178 INFO L225 Difference]: With dead ends: 537 [2018-02-02 20:37:22,178 INFO L226 Difference]: Without dead ends: 537 [2018-02-02 20:37:22,178 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 4 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 36 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2018-02-02 20:37:22,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 537 states. [2018-02-02 20:37:22,180 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 537 to 452. [2018-02-02 20:37:22,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 452 states. [2018-02-02 20:37:22,181 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 452 states to 452 states and 504 transitions. [2018-02-02 20:37:22,181 INFO L78 Accepts]: Start accepts. Automaton has 452 states and 504 transitions. Word has length 84 [2018-02-02 20:37:22,181 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:22,181 INFO L432 AbstractCegarLoop]: Abstraction has 452 states and 504 transitions. [2018-02-02 20:37:22,181 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-02 20:37:22,181 INFO L276 IsEmpty]: Start isEmpty. Operand 452 states and 504 transitions. [2018-02-02 20:37:22,182 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-02 20:37:22,182 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:22,182 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:22,182 INFO L371 AbstractCegarLoop]: === Iteration 68 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:22,183 INFO L82 PathProgramCache]: Analyzing trace with hash 826486901, now seen corresponding path program 1 times [2018-02-02 20:37:22,183 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:22,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:22,193 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:22,235 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-02 20:37:22,236 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:22,236 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-02 20:37:22,236 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:22,236 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-02 20:37:22,236 INFO L182 omatonBuilderFactory]: Interpolants [67191#false, 67190#true, 67193#(not (= |ldv_malloc_#res.base| 0)), 67192#(not (= |ldv_malloc_#t~malloc4.base| 0)), 67195#(not (= alloc_fix_12_~priv~0.base 0)), 67194#(not (= |alloc_fix_12_#t~ret48.base| 0))] [2018-02-02 20:37:22,236 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-02 20:37:22,237 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:37:22,237 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:37:22,237 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:37:22,237 INFO L87 Difference]: Start difference. First operand 452 states and 504 transitions. Second operand 6 states. [2018-02-02 20:37:22,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:22,257 INFO L93 Difference]: Finished difference Result 444 states and 495 transitions. [2018-02-02 20:37:22,258 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-02 20:37:22,258 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 85 [2018-02-02 20:37:22,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:22,259 INFO L225 Difference]: With dead ends: 444 [2018-02-02 20:37:22,259 INFO L226 Difference]: Without dead ends: 444 [2018-02-02 20:37:22,259 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:37:22,259 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 444 states. [2018-02-02 20:37:22,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 444 to 444. [2018-02-02 20:37:22,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 444 states. [2018-02-02 20:37:22,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 444 states to 444 states and 495 transitions. [2018-02-02 20:37:22,262 INFO L78 Accepts]: Start accepts. Automaton has 444 states and 495 transitions. Word has length 85 [2018-02-02 20:37:22,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:22,263 INFO L432 AbstractCegarLoop]: Abstraction has 444 states and 495 transitions. [2018-02-02 20:37:22,263 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:37:22,263 INFO L276 IsEmpty]: Start isEmpty. Operand 444 states and 495 transitions. [2018-02-02 20:37:22,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-02 20:37:22,263 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:22,263 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:22,263 INFO L371 AbstractCegarLoop]: === Iteration 69 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:22,264 INFO L82 PathProgramCache]: Analyzing trace with hash 1569918071, now seen corresponding path program 1 times [2018-02-02 20:37:22,264 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:22,274 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:22,275 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:22,518 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 46 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 20:37:22,519 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:22,519 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-02 20:37:22,519 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:22,519 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 6 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:37:22,519 INFO L182 omatonBuilderFactory]: Interpolants [68097#(and (not (= entry_point_~fe~2.base |entry_point_#t~ret66.base|)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 68096#(and (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 68099#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 68098#(and (not (= entry_point_~adapter~0.base entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~adapter~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 68101#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|))) (= 0 |alloc_fix_12_#t~ret48.base|)), 68100#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 68103#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 68102#(and (= 0 alloc_fix_12_~priv~0.base) (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 68087#false, 68086#true, 68089#(= (select |#valid| |ldv_malloc_#res.base|) 1), 68088#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 68091#(= 1 (select |#valid| entry_point_~fe~2.base)), 68090#(= (select |#valid| |entry_point_#t~ret62.base|) 1), 68093#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 68092#(= |#valid| |old(#valid)|), 68095#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~fe~2.base |entry_point_#t~ret64.base|)) (= 1 (select |#valid| entry_point_~fe~2.base))), 68094#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-02 20:37:22,519 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 46 proven. 12 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-02 20:37:22,520 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-02 20:37:22,520 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-02 20:37:22,520 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=257, Unknown=0, NotChecked=0, Total=306 [2018-02-02 20:37:22,520 INFO L87 Difference]: Start difference. First operand 444 states and 495 transitions. Second operand 18 states. [2018-02-02 20:37:23,616 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:23,617 INFO L93 Difference]: Finished difference Result 530 states and 605 transitions. [2018-02-02 20:37:23,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-02 20:37:23,617 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 85 [2018-02-02 20:37:23,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:23,618 INFO L225 Difference]: With dead ends: 530 [2018-02-02 20:37:23,618 INFO L226 Difference]: Without dead ends: 530 [2018-02-02 20:37:23,618 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 8 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2018-02-02 20:37:23,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 530 states. [2018-02-02 20:37:23,621 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 530 to 445. [2018-02-02 20:37:23,621 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445 states. [2018-02-02 20:37:23,621 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 496 transitions. [2018-02-02 20:37:23,621 INFO L78 Accepts]: Start accepts. Automaton has 445 states and 496 transitions. Word has length 85 [2018-02-02 20:37:23,621 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:23,621 INFO L432 AbstractCegarLoop]: Abstraction has 445 states and 496 transitions. [2018-02-02 20:37:23,621 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-02 20:37:23,621 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 496 transitions. [2018-02-02 20:37:23,622 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-02-02 20:37:23,622 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:23,622 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:23,622 INFO L371 AbstractCegarLoop]: === Iteration 70 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:23,622 INFO L82 PathProgramCache]: Analyzing trace with hash 1422820228, now seen corresponding path program 1 times [2018-02-02 20:37:23,623 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:23,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:23,630 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:24,053 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 17 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-02 20:37:24,053 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:24,053 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-02 20:37:24,053 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:24,053 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 11 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-02 20:37:24,053 INFO L182 omatonBuilderFactory]: Interpolants [69089#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 69088#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 69091#(= |#valid| |old(#valid)|), 69090#(= 1 (select |#valid| entry_point_~cfg~2.base)), 69093#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 69092#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 69095#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 69094#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 69097#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 69096#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 69099#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret64.base|))), 69098#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 69101#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 69100#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 69103#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~adapter~0.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~adapter~0.base 0)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 69102#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret66.base|)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0))), 69105#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 69104#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 69107#(and (= 0 alloc_fix_12_~priv~0.base) (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 69106#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|))) (= 0 |alloc_fix_12_#t~ret48.base|)), 69108#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 69085#true, 69087#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 69086#false] [2018-02-02 20:37:24,054 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 17 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-02 20:37:24,054 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-02 20:37:24,054 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-02 20:37:24,054 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=476, Unknown=0, NotChecked=0, Total=552 [2018-02-02 20:37:24,054 INFO L87 Difference]: Start difference. First operand 445 states and 496 transitions. Second operand 24 states. [2018-02-02 20:37:25,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:25,099 INFO L93 Difference]: Finished difference Result 531 states and 606 transitions. [2018-02-02 20:37:25,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 20:37:25,100 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 86 [2018-02-02 20:37:25,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:25,100 INFO L225 Difference]: With dead ends: 531 [2018-02-02 20:37:25,101 INFO L226 Difference]: Without dead ends: 531 [2018-02-02 20:37:25,101 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 7 SyntacticMatches, 5 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 134 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=103, Invalid=653, Unknown=0, NotChecked=0, Total=756 [2018-02-02 20:37:25,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states. [2018-02-02 20:37:25,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 446. [2018-02-02 20:37:25,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-02-02 20:37:25,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 497 transitions. [2018-02-02 20:37:25,104 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 497 transitions. Word has length 86 [2018-02-02 20:37:25,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:25,105 INFO L432 AbstractCegarLoop]: Abstraction has 446 states and 497 transitions. [2018-02-02 20:37:25,105 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-02 20:37:25,105 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 497 transitions. [2018-02-02 20:37:25,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-02 20:37:25,105 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:25,105 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:25,105 INFO L371 AbstractCegarLoop]: === Iteration 71 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:25,105 INFO L82 PathProgramCache]: Analyzing trace with hash 98912465, now seen corresponding path program 1 times [2018-02-02 20:37:25,106 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:25,112 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:25,112 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:25,125 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:25,125 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:25,125 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 20:37:25,125 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:25,126 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 20:37:25,126 INFO L182 omatonBuilderFactory]: Interpolants [70096#(= 1 (select |#valid| |ldv_m88ts2022_rd_reg_~#reg.base|)), 70095#false, 70094#true] [2018-02-02 20:37:25,126 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:25,126 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 20:37:25,126 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 20:37:25,126 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:37:25,126 INFO L87 Difference]: Start difference. First operand 446 states and 497 transitions. Second operand 3 states. [2018-02-02 20:37:25,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:25,201 INFO L93 Difference]: Finished difference Result 445 states and 496 transitions. [2018-02-02 20:37:25,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 20:37:25,201 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2018-02-02 20:37:25,201 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:25,202 INFO L225 Difference]: With dead ends: 445 [2018-02-02 20:37:25,202 INFO L226 Difference]: Without dead ends: 445 [2018-02-02 20:37:25,202 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:37:25,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states. [2018-02-02 20:37:25,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 445. [2018-02-02 20:37:25,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445 states. [2018-02-02 20:37:25,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 496 transitions. [2018-02-02 20:37:25,205 INFO L78 Accepts]: Start accepts. Automaton has 445 states and 496 transitions. Word has length 89 [2018-02-02 20:37:25,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:25,205 INFO L432 AbstractCegarLoop]: Abstraction has 445 states and 496 transitions. [2018-02-02 20:37:25,205 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 20:37:25,205 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 496 transitions. [2018-02-02 20:37:25,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-02 20:37:25,206 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:25,206 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:25,206 INFO L371 AbstractCegarLoop]: === Iteration 72 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:25,206 INFO L82 PathProgramCache]: Analyzing trace with hash 98912466, now seen corresponding path program 1 times [2018-02-02 20:37:25,207 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:25,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:25,213 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:25,226 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:25,226 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:25,226 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-02 20:37:25,226 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:25,227 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 20:37:25,227 INFO L182 omatonBuilderFactory]: Interpolants [70987#true, 70989#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 70988#false, 70990#(<= |#Ultimate.C_memcpy_size| 0)] [2018-02-02 20:37:25,227 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:25,227 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-02 20:37:25,227 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-02 20:37:25,227 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-02 20:37:25,227 INFO L87 Difference]: Start difference. First operand 445 states and 496 transitions. Second operand 4 states. [2018-02-02 20:37:25,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:25,239 INFO L93 Difference]: Finished difference Result 451 states and 503 transitions. [2018-02-02 20:37:25,239 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-02 20:37:25,239 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 89 [2018-02-02 20:37:25,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:25,240 INFO L225 Difference]: With dead ends: 451 [2018-02-02 20:37:25,240 INFO L226 Difference]: Without dead ends: 449 [2018-02-02 20:37:25,240 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:25,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states. [2018-02-02 20:37:25,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2018-02-02 20:37:25,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-02 20:37:25,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 501 transitions. [2018-02-02 20:37:25,245 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 501 transitions. Word has length 89 [2018-02-02 20:37:25,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:25,245 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 501 transitions. [2018-02-02 20:37:25,245 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-02 20:37:25,245 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 501 transitions. [2018-02-02 20:37:25,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-02 20:37:25,246 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:25,246 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:25,246 INFO L371 AbstractCegarLoop]: === Iteration 73 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:25,246 INFO L82 PathProgramCache]: Analyzing trace with hash 1157754395, now seen corresponding path program 1 times [2018-02-02 20:37:25,247 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:25,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:25,263 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:25,750 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 17 proven. 28 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-02 20:37:25,750 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:25,750 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 20:37:25,750 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:25,751 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:37:25,751 INFO L182 omatonBuilderFactory]: Interpolants [71893#true, 71895#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 71894#false, 71897#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 71896#(= (select |#valid| |ldv_malloc_#res.base|) 1), 71899#(= |#valid| |old(#valid)|), 71898#(= (select |#valid| entry_point_~client~0.base) 1), 71901#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 71900#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 71903#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 71902#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|))), 71905#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 71904#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71907#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= (select |#valid| entry_point_~client~0.base) 1) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71906#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 71909#(and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71908#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71911#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71910#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71913#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 71912#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0)) (not (= 0 entry_point_~cfg~2.base))), 71915#(and (= alloc_fix_12_~client.base |alloc_fix_12_#in~client.base|) (= |#valid| |old(#valid)|)), 71914#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= (select |#valid| entry_point_~client~0.base) 0))), 71917#(or (= 0 (select |old(#valid)| |alloc_fix_12_#in~client.base|)) (and (= 1 (select |#valid| |alloc_fix_12_#in~client.base|)) (not (= |alloc_fix_12_~#chip_id~0.base| |alloc_fix_12_#in~client.base|)))), 71916#(and (or (= 0 (select |old(#valid)| |alloc_fix_12_#in~client.base|)) (not (= alloc_fix_12_~client.base |alloc_fix_12_~#chip_id~0.base|))) (= alloc_fix_12_~client.base |alloc_fix_12_#in~client.base|)), 71919#(or (= 0 (select |old(#valid)| |alloc_fix_12_#in~client.base|)) (and (= 1 (select |#valid| |alloc_fix_12_#in~client.base|)) (not (= |alloc_fix_12_~#chip_id~0.base| |alloc_fix_12_#in~client.base|)) (= 0 |alloc_fix_12_#t~ret48.base|))), 71918#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 71921#(or (= 1 (select |#valid| |alloc_fix_12_#in~client.base|)) (= 0 (select |old(#valid)| |alloc_fix_12_#in~client.base|))), 71920#(or (= 0 (select |old(#valid)| |alloc_fix_12_#in~client.base|)) (and (= 1 (select |#valid| |alloc_fix_12_#in~client.base|)) (= 0 alloc_fix_12_~priv~0.base) (not (= |alloc_fix_12_~#chip_id~0.base| |alloc_fix_12_#in~client.base|)))), 71922#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= entry_point_~addr~0.base entry_point_~client~0.base)) (not (= 0 entry_point_~fe~2.base)) (= 1 (select (store |#valid| entry_point_~adapter~0.base 0) entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base)))] [2018-02-02 20:37:25,751 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 17 proven. 28 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-02 20:37:25,751 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 20:37:25,751 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 20:37:25,751 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=96, Invalid=774, Unknown=0, NotChecked=0, Total=870 [2018-02-02 20:37:25,751 INFO L87 Difference]: Start difference. First operand 449 states and 501 transitions. Second operand 30 states. [2018-02-02 20:37:26,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:26,956 INFO L93 Difference]: Finished difference Result 507 states and 573 transitions. [2018-02-02 20:37:26,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-02 20:37:26,957 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 87 [2018-02-02 20:37:26,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:26,958 INFO L225 Difference]: With dead ends: 507 [2018-02-02 20:37:26,958 INFO L226 Difference]: Without dead ends: 507 [2018-02-02 20:37:26,958 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 11 SyntacticMatches, 6 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 344 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=159, Invalid=1401, Unknown=0, NotChecked=0, Total=1560 [2018-02-02 20:37:26,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states. [2018-02-02 20:37:26,960 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 450. [2018-02-02 20:37:26,960 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 450 states. [2018-02-02 20:37:26,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 502 transitions. [2018-02-02 20:37:26,961 INFO L78 Accepts]: Start accepts. Automaton has 450 states and 502 transitions. Word has length 87 [2018-02-02 20:37:26,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:26,961 INFO L432 AbstractCegarLoop]: Abstraction has 450 states and 502 transitions. [2018-02-02 20:37:26,961 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 20:37:26,961 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 502 transitions. [2018-02-02 20:37:26,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-02 20:37:26,961 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:26,962 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:26,962 INFO L371 AbstractCegarLoop]: === Iteration 74 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:26,962 INFO L82 PathProgramCache]: Analyzing trace with hash 1000059677, now seen corresponding path program 1 times [2018-02-02 20:37:26,962 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:26,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:26,969 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:26,986 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:26,986 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:26,986 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-02 20:37:26,986 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:26,987 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 20:37:26,987 INFO L182 omatonBuilderFactory]: Interpolants [72901#false, 72900#true, 72903#(<= |#Ultimate.C_memcpy_#t~loopctr71| 1), 72902#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 72904#(<= |#Ultimate.C_memcpy_size| 1)] [2018-02-02 20:37:26,987 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:26,987 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-02 20:37:26,987 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-02 20:37:26,987 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-02-02 20:37:26,987 INFO L87 Difference]: Start difference. First operand 450 states and 502 transitions. Second operand 5 states. [2018-02-02 20:37:27,011 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:27,011 INFO L93 Difference]: Finished difference Result 457 states and 512 transitions. [2018-02-02 20:37:27,012 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-02 20:37:27,012 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-02-02 20:37:27,012 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:27,012 INFO L225 Difference]: With dead ends: 457 [2018-02-02 20:37:27,012 INFO L226 Difference]: Without dead ends: 457 [2018-02-02 20:37:27,012 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:37:27,013 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 457 states. [2018-02-02 20:37:27,015 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 457 to 457. [2018-02-02 20:37:27,015 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 457 states. [2018-02-02 20:37:27,015 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 512 transitions. [2018-02-02 20:37:27,015 INFO L78 Accepts]: Start accepts. Automaton has 457 states and 512 transitions. Word has length 90 [2018-02-02 20:37:27,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:27,015 INFO L432 AbstractCegarLoop]: Abstraction has 457 states and 512 transitions. [2018-02-02 20:37:27,015 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-02 20:37:27,015 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 512 transitions. [2018-02-02 20:37:27,016 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-02-02 20:37:27,016 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:27,016 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:27,016 INFO L371 AbstractCegarLoop]: === Iteration 75 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:27,016 INFO L82 PathProgramCache]: Analyzing trace with hash -1129147854, now seen corresponding path program 2 times [2018-02-02 20:37:27,016 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:27,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:27,023 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:27,053 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:27,053 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:27,053 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-02 20:37:27,054 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:27,054 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 20:37:27,054 INFO L182 omatonBuilderFactory]: Interpolants [73825#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 73824#false, 73827#(<= |#Ultimate.C_memcpy_#t~loopctr71| 2), 73826#(<= |#Ultimate.C_memcpy_#t~loopctr71| 1), 73828#(<= |#Ultimate.C_memcpy_size| 2), 73823#true] [2018-02-02 20:37:27,054 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:27,054 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-02 20:37:27,054 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-02 20:37:27,054 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-02-02 20:37:27,054 INFO L87 Difference]: Start difference. First operand 457 states and 512 transitions. Second operand 6 states. [2018-02-02 20:37:27,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:27,089 INFO L93 Difference]: Finished difference Result 466 states and 524 transitions. [2018-02-02 20:37:27,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-02 20:37:27,089 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 91 [2018-02-02 20:37:27,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:27,090 INFO L225 Difference]: With dead ends: 466 [2018-02-02 20:37:27,090 INFO L226 Difference]: Without dead ends: 466 [2018-02-02 20:37:27,090 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-02-02 20:37:27,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2018-02-02 20:37:27,093 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 461. [2018-02-02 20:37:27,093 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-02 20:37:27,093 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-02 20:37:27,094 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 91 [2018-02-02 20:37:27,094 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:27,094 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-02 20:37:27,094 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-02 20:37:27,094 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-02 20:37:27,094 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-02 20:37:27,094 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:27,094 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:27,094 INFO L371 AbstractCegarLoop]: === Iteration 76 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:27,095 INFO L82 PathProgramCache]: Analyzing trace with hash 2074285145, now seen corresponding path program 1 times [2018-02-02 20:37:27,095 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:27,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:27,104 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:27,717 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 13 proven. 17 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-02-02 20:37:27,717 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:27,717 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-02 20:37:27,718 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:27,718 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 5 proven. 5 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-02 20:37:27,718 INFO L182 omatonBuilderFactory]: Interpolants [74763#false, 74762#true, 74765#(= |#valid| |old(#valid)|), 74764#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 74767#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 74766#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 74769#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 74768#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 74771#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret60.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 74770#(and (or (= (@diff |old(#valid)| |#valid|) |ldv_malloc_#res.base|) (= |#valid| |old(#valid)|)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 74773#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 74772#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 74775#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 74774#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 74777#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= 0 entry_point_~fe~2.base)) (or (= entry_point_~fe~2.base |entry_point_#t~ret64.base|) (and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))))), 74776#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 74779#(and (not (= entry_point_~addr~0.base 0)) (or (= entry_point_~addr~0.base entry_point_~fe~2.base) (and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|)) (not (= |entry_point_#t~ret66.base| 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))) (not (= 0 entry_point_~fe~2.base))), 74778#(and (or (= entry_point_~addr~0.base entry_point_~fe~2.base) (and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))) (not (= entry_point_~addr~0.base 0)) (not (= 0 entry_point_~fe~2.base))), 74781#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 74780#(and (not (= entry_point_~addr~0.base 0)) (not (= 0 entry_point_~fe~2.base)) (or (= entry_point_~addr~0.base entry_point_~fe~2.base) (and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~adapter~0.base 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))))), 74783#(and (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|))) (= 0 |alloc_fix_12_#t~ret48.base|)), 74782#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 74785#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 74784#(and (= 0 alloc_fix_12_~priv~0.base) (= 0 (select |old(#valid)| |alloc_fix_12_~#chip_id~0.base|)) (= |#valid| (store |old(#valid)| |alloc_fix_12_~#chip_id~0.base| (select |#valid| |alloc_fix_12_~#chip_id~0.base|)))), 74786#(and (or (not (= 1 (select |#valid| entry_point_~fe~2.base))) (and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)) (= 1 (select (store |#valid| entry_point_~fe~2.base 0) |~#ldv_global_msg_list.base|)))) (not (= 0 entry_point_~fe~2.base)))] [2018-02-02 20:37:27,718 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 13 proven. 17 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-02-02 20:37:27,718 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-02 20:37:27,718 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-02 20:37:27,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=521, Unknown=0, NotChecked=0, Total=600 [2018-02-02 20:37:27,719 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 25 states. [2018-02-02 20:37:29,350 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:29,351 INFO L93 Difference]: Finished difference Result 575 states and 648 transitions. [2018-02-02 20:37:29,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-02 20:37:29,351 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 90 [2018-02-02 20:37:29,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:29,352 INFO L225 Difference]: With dead ends: 575 [2018-02-02 20:37:29,352 INFO L226 Difference]: Without dead ends: 575 [2018-02-02 20:37:29,352 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 63 GetRequests, 15 SyntacticMatches, 9 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 465 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=197, Invalid=1443, Unknown=0, NotChecked=0, Total=1640 [2018-02-02 20:37:29,352 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states. [2018-02-02 20:37:29,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 464. [2018-02-02 20:37:29,355 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:37:29,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 522 transitions. [2018-02-02 20:37:29,355 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 522 transitions. Word has length 90 [2018-02-02 20:37:29,355 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:29,356 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 522 transitions. [2018-02-02 20:37:29,356 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-02 20:37:29,356 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 522 transitions. [2018-02-02 20:37:29,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-02 20:37:29,356 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:29,356 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:29,356 INFO L371 AbstractCegarLoop]: === Iteration 77 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:29,356 INFO L82 PathProgramCache]: Analyzing trace with hash 1584895421, now seen corresponding path program 3 times [2018-02-02 20:37:29,357 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:29,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:29,364 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:29,384 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:29,384 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:29,384 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-02 20:37:29,385 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:29,385 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 20:37:29,385 INFO L182 omatonBuilderFactory]: Interpolants [75859#false, 75858#true, 75861#(<= |#Ultimate.C_memcpy_#t~loopctr71| 1), 75860#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 75863#(<= |#Ultimate.C_memcpy_#t~loopctr71| 3), 75862#(<= |#Ultimate.C_memcpy_#t~loopctr71| 2), 75864#(<= |#Ultimate.C_memcpy_size| 3)] [2018-02-02 20:37:29,385 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-02 20:37:29,385 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-02 20:37:29,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-02 20:37:29,385 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-02-02 20:37:29,385 INFO L87 Difference]: Start difference. First operand 464 states and 522 transitions. Second operand 7 states. [2018-02-02 20:37:29,417 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:29,417 INFO L93 Difference]: Finished difference Result 478 states and 540 transitions. [2018-02-02 20:37:29,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-02 20:37:29,417 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 92 [2018-02-02 20:37:29,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:29,418 INFO L225 Difference]: With dead ends: 478 [2018-02-02 20:37:29,418 INFO L226 Difference]: Without dead ends: 478 [2018-02-02 20:37:29,418 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2018-02-02 20:37:29,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-02 20:37:29,421 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 465. [2018-02-02 20:37:29,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 465 states. [2018-02-02 20:37:29,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 524 transitions. [2018-02-02 20:37:29,421 INFO L78 Accepts]: Start accepts. Automaton has 465 states and 524 transitions. Word has length 92 [2018-02-02 20:37:29,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:29,422 INFO L432 AbstractCegarLoop]: Abstraction has 465 states and 524 transitions. [2018-02-02 20:37:29,422 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-02 20:37:29,422 INFO L276 IsEmpty]: Start isEmpty. Operand 465 states and 524 transitions. [2018-02-02 20:37:29,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-02 20:37:29,422 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:29,422 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:29,422 INFO L371 AbstractCegarLoop]: === Iteration 78 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:29,422 INFO L82 PathProgramCache]: Analyzing trace with hash -179108974, now seen corresponding path program 4 times [2018-02-02 20:37:29,423 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:29,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:29,432 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:29,477 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-02 20:37:29,477 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-02 20:37:29,477 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-02 20:37:29,477 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:29,478 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-02 20:37:29,478 INFO L182 omatonBuilderFactory]: Interpolants [76817#false, 76816#true, 76818#(and (= |ldv_m88ts2022_rd_reg_~#reg.offset| 0) (= (select |#length| |ldv_m88ts2022_rd_reg_~#reg.base|) 1))] [2018-02-02 20:37:29,478 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-02 20:37:29,478 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-02 20:37:29,479 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-02 20:37:29,479 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:37:29,479 INFO L87 Difference]: Start difference. First operand 465 states and 524 transitions. Second operand 3 states. [2018-02-02 20:37:29,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:29,560 INFO L93 Difference]: Finished difference Result 464 states and 523 transitions. [2018-02-02 20:37:29,560 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-02 20:37:29,560 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 93 [2018-02-02 20:37:29,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:29,561 INFO L225 Difference]: With dead ends: 464 [2018-02-02 20:37:29,561 INFO L226 Difference]: Without dead ends: 464 [2018-02-02 20:37:29,561 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-02 20:37:29,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2018-02-02 20:37:29,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 464. [2018-02-02 20:37:29,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-02 20:37:29,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 523 transitions. [2018-02-02 20:37:29,565 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 523 transitions. Word has length 93 [2018-02-02 20:37:29,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:29,565 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 523 transitions. [2018-02-02 20:37:29,565 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-02 20:37:29,565 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 523 transitions. [2018-02-02 20:37:29,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-02 20:37:29,566 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:29,566 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:29,566 INFO L371 AbstractCegarLoop]: === Iteration 79 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:29,566 INFO L82 PathProgramCache]: Analyzing trace with hash 523210170, now seen corresponding path program 1 times [2018-02-02 20:37:29,567 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:29,586 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:29,587 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:30,484 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-02-02 20:37:30,484 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:30,484 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-02 20:37:30,484 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:30,484 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:37:30,484 INFO L182 omatonBuilderFactory]: Interpolants [77761#(and (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 77760#(and (or (= |#valid| |old(#valid)|) (= (select |old(#valid)| (@diff |old(#valid)| |#valid|)) 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 77763#(and (not (= entry_point_~addr~0.base 0)) (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (or (= entry_point_~addr~0.base entry_point_~cfg~2.base) (= 1 (select |#valid| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (not (= entry_point_~client~0.base 0))), 77762#(and (not (= |entry_point_#t~ret64.base| 0)) (or (and (or (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= |entry_point_#t~ret64.base| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (= |entry_point_#t~ret64.base| entry_point_~cfg~2.base) (= 1 (select |#valid| entry_point_~cfg~2.base))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 77765#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 77764#(and (or (and (= 1 (select |#valid| entry_point_~client~0.base)) (or (= entry_point_~addr~0.base entry_point_~cfg~2.base) (= 1 (select |#valid| entry_point_~cfg~2.base))) (or (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base 0))), 77767#(and (or (and (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (= entry_point_~addr~0.base |entry_point_#t~ret66.base|) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= |entry_point_#t~ret66.base| 0)) (not (= entry_point_~client~0.base 0))), 77766#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 77769#(= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|), 77768#(and (not (= entry_point_~addr~0.base 0)) (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (= entry_point_~addr~0.base entry_point_~adapter~0.base)) (or (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base) (and (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))))) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base 0))), 77771#(and (or (and (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 77770#(and (not (= entry_point_~addr~0.base 0)) (or (= 0 (select |#valid| entry_point_~addr~0.base)) (and (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 77773#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 77772#(and (not (= entry_point_~client~0.base 0)) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 77775#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 77774#(or (not (= 1 (select |#valid| |~#ldv_global_msg_list.base|))) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 77776#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base)), 77747#true, 77749#(= 1 (select |#valid| |~#ldv_global_msg_list.base|)), 77748#false, 77751#(= |#valid| |old(#valid)|), 77750#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|))), 77753#(and (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 77752#(and (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 77755#(and (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 77754#(and (not (= |entry_point_#t~ret59.base| 0)) (or (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|) (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))))), 77757#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 77756#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 77759#(and (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 77758#(and (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-02 20:37:30,485 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-02-02 20:37:30,485 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-02 20:37:30,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-02 20:37:30,485 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=783, Unknown=0, NotChecked=0, Total=870 [2018-02-02 20:37:30,485 INFO L87 Difference]: Start difference. First operand 464 states and 523 transitions. Second operand 30 states. [2018-02-02 20:37:34,344 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-02 20:37:34,344 INFO L93 Difference]: Finished difference Result 715 states and 852 transitions. [2018-02-02 20:37:34,344 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-02-02 20:37:34,344 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 92 [2018-02-02 20:37:34,344 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-02 20:37:34,345 INFO L225 Difference]: With dead ends: 715 [2018-02-02 20:37:34,346 INFO L226 Difference]: Without dead ends: 715 [2018-02-02 20:37:34,346 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 13 SyntacticMatches, 9 SemanticMatches, 61 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 738 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=459, Invalid=3447, Unknown=0, NotChecked=0, Total=3906 [2018-02-02 20:37:34,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 715 states. [2018-02-02 20:37:34,350 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 715 to 473. [2018-02-02 20:37:34,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-02 20:37:34,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 534 transitions. [2018-02-02 20:37:34,351 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 534 transitions. Word has length 92 [2018-02-02 20:37:34,351 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-02 20:37:34,351 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 534 transitions. [2018-02-02 20:37:34,351 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-02 20:37:34,351 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 534 transitions. [2018-02-02 20:37:34,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-02 20:37:34,352 INFO L343 BasicCegarLoop]: Found error trace [2018-02-02 20:37:34,352 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-02 20:37:34,352 INFO L371 AbstractCegarLoop]: === Iteration 80 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-02 20:37:34,352 INFO L82 PathProgramCache]: Analyzing trace with hash 523210171, now seen corresponding path program 1 times [2018-02-02 20:37:34,352 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-02 20:37:34,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-02 20:37:34,373 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-02 20:37:36,020 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-02-02 20:37:36,020 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-02 20:37:36,020 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-02 20:37:36,020 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-02 20:37:36,021 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-02 20:37:36,021 INFO L182 omatonBuilderFactory]: Interpolants [79041#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 79040#(= |#valid| |old(#valid)|), 79043#(and (not (= |entry_point_#t~ret59.base| 0)) (or (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|) (and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= (select |#valid| |entry_point_#t~ret59.base|) 1)))), 79042#(and (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= (select |#valid| |ldv_malloc_#res.base|) 1) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 79045#(and (= |ldv_malloc_#t~malloc4.offset| 0) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 79044#(and (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| entry_point_~client~0.base) 1) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)))) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 79047#(and (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.offset| |entry_point_#t~ret60.offset|) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)))) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 79046#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |ldv_malloc_#res.offset| 0) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 79049#(and (= 0 |ldv_malloc_#res.offset|) (or (= |#valid| |old(#valid)|) (and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 79048#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))))), 79051#(and (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 79050#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| entry_point_~cfg~2.base) (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (= (select |#valid| entry_point_~cfg~2.base) 1)), 79053#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret64.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= |entry_point_#t~ret64.base| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 79052#(and (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 79055#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~addr~0.base 0)) (or (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 79054#(and (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (= |~#ldv_global_msg_list.offset| 0) (not (= entry_point_~addr~0.base 0)) (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 79057#(and (= 0 |ldv_malloc_#res.offset|) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 79056#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|) (not (= |ldv_malloc_#t~malloc4.base| 0))), 79059#(and (or (and (or (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base) (and (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|))) (not (= entry_point_~addr~0.base 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (= |~#ldv_global_msg_list.offset| entry_point_~adapter~0.offset)) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (and (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= entry_point_~adapter~0.base entry_point_~addr~0.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 79058#(and (or (and (not (= entry_point_~addr~0.base 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= |~#ldv_global_msg_list.offset| |entry_point_#t~ret66.offset|) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |entry_point_#t~ret66.base| 0)) (<= 0 |~#ldv_global_msg_list.offset|) (or (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 79061#(and (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 79060#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (= |#funAddr~master_xfer.offset| (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (or (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base) (and (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= entry_point_~adapter~0.base entry_point_~addr~0.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 79063#(and (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |alloc_fix_12_#t~mem46.base| (select (select |old(#memory_$Pointer$.base)| |alloc_fix_12_#in~client.base|) |alloc_fix_12_#in~client.offset|)) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 79062#(and (= alloc_fix_12_~client.offset |alloc_fix_12_#in~client.offset|) (= alloc_fix_12_~client.base |alloc_fix_12_#in~client.base|) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 79065#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (= |#funAddr~master_xfer.offset| (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= entry_point_~adapter~0.base entry_point_~addr~0.base)) (or (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base) (and (or (<= 0 |~#ldv_global_msg_list.offset|) (< 3 (select |#length| |~#ldv_global_msg_list.base|))) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 79064#(and (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= alloc_fix_12_~cfg~0.base (select (select |old(#memory_$Pointer$.base)| |alloc_fix_12_#in~client.base|) |alloc_fix_12_#in~client.offset|)) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 79067#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (or (<= 0 |~#ldv_global_msg_list.offset|) (< 3 (select |#length| |~#ldv_global_msg_list.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 79066#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (not (= entry_point_~addr~0.base 0)) (or (= |#funAddr~master_xfer.offset| (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (and (or (<= 0 |~#ldv_global_msg_list.offset|) (< 3 (select |#length| |~#ldv_global_msg_list.base|))) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)))) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (or (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= 1 (select |#valid| entry_point_~addr~0.base)))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 79069#(or (and (or (<= 0 |~#ldv_global_msg_list.offset|) (< 3 (select |#length| |~#ldv_global_msg_list.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (not (= 1 (select |#valid| |~#ldv_global_msg_list.base|)))), 79068#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (or (<= 0 |~#ldv_global_msg_list.offset|) (< 3 (select |#length| |~#ldv_global_msg_list.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 79071#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 79070#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 79037#false, 79036#true, 79039#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1)), 79038#(and (= 0 |~#ldv_global_msg_list.offset|) (= (select |#valid| |~#ldv_global_msg_list.base|) 1))] [2018-02-02 20:37:36,021 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 31 trivial. 0 not checked. [2018-02-02 20:37:36,021 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-02 20:37:36,021 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-02 20:37:36,021 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=1162, Unknown=0, NotChecked=0, Total=1260 [2018-02-02 20:37:36,022 INFO L87 Difference]: Start difference. First operand 473 states and 534 transitions. Second operand 36 states. Received shutdown request... [2018-02-02 20:37:37,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-02 20:37:37,135 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-02 20:37:37,139 WARN L185 ceAbstractionStarter]: Timeout [2018-02-02 20:37:37,139 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 02.02 08:37:37 BoogieIcfgContainer [2018-02-02 20:37:37,140 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-02 20:37:37,140 INFO L168 Benchmark]: Toolchain (without parser) took 70834.02 ms. Allocated memory was 402.1 MB in the beginning and 1.7 GB in the end (delta: 1.3 GB). Free memory was 359.0 MB in the beginning and 1.4 GB in the end (delta: -996.3 MB). Peak memory consumption was 324.4 MB. Max. memory is 5.3 GB. [2018-02-02 20:37:37,141 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 402.1 MB. Free memory is still 364.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-02 20:37:37,141 INFO L168 Benchmark]: CACSL2BoogieTranslator took 215.64 ms. Allocated memory is still 402.1 MB. Free memory was 359.0 MB in the beginning and 340.4 MB in the end (delta: 18.6 MB). Peak memory consumption was 18.6 MB. Max. memory is 5.3 GB. [2018-02-02 20:37:37,141 INFO L168 Benchmark]: Boogie Preprocessor took 43.59 ms. Allocated memory is still 402.1 MB. Free memory was 340.4 MB in the beginning and 337.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-02 20:37:37,141 INFO L168 Benchmark]: RCFGBuilder took 738.48 ms. Allocated memory was 402.1 MB in the beginning and 425.7 MB in the end (delta: 23.6 MB). Free memory was 337.8 MB in the beginning and 385.8 MB in the end (delta: -48.1 MB). Peak memory consumption was 99.6 MB. Max. memory is 5.3 GB. [2018-02-02 20:37:37,142 INFO L168 Benchmark]: TraceAbstraction took 69833.34 ms. Allocated memory was 425.7 MB in the beginning and 1.7 GB in the end (delta: 1.3 GB). Free memory was 385.8 MB in the beginning and 1.4 GB in the end (delta: -969.5 MB). Peak memory consumption was 327.6 MB. Max. memory is 5.3 GB. [2018-02-02 20:37:37,143 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 402.1 MB. Free memory is still 364.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 215.64 ms. Allocated memory is still 402.1 MB. Free memory was 359.0 MB in the beginning and 340.4 MB in the end (delta: 18.6 MB). Peak memory consumption was 18.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 43.59 ms. Allocated memory is still 402.1 MB. Free memory was 340.4 MB in the beginning and 337.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 738.48 ms. Allocated memory was 402.1 MB in the beginning and 425.7 MB in the end (delta: 23.6 MB). Free memory was 337.8 MB in the beginning and 385.8 MB in the end (delta: -48.1 MB). Peak memory consumption was 99.6 MB. Max. memory is 5.3 GB. * TraceAbstraction took 69833.34 ms. Allocated memory was 425.7 MB in the beginning and 1.7 GB in the end (delta: 1.3 GB). Free memory was 385.8 MB in the beginning and 1.4 GB in the end (delta: -969.5 MB). Peak memory consumption was 327.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1620]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1620). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1560). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1560). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1564). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1564). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1575). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1575). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1572). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1572). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1593). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1610). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1614). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1585). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1585). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1608). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1614). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1598). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1600). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1606). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1589). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1612). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1598). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1608). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1610). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1612). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1593). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1589). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1600). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1606). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was constructing difference of abstraction (473states) and interpolant automaton (currently 20 states, 36 states before enhancement), while PredicateComparison was comparing new predicate (quantifier-free) to 52 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 28 procedures, 416 locations, 141 error locations. TIMEOUT Result, 69.8s OverallTime, 80 OverallIterations, 6 TraceHistogramMax, 50.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 28343 SDtfs, 17060 SDslu, 109854 SDs, 0 SdLazy, 92139 SolverSat, 4689 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 36.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1449 GetRequests, 292 SyntacticMatches, 171 SemanticMatches, 985 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3864 ImplicationChecksByTransitivity, 17.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=538occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 2942/3414 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.5s AutomataMinimizationTime, 79 MinimizatonAttempts, 3711 StatesRemovedByMinimization, 66 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 17.5s InterpolantComputationTime, 4399 NumberOfCodeBlocks, 4399 NumberOfCodeBlocksAsserted, 80 NumberOfCheckSat, 4319 ConstructedInterpolants, 0 QuantifiedInterpolants, 1956902 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 80 InterpolantComputations, 29 PerfectInterpolantSequences, 2942/3414 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-02_20-37-37-149.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-02_20-37-37-149.csv Completed graceful shutdown