java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_false-valid-free.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-ccafca9-m [2018-02-04 03:06:25,744 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 03:06:25,745 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 03:06:25,757 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 03:06:25,757 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 03:06:25,758 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 03:06:25,759 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 03:06:25,760 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 03:06:25,762 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 03:06:25,762 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 03:06:25,763 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 03:06:25,763 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 03:06:25,764 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 03:06:25,765 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 03:06:25,766 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 03:06:25,769 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 03:06:25,771 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 03:06:25,773 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 03:06:25,774 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 03:06:25,775 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 03:06:25,776 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 03:06:25,777 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 03:06:25,777 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 03:06:25,778 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 03:06:25,779 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 03:06:25,780 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 03:06:25,780 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 03:06:25,780 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 03:06:25,781 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 03:06:25,781 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 03:06:25,781 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 03:06:25,781 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-04 03:06:25,791 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 03:06:25,791 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 03:06:25,793 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 03:06:25,793 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 03:06:25,793 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 03:06:25,793 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 03:06:25,793 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 03:06:25,794 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 03:06:25,794 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 03:06:25,794 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 03:06:25,794 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 03:06:25,794 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 03:06:25,794 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 03:06:25,795 INFO L133 SettingsManager]: * SV-COMP memtrack compatibility mode=true [2018-02-04 03:06:25,795 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 03:06:25,795 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 03:06:25,795 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 03:06:25,795 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 03:06:25,795 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 03:06:25,796 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 03:06:25,796 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 03:06:25,796 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 03:06:25,796 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-04 03:06:25,825 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 03:06:25,834 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 03:06:25,837 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 03:06:25,838 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 03:06:25,838 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 03:06:25,839 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_false-valid-free.i [2018-02-04 03:06:25,996 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 03:06:25,997 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 03:06:25,997 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 03:06:25,998 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 03:06:26,002 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 03:06:26,003 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 03:06:25" (1/1) ... [2018-02-04 03:06:26,005 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@63bdc3e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26, skipping insertion in model container [2018-02-04 03:06:26,005 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 03:06:25" (1/1) ... [2018-02-04 03:06:26,016 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 03:06:26,068 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 03:06:26,185 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 03:06:26,218 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 03:06:26,231 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26 WrapperNode [2018-02-04 03:06:26,231 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 03:06:26,232 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 03:06:26,232 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 03:06:26,232 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 03:06:26,241 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,241 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,252 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,253 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,265 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,270 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,273 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... [2018-02-04 03:06:26,277 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 03:06:26,277 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 03:06:26,278 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 03:06:26,278 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 03:06:26,279 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 03:06:26,314 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 03:06:26,314 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 03:06:26,314 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-04 03:06:26,314 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 03:06:26,314 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-04 03:06:26,314 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-04 03:06:26,315 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_get_clientdata [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_set_clientdata [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure master_xfer [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_transfer [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_m88ts2022_rd_reg [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure alloc_12 [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure free_12 [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 03:06:26,316 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 03:06:26,316 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 03:06:26,316 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 03:06:26,316 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 03:06:26,316 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 03:06:26,316 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-02-04 03:06:26,317 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure memcpy [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-02-04 03:06:26,317 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_get_clientdata [2018-02-04 03:06:26,318 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_set_clientdata [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure master_xfer [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_transfer [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_m88ts2022_rd_reg [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure alloc_12 [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure free_12 [2018-02-04 03:06:26,319 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 03:06:26,320 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 03:06:26,320 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 03:06:26,320 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 03:06:26,851 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-04 03:06:26,929 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 03:06:26,929 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 03:06:26 BoogieIcfgContainer [2018-02-04 03:06:26,930 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 03:06:26,930 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 03:06:26,930 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 03:06:26,932 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 03:06:26,933 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 03:06:25" (1/3) ... [2018-02-04 03:06:26,933 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d9f38bf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 03:06:26, skipping insertion in model container [2018-02-04 03:06:26,933 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:06:26" (2/3) ... [2018-02-04 03:06:26,934 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1d9f38bf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 03:06:26, skipping insertion in model container [2018-02-04 03:06:26,934 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 03:06:26" (3/3) ... [2018-02-04 03:06:26,936 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test12_false-valid-free.i [2018-02-04 03:06:26,943 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-04 03:06:26,950 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 141 error locations. [2018-02-04 03:06:26,983 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 03:06:26,983 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 03:06:26,983 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-04 03:06:26,983 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-04 03:06:26,983 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 03:06:26,983 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 03:06:26,983 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 03:06:26,984 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 03:06:26,984 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 03:06:27,004 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states. [2018-02-04 03:06:27,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-04 03:06:27,012 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:27,013 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-04 03:06:27,013 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:27,018 INFO L82 PathProgramCache]: Analyzing trace with hash 18685926, now seen corresponding path program 1 times [2018-02-04 03:06:27,065 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:27,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:27,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:27,201 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,203 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:27,203 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 03:06:27,204 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:27,205 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,206 INFO L182 omatonBuilderFactory]: Interpolants [401#true, 402#false, 403#(= 1 (select |#valid| |~#ldv_global_msg_list.base|))] [2018-02-04 03:06:27,206 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,207 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 03:06:27,220 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 03:06:27,220 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:06:27,222 INFO L87 Difference]: Start difference. First operand 398 states. Second operand 3 states. [2018-02-04 03:06:27,522 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:27,522 INFO L93 Difference]: Finished difference Result 487 states and 527 transitions. [2018-02-04 03:06:27,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 03:06:27,524 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-04 03:06:27,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:27,534 INFO L225 Difference]: With dead ends: 487 [2018-02-04 03:06:27,534 INFO L226 Difference]: Without dead ends: 481 [2018-02-04 03:06:27,535 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:06:27,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-04 03:06:27,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 436. [2018-02-04 03:06:27,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-02-04 03:06:27,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 491 transitions. [2018-02-04 03:06:27,577 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 491 transitions. Word has length 4 [2018-02-04 03:06:27,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:27,577 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 491 transitions. [2018-02-04 03:06:27,577 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 03:06:27,577 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 491 transitions. [2018-02-04 03:06:27,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-04 03:06:27,577 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:27,577 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-04 03:06:27,578 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:27,578 INFO L82 PathProgramCache]: Analyzing trace with hash 18685927, now seen corresponding path program 1 times [2018-02-04 03:06:27,579 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:27,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:27,592 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:27,622 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,622 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:27,622 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 03:06:27,622 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:27,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,623 INFO L182 omatonBuilderFactory]: Interpolants [1328#false, 1329#(and (= |~#ldv_global_msg_list.offset| 0) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 1327#true] [2018-02-04 03:06:27,623 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,624 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 03:06:27,625 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 03:06:27,625 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:06:27,625 INFO L87 Difference]: Start difference. First operand 436 states and 491 transitions. Second operand 3 states. [2018-02-04 03:06:27,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:27,771 INFO L93 Difference]: Finished difference Result 567 states and 652 transitions. [2018-02-04 03:06:27,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 03:06:27,772 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-04 03:06:27,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:27,774 INFO L225 Difference]: With dead ends: 567 [2018-02-04 03:06:27,774 INFO L226 Difference]: Without dead ends: 567 [2018-02-04 03:06:27,775 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:06:27,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-02-04 03:06:27,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 497. [2018-02-04 03:06:27,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 497 states. [2018-02-04 03:06:27,795 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 497 states to 497 states and 602 transitions. [2018-02-04 03:06:27,795 INFO L78 Accepts]: Start accepts. Automaton has 497 states and 602 transitions. Word has length 4 [2018-02-04 03:06:27,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:27,796 INFO L432 AbstractCegarLoop]: Abstraction has 497 states and 602 transitions. [2018-02-04 03:06:27,796 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 03:06:27,796 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 602 transitions. [2018-02-04 03:06:27,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 03:06:27,797 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:27,797 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:27,797 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:27,797 INFO L82 PathProgramCache]: Analyzing trace with hash -2098584656, now seen corresponding path program 1 times [2018-02-04 03:06:27,799 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:27,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:27,820 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:27,869 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,869 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:27,869 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:27,869 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:27,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,870 INFO L182 omatonBuilderFactory]: Interpolants [2394#true, 2395#false, 2396#(not (= |ldv_malloc_#t~malloc4.base| 0)), 2397#(not (= |ldv_malloc_#res.base| 0)), 2398#(not (= |entry_point_#t~ret59.base| 0)), 2399#(not (= entry_point_~client~0.base 0))] [2018-02-04 03:06:27,870 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:27,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:27,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:27,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:27,871 INFO L87 Difference]: Start difference. First operand 497 states and 602 transitions. Second operand 6 states. [2018-02-04 03:06:27,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:27,933 INFO L93 Difference]: Finished difference Result 543 states and 666 transitions. [2018-02-04 03:06:27,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:27,935 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-04 03:06:27,935 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:27,938 INFO L225 Difference]: With dead ends: 543 [2018-02-04 03:06:27,938 INFO L226 Difference]: Without dead ends: 543 [2018-02-04 03:06:27,938 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:27,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-02-04 03:06:27,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 496. [2018-02-04 03:06:27,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 496 states. [2018-02-04 03:06:27,957 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 604 transitions. [2018-02-04 03:06:27,957 INFO L78 Accepts]: Start accepts. Automaton has 496 states and 604 transitions. Word has length 21 [2018-02-04 03:06:27,958 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:27,958 INFO L432 AbstractCegarLoop]: Abstraction has 496 states and 604 transitions. [2018-02-04 03:06:27,958 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:27,958 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 604 transitions. [2018-02-04 03:06:27,958 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 03:06:27,959 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:27,959 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:27,959 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:27,959 INFO L82 PathProgramCache]: Analyzing trace with hash -1744465714, now seen corresponding path program 1 times [2018-02-04 03:06:27,961 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:27,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:27,979 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:28,041 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:28,041 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:28,041 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 03:06:28,042 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:28,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:28,042 INFO L182 omatonBuilderFactory]: Interpolants [3441#true, 3442#false, 3443#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 3444#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 3445#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-04 03:06:28,042 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:28,042 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:28,042 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:28,043 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:28,043 INFO L87 Difference]: Start difference. First operand 496 states and 604 transitions. Second operand 5 states. [2018-02-04 03:06:28,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:28,333 INFO L93 Difference]: Finished difference Result 571 states and 703 transitions. [2018-02-04 03:06:28,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:28,333 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2018-02-04 03:06:28,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:28,335 INFO L225 Difference]: With dead ends: 571 [2018-02-04 03:06:28,335 INFO L226 Difference]: Without dead ends: 571 [2018-02-04 03:06:28,336 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:28,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-04 03:06:28,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 538. [2018-02-04 03:06:28,349 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-04 03:06:28,351 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 661 transitions. [2018-02-04 03:06:28,351 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 661 transitions. Word has length 21 [2018-02-04 03:06:28,352 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:28,352 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 661 transitions. [2018-02-04 03:06:28,352 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:28,352 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 661 transitions. [2018-02-04 03:06:28,352 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 03:06:28,352 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:28,353 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:28,353 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:28,353 INFO L82 PathProgramCache]: Analyzing trace with hash -1744465713, now seen corresponding path program 1 times [2018-02-04 03:06:28,355 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:28,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:28,368 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:28,485 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:28,485 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:28,486 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:28,486 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:28,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:28,486 INFO L182 omatonBuilderFactory]: Interpolants [4560#false, 4561#(and (= 0 |~#ldv_global_msg_list.offset|) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 4562#(and (= 8 (select |#length| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 4563#(= |old(#length)| |#length|), 4564#(and (= 0 |ldv_destroy_msgs_#t~mem23.offset|) (= 8 (select |#length| |ldv_destroy_msgs_#t~mem23.base|))), 4565#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 4) 0) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4)) (= (select |#length| ldv_destroy_msgs_~msg~1.base) 8)), 4559#true] [2018-02-04 03:06:28,486 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:28,486 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:28,486 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:28,486 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:28,487 INFO L87 Difference]: Start difference. First operand 538 states and 661 transitions. Second operand 7 states. [2018-02-04 03:06:29,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:29,352 INFO L93 Difference]: Finished difference Result 668 states and 771 transitions. [2018-02-04 03:06:29,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:06:29,352 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-02-04 03:06:29,353 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:29,356 INFO L225 Difference]: With dead ends: 668 [2018-02-04 03:06:29,356 INFO L226 Difference]: Without dead ends: 668 [2018-02-04 03:06:29,356 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:06:29,357 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states. [2018-02-04 03:06:29,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 538. [2018-02-04 03:06:29,369 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-04 03:06:29,372 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 660 transitions. [2018-02-04 03:06:29,372 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 660 transitions. Word has length 21 [2018-02-04 03:06:29,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:29,372 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 660 transitions. [2018-02-04 03:06:29,373 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:29,373 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 660 transitions. [2018-02-04 03:06:29,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 03:06:29,373 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:29,374 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:29,374 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:29,374 INFO L82 PathProgramCache]: Analyzing trace with hash -1603523080, now seen corresponding path program 1 times [2018-02-04 03:06:29,376 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:29,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:29,384 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:29,449 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:29,450 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:29,450 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:06:29,450 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:29,451 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:29,451 INFO L182 omatonBuilderFactory]: Interpolants [5784#true, 5785#false, 5786#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 5787#(and (= 0 |entry_point_#t~ret59.base|) (= 0 |entry_point_#t~ret59.offset|)), 5788#(and (= 0 entry_point_~client~0.offset) (= entry_point_~client~0.base 0))] [2018-02-04 03:06:29,451 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:29,451 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:29,451 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:29,452 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:29,452 INFO L87 Difference]: Start difference. First operand 538 states and 660 transitions. Second operand 5 states. [2018-02-04 03:06:29,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:29,479 INFO L93 Difference]: Finished difference Result 503 states and 588 transitions. [2018-02-04 03:06:29,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:06:29,480 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 24 [2018-02-04 03:06:29,483 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:29,485 INFO L225 Difference]: With dead ends: 503 [2018-02-04 03:06:29,485 INFO L226 Difference]: Without dead ends: 503 [2018-02-04 03:06:29,486 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:29,486 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-04 03:06:29,493 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 495. [2018-02-04 03:06:29,493 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-02-04 03:06:29,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 574 transitions. [2018-02-04 03:06:29,495 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 574 transitions. Word has length 24 [2018-02-04 03:06:29,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:29,495 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 574 transitions. [2018-02-04 03:06:29,495 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:29,495 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 574 transitions. [2018-02-04 03:06:29,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 03:06:29,496 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:29,496 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:29,496 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:29,496 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705302, now seen corresponding path program 1 times [2018-02-04 03:06:29,497 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:29,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:29,508 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:29,540 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:29,540 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:29,540 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:06:29,540 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:29,541 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:29,541 INFO L182 omatonBuilderFactory]: Interpolants [6787#true, 6788#false, 6789#(= 0 |ldv_malloc_#t~malloc4.offset|), 6790#(= 0 |ldv_malloc_#res.offset|), 6791#(= 0 |entry_point_#t~ret59.offset|), 6792#(= 0 entry_point_~client~0.offset)] [2018-02-04 03:06:29,541 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:29,541 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:29,541 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:29,541 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:29,541 INFO L87 Difference]: Start difference. First operand 495 states and 574 transitions. Second operand 6 states. [2018-02-04 03:06:29,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:29,568 INFO L93 Difference]: Finished difference Result 496 states and 579 transitions. [2018-02-04 03:06:29,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:29,568 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-02-04 03:06:29,568 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:29,570 INFO L225 Difference]: With dead ends: 496 [2018-02-04 03:06:29,570 INFO L226 Difference]: Without dead ends: 496 [2018-02-04 03:06:29,570 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:29,570 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-02-04 03:06:29,576 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 494. [2018-02-04 03:06:29,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 494 states. [2018-02-04 03:06:29,578 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 494 states to 494 states and 572 transitions. [2018-02-04 03:06:29,578 INFO L78 Accepts]: Start accepts. Automaton has 494 states and 572 transitions. Word has length 26 [2018-02-04 03:06:29,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:29,579 INFO L432 AbstractCegarLoop]: Abstraction has 494 states and 572 transitions. [2018-02-04 03:06:29,579 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:29,579 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 572 transitions. [2018-02-04 03:06:29,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 03:06:29,579 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:29,579 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:29,580 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:29,580 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705303, now seen corresponding path program 1 times [2018-02-04 03:06:29,581 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:29,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:29,590 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:29,619 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:29,619 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:29,619 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-04 03:06:29,619 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:29,620 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:29,620 INFO L182 omatonBuilderFactory]: Interpolants [7792#(= |#valid| |old(#valid)|), 7786#true, 7787#false, 7788#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 7789#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 7790#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 7791#(= 1 (select |#valid| entry_point_~client~0.base))] [2018-02-04 03:06:29,620 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:29,620 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:29,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:29,620 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:29,620 INFO L87 Difference]: Start difference. First operand 494 states and 572 transitions. Second operand 7 states. [2018-02-04 03:06:30,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:30,347 INFO L93 Difference]: Finished difference Result 597 states and 705 transitions. [2018-02-04 03:06:30,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:30,349 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-02-04 03:06:30,349 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:30,352 INFO L225 Difference]: With dead ends: 597 [2018-02-04 03:06:30,352 INFO L226 Difference]: Without dead ends: 592 [2018-02-04 03:06:30,353 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:30,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2018-02-04 03:06:30,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 521. [2018-02-04 03:06:30,363 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-02-04 03:06:30,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 620 transitions. [2018-02-04 03:06:30,365 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 620 transitions. Word has length 26 [2018-02-04 03:06:30,365 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:30,365 INFO L432 AbstractCegarLoop]: Abstraction has 521 states and 620 transitions. [2018-02-04 03:06:30,365 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:30,365 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 620 transitions. [2018-02-04 03:06:30,366 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 03:06:30,366 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:30,366 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:30,366 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:30,366 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705304, now seen corresponding path program 1 times [2018-02-04 03:06:30,367 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:30,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:30,376 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:30,410 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:30,410 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:30,410 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:06:30,410 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:30,411 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,411 INFO L182 omatonBuilderFactory]: Interpolants [8913#true, 8914#false, 8915#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 8916#(and (= 0 |entry_point_#t~ret60.base|) (= 0 |entry_point_#t~ret60.offset|)), 8917#(and (= 0 entry_point_~cfg~2.offset) (= 0 entry_point_~cfg~2.base))] [2018-02-04 03:06:30,411 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:30,411 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:30,411 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:30,411 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:30,411 INFO L87 Difference]: Start difference. First operand 521 states and 620 transitions. Second operand 5 states. [2018-02-04 03:06:30,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:30,426 INFO L93 Difference]: Finished difference Result 523 states and 619 transitions. [2018-02-04 03:06:30,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:06:30,426 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-02-04 03:06:30,426 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:30,428 INFO L225 Difference]: With dead ends: 523 [2018-02-04 03:06:30,428 INFO L226 Difference]: Without dead ends: 523 [2018-02-04 03:06:30,428 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:30,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-02-04 03:06:30,434 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 520. [2018-02-04 03:06:30,434 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-02-04 03:06:30,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 617 transitions. [2018-02-04 03:06:30,436 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 617 transitions. Word has length 26 [2018-02-04 03:06:30,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:30,436 INFO L432 AbstractCegarLoop]: Abstraction has 520 states and 617 transitions. [2018-02-04 03:06:30,436 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:30,436 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 617 transitions. [2018-02-04 03:06:30,437 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 03:06:30,437 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:30,437 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:30,437 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:30,437 INFO L82 PathProgramCache]: Analyzing trace with hash -1000460798, now seen corresponding path program 1 times [2018-02-04 03:06:30,438 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:30,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:30,447 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:30,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,469 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:30,469 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 03:06:30,469 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:30,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,470 INFO L182 omatonBuilderFactory]: Interpolants [9961#true, 9962#false, 9963#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base)), 9964#(= 1 (select |#valid| |ldv_list_del_#in~entry.base|)), 9965#(= 1 (select |#valid| ldv_list_del_~entry.base))] [2018-02-04 03:06:30,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,470 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:30,470 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:30,470 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:30,470 INFO L87 Difference]: Start difference. First operand 520 states and 617 transitions. Second operand 5 states. [2018-02-04 03:06:30,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:30,730 INFO L93 Difference]: Finished difference Result 541 states and 644 transitions. [2018-02-04 03:06:30,730 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:30,730 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-02-04 03:06:30,730 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:30,732 INFO L225 Difference]: With dead ends: 541 [2018-02-04 03:06:30,732 INFO L226 Difference]: Without dead ends: 541 [2018-02-04 03:06:30,732 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:30,732 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-02-04 03:06:30,737 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 537. [2018-02-04 03:06:30,738 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-02-04 03:06:30,739 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 638 transitions. [2018-02-04 03:06:30,739 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 638 transitions. Word has length 27 [2018-02-04 03:06:30,739 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:30,739 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 638 transitions. [2018-02-04 03:06:30,739 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:30,739 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 638 transitions. [2018-02-04 03:06:30,740 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 03:06:30,740 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:30,740 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:30,740 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:30,740 INFO L82 PathProgramCache]: Analyzing trace with hash -1000460797, now seen corresponding path program 1 times [2018-02-04 03:06:30,741 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:30,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:30,748 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:30,915 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,916 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:30,916 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 03:06:30,916 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:30,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,916 INFO L182 omatonBuilderFactory]: Interpolants [11046#true, 11047#false, 11048#(and (= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11049#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11050#(and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= (+ |~#ldv_global_msg_list.offset| 8) (select |#length| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (= (select |#length| |~#ldv_global_msg_list.base|) 8)), 11051#(and (<= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 11052#(and (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|) (<= |~#ldv_global_msg_list.offset| 0) (<= 0 |~#ldv_global_msg_list.offset|)), 11053#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|))] [2018-02-04 03:06:30,916 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:30,916 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 03:06:30,917 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 03:06:30,917 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:30,917 INFO L87 Difference]: Start difference. First operand 537 states and 638 transitions. Second operand 8 states. [2018-02-04 03:06:31,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:31,273 INFO L93 Difference]: Finished difference Result 500 states and 568 transitions. [2018-02-04 03:06:31,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:06:31,273 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-02-04 03:06:31,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:31,275 INFO L225 Difference]: With dead ends: 500 [2018-02-04 03:06:31,276 INFO L226 Difference]: Without dead ends: 488 [2018-02-04 03:06:31,276 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-02-04 03:06:31,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2018-02-04 03:06:31,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 477. [2018-02-04 03:06:31,283 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 477 states. [2018-02-04 03:06:31,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 550 transitions. [2018-02-04 03:06:31,284 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 550 transitions. Word has length 27 [2018-02-04 03:06:31,285 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:31,285 INFO L432 AbstractCegarLoop]: Abstraction has 477 states and 550 transitions. [2018-02-04 03:06:31,285 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 03:06:31,285 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 550 transitions. [2018-02-04 03:06:31,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 03:06:31,285 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:31,285 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:31,286 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:31,286 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219079, now seen corresponding path program 1 times [2018-02-04 03:06:31,287 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:31,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:31,294 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:31,332 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:31,332 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:31,332 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:31,332 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:31,332 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 03:06:31,333 INFO L182 omatonBuilderFactory]: Interpolants [12039#true, 12040#false, 12041#(not (= |ldv_malloc_#t~malloc4.base| 0)), 12042#(not (= |ldv_malloc_#res.base| 0)), 12043#(not (= |entry_point_#t~ret60.base| 0)), 12044#(not (= entry_point_~cfg~2.base 0))] [2018-02-04 03:06:31,333 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:31,333 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:31,333 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:31,333 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:31,333 INFO L87 Difference]: Start difference. First operand 477 states and 550 transitions. Second operand 6 states. [2018-02-04 03:06:31,361 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:31,361 INFO L93 Difference]: Finished difference Result 478 states and 549 transitions. [2018-02-04 03:06:31,361 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:31,361 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-04 03:06:31,362 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:31,363 INFO L225 Difference]: With dead ends: 478 [2018-02-04 03:06:31,363 INFO L226 Difference]: Without dead ends: 478 [2018-02-04 03:06:31,363 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:31,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-04 03:06:31,368 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 476. [2018-02-04 03:06:31,368 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 476 states. [2018-02-04 03:06:31,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 476 states to 476 states and 547 transitions. [2018-02-04 03:06:31,369 INFO L78 Accepts]: Start accepts. Automaton has 476 states and 547 transitions. Word has length 28 [2018-02-04 03:06:31,369 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:31,369 INFO L432 AbstractCegarLoop]: Abstraction has 476 states and 547 transitions. [2018-02-04 03:06:31,369 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:31,369 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 547 transitions. [2018-02-04 03:06:31,369 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 03:06:31,370 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:31,370 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:31,370 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:31,370 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219079, now seen corresponding path program 1 times [2018-02-04 03:06:31,371 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:31,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:31,380 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:31,431 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:31,431 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:31,431 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-04 03:06:31,431 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:31,432 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:31,432 INFO L182 omatonBuilderFactory]: Interpolants [13008#(and (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 13009#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 13001#true, 13002#false, 13003#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 13004#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 13005#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 13006#(= 1 (select |#valid| entry_point_~client~0.base)), 13007#(= |#valid| |old(#valid)|)] [2018-02-04 03:06:31,432 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:31,432 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 03:06:31,432 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 03:06:31,432 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:06:31,433 INFO L87 Difference]: Start difference. First operand 476 states and 547 transitions. Second operand 9 states. [2018-02-04 03:06:32,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:32,349 INFO L93 Difference]: Finished difference Result 582 states and 680 transitions. [2018-02-04 03:06:32,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 03:06:32,349 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-02-04 03:06:32,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:32,352 INFO L225 Difference]: With dead ends: 582 [2018-02-04 03:06:32,352 INFO L226 Difference]: Without dead ends: 582 [2018-02-04 03:06:32,352 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=32, Invalid=100, Unknown=0, NotChecked=0, Total=132 [2018-02-04 03:06:32,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2018-02-04 03:06:32,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 461. [2018-02-04 03:06:32,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-04 03:06:32,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-04 03:06:32,361 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 28 [2018-02-04 03:06:32,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:32,361 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-04 03:06:32,361 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 03:06:32,361 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-04 03:06:32,362 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 03:06:32,362 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:32,362 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:32,362 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:32,362 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219078, now seen corresponding path program 1 times [2018-02-04 03:06:32,363 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:32,373 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:32,374 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:32,562 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:32,562 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:32,562 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 03:06:32,562 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:32,562 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:32,563 INFO L182 omatonBuilderFactory]: Interpolants [14064#(and (<= 20 (select |#length| |entry_point_#t~ret59.base|)) (= 0 |entry_point_#t~ret59.offset|) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 14065#(and (= (select |#valid| entry_point_~client~0.base) 1) (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 14066#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 14067#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 14068#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 14069#(and (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 14059#true, 14060#false, 14061#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 14062#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 14063#(and (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|)))] [2018-02-04 03:06:32,563 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:32,563 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:06:32,563 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:06:32,563 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:06:32,563 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 11 states. [2018-02-04 03:06:34,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:34,124 INFO L93 Difference]: Finished difference Result 632 states and 736 transitions. [2018-02-04 03:06:34,124 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 03:06:34,124 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 28 [2018-02-04 03:06:34,124 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:34,126 INFO L225 Difference]: With dead ends: 632 [2018-02-04 03:06:34,126 INFO L226 Difference]: Without dead ends: 632 [2018-02-04 03:06:34,127 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=217, Unknown=0, NotChecked=0, Total=272 [2018-02-04 03:06:34,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 632 states. [2018-02-04 03:06:34,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 632 to 473. [2018-02-04 03:06:34,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-04 03:06:34,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 544 transitions. [2018-02-04 03:06:34,136 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 544 transitions. Word has length 28 [2018-02-04 03:06:34,136 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:34,137 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 544 transitions. [2018-02-04 03:06:34,137 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:06:34,137 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 544 transitions. [2018-02-04 03:06:34,137 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 03:06:34,137 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:34,137 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:34,138 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:34,138 INFO L82 PathProgramCache]: Analyzing trace with hash -562803403, now seen corresponding path program 1 times [2018-02-04 03:06:34,139 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:34,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:34,148 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:34,246 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:34,246 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:34,246 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-04 03:06:34,246 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:34,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:34,247 INFO L182 omatonBuilderFactory]: Interpolants [15187#true, 15188#false, 15189#(= 1 (select |#valid| |~#ldv_global_msg_list.base|)), 15190#(= |#valid| |old(#valid)|), 15191#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 15192#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15193#(and (not (= |entry_point_#t~ret59.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 15194#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:06:34,247 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:34,247 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 03:06:34,247 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 03:06:34,247 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:34,247 INFO L87 Difference]: Start difference. First operand 473 states and 544 transitions. Second operand 8 states. [2018-02-04 03:06:34,963 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:34,963 INFO L93 Difference]: Finished difference Result 569 states and 639 transitions. [2018-02-04 03:06:34,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 03:06:34,964 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-02-04 03:06:34,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:34,965 INFO L225 Difference]: With dead ends: 569 [2018-02-04 03:06:34,965 INFO L226 Difference]: Without dead ends: 569 [2018-02-04 03:06:34,965 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 5 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=81, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:06:34,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 569 states. [2018-02-04 03:06:34,971 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 569 to 473. [2018-02-04 03:06:34,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-04 03:06:34,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 543 transitions. [2018-02-04 03:06:34,973 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 543 transitions. Word has length 29 [2018-02-04 03:06:34,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:34,973 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 543 transitions. [2018-02-04 03:06:34,973 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 03:06:34,973 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 543 transitions. [2018-02-04 03:06:34,973 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 03:06:34,973 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:34,973 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:34,974 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:34,974 INFO L82 PathProgramCache]: Analyzing trace with hash -562803402, now seen corresponding path program 1 times [2018-02-04 03:06:34,975 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:34,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:34,984 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:35,056 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:35,056 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:35,056 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-04 03:06:35,057 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:35,057 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:35,057 INFO L182 omatonBuilderFactory]: Interpolants [16243#true, 16244#false, 16245#(and (= |~#ldv_global_msg_list.offset| 0) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 16246#(and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 8 (select |#length| |~#ldv_global_msg_list.base|))), 16247#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16248#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 16249#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16250#(= |old(#length)| |#length|)] [2018-02-04 03:06:35,057 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:35,057 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 03:06:35,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 03:06:35,057 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=38, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:35,057 INFO L87 Difference]: Start difference. First operand 473 states and 543 transitions. Second operand 8 states. [2018-02-04 03:06:35,841 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:35,841 INFO L93 Difference]: Finished difference Result 635 states and 718 transitions. [2018-02-04 03:06:35,841 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 03:06:35,841 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 29 [2018-02-04 03:06:35,841 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:35,843 INFO L225 Difference]: With dead ends: 635 [2018-02-04 03:06:35,843 INFO L226 Difference]: Without dead ends: 635 [2018-02-04 03:06:35,843 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:06:35,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 635 states. [2018-02-04 03:06:35,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 635 to 472. [2018-02-04 03:06:35,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-04 03:06:35,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 541 transitions. [2018-02-04 03:06:35,853 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 541 transitions. Word has length 29 [2018-02-04 03:06:35,853 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:35,853 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 541 transitions. [2018-02-04 03:06:35,853 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 03:06:35,853 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 541 transitions. [2018-02-04 03:06:35,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-02-04 03:06:35,853 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:35,854 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:35,854 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:35,854 INFO L82 PathProgramCache]: Analyzing trace with hash 311817911, now seen corresponding path program 1 times [2018-02-04 03:06:35,855 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:35,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:35,866 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:35,966 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 03:06:35,967 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:35,967 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:06:35,967 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:35,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:35,968 INFO L182 omatonBuilderFactory]: Interpolants [17370#true, 17371#false, 17372#(= 0 |~#ldv_global_msg_list.offset|), 17373#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 17374#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 17375#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4)))] [2018-02-04 03:06:35,968 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 03:06:35,968 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:35,968 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:35,968 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:35,968 INFO L87 Difference]: Start difference. First operand 472 states and 541 transitions. Second operand 6 states. [2018-02-04 03:06:36,254 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:36,254 INFO L93 Difference]: Finished difference Result 481 states and 550 transitions. [2018-02-04 03:06:36,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:36,255 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-02-04 03:06:36,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:36,256 INFO L225 Difference]: With dead ends: 481 [2018-02-04 03:06:36,256 INFO L226 Difference]: Without dead ends: 481 [2018-02-04 03:06:36,256 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-02-04 03:06:36,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-04 03:06:36,262 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 472. [2018-02-04 03:06:36,262 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-04 03:06:36,263 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 540 transitions. [2018-02-04 03:06:36,263 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 540 transitions. Word has length 31 [2018-02-04 03:06:36,263 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:36,263 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 540 transitions. [2018-02-04 03:06:36,263 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:36,263 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 540 transitions. [2018-02-04 03:06:36,263 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 03:06:36,263 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:36,263 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:36,264 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:36,264 INFO L82 PathProgramCache]: Analyzing trace with hash -156377544, now seen corresponding path program 1 times [2018-02-04 03:06:36,264 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:36,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:36,271 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:36,297 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:36,297 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:36,297 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:06:36,298 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:36,298 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 03:06:36,298 INFO L182 omatonBuilderFactory]: Interpolants [18338#true, 18339#false, 18340#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 18341#(and (= 0 |entry_point_#t~ret62.base|) (= 0 |entry_point_#t~ret62.offset|)), 18342#(and (= 0 entry_point_~fe~2.base) (= 0 entry_point_~fe~2.offset))] [2018-02-04 03:06:36,298 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:36,298 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:36,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:36,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:36,299 INFO L87 Difference]: Start difference. First operand 472 states and 540 transitions. Second operand 5 states. [2018-02-04 03:06:36,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:36,323 INFO L93 Difference]: Finished difference Result 478 states and 542 transitions. [2018-02-04 03:06:36,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:06:36,324 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 36 [2018-02-04 03:06:36,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:36,325 INFO L225 Difference]: With dead ends: 478 [2018-02-04 03:06:36,325 INFO L226 Difference]: Without dead ends: 478 [2018-02-04 03:06:36,325 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:36,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-04 03:06:36,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 470. [2018-02-04 03:06:36,331 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-04 03:06:36,332 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-04 03:06:36,332 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-04 03:06:36,332 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:36,332 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-04 03:06:36,332 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:36,332 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-04 03:06:36,333 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 03:06:36,333 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:36,333 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:36,333 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:36,333 INFO L82 PathProgramCache]: Analyzing trace with hash -156377559, now seen corresponding path program 1 times [2018-02-04 03:06:36,334 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:36,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:36,342 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:36,370 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:36,370 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:36,370 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:06:36,370 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:36,371 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 03:06:36,371 INFO L182 omatonBuilderFactory]: Interpolants [19296#(= 0 entry_point_~cfg~2.offset), 19291#true, 19292#false, 19293#(= 0 |ldv_malloc_#t~malloc4.offset|), 19294#(= 0 |ldv_malloc_#res.offset|), 19295#(= 0 |entry_point_#t~ret60.offset|)] [2018-02-04 03:06:36,371 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:36,371 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:36,371 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:36,371 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:36,372 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 6 states. [2018-02-04 03:06:36,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:36,399 INFO L93 Difference]: Finished difference Result 469 states and 532 transitions. [2018-02-04 03:06:36,399 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:36,400 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-02-04 03:06:36,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:36,401 INFO L225 Difference]: With dead ends: 469 [2018-02-04 03:06:36,401 INFO L226 Difference]: Without dead ends: 469 [2018-02-04 03:06:36,401 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:36,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-04 03:06:36,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 469. [2018-02-04 03:06:36,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-04 03:06:36,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 532 transitions. [2018-02-04 03:06:36,408 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 532 transitions. Word has length 36 [2018-02-04 03:06:36,408 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:36,408 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 532 transitions. [2018-02-04 03:06:36,408 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:36,408 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 532 transitions. [2018-02-04 03:06:36,409 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 03:06:36,409 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:36,409 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:36,409 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:36,409 INFO L82 PathProgramCache]: Analyzing trace with hash -156377558, now seen corresponding path program 1 times [2018-02-04 03:06:36,410 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:36,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:36,417 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:36,449 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:36,450 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:36,450 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-04 03:06:36,450 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:36,450 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 03:06:36,451 INFO L182 omatonBuilderFactory]: Interpolants [20240#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 20241#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 20242#(= 1 (select |#valid| entry_point_~cfg~2.base)), 20243#(= |#valid| |old(#valid)|), 20237#true, 20238#false, 20239#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))] [2018-02-04 03:06:36,451 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:36,451 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:36,451 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:36,451 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:36,451 INFO L87 Difference]: Start difference. First operand 469 states and 532 transitions. Second operand 7 states. [2018-02-04 03:06:37,027 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:37,028 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-04 03:06:37,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:37,028 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-02-04 03:06:37,028 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:37,029 INFO L225 Difference]: With dead ends: 540 [2018-02-04 03:06:37,029 INFO L226 Difference]: Without dead ends: 540 [2018-02-04 03:06:37,029 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:37,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-04 03:06:37,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 470. [2018-02-04 03:06:37,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-04 03:06:37,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-04 03:06:37,034 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-04 03:06:37,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:37,035 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-04 03:06:37,035 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:37,035 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-04 03:06:37,035 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-02-04 03:06:37,035 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:37,035 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:37,035 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:37,035 INFO L82 PathProgramCache]: Analyzing trace with hash -552736786, now seen corresponding path program 1 times [2018-02-04 03:06:37,036 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:37,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:37,042 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:37,145 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:37,145 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:37,145 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-04 03:06:37,145 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:37,146 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 1 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:37,146 INFO L182 omatonBuilderFactory]: Interpolants [21264#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 21265#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 21266#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 21267#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 21256#true, 21257#false, 21258#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 21259#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 21260#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 21261#(= 1 (select |#valid| entry_point_~client~0.base)), 21262#(= |#valid| |old(#valid)|), 21263#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)))] [2018-02-04 03:06:37,146 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:37,146 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 03:06:37,146 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 03:06:37,146 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-02-04 03:06:37,147 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 12 states. [2018-02-04 03:06:37,857 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:37,857 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-04 03:06:37,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:06:37,858 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 37 [2018-02-04 03:06:37,858 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:37,859 INFO L225 Difference]: With dead ends: 540 [2018-02-04 03:06:37,859 INFO L226 Difference]: Without dead ends: 540 [2018-02-04 03:06:37,860 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:06:37,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-04 03:06:37,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 471. [2018-02-04 03:06:37,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-04 03:06:37,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-04 03:06:37,864 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 37 [2018-02-04 03:06:37,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:37,865 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-04 03:06:37,865 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 03:06:37,865 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-04 03:06:37,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 03:06:37,865 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:37,866 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:37,866 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:37,866 INFO L82 PathProgramCache]: Analyzing trace with hash -689007910, now seen corresponding path program 1 times [2018-02-04 03:06:37,867 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:37,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:37,877 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:37,942 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:37,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:37,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-04 03:06:37,943 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:37,943 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 03:06:37,944 INFO L182 omatonBuilderFactory]: Interpolants [22288#(= 1 (select |#valid| entry_point_~cfg~2.base)), 22289#(= |#valid| |old(#valid)|), 22290#(and (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 22291#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 22283#true, 22284#false, 22285#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 22286#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 22287#(= 1 (select |#valid| |entry_point_#t~ret60.base|))] [2018-02-04 03:06:37,944 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:37,944 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 03:06:37,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 03:06:37,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:06:37,945 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 9 states. [2018-02-04 03:06:38,772 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:38,772 INFO L93 Difference]: Finished difference Result 577 states and 667 transitions. [2018-02-04 03:06:38,772 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 03:06:38,772 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 38 [2018-02-04 03:06:38,772 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:38,774 INFO L225 Difference]: With dead ends: 577 [2018-02-04 03:06:38,774 INFO L226 Difference]: Without dead ends: 577 [2018-02-04 03:06:38,774 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-02-04 03:06:38,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states. [2018-02-04 03:06:38,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 471. [2018-02-04 03:06:38,778 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-04 03:06:38,778 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-04 03:06:38,778 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 38 [2018-02-04 03:06:38,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:38,783 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-04 03:06:38,783 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 03:06:38,783 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-04 03:06:38,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 03:06:38,784 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:38,784 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:38,784 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:38,784 INFO L82 PathProgramCache]: Analyzing trace with hash -689007909, now seen corresponding path program 1 times [2018-02-04 03:06:38,785 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:38,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:38,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:38,999 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 03:06:38,999 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:38,999 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 03:06:38,999 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:38,999 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:39,000 INFO L182 omatonBuilderFactory]: Interpolants [23344#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 23345#(and (= 0 |ldv_malloc_#t~malloc4.offset|) (or (and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|))) (<= (+ |ldv_malloc_#in~size| 1) 0) (<= 2147483648 |ldv_malloc_#in~size|))), 23346#(and (= 0 |ldv_malloc_#res.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (= (select |#valid| |ldv_malloc_#res.base|) 1)) (<= 2147483648 |ldv_malloc_#in~size|))), 23347#(and (= 0 |entry_point_#t~ret60.offset|) (= (select |#valid| |entry_point_#t~ret60.base|) 1) (<= 4 (select |#length| |entry_point_#t~ret60.base|))), 23348#(and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (= 0 entry_point_~cfg~2.offset)), 23349#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 23350#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 23351#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 23352#(and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= entry_point_~cfg~2.offset 0)), 23342#true, 23343#false] [2018-02-04 03:06:39,000 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 03:06:39,000 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:06:39,000 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:06:39,000 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:06:39,000 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 11 states. [2018-02-04 03:06:40,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:40,338 INFO L93 Difference]: Finished difference Result 620 states and 717 transitions. [2018-02-04 03:06:40,338 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:06:40,338 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-02-04 03:06:40,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:40,340 INFO L225 Difference]: With dead ends: 620 [2018-02-04 03:06:40,340 INFO L226 Difference]: Without dead ends: 620 [2018-02-04 03:06:40,340 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=141, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:06:40,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 620 states. [2018-02-04 03:06:40,344 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 620 to 470. [2018-02-04 03:06:40,344 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-04 03:06:40,345 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-04 03:06:40,345 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 38 [2018-02-04 03:06:40,345 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:40,345 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-04 03:06:40,345 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:06:40,346 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-04 03:06:40,346 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 03:06:40,346 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:40,346 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:40,346 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:40,346 INFO L82 PathProgramCache]: Analyzing trace with hash 115591052, now seen corresponding path program 1 times [2018-02-04 03:06:40,347 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:40,351 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:40,352 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:40,401 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:40,402 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:40,402 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:40,402 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:40,402 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 03:06:40,402 INFO L182 omatonBuilderFactory]: Interpolants [24450#true, 24451#false, 24452#(not (= |ldv_malloc_#t~malloc4.base| 0)), 24453#(not (= |ldv_malloc_#res.base| 0)), 24454#(not (= |entry_point_#t~ret62.base| 0)), 24455#(not (= entry_point_~fe~2.base 0))] [2018-02-04 03:06:40,402 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:40,402 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:40,403 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:40,403 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:40,403 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 6 states. [2018-02-04 03:06:40,418 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:40,418 INFO L93 Difference]: Finished difference Result 472 states and 535 transitions. [2018-02-04 03:06:40,419 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:40,419 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-02-04 03:06:40,419 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:40,420 INFO L225 Difference]: With dead ends: 472 [2018-02-04 03:06:40,420 INFO L226 Difference]: Without dead ends: 472 [2018-02-04 03:06:40,420 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:40,420 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 472 states. [2018-02-04 03:06:40,425 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 472 to 469. [2018-02-04 03:06:40,425 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-04 03:06:40,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 531 transitions. [2018-02-04 03:06:40,427 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 531 transitions. Word has length 39 [2018-02-04 03:06:40,427 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:40,427 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 531 transitions. [2018-02-04 03:06:40,427 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:40,427 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 531 transitions. [2018-02-04 03:06:40,427 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-04 03:06:40,427 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:40,428 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:40,428 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:40,428 INFO L82 PathProgramCache]: Analyzing trace with hash 323501758, now seen corresponding path program 1 times [2018-02-04 03:06:40,429 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:40,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:40,439 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:40,604 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:40,604 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:40,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 03:06:40,605 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:40,605 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 03:06:40,605 INFO L182 omatonBuilderFactory]: Interpolants [25408#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~cfg~2.base 0)) (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 25409#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= 1 (select |#valid| entry_point_~client~0.base))) (= 1 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0))), 25399#true, 25400#false, 25401#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 25402#(= |#valid| |old(#valid)|), 25403#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 25404#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 25405#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 25406#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 25407#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)))) (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:06:40,605 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:40,605 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:06:40,605 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:06:40,605 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:06:40,605 INFO L87 Difference]: Start difference. First operand 469 states and 531 transitions. Second operand 11 states. [2018-02-04 03:06:41,630 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:41,630 INFO L93 Difference]: Finished difference Result 566 states and 631 transitions. [2018-02-04 03:06:41,630 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 03:06:41,630 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 40 [2018-02-04 03:06:41,631 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:41,632 INFO L225 Difference]: With dead ends: 566 [2018-02-04 03:06:41,632 INFO L226 Difference]: Without dead ends: 566 [2018-02-04 03:06:41,632 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 9 SyntacticMatches, 4 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=192, Unknown=0, NotChecked=0, Total=240 [2018-02-04 03:06:41,632 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 566 states. [2018-02-04 03:06:41,635 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 566 to 472. [2018-02-04 03:06:41,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-04 03:06:41,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 535 transitions. [2018-02-04 03:06:41,637 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 535 transitions. Word has length 40 [2018-02-04 03:06:41,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:41,637 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 535 transitions. [2018-02-04 03:06:41,637 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:06:41,637 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 535 transitions. [2018-02-04 03:06:41,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 03:06:41,637 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:41,637 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:41,638 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:41,638 INFO L82 PathProgramCache]: Analyzing trace with hash 1592821110, now seen corresponding path program 1 times [2018-02-04 03:06:41,638 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:41,645 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:41,645 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:41,756 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:41,756 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:41,756 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-04 03:06:41,756 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:41,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 03:06:41,756 INFO L182 omatonBuilderFactory]: Interpolants [26464#(and (= |#valid| (store |old(#valid)| entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0))), 26458#true, 26459#false, 26460#(= |#valid| |old(#valid)|), 26461#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 26462#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0))), 26463#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (= |#valid| (store |old(#valid)| |entry_point_#t~ret59.base| (select |#valid| |entry_point_#t~ret59.base|))))] [2018-02-04 03:06:41,757 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:41,757 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:41,757 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:41,757 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:41,757 INFO L87 Difference]: Start difference. First operand 472 states and 535 transitions. Second operand 7 states. [2018-02-04 03:06:42,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:42,322 INFO L93 Difference]: Finished difference Result 532 states and 608 transitions. [2018-02-04 03:06:42,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 03:06:42,322 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 39 [2018-02-04 03:06:42,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:42,323 INFO L225 Difference]: With dead ends: 532 [2018-02-04 03:06:42,323 INFO L226 Difference]: Without dead ends: 514 [2018-02-04 03:06:42,323 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:06:42,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 514 states. [2018-02-04 03:06:42,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 514 to 455. [2018-02-04 03:06:42,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 455 states. [2018-02-04 03:06:42,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 455 states to 455 states and 517 transitions. [2018-02-04 03:06:42,327 INFO L78 Accepts]: Start accepts. Automaton has 455 states and 517 transitions. Word has length 39 [2018-02-04 03:06:42,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:42,328 INFO L432 AbstractCegarLoop]: Abstraction has 455 states and 517 transitions. [2018-02-04 03:06:42,328 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:42,328 INFO L276 IsEmpty]: Start isEmpty. Operand 455 states and 517 transitions. [2018-02-04 03:06:42,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 03:06:42,328 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:42,328 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:42,329 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:42,329 INFO L82 PathProgramCache]: Analyzing trace with hash 1647553023, now seen corresponding path program 1 times [2018-02-04 03:06:42,330 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:42,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:42,340 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:42,462 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:42,462 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:42,462 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-04 03:06:42,462 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:42,463 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:42,463 INFO L182 omatonBuilderFactory]: Interpolants [27456#true, 27457#false, 27458#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 27459#(not (= |ldv_malloc_#t~malloc4.base| 0)), 27460#(not (= |ldv_malloc_#res.base| 0)), 27461#(and (not (= |entry_point_#t~ret59.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 27462#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 27463#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 27464#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 27465#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-04 03:06:42,463 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:42,463 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 03:06:42,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 03:06:42,464 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-04 03:06:42,464 INFO L87 Difference]: Start difference. First operand 455 states and 517 transitions. Second operand 10 states. [2018-02-04 03:06:42,959 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:42,959 INFO L93 Difference]: Finished difference Result 481 states and 547 transitions. [2018-02-04 03:06:42,959 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 03:06:42,959 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-04 03:06:42,959 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:42,960 INFO L225 Difference]: With dead ends: 481 [2018-02-04 03:06:42,961 INFO L226 Difference]: Without dead ends: 481 [2018-02-04 03:06:42,961 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=57, Invalid=215, Unknown=0, NotChecked=0, Total=272 [2018-02-04 03:06:42,961 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-04 03:06:42,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 464. [2018-02-04 03:06:42,964 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-04 03:06:42,965 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 528 transitions. [2018-02-04 03:06:42,965 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 528 transitions. Word has length 42 [2018-02-04 03:06:42,965 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:42,965 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 528 transitions. [2018-02-04 03:06:42,965 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 03:06:42,965 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 528 transitions. [2018-02-04 03:06:42,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 03:06:42,965 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:42,965 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:42,966 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:42,966 INFO L82 PathProgramCache]: Analyzing trace with hash 1647553024, now seen corresponding path program 1 times [2018-02-04 03:06:42,966 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:42,975 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:42,976 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:43,181 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:43,181 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:43,181 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 03:06:43,182 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:43,182 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:43,182 INFO L182 omatonBuilderFactory]: Interpolants [28432#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 28433#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 28434#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 28435#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 28425#true, 28426#false, 28427#(= 0 |~#ldv_global_msg_list.offset|), 28428#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 28429#(not (= |ldv_malloc_#t~malloc4.base| 0)), 28430#(not (= |ldv_malloc_#res.base| 0)), 28431#(and (or (not (= |entry_point_#t~ret59.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|))] [2018-02-04 03:06:43,182 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:43,183 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:06:43,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:06:43,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:06:43,183 INFO L87 Difference]: Start difference. First operand 464 states and 528 transitions. Second operand 11 states. [2018-02-04 03:06:43,882 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:43,882 INFO L93 Difference]: Finished difference Result 482 states and 548 transitions. [2018-02-04 03:06:43,882 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 03:06:43,882 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 42 [2018-02-04 03:06:43,882 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:43,883 INFO L225 Difference]: With dead ends: 482 [2018-02-04 03:06:43,883 INFO L226 Difference]: Without dead ends: 482 [2018-02-04 03:06:43,883 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=113, Invalid=439, Unknown=0, NotChecked=0, Total=552 [2018-02-04 03:06:43,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 482 states. [2018-02-04 03:06:43,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 482 to 464. [2018-02-04 03:06:43,886 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-04 03:06:43,887 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-04 03:06:43,887 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 42 [2018-02-04 03:06:43,887 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:43,887 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-04 03:06:43,887 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:06:43,887 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-04 03:06:43,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-04 03:06:43,887 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:43,888 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:43,888 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:43,888 INFO L82 PathProgramCache]: Analyzing trace with hash -824107646, now seen corresponding path program 1 times [2018-02-04 03:06:43,888 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:43,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:43,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:43,920 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-04 03:06:43,920 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:43,920 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:06:43,920 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:43,921 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 03:06:43,921 INFO L182 omatonBuilderFactory]: Interpolants [29409#true, 29410#false, 29411#(= 0 |ldv_malloc_#t~malloc4.offset|), 29412#(= 0 |ldv_malloc_#res.offset|), 29413#(= 0 |entry_point_#t~ret62.offset|), 29414#(= 0 entry_point_~fe~2.offset)] [2018-02-04 03:06:43,921 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-04 03:06:43,921 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:43,921 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:43,921 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:43,921 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 6 states. [2018-02-04 03:06:43,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:43,936 INFO L93 Difference]: Finished difference Result 463 states and 526 transitions. [2018-02-04 03:06:43,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:43,937 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-02-04 03:06:43,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:43,938 INFO L225 Difference]: With dead ends: 463 [2018-02-04 03:06:43,938 INFO L226 Difference]: Without dead ends: 463 [2018-02-04 03:06:43,938 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:43,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2018-02-04 03:06:43,941 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 463. [2018-02-04 03:06:43,942 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-04 03:06:43,942 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 526 transitions. [2018-02-04 03:06:43,942 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 526 transitions. Word has length 46 [2018-02-04 03:06:43,942 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:43,942 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 526 transitions. [2018-02-04 03:06:43,943 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:43,943 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 526 transitions. [2018-02-04 03:06:43,943 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-04 03:06:43,943 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:43,943 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:43,943 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:43,943 INFO L82 PathProgramCache]: Analyzing trace with hash -824107645, now seen corresponding path program 1 times [2018-02-04 03:06:43,944 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:43,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:43,949 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:43,986 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:43,987 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:43,987 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-04 03:06:43,987 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:43,988 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 03:06:43,988 INFO L182 omatonBuilderFactory]: Interpolants [30343#true, 30344#false, 30345#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 30346#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 30347#(= 1 (select |#valid| |entry_point_#t~ret62.base|)), 30348#(= 1 (select |#valid| entry_point_~fe~2.base)), 30349#(= |#valid| |old(#valid)|)] [2018-02-04 03:06:43,988 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:43,988 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:43,988 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:43,988 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:43,989 INFO L87 Difference]: Start difference. First operand 463 states and 526 transitions. Second operand 7 states. [2018-02-04 03:06:44,532 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:44,532 INFO L93 Difference]: Finished difference Result 531 states and 610 transitions. [2018-02-04 03:06:44,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:44,532 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 46 [2018-02-04 03:06:44,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:44,534 INFO L225 Difference]: With dead ends: 531 [2018-02-04 03:06:44,534 INFO L226 Difference]: Without dead ends: 531 [2018-02-04 03:06:44,534 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:44,535 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 531 states. [2018-02-04 03:06:44,540 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 531 to 464. [2018-02-04 03:06:44,540 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-04 03:06:44,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-04 03:06:44,541 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 46 [2018-02-04 03:06:44,541 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:44,541 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-04 03:06:44,542 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:44,542 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-04 03:06:44,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 03:06:44,542 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:44,542 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:44,542 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:44,543 INFO L82 PathProgramCache]: Analyzing trace with hash 222466993, now seen corresponding path program 1 times [2018-02-04 03:06:44,543 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:44,551 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:44,552 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:44,715 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 03:06:44,716 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:44,716 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-04 03:06:44,716 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:44,716 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 03:06:44,717 INFO L182 omatonBuilderFactory]: Interpolants [31347#true, 31348#false, 31349#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 31350#(= (select |#valid| |ldv_malloc_#res.base|) 1), 31351#(= (select |#valid| |entry_point_#t~ret60.base|) 1), 31352#(= (select |#valid| entry_point_~cfg~2.base) 1), 31353#(= |#valid| |old(#valid)|), 31354#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 31355#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 31356#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 31357#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 31358#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)))] [2018-02-04 03:06:44,717 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 03:06:44,717 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 03:06:44,717 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 03:06:44,717 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=109, Unknown=0, NotChecked=0, Total=132 [2018-02-04 03:06:44,717 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 12 states. [2018-02-04 03:06:45,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:45,605 INFO L93 Difference]: Finished difference Result 534 states and 613 transitions. [2018-02-04 03:06:45,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:06:45,606 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 47 [2018-02-04 03:06:45,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:45,607 INFO L225 Difference]: With dead ends: 534 [2018-02-04 03:06:45,607 INFO L226 Difference]: Without dead ends: 534 [2018-02-04 03:06:45,607 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=34, Invalid=148, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:06:45,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 534 states. [2018-02-04 03:06:45,611 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 534 to 465. [2018-02-04 03:06:45,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 465 states. [2018-02-04 03:06:45,612 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 465 states to 465 states and 528 transitions. [2018-02-04 03:06:45,612 INFO L78 Accepts]: Start accepts. Automaton has 465 states and 528 transitions. Word has length 47 [2018-02-04 03:06:45,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:45,613 INFO L432 AbstractCegarLoop]: Abstraction has 465 states and 528 transitions. [2018-02-04 03:06:45,613 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 03:06:45,613 INFO L276 IsEmpty]: Start isEmpty. Operand 465 states and 528 transitions. [2018-02-04 03:06:45,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 03:06:45,613 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:45,613 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:45,613 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:45,613 INFO L82 PathProgramCache]: Analyzing trace with hash 1340530292, now seen corresponding path program 1 times [2018-02-04 03:06:45,614 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:45,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:45,625 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:45,824 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:45,824 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:45,824 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 03:06:45,824 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:45,825 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:45,825 INFO L182 omatonBuilderFactory]: Interpolants [32368#(and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 32369#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 32370#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 32371#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 32372#(and (or (= |~#ldv_global_msg_list.offset| 0) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4))) (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 32373#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 32362#true, 32363#false, 32364#(= 0 |~#ldv_global_msg_list.offset|), 32365#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 32366#(not (= |ldv_malloc_#t~malloc4.base| 0)), 32367#(not (= |ldv_malloc_#res.base| 0))] [2018-02-04 03:06:45,825 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:45,825 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 03:06:45,825 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 03:06:45,825 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2018-02-04 03:06:45,826 INFO L87 Difference]: Start difference. First operand 465 states and 528 transitions. Second operand 12 states. [2018-02-04 03:06:46,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:46,312 INFO L93 Difference]: Finished difference Result 469 states and 529 transitions. [2018-02-04 03:06:46,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 03:06:46,312 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 48 [2018-02-04 03:06:46,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:46,313 INFO L225 Difference]: With dead ends: 469 [2018-02-04 03:06:46,313 INFO L226 Difference]: Without dead ends: 469 [2018-02-04 03:06:46,314 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 4 SyntacticMatches, 4 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=104, Invalid=402, Unknown=0, NotChecked=0, Total=506 [2018-02-04 03:06:46,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-04 03:06:46,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 463. [2018-02-04 03:06:46,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-04 03:06:46,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 524 transitions. [2018-02-04 03:06:46,317 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 524 transitions. Word has length 48 [2018-02-04 03:06:46,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:46,318 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 524 transitions. [2018-02-04 03:06:46,318 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 03:06:46,318 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 524 transitions. [2018-02-04 03:06:46,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 03:06:46,318 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:46,318 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:46,318 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:46,318 INFO L82 PathProgramCache]: Analyzing trace with hash 1800754789, now seen corresponding path program 1 times [2018-02-04 03:06:46,319 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:46,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:46,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:46,359 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:06:46,360 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:46,360 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:46,360 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:46,360 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:46,360 INFO L182 omatonBuilderFactory]: Interpolants [33328#true, 33329#false, 33330#(not (= |ldv_malloc_#t~malloc4.base| 0)), 33331#(not (= |ldv_malloc_#res.base| 0)), 33332#(not (= |entry_point_#t~ret64.base| 0)), 33333#(not (= entry_point_~addr~0.base 0))] [2018-02-04 03:06:46,360 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:06:46,361 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:46,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:46,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:46,361 INFO L87 Difference]: Start difference. First operand 463 states and 524 transitions. Second operand 6 states. [2018-02-04 03:06:46,389 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:46,389 INFO L93 Difference]: Finished difference Result 484 states and 549 transitions. [2018-02-04 03:06:46,390 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:46,390 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-02-04 03:06:46,390 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:46,391 INFO L225 Difference]: With dead ends: 484 [2018-02-04 03:06:46,391 INFO L226 Difference]: Without dead ends: 484 [2018-02-04 03:06:46,392 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:46,392 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 484 states. [2018-02-04 03:06:46,396 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 484 to 463. [2018-02-04 03:06:46,396 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-04 03:06:46,397 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 523 transitions. [2018-02-04 03:06:46,397 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 523 transitions. Word has length 48 [2018-02-04 03:06:46,397 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:46,397 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 523 transitions. [2018-02-04 03:06:46,397 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:46,397 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 523 transitions. [2018-02-04 03:06:46,398 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 03:06:46,398 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:46,398 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:46,398 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:46,398 INFO L82 PathProgramCache]: Analyzing trace with hash 1800754818, now seen corresponding path program 1 times [2018-02-04 03:06:46,399 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:46,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:46,408 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:46,673 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:46,674 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:46,674 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 03:06:46,674 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:46,674 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 1 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:06:46,674 INFO L182 omatonBuilderFactory]: Interpolants [34283#true, 34284#false, 34285#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (and (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0)) (<= |ldv_malloc_#in~size| ldv_malloc_~size))) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (div ldv_malloc_~size 4294967296) 0))), 34286#(or (and (or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (= 0 |ldv_malloc_#t~malloc4.offset|) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|))) (<= 2147483648 |ldv_malloc_#in~size|)) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1)) (<= 4294967296 |ldv_malloc_#in~size|)), 34287#(or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (= 0 |ldv_malloc_#res.offset|) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (= (select |#valid| |ldv_malloc_#res.base|) 1)) (<= 2147483648 |ldv_malloc_#in~size|)), 34288#(and (<= 20 (select |#length| |entry_point_#t~ret59.base|)) (= 0 |entry_point_#t~ret59.offset|) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 34289#(and (= (select |#valid| entry_point_~client~0.base) 1) (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 34290#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 34291#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 34292#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 34293#(and (= entry_point_~client~0.offset 0) (<= 20 (select |#length| entry_point_~client~0.base))), 34294#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 34295#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 03:06:46,674 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:46,675 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 03:06:46,675 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 03:06:46,675 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:06:46,675 INFO L87 Difference]: Start difference. First operand 463 states and 523 transitions. Second operand 13 states. [2018-02-04 03:06:48,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:48,115 INFO L93 Difference]: Finished difference Result 596 states and 688 transitions. [2018-02-04 03:06:48,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 03:06:48,116 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 48 [2018-02-04 03:06:48,116 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:48,117 INFO L225 Difference]: With dead ends: 596 [2018-02-04 03:06:48,117 INFO L226 Difference]: Without dead ends: 596 [2018-02-04 03:06:48,117 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=66, Invalid=240, Unknown=0, NotChecked=0, Total=306 [2018-02-04 03:06:48,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 596 states. [2018-02-04 03:06:48,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 596 to 456. [2018-02-04 03:06:48,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 456 states. [2018-02-04 03:06:48,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 456 states to 456 states and 513 transitions. [2018-02-04 03:06:48,121 INFO L78 Accepts]: Start accepts. Automaton has 456 states and 513 transitions. Word has length 48 [2018-02-04 03:06:48,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:48,121 INFO L432 AbstractCegarLoop]: Abstraction has 456 states and 513 transitions. [2018-02-04 03:06:48,121 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 03:06:48,121 INFO L276 IsEmpty]: Start isEmpty. Operand 456 states and 513 transitions. [2018-02-04 03:06:48,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 03:06:48,122 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:48,122 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:48,122 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:48,122 INFO L82 PathProgramCache]: Analyzing trace with hash -1693457593, now seen corresponding path program 1 times [2018-02-04 03:06:48,123 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:48,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:48,128 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:48,338 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-04 03:06:48,338 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:48,338 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 03:06:48,338 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:48,338 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 03:06:48,338 INFO L182 omatonBuilderFactory]: Interpolants [35360#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 35361#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 35362#(= 1 (select |#valid| |entry_point_#t~ret59.base|)), 35363#(= 1 (select |#valid| entry_point_~client~0.base)), 35364#(= |#valid| |old(#valid)|), 35365#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 35366#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 35367#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= |entry_point_#t~ret60.base| entry_point_~client~0.base))), 35368#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 35369#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35370#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 35371#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 35372#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35373#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 35358#true, 35359#false] [2018-02-04 03:06:48,338 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 11 proven. 12 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-04 03:06:48,339 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 03:06:48,339 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 03:06:48,339 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2018-02-04 03:06:48,339 INFO L87 Difference]: Start difference. First operand 456 states and 513 transitions. Second operand 16 states. [2018-02-04 03:06:49,099 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:49,099 INFO L93 Difference]: Finished difference Result 517 states and 587 transitions. [2018-02-04 03:06:49,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 03:06:49,100 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 48 [2018-02-04 03:06:49,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:49,101 INFO L225 Difference]: With dead ends: 517 [2018-02-04 03:06:49,101 INFO L226 Difference]: Without dead ends: 517 [2018-02-04 03:06:49,101 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 3 SyntacticMatches, 5 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-02-04 03:06:49,101 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 517 states. [2018-02-04 03:06:49,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 517 to 457. [2018-02-04 03:06:49,104 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 457 states. [2018-02-04 03:06:49,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 514 transitions. [2018-02-04 03:06:49,105 INFO L78 Accepts]: Start accepts. Automaton has 457 states and 514 transitions. Word has length 48 [2018-02-04 03:06:49,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:49,105 INFO L432 AbstractCegarLoop]: Abstraction has 457 states and 514 transitions. [2018-02-04 03:06:49,105 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 03:06:49,105 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 514 transitions. [2018-02-04 03:06:49,105 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-04 03:06:49,105 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:49,105 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:49,105 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:49,105 INFO L82 PathProgramCache]: Analyzing trace with hash -1108813627, now seen corresponding path program 1 times [2018-02-04 03:06:49,106 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:49,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:49,115 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:49,472 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:06:49,473 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:49,473 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 03:06:49,473 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:49,474 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 03:06:49,474 INFO L182 omatonBuilderFactory]: Interpolants [36354#true, 36355#false, 36356#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 36357#(= |#valid| |old(#valid)|), 36358#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 36359#(and (or (= (@diff |old(#valid)| |#valid|) |ldv_malloc_#res.base|) (= |#valid| |old(#valid)|)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 36360#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 36361#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 36362#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 36363#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 36364#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret60.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 36365#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 36366#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 36367#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:06:49,474 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:06:49,474 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 03:06:49,474 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 03:06:49,475 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=143, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:06:49,475 INFO L87 Difference]: Start difference. First operand 457 states and 514 transitions. Second operand 14 states. [2018-02-04 03:06:50,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:50,261 INFO L93 Difference]: Finished difference Result 551 states and 611 transitions. [2018-02-04 03:06:50,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 03:06:50,261 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 51 [2018-02-04 03:06:50,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:50,263 INFO L225 Difference]: With dead ends: 551 [2018-02-04 03:06:50,263 INFO L226 Difference]: Without dead ends: 551 [2018-02-04 03:06:50,263 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 9 SyntacticMatches, 8 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=56, Invalid=216, Unknown=0, NotChecked=0, Total=272 [2018-02-04 03:06:50,263 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-02-04 03:06:50,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 460. [2018-02-04 03:06:50,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-04 03:06:50,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 518 transitions. [2018-02-04 03:06:50,267 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 518 transitions. Word has length 51 [2018-02-04 03:06:50,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:50,267 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 518 transitions. [2018-02-04 03:06:50,267 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 03:06:50,267 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 518 transitions. [2018-02-04 03:06:50,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-04 03:06:50,268 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:50,268 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:50,268 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:50,268 INFO L82 PathProgramCache]: Analyzing trace with hash -491855937, now seen corresponding path program 1 times [2018-02-04 03:06:50,269 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:50,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:50,279 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:50,709 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:50,709 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:50,709 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-04 03:06:50,710 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:50,710 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 03:06:50,710 INFO L182 omatonBuilderFactory]: Interpolants [37392#(and (not (= |entry_point_#t~ret60.base| 0)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))))) (not (= entry_point_~client~0.base 0))), 37393#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base 0))), 37394#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 37385#true, 37386#false, 37387#(= |#valid| |old(#valid)|), 37388#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 37389#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0))), 37390#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 37391#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 03:06:50,710 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:50,711 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 03:06:50,711 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 03:06:50,711 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-02-04 03:06:50,711 INFO L87 Difference]: Start difference. First operand 460 states and 518 transitions. Second operand 10 states. [2018-02-04 03:06:51,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:51,957 INFO L93 Difference]: Finished difference Result 520 states and 591 transitions. [2018-02-04 03:06:51,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 03:06:51,957 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 50 [2018-02-04 03:06:51,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:51,958 INFO L225 Difference]: With dead ends: 520 [2018-02-04 03:06:51,959 INFO L226 Difference]: Without dead ends: 503 [2018-02-04 03:06:51,959 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 10 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=33, Invalid=123, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:06:51,959 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-04 03:06:51,963 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 446. [2018-02-04 03:06:51,963 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-02-04 03:06:51,964 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 503 transitions. [2018-02-04 03:06:51,964 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 503 transitions. Word has length 50 [2018-02-04 03:06:51,964 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:51,964 INFO L432 AbstractCegarLoop]: Abstraction has 446 states and 503 transitions. [2018-02-04 03:06:51,964 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 03:06:51,964 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 503 transitions. [2018-02-04 03:06:51,965 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-04 03:06:51,965 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:51,965 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:51,965 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:51,965 INFO L82 PathProgramCache]: Analyzing trace with hash -417997242, now seen corresponding path program 1 times [2018-02-04 03:06:51,966 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:51,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:51,978 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:52,168 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:06:52,168 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:52,168 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 03:06:52,169 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:52,169 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 03:06:52,169 INFO L182 omatonBuilderFactory]: Interpolants [38368#false, 38369#(= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)), 38370#(not (= |ldv_malloc_#t~malloc4.base| 0)), 38371#(not (= |ldv_malloc_#res.base| 0)), 38372#(and (not (= |entry_point_#t~ret59.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 38373#(and (not (= entry_point_~client~0.base 0)) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 38374#(and (or (and (not (= |entry_point_#t~ret60.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 38375#(and (or (and (or (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 38376#(and (or (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (not (= entry_point_~client~0.base 0))), 38377#(or (= 0 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 38378#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 38379#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base)), 38367#true] [2018-02-04 03:06:52,169 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:06:52,169 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 03:06:52,170 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 03:06:52,170 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:06:52,170 INFO L87 Difference]: Start difference. First operand 446 states and 503 transitions. Second operand 13 states. [2018-02-04 03:06:52,815 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:52,816 INFO L93 Difference]: Finished difference Result 485 states and 548 transitions. [2018-02-04 03:06:52,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 03:06:52,816 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 53 [2018-02-04 03:06:52,816 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:52,817 INFO L225 Difference]: With dead ends: 485 [2018-02-04 03:06:52,817 INFO L226 Difference]: Without dead ends: 485 [2018-02-04 03:06:52,817 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 4 SyntacticMatches, 7 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=455, Unknown=0, NotChecked=0, Total=552 [2018-02-04 03:06:52,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 485 states. [2018-02-04 03:06:52,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 485 to 462. [2018-02-04 03:06:52,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-04 03:06:52,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 529 transitions. [2018-02-04 03:06:52,823 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 529 transitions. Word has length 53 [2018-02-04 03:06:52,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:52,823 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 529 transitions. [2018-02-04 03:06:52,823 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 03:06:52,823 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 529 transitions. [2018-02-04 03:06:52,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-04 03:06:52,824 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:52,824 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:52,824 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:52,824 INFO L82 PathProgramCache]: Analyzing trace with hash -417997241, now seen corresponding path program 1 times [2018-02-04 03:06:52,825 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:52,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:52,835 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:53,210 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:06:53,211 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:53,211 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 03:06:53,212 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:53,213 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 03:06:53,213 INFO L182 omatonBuilderFactory]: Interpolants [39360#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 39361#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 39362#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 39349#true, 39350#false, 39351#(= 0 |~#ldv_global_msg_list.offset|), 39352#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 39353#(not (= |ldv_malloc_#t~malloc4.base| 0)), 39354#(not (= |ldv_malloc_#res.base| 0)), 39355#(and (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)), 39356#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39357#(and (or (and (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39358#(and (or (and (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (or (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base) (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 39359#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:06:53,213 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:06:53,213 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 03:06:53,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 03:06:53,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:06:53,214 INFO L87 Difference]: Start difference. First operand 462 states and 529 transitions. Second operand 14 states. [2018-02-04 03:06:54,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:54,266 INFO L93 Difference]: Finished difference Result 486 states and 549 transitions. [2018-02-04 03:06:54,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 03:06:54,267 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 53 [2018-02-04 03:06:54,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:54,268 INFO L225 Difference]: With dead ends: 486 [2018-02-04 03:06:54,268 INFO L226 Difference]: Without dead ends: 486 [2018-02-04 03:06:54,268 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 176 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=163, Invalid=767, Unknown=0, NotChecked=0, Total=930 [2018-02-04 03:06:54,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 486 states. [2018-02-04 03:06:54,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 486 to 462. [2018-02-04 03:06:54,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-04 03:06:54,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 528 transitions. [2018-02-04 03:06:54,272 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 528 transitions. Word has length 53 [2018-02-04 03:06:54,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:54,273 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 528 transitions. [2018-02-04 03:06:54,273 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 03:06:54,273 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 528 transitions. [2018-02-04 03:06:54,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-04 03:06:54,273 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:54,273 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:54,273 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:54,273 INFO L82 PathProgramCache]: Analyzing trace with hash -2129232769, now seen corresponding path program 1 times [2018-02-04 03:06:54,274 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:54,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:54,279 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:54,318 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-04 03:06:54,318 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:54,318 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:06:54,319 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:54,319 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:06:54,319 INFO L182 omatonBuilderFactory]: Interpolants [40346#true, 40347#false, 40348#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 40349#(and (= 0 |entry_point_#t~ret64.offset|) (= 0 |entry_point_#t~ret64.base|)), 40350#(and (= entry_point_~addr~0.offset 0) (= entry_point_~addr~0.base 0))] [2018-02-04 03:06:54,319 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-04 03:06:54,319 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:54,320 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:54,320 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:54,320 INFO L87 Difference]: Start difference. First operand 462 states and 528 transitions. Second operand 5 states. [2018-02-04 03:06:54,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:54,332 INFO L93 Difference]: Finished difference Result 464 states and 529 transitions. [2018-02-04 03:06:54,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:06:54,333 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 54 [2018-02-04 03:06:54,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:54,334 INFO L225 Difference]: With dead ends: 464 [2018-02-04 03:06:54,334 INFO L226 Difference]: Without dead ends: 464 [2018-02-04 03:06:54,335 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:54,335 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 464 states. [2018-02-04 03:06:54,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 464 to 462. [2018-02-04 03:06:54,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-04 03:06:54,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 527 transitions. [2018-02-04 03:06:54,340 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 527 transitions. Word has length 54 [2018-02-04 03:06:54,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:54,341 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 527 transitions. [2018-02-04 03:06:54,341 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:54,341 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 527 transitions. [2018-02-04 03:06:54,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 03:06:54,341 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:54,341 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:54,341 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:54,342 INFO L82 PathProgramCache]: Analyzing trace with hash 1178383201, now seen corresponding path program 2 times [2018-02-04 03:06:54,342 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:54,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:54,350 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:54,382 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-04 03:06:54,383 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:54,383 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:06:54,383 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:54,383 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 03:06:54,383 INFO L182 omatonBuilderFactory]: Interpolants [41280#(= 0 |ldv_malloc_#res.offset|), 41281#(= 0 |entry_point_#t~ret64.offset|), 41282#(= entry_point_~addr~0.offset 0), 41277#true, 41278#false, 41279#(= 0 |ldv_malloc_#t~malloc4.offset|)] [2018-02-04 03:06:54,384 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-04 03:06:54,384 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:54,384 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:54,384 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:54,384 INFO L87 Difference]: Start difference. First operand 462 states and 527 transitions. Second operand 6 states. [2018-02-04 03:06:54,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:54,404 INFO L93 Difference]: Finished difference Result 461 states and 525 transitions. [2018-02-04 03:06:54,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:54,405 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 56 [2018-02-04 03:06:54,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:54,407 INFO L225 Difference]: With dead ends: 461 [2018-02-04 03:06:54,407 INFO L226 Difference]: Without dead ends: 461 [2018-02-04 03:06:54,407 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:54,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 461 states. [2018-02-04 03:06:54,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 461 to 461. [2018-02-04 03:06:54,412 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-04 03:06:54,413 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 525 transitions. [2018-02-04 03:06:54,413 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 525 transitions. Word has length 56 [2018-02-04 03:06:54,413 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:54,413 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 525 transitions. [2018-02-04 03:06:54,413 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:54,413 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 525 transitions. [2018-02-04 03:06:54,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 03:06:54,414 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:54,414 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:54,414 INFO L371 AbstractCegarLoop]: === Iteration 42 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:54,414 INFO L82 PathProgramCache]: Analyzing trace with hash 1178383202, now seen corresponding path program 1 times [2018-02-04 03:06:54,415 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:54,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:54,422 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:54,462 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:06:54,462 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:54,462 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-04 03:06:54,462 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:54,463 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 03:06:54,463 INFO L182 omatonBuilderFactory]: Interpolants [42208#false, 42209#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 42210#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 42211#(= 1 (select |#valid| |entry_point_#t~ret64.base|)), 42212#(= 1 (select |#valid| entry_point_~addr~0.base)), 42213#(= |#valid| |old(#valid)|), 42207#true] [2018-02-04 03:06:54,463 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 23 proven. 2 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:06:54,463 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:54,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:54,463 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:54,463 INFO L87 Difference]: Start difference. First operand 461 states and 525 transitions. Second operand 7 states. [2018-02-04 03:06:54,998 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:54,998 INFO L93 Difference]: Finished difference Result 526 states and 607 transitions. [2018-02-04 03:06:54,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:54,999 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 56 [2018-02-04 03:06:54,999 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:55,000 INFO L225 Difference]: With dead ends: 526 [2018-02-04 03:06:55,000 INFO L226 Difference]: Without dead ends: 526 [2018-02-04 03:06:55,000 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 03:06:55,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states. [2018-02-04 03:06:55,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 464. [2018-02-04 03:06:55,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-04 03:06:55,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 529 transitions. [2018-02-04 03:06:55,005 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 529 transitions. Word has length 56 [2018-02-04 03:06:55,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:55,006 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 529 transitions. [2018-02-04 03:06:55,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:55,006 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 529 transitions. [2018-02-04 03:06:55,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-04 03:06:55,006 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:55,006 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:55,006 INFO L371 AbstractCegarLoop]: === Iteration 43 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:55,006 INFO L82 PathProgramCache]: Analyzing trace with hash -2124826194, now seen corresponding path program 1 times [2018-02-04 03:06:55,007 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:55,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:55,015 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:55,129 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 31 proven. 7 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 03:06:55,129 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:55,129 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 03:06:55,129 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:55,130 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 5 proven. 3 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 03:06:55,130 INFO L182 omatonBuilderFactory]: Interpolants [43216#(and (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 43206#true, 43207#false, 43208#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 43209#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 43210#(= 1 (select |#valid| |entry_point_#t~ret62.base|)), 43211#(= 1 (select |#valid| entry_point_~fe~2.base)), 43212#(= |#valid| |old(#valid)|), 43213#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 43214#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 43215#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= |entry_point_#t~ret64.base| entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~fe~2.base)))] [2018-02-04 03:06:55,130 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 31 proven. 7 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 03:06:55,130 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:06:55,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:06:55,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:06:55,131 INFO L87 Difference]: Start difference. First operand 464 states and 529 transitions. Second operand 11 states. [2018-02-04 03:06:55,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:55,982 INFO L93 Difference]: Finished difference Result 522 states and 600 transitions. [2018-02-04 03:06:55,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 03:06:55,982 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 57 [2018-02-04 03:06:55,982 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:55,983 INFO L225 Difference]: With dead ends: 522 [2018-02-04 03:06:55,983 INFO L226 Difference]: Without dead ends: 522 [2018-02-04 03:06:55,983 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=32, Invalid=124, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:06:55,984 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 522 states. [2018-02-04 03:06:55,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 522 to 464. [2018-02-04 03:06:55,987 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-04 03:06:55,987 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 528 transitions. [2018-02-04 03:06:55,988 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 528 transitions. Word has length 57 [2018-02-04 03:06:55,988 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:55,988 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 528 transitions. [2018-02-04 03:06:55,988 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:06:55,988 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 528 transitions. [2018-02-04 03:06:55,988 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-02-04 03:06:55,989 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:55,989 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:55,989 INFO L371 AbstractCegarLoop]: === Iteration 44 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:55,989 INFO L82 PathProgramCache]: Analyzing trace with hash -2124824882, now seen corresponding path program 1 times [2018-02-04 03:06:55,990 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:55,997 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:55,998 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:56,036 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-04 03:06:56,037 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:56,037 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:06:56,037 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:56,037 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-04 03:06:56,037 INFO L182 omatonBuilderFactory]: Interpolants [44208#false, 44209#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 44210#(and (= 0 |entry_point_#t~ret66.base|) (= 0 |entry_point_#t~ret66.offset|)), 44211#(and (= entry_point_~adapter~0.base 0) (= 0 entry_point_~adapter~0.offset)), 44207#true] [2018-02-04 03:06:56,037 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 44 trivial. 0 not checked. [2018-02-04 03:06:56,037 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:06:56,037 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:06:56,037 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:56,038 INFO L87 Difference]: Start difference. First operand 464 states and 528 transitions. Second operand 5 states. [2018-02-04 03:06:56,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:56,049 INFO L93 Difference]: Finished difference Result 469 states and 529 transitions. [2018-02-04 03:06:56,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:06:56,050 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 57 [2018-02-04 03:06:56,050 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:56,051 INFO L225 Difference]: With dead ends: 469 [2018-02-04 03:06:56,051 INFO L226 Difference]: Without dead ends: 469 [2018-02-04 03:06:56,051 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:06:56,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-04 03:06:56,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 464. [2018-02-04 03:06:56,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 464 states. [2018-02-04 03:06:56,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 464 states to 464 states and 527 transitions. [2018-02-04 03:06:56,054 INFO L78 Accepts]: Start accepts. Automaton has 464 states and 527 transitions. Word has length 57 [2018-02-04 03:06:56,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:56,054 INFO L432 AbstractCegarLoop]: Abstraction has 464 states and 527 transitions. [2018-02-04 03:06:56,054 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:06:56,055 INFO L276 IsEmpty]: Start isEmpty. Operand 464 states and 527 transitions. [2018-02-04 03:06:56,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-04 03:06:56,055 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:56,055 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:56,055 INFO L371 AbstractCegarLoop]: === Iteration 45 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:56,055 INFO L82 PathProgramCache]: Analyzing trace with hash 1982392068, now seen corresponding path program 1 times [2018-02-04 03:06:56,056 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:56,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:56,061 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:56,084 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:06:56,085 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:56,085 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:56,085 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:56,085 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:06:56,085 INFO L182 omatonBuilderFactory]: Interpolants [45145#true, 45146#false, 45147#(not (= |ldv_malloc_#t~malloc4.base| 0)), 45148#(not (= |ldv_malloc_#res.base| 0)), 45149#(not (= |entry_point_#t~ret66.base| 0)), 45150#(not (= entry_point_~adapter~0.base 0))] [2018-02-04 03:06:56,086 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:06:56,086 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:56,086 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:56,086 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:56,086 INFO L87 Difference]: Start difference. First operand 464 states and 527 transitions. Second operand 6 states. [2018-02-04 03:06:56,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:56,109 INFO L93 Difference]: Finished difference Result 467 states and 526 transitions. [2018-02-04 03:06:56,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:56,110 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 58 [2018-02-04 03:06:56,110 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:56,112 INFO L225 Difference]: With dead ends: 467 [2018-02-04 03:06:56,112 INFO L226 Difference]: Without dead ends: 467 [2018-02-04 03:06:56,112 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:56,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 467 states. [2018-02-04 03:06:56,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 467 to 463. [2018-02-04 03:06:56,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-04 03:06:56,117 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 524 transitions. [2018-02-04 03:06:56,118 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 524 transitions. Word has length 58 [2018-02-04 03:06:56,118 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:56,118 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 524 transitions. [2018-02-04 03:06:56,118 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:56,118 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 524 transitions. [2018-02-04 03:06:56,118 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-04 03:06:56,119 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:56,119 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:56,119 INFO L371 AbstractCegarLoop]: === Iteration 46 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:56,119 INFO L82 PathProgramCache]: Analyzing trace with hash -1445102362, now seen corresponding path program 1 times [2018-02-04 03:06:56,120 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:56,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:56,128 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:56,355 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 30 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:56,355 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:56,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 03:06:56,355 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:56,356 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:56,356 INFO L182 omatonBuilderFactory]: Interpolants [46083#true, 46084#false, 46085#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 46086#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 46087#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 46088#(= 1 (select |#valid| entry_point_~cfg~2.base)), 46089#(= |#valid| |old(#valid)|), 46090#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 46091#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 46092#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 46093#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 46094#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 46095#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 46096#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 46097#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret64.base|))), 46098#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)))] [2018-02-04 03:06:56,356 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 30 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 03:06:56,356 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 03:06:56,356 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 03:06:56,356 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=39, Invalid=201, Unknown=0, NotChecked=0, Total=240 [2018-02-04 03:06:56,356 INFO L87 Difference]: Start difference. First operand 463 states and 524 transitions. Second operand 16 states. [2018-02-04 03:06:57,087 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:57,087 INFO L93 Difference]: Finished difference Result 520 states and 595 transitions. [2018-02-04 03:06:57,087 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 03:06:57,087 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 58 [2018-02-04 03:06:57,087 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:57,088 INFO L225 Difference]: With dead ends: 520 [2018-02-04 03:06:57,088 INFO L226 Difference]: Without dead ends: 520 [2018-02-04 03:06:57,089 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 3 SyntacticMatches, 4 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-02-04 03:06:57,089 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 520 states. [2018-02-04 03:06:57,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 520 to 463. [2018-02-04 03:06:57,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-04 03:06:57,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 523 transitions. [2018-02-04 03:06:57,092 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 523 transitions. Word has length 58 [2018-02-04 03:06:57,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:57,093 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 523 transitions. [2018-02-04 03:06:57,093 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 03:06:57,093 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 523 transitions. [2018-02-04 03:06:57,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 03:06:57,093 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:57,093 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:57,093 INFO L371 AbstractCegarLoop]: === Iteration 47 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:57,093 INFO L82 PathProgramCache]: Analyzing trace with hash -1825799813, now seen corresponding path program 1 times [2018-02-04 03:06:57,094 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:57,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:57,102 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:57,530 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:06:57,530 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:57,530 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 03:06:57,530 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:57,531 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-02-04 03:06:57,531 INFO L182 omatonBuilderFactory]: Interpolants [47088#true, 47089#false, 47090#(= 0 |~#ldv_global_msg_list.offset|), 47091#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|))), 47092#(not (= |ldv_malloc_#t~malloc4.base| 0)), 47093#(not (= |ldv_malloc_#res.base| 0)), 47094#(and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret59.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 47095#(and (not (= entry_point_~client~0.base 0)) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 47096#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 47097#(and (or (and (or (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (or (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))), 47098#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|))) (not (= entry_point_~client~0.base 0))), 47099#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 47100#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 47101#(and (or (and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)) (< (+ ldv_destroy_msgs_~msg~1.offset 4) |~#ldv_global_msg_list.offset|)) (or (= |~#ldv_global_msg_list.offset| 0) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)))), 47102#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|))] [2018-02-04 03:06:57,531 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:06:57,531 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 03:06:57,532 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 03:06:57,532 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=173, Unknown=0, NotChecked=0, Total=210 [2018-02-04 03:06:57,532 INFO L87 Difference]: Start difference. First operand 463 states and 523 transitions. Second operand 15 states. [2018-02-04 03:06:58,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:58,454 INFO L93 Difference]: Finished difference Result 469 states and 523 transitions. [2018-02-04 03:06:58,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 03:06:58,454 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2018-02-04 03:06:58,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:58,455 INFO L225 Difference]: With dead ends: 469 [2018-02-04 03:06:58,455 INFO L226 Difference]: Without dead ends: 469 [2018-02-04 03:06:58,455 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 5 SyntacticMatches, 7 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 181 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=152, Invalid=718, Unknown=0, NotChecked=0, Total=870 [2018-02-04 03:06:58,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-04 03:06:58,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 461. [2018-02-04 03:06:58,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-04 03:06:58,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-04 03:06:58,459 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 59 [2018-02-04 03:06:58,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:58,459 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-04 03:06:58,459 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 03:06:58,459 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-04 03:06:58,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 03:06:58,459 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:58,460 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:58,460 INFO L371 AbstractCegarLoop]: === Iteration 48 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:58,460 INFO L82 PathProgramCache]: Analyzing trace with hash 1324613484, now seen corresponding path program 1 times [2018-02-04 03:06:58,460 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:58,467 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:58,468 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:58,499 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:06:58,499 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:58,499 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:06:58,499 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:58,500 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:06:58,500 INFO L182 omatonBuilderFactory]: Interpolants [48064#false, 48065#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 48066#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 48067#(= 1 (select |#valid| |entry_point_#t~ret66.base|)), 48068#(= 1 (select |#valid| entry_point_~adapter~0.base)), 48063#true] [2018-02-04 03:06:58,500 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:06:58,500 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:06:58,500 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:06:58,500 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:06:58,501 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 6 states. [2018-02-04 03:06:58,804 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:58,804 INFO L93 Difference]: Finished difference Result 460 states and 517 transitions. [2018-02-04 03:06:58,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:06:58,805 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 59 [2018-02-04 03:06:58,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:58,806 INFO L225 Difference]: With dead ends: 460 [2018-02-04 03:06:58,806 INFO L226 Difference]: Without dead ends: 460 [2018-02-04 03:06:58,806 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:58,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states. [2018-02-04 03:06:58,809 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 460. [2018-02-04 03:06:58,809 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-04 03:06:58,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 517 transitions. [2018-02-04 03:06:58,810 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 517 transitions. Word has length 59 [2018-02-04 03:06:58,810 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:58,810 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 517 transitions. [2018-02-04 03:06:58,810 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:06:58,810 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 517 transitions. [2018-02-04 03:06:58,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 03:06:58,810 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:58,810 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:58,810 INFO L371 AbstractCegarLoop]: === Iteration 49 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:58,811 INFO L82 PathProgramCache]: Analyzing trace with hash 1324613485, now seen corresponding path program 1 times [2018-02-04 03:06:58,811 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:58,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:58,818 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:58,916 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-02-04 03:06:58,916 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:06:58,916 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:06:58,916 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:58,916 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 03:06:58,916 INFO L182 omatonBuilderFactory]: Interpolants [48992#false, 48993#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (<= |ldv_malloc_#in~size| ldv_malloc_~size)) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0))), 48994#(and (= 0 |ldv_malloc_#t~malloc4.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 48995#(and (= 0 |ldv_malloc_#res.offset|) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= 2147483648 |ldv_malloc_#in~size|))), 48996#(and (<= 4 (select |#length| |entry_point_#t~ret66.base|)) (= 0 |entry_point_#t~ret66.offset|)), 48997#(and (<= 4 (select |#length| entry_point_~adapter~0.base)) (= 0 entry_point_~adapter~0.offset)), 48991#true] [2018-02-04 03:06:58,916 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-02-04 03:06:58,917 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:06:58,917 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:06:58,917 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:06:58,917 INFO L87 Difference]: Start difference. First operand 460 states and 517 transitions. Second operand 7 states. [2018-02-04 03:06:59,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:06:59,191 INFO L93 Difference]: Finished difference Result 459 states and 516 transitions. [2018-02-04 03:06:59,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:06:59,191 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 59 [2018-02-04 03:06:59,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:06:59,192 INFO L225 Difference]: With dead ends: 459 [2018-02-04 03:06:59,192 INFO L226 Difference]: Without dead ends: 459 [2018-02-04 03:06:59,193 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:06:59,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 459 states. [2018-02-04 03:06:59,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 459 to 459. [2018-02-04 03:06:59,196 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-04 03:06:59,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 516 transitions. [2018-02-04 03:06:59,196 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 516 transitions. Word has length 59 [2018-02-04 03:06:59,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:06:59,196 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 516 transitions. [2018-02-04 03:06:59,196 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:06:59,196 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 516 transitions. [2018-02-04 03:06:59,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 03:06:59,197 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:06:59,197 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:06:59,197 INFO L371 AbstractCegarLoop]: === Iteration 50 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:06:59,197 INFO L82 PathProgramCache]: Analyzing trace with hash -1848500046, now seen corresponding path program 1 times [2018-02-04 03:06:59,197 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:06:59,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:06:59,204 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:06:59,514 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 14 proven. 20 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:06:59,515 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:06:59,515 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-04 03:06:59,515 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:06:59,515 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 6 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-02-04 03:06:59,516 INFO L182 omatonBuilderFactory]: Interpolants [49920#true, 49921#false, 49922#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 49923#(= (select |#valid| |ldv_malloc_#res.base|) 1), 49924#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 49925#(= (select |#valid| entry_point_~client~0.base) 1), 49926#(= |#valid| |old(#valid)|), 49927#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 49928#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 49929#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|))), 49930#(and (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 49931#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49932#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 49933#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 49934#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= (select |#valid| entry_point_~client~0.base) 1) (not (= |entry_point_#t~ret62.base| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49935#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49936#(and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49937#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 49938#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)))] [2018-02-04 03:06:59,516 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 14 proven. 20 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:06:59,516 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 03:06:59,516 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 03:06:59,516 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=290, Unknown=0, NotChecked=0, Total=342 [2018-02-04 03:06:59,516 INFO L87 Difference]: Start difference. First operand 459 states and 516 transitions. Second operand 19 states. [2018-02-04 03:07:00,323 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:00,323 INFO L93 Difference]: Finished difference Result 518 states and 587 transitions. [2018-02-04 03:07:00,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 03:07:00,323 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-02-04 03:07:00,323 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:00,324 INFO L225 Difference]: With dead ends: 518 [2018-02-04 03:07:00,324 INFO L226 Difference]: Without dead ends: 518 [2018-02-04 03:07:00,324 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 7 SyntacticMatches, 5 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=429, Unknown=0, NotChecked=0, Total=506 [2018-02-04 03:07:00,325 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 518 states. [2018-02-04 03:07:00,327 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 518 to 459. [2018-02-04 03:07:00,328 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-04 03:07:00,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 515 transitions. [2018-02-04 03:07:00,328 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 515 transitions. Word has length 59 [2018-02-04 03:07:00,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:00,328 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 515 transitions. [2018-02-04 03:07:00,328 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 03:07:00,328 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 515 transitions. [2018-02-04 03:07:00,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-02-04 03:07:00,329 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:00,329 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:00,329 INFO L371 AbstractCegarLoop]: === Iteration 51 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:00,329 INFO L82 PathProgramCache]: Analyzing trace with hash 1406279546, now seen corresponding path program 1 times [2018-02-04 03:07:00,329 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:00,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:00,337 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:00,707 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 4 proven. 12 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-04 03:07:00,708 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:00,708 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 03:07:00,708 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:00,708 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:07:00,709 INFO L182 omatonBuilderFactory]: Interpolants [50924#true, 50925#false, 50926#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 50927#(= |#valid| |old(#valid)|), 50928#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 50929#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 50930#(and (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 50931#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~client~0.base 0))), 50932#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 50933#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret60.base| 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 50934#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50935#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= (select |#valid| entry_point_~client~0.base) 1) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50936#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50937#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50938#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |entry_point_#t~ret64.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 50939#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:07:00,709 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 4 proven. 12 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-04 03:07:00,709 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 03:07:00,709 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 03:07:00,709 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=187, Unknown=0, NotChecked=0, Total=240 [2018-02-04 03:07:00,709 INFO L87 Difference]: Start difference. First operand 459 states and 515 transitions. Second operand 16 states. [2018-02-04 03:07:01,639 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:01,639 INFO L93 Difference]: Finished difference Result 547 states and 603 transitions. [2018-02-04 03:07:01,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 03:07:01,639 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 62 [2018-02-04 03:07:01,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:01,640 INFO L225 Difference]: With dead ends: 547 [2018-02-04 03:07:01,640 INFO L226 Difference]: Without dead ends: 547 [2018-02-04 03:07:01,641 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 13 SyntacticMatches, 7 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 85 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=100, Invalid=406, Unknown=0, NotChecked=0, Total=506 [2018-02-04 03:07:01,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-02-04 03:07:01,645 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 453. [2018-02-04 03:07:01,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 453 states. [2018-02-04 03:07:01,646 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 507 transitions. [2018-02-04 03:07:01,646 INFO L78 Accepts]: Start accepts. Automaton has 453 states and 507 transitions. Word has length 62 [2018-02-04 03:07:01,646 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:01,646 INFO L432 AbstractCegarLoop]: Abstraction has 453 states and 507 transitions. [2018-02-04 03:07:01,647 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 03:07:01,647 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 507 transitions. [2018-02-04 03:07:01,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-04 03:07:01,647 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:01,647 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:01,647 INFO L371 AbstractCegarLoop]: === Iteration 52 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:01,647 INFO L82 PathProgramCache]: Analyzing trace with hash 1796726022, now seen corresponding path program 1 times [2018-02-04 03:07:01,648 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:01,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:01,658 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:02,899 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:07:02,899 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:02,899 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 03:07:02,899 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:02,900 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 03:07:02,900 INFO L182 omatonBuilderFactory]: Interpolants [51968#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store |#valid| entry_point_~cfg~2.base 0) (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~cfg~2.base) (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 51969#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 51954#true, 51955#false, 51956#(= |#valid| |old(#valid)|), 51957#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 51958#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51959#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51960#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51961#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 51962#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= (select |#valid| |ldv_malloc_#res.base|) 1) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 51963#(and (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (= (select |#valid| |entry_point_#t~ret60.base|) 1))) (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base 0))), 51964#(and (not (= entry_point_~cfg~2.base 0)) (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |#valid| entry_point_~cfg~2.base) 1))) (not (= entry_point_~client~0.base 0))), 51965#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (= (select |#valid| entry_point_~client~0.base) 1) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |#valid| entry_point_~cfg~2.base) 1))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 51966#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (store (store (store |old(#valid)| |entry_point_#t~ret62.base| (select |#valid| |entry_point_#t~ret62.base|)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| |entry_point_#t~ret62.base|) 0) (not (= |entry_point_#t~ret62.base| entry_point_~client~0.base)))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 51967#(and (or (= entry_point_~cfg~2.base entry_point_~client~0.base) (and (not (= entry_point_~fe~2.base 0)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:07:02,900 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:07:02,901 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 03:07:02,901 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 03:07:02,901 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-04 03:07:02,901 INFO L87 Difference]: Start difference. First operand 453 states and 507 transitions. Second operand 16 states. [2018-02-04 03:07:04,664 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:04,664 INFO L93 Difference]: Finished difference Result 517 states and 584 transitions. [2018-02-04 03:07:04,664 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 03:07:04,664 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 61 [2018-02-04 03:07:04,664 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:04,665 INFO L225 Difference]: With dead ends: 517 [2018-02-04 03:07:04,665 INFO L226 Difference]: Without dead ends: 508 [2018-02-04 03:07:04,666 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 10 SyntacticMatches, 7 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 45 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=60, Invalid=320, Unknown=0, NotChecked=0, Total=380 [2018-02-04 03:07:04,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 508 states. [2018-02-04 03:07:04,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 508 to 451. [2018-02-04 03:07:04,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2018-02-04 03:07:04,671 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 504 transitions. [2018-02-04 03:07:04,671 INFO L78 Accepts]: Start accepts. Automaton has 451 states and 504 transitions. Word has length 61 [2018-02-04 03:07:04,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:04,683 INFO L432 AbstractCegarLoop]: Abstraction has 451 states and 504 transitions. [2018-02-04 03:07:04,683 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 03:07:04,683 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 504 transitions. [2018-02-04 03:07:04,683 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 03:07:04,683 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:04,683 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:04,683 INFO L371 AbstractCegarLoop]: === Iteration 53 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:04,683 INFO L82 PathProgramCache]: Analyzing trace with hash 169449372, now seen corresponding path program 1 times [2018-02-04 03:07:04,684 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:04,689 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:04,690 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:04,734 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-04 03:07:04,734 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:04,734 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 03:07:04,734 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:04,735 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 03:07:04,735 INFO L182 omatonBuilderFactory]: Interpolants [52946#true, 52947#false, 52948#(= (select |#valid| entry_point_~client~0.base) 1), 52949#(= (select |#valid| |alloc_12_#in~client.base|) 1), 52950#(= 1 (select |#valid| alloc_12_~client.base))] [2018-02-04 03:07:04,735 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-04 03:07:04,735 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:07:04,736 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:07:04,736 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:07:04,736 INFO L87 Difference]: Start difference. First operand 451 states and 504 transitions. Second operand 5 states. [2018-02-04 03:07:04,983 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:04,983 INFO L93 Difference]: Finished difference Result 450 states and 503 transitions. [2018-02-04 03:07:04,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:07:04,985 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 64 [2018-02-04 03:07:04,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:04,986 INFO L225 Difference]: With dead ends: 450 [2018-02-04 03:07:04,987 INFO L226 Difference]: Without dead ends: 450 [2018-02-04 03:07:04,987 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:07:04,987 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-02-04 03:07:04,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 450. [2018-02-04 03:07:04,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 450 states. [2018-02-04 03:07:04,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 450 states to 450 states and 503 transitions. [2018-02-04 03:07:04,993 INFO L78 Accepts]: Start accepts. Automaton has 450 states and 503 transitions. Word has length 64 [2018-02-04 03:07:04,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:04,993 INFO L432 AbstractCegarLoop]: Abstraction has 450 states and 503 transitions. [2018-02-04 03:07:04,993 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:07:04,993 INFO L276 IsEmpty]: Start isEmpty. Operand 450 states and 503 transitions. [2018-02-04 03:07:04,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 03:07:04,994 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:04,994 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:04,994 INFO L371 AbstractCegarLoop]: === Iteration 54 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:04,994 INFO L82 PathProgramCache]: Analyzing trace with hash 169449373, now seen corresponding path program 1 times [2018-02-04 03:07:04,995 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:05,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:05,005 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:05,104 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:07:05,104 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:05,104 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-04 03:07:05,104 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:05,104 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 03:07:05,105 INFO L182 omatonBuilderFactory]: Interpolants [53856#(= 0 |ldv_malloc_#res.offset|), 53857#(= 0 |entry_point_#t~ret59.offset|), 53858#(= 0 entry_point_~client~0.offset), 53859#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 0 entry_point_~client~0.offset) (<= 16 (select |#length| entry_point_~client~0.base))), 53860#(and (<= 16 (select |#length| |alloc_12_#in~client.base|)) (= 0 |alloc_12_#in~client.offset|) (= (select |#valid| |alloc_12_#in~client.base|) 1)), 53861#(and (= alloc_12_~client.offset 0) (= (select |#valid| alloc_12_~client.base) 1) (<= 16 (select |#length| alloc_12_~client.base))), 53862#(and (= alloc_12_~client.offset 0) (<= 16 (select |#length| alloc_12_~client.base))), 53853#true, 53854#false, 53855#(= 0 |ldv_malloc_#t~malloc4.offset|)] [2018-02-04 03:07:05,105 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:07:05,105 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 03:07:05,105 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 03:07:05,105 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=71, Unknown=0, NotChecked=0, Total=90 [2018-02-04 03:07:05,105 INFO L87 Difference]: Start difference. First operand 450 states and 503 transitions. Second operand 10 states. [2018-02-04 03:07:05,419 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:05,419 INFO L93 Difference]: Finished difference Result 449 states and 502 transitions. [2018-02-04 03:07:05,420 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:07:05,420 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 64 [2018-02-04 03:07:05,420 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:05,421 INFO L225 Difference]: With dead ends: 449 [2018-02-04 03:07:05,421 INFO L226 Difference]: Without dead ends: 449 [2018-02-04 03:07:05,422 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=104, Unknown=0, NotChecked=0, Total=132 [2018-02-04 03:07:05,422 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 449 states. [2018-02-04 03:07:05,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 449 to 449. [2018-02-04 03:07:05,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-04 03:07:05,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 502 transitions. [2018-02-04 03:07:05,428 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 502 transitions. Word has length 64 [2018-02-04 03:07:05,428 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:05,428 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 502 transitions. [2018-02-04 03:07:05,428 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 03:07:05,428 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 502 transitions. [2018-02-04 03:07:05,429 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-04 03:07:05,429 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:05,429 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:05,429 INFO L371 AbstractCegarLoop]: === Iteration 55 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:05,429 INFO L82 PathProgramCache]: Analyzing trace with hash -367900259, now seen corresponding path program 1 times [2018-02-04 03:07:05,430 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:05,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:05,444 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:05,795 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 27 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 03:07:05,795 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:05,795 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-04 03:07:05,795 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:05,796 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 17 proven. 3 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 03:07:05,796 INFO L182 omatonBuilderFactory]: Interpolants [54784#(and (or (= entry_point_~adapter~0.base (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) (= 1 (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)))) (not (= entry_point_~client~0.base entry_point_~adapter~0.base))), 54785#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|))), 54786#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset))), 54787#(= 1 (select |#valid| |alloc_12_#t~mem46.base|)), 54788#(= 1 (select |#valid| alloc_12_~cfg~0.base)), 54765#true, 54766#false, 54767#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 54768#(= (select |#valid| |ldv_malloc_#res.base|) 1), 54769#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 54770#(= (select |#valid| entry_point_~client~0.base) 1), 54771#(= |#valid| |old(#valid)|), 54772#(= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)), 54773#(= 0 (select |old(#valid)| |ldv_malloc_#res.base|)), 54774#(not (= entry_point_~client~0.base |entry_point_#t~ret60.base|)), 54775#(not (= entry_point_~client~0.base entry_point_~cfg~2.base)), 54776#(and (= (select |#valid| entry_point_~client~0.base) 1) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54777#(and (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54778#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 54779#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 54780#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 54781#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)))), 54782#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 54783#(and (or (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= |entry_point_#t~ret66.base| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|)))] [2018-02-04 03:07:05,796 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 27 proven. 20 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 03:07:05,796 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 03:07:05,796 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 03:07:05,796 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=496, Unknown=0, NotChecked=0, Total=552 [2018-02-04 03:07:05,796 INFO L87 Difference]: Start difference. First operand 449 states and 502 transitions. Second operand 24 states. [2018-02-04 03:07:07,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:07,750 INFO L93 Difference]: Finished difference Result 549 states and 629 transitions. [2018-02-04 03:07:07,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 03:07:07,750 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 66 [2018-02-04 03:07:07,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:07,752 INFO L225 Difference]: With dead ends: 549 [2018-02-04 03:07:07,752 INFO L226 Difference]: Without dead ends: 549 [2018-02-04 03:07:07,752 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 7 SyntacticMatches, 3 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 254 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=163, Invalid=1397, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 03:07:07,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 549 states. [2018-02-04 03:07:07,757 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 549 to 447. [2018-02-04 03:07:07,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 447 states. [2018-02-04 03:07:07,758 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 447 states to 447 states and 500 transitions. [2018-02-04 03:07:07,758 INFO L78 Accepts]: Start accepts. Automaton has 447 states and 500 transitions. Word has length 66 [2018-02-04 03:07:07,758 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:07,758 INFO L432 AbstractCegarLoop]: Abstraction has 447 states and 500 transitions. [2018-02-04 03:07:07,758 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 03:07:07,758 INFO L276 IsEmpty]: Start isEmpty. Operand 447 states and 500 transitions. [2018-02-04 03:07:07,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-04 03:07:07,758 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:07,758 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:07,759 INFO L371 AbstractCegarLoop]: === Iteration 56 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:07,759 INFO L82 PathProgramCache]: Analyzing trace with hash -367900258, now seen corresponding path program 1 times [2018-02-04 03:07:07,759 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:07,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:07,773 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:08,462 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 30 proven. 24 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 03:07:08,462 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:08,462 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-04 03:07:08,462 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:08,462 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 16 proven. 5 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 03:07:08,462 INFO L182 omatonBuilderFactory]: Interpolants [55817#true, 55818#false, 55819#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1), 55820#(= (select |#valid| |ldv_malloc_#res.base|) 1), 55821#(= (select |#valid| |entry_point_#t~ret59.base|) 1), 55822#(= (select |#valid| entry_point_~client~0.base) 1), 55823#(= |#valid| |old(#valid)|), 55824#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|)), 55825#(and (= 0 |ldv_malloc_#res.offset|) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|))), 55826#(and (= 0 |entry_point_#t~ret60.offset|) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|))), 55827#(and (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= 0 entry_point_~cfg~2.offset)), 55828#(and (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (= entry_point_~cfg~2.offset 0) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (= entry_point_~cfg~2.base (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))), 55829#(and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset))), 55830#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 55831#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 55832#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 55833#(and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 0))), 55834#(and (= (select |#valid| entry_point_~client~0.base) 1) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 0))), 55835#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 55836#(and (or (= |#valid| |old(#valid)|) (and (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= 0 |ldv_malloc_#res.offset|) (= (select |#length| |ldv_malloc_#res.base|) (select |#length| (@diff |old(#valid)| |#valid|))))) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (and (= (select |#length| |ldv_malloc_#res.base|) (select |#length| (@diff |old(#length)| |#length|))) (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| (@diff |old(#length)| |#length|)) 1)) (= |old(#length)| |#length|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 55837#(and (or (and (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 0))) (and (= (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset)) 1) (= (select |#length| |entry_point_#t~ret66.base|) (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset))) (= 0 |entry_point_#t~ret66.offset|))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset)) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|))), 55838#(and (or (and (= (select |#length| entry_point_~adapter~0.base) (select |#length| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset))) (= 0 entry_point_~adapter~0.offset) (= (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) 1)) (and (<= 4 (select |#length| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset))) (not (= (select |#valid| (select (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base) entry_point_~client~0.offset)) 0)))) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (= 0 (select (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.offset) entry_point_~client~0.offset))), 55839#(and (= 0 (select (select |#memory_$Pointer$.offset| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|)) 0)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| |alloc_12_#in~client.base|) |alloc_12_#in~client.offset|)))), 55840#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_12_~client.base) alloc_12_~client.offset)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset)) 0))), 55841#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_12_~client.base) alloc_12_~client.offset)) (<= 4 (select |#length| (select (select |#memory_$Pointer$.base| alloc_12_~client.base) alloc_12_~client.offset)))), 55842#(and (= 0 |alloc_12_#t~mem46.offset|) (<= 4 (select |#length| |alloc_12_#t~mem46.base|))), 55843#(and (= alloc_12_~cfg~0.offset 0) (< 3 (select |#length| alloc_12_~cfg~0.base)))] [2018-02-04 03:07:08,463 INFO L134 CoverageAnalysis]: Checked inductivity of 60 backedges. 30 proven. 24 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 03:07:08,463 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 03:07:08,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 03:07:08,463 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=639, Unknown=0, NotChecked=0, Total=702 [2018-02-04 03:07:08,463 INFO L87 Difference]: Start difference. First operand 447 states and 500 transitions. Second operand 27 states. [2018-02-04 03:07:11,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:11,631 INFO L93 Difference]: Finished difference Result 557 states and 637 transitions. [2018-02-04 03:07:11,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-04 03:07:11,632 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 66 [2018-02-04 03:07:11,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:11,633 INFO L225 Difference]: With dead ends: 557 [2018-02-04 03:07:11,633 INFO L226 Difference]: Without dead ends: 557 [2018-02-04 03:07:11,633 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 2 SyntacticMatches, 6 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 273 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=186, Invalid=1706, Unknown=0, NotChecked=0, Total=1892 [2018-02-04 03:07:11,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-02-04 03:07:11,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 449. [2018-02-04 03:07:11,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 449 states. [2018-02-04 03:07:11,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 449 states to 449 states and 506 transitions. [2018-02-04 03:07:11,638 INFO L78 Accepts]: Start accepts. Automaton has 449 states and 506 transitions. Word has length 66 [2018-02-04 03:07:11,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:11,638 INFO L432 AbstractCegarLoop]: Abstraction has 449 states and 506 transitions. [2018-02-04 03:07:11,638 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 03:07:11,638 INFO L276 IsEmpty]: Start isEmpty. Operand 449 states and 506 transitions. [2018-02-04 03:07:11,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-02-04 03:07:11,639 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:11,639 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:11,639 INFO L371 AbstractCegarLoop]: === Iteration 57 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:11,639 INFO L82 PathProgramCache]: Analyzing trace with hash 1079248251, now seen corresponding path program 1 times [2018-02-04 03:07:11,640 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:11,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:11,654 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:15,924 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-04 03:07:15,924 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:15,924 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-04 03:07:15,924 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:15,925 INFO L134 CoverageAnalysis]: Checked inductivity of 16 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 03:07:15,925 INFO L182 omatonBuilderFactory]: Interpolants [56896#(and (not (= |entry_point_#t~ret62.base| 0)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (store (store (store |old(#valid)| |entry_point_#t~ret62.base| (select |#valid| |entry_point_#t~ret62.base|)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| |entry_point_#t~ret62.base|) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56897#(and (not (= entry_point_~fe~2.base 0)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56898#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |#valid|) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (= 1 (select |#valid| entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0))) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56899#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (not (= |entry_point_#t~ret64.base| entry_point_~cfg~2.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (or (= entry_point_~fe~2.base |entry_point_#t~ret64.base|) (and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (= (select |old(#valid)| |entry_point_#t~ret64.base|) 0) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= (select |old(#valid)| entry_point_~fe~2.base) 0) (= |#valid| (store (store (store (store |old(#valid)| entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base)) |entry_point_#t~ret64.base| (select |#valid| |entry_point_#t~ret64.base|))))) (not (= entry_point_~fe~2.base entry_point_~client~0.base)))) (not (= |entry_point_#t~ret64.base| 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56900#(and (or (= entry_point_~addr~0.base entry_point_~fe~2.base) (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= |#valid| (store (store (store (store |old(#valid)| entry_point_~addr~0.base (select |#valid| entry_point_~addr~0.base)) entry_point_~cfg~2.base (select |#valid| entry_point_~cfg~2.base)) entry_point_~fe~2.base (select |#valid| entry_point_~fe~2.base)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~addr~0.base) 0) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (not (= entry_point_~addr~0.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~fe~2.base) 0) (not (= entry_point_~addr~0.base entry_point_~client~0.base)))) (not (= entry_point_~addr~0.base 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56901#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (= (select |#valid| entry_point_~fe~2.base) 0) (and (= (store (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~cfg~2.base)) entry_point_~fe~2.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~fe~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~fe~2.base 0)) (= (select |old(#valid)| entry_point_~fe~2.base) (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~fe~2.base entry_point_~client~0.base)))) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56902#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= (store |#valid| entry_point_~cfg~2.base 0) (store (store |old(#valid)| entry_point_~cfg~2.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) entry_point_~client~0.base (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base))) (= (select |old(#valid)| entry_point_~cfg~2.base) (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~cfg~2.base)) (= (select |old(#valid)| entry_point_~client~0.base) 0))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 56903#(and (or (and (= (select |old(#valid)| entry_point_~client~0.base) (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (= (select |old(#valid)| (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))) (select (store |#valid| entry_point_~client~0.base 0) (@diff (store |old(#valid)| entry_point_~client~0.base (select (store |#valid| entry_point_~client~0.base 0) entry_point_~client~0.base)) (store |#valid| entry_point_~client~0.base 0))))) (= 0 (select |#valid| entry_point_~client~0.base))) (not (= entry_point_~client~0.base 0))), 56904#(and (= |#valid| |old(#valid)|) (= (select |#valid| |~#ldv_global_msg_list.base|) 1)), 56884#true, 56885#false, 56886#(= |#valid| |old(#valid)|), 56887#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 56888#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= |#valid| (store |old(#valid)| |ldv_malloc_#res.base| (select |#valid| |ldv_malloc_#res.base|))) (not (= |ldv_malloc_#res.base| 0))), 56889#(and (= (select |old(#valid)| |entry_point_#t~ret59.base|) 0) (not (= |entry_point_#t~ret59.base| 0)) (or (= |#valid| |old(#valid)|) (= (@diff |old(#valid)| |#valid|) |entry_point_#t~ret59.base|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56890#(and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (not (= entry_point_~client~0.base 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56891#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))) (= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|))), 56892#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (= 1 (select |#valid| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 56893#(and (not (= |entry_point_#t~ret60.base| 0)) (or (= entry_point_~client~0.base |entry_point_#t~ret60.base|) (and (= (select |old(#valid)| |entry_point_#t~ret60.base|) 0) (= 1 (select |#valid| |entry_point_#t~ret60.base|)) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= |#valid| (store (store |old(#valid)| |entry_point_#t~ret60.base| (select |#valid| |entry_point_#t~ret60.base|)) entry_point_~client~0.base (select |#valid| entry_point_~client~0.base))))) (not (= entry_point_~client~0.base 0))), 56894#(and (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (or (= entry_point_~client~0.base (@diff |old(#valid)| |#valid|)) (= entry_point_~cfg~2.base (@diff |old(#valid)| |#valid|))) (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= 1 (select |#valid| entry_point_~cfg~2.base)) (or (= entry_point_~client~0.base (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)) (= entry_point_~cfg~2.base (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))))) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base 0))), 56895#(and (= 1 (select |#valid| entry_point_~client~0.base)) (or (= entry_point_~client~0.base entry_point_~cfg~2.base) (and (= (select |old(#valid)| entry_point_~cfg~2.base) 0) (= |#valid| (store (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|) (select |#valid| (@diff (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))) |#valid|)))) (= (select |old(#valid)| entry_point_~client~0.base) 0) (= 1 (select |#valid| entry_point_~cfg~2.base)))) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)))] [2018-02-04 03:07:15,925 INFO L134 CoverageAnalysis]: Checked inductivity of 52 backedges. 3 proven. 14 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-04 03:07:15,925 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 03:07:15,925 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 03:07:15,926 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=371, Unknown=0, NotChecked=0, Total=420 [2018-02-04 03:07:15,926 INFO L87 Difference]: Start difference. First operand 449 states and 506 transitions. Second operand 21 states. [2018-02-04 03:07:18,189 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:18,189 INFO L93 Difference]: Finished difference Result 526 states and 588 transitions. [2018-02-04 03:07:18,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-04 03:07:18,190 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 72 [2018-02-04 03:07:18,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:18,191 INFO L225 Difference]: With dead ends: 526 [2018-02-04 03:07:18,191 INFO L226 Difference]: Without dead ends: 507 [2018-02-04 03:07:18,191 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 14 SyntacticMatches, 6 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 91 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=97, Invalid=605, Unknown=0, NotChecked=0, Total=702 [2018-02-04 03:07:18,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 507 states. [2018-02-04 03:07:18,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 507 to 437. [2018-02-04 03:07:18,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-02-04 03:07:18,194 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 493 transitions. [2018-02-04 03:07:18,194 INFO L78 Accepts]: Start accepts. Automaton has 437 states and 493 transitions. Word has length 72 [2018-02-04 03:07:18,194 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:18,194 INFO L432 AbstractCegarLoop]: Abstraction has 437 states and 493 transitions. [2018-02-04 03:07:18,194 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 03:07:18,194 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 493 transitions. [2018-02-04 03:07:18,195 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-04 03:07:18,195 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:18,195 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:18,195 INFO L371 AbstractCegarLoop]: === Iteration 58 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:18,195 INFO L82 PathProgramCache]: Analyzing trace with hash -1899930997, now seen corresponding path program 1 times [2018-02-04 03:07:18,196 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:18,200 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:18,201 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:18,255 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-04 03:07:18,255 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:18,255 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:07:18,255 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:18,255 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-02-04 03:07:18,255 INFO L182 omatonBuilderFactory]: Interpolants [57880#true, 57881#false, 57882#(and (= 0 |ldv_malloc_#res.offset|) (= 0 |ldv_malloc_#res.base|)), 57883#(and (= 0 |alloc_12_#t~ret48.base|) (= 0 |alloc_12_#t~ret48.offset|)), 57884#(and (= 0 alloc_12_~priv~0.offset) (= alloc_12_~priv~0.base 0))] [2018-02-04 03:07:18,255 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-04 03:07:18,256 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:07:18,256 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:07:18,256 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:07:18,256 INFO L87 Difference]: Start difference. First operand 437 states and 493 transitions. Second operand 5 states. [2018-02-04 03:07:18,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:18,271 INFO L93 Difference]: Finished difference Result 442 states and 494 transitions. [2018-02-04 03:07:18,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:07:18,271 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 75 [2018-02-04 03:07:18,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:18,272 INFO L225 Difference]: With dead ends: 442 [2018-02-04 03:07:18,272 INFO L226 Difference]: Without dead ends: 442 [2018-02-04 03:07:18,272 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:07:18,273 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 442 states. [2018-02-04 03:07:18,275 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 442 to 437. [2018-02-04 03:07:18,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 437 states. [2018-02-04 03:07:18,276 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 437 states to 437 states and 489 transitions. [2018-02-04 03:07:18,276 INFO L78 Accepts]: Start accepts. Automaton has 437 states and 489 transitions. Word has length 75 [2018-02-04 03:07:18,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:18,277 INFO L432 AbstractCegarLoop]: Abstraction has 437 states and 489 transitions. [2018-02-04 03:07:18,277 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:07:18,277 INFO L276 IsEmpty]: Start isEmpty. Operand 437 states and 489 transitions. [2018-02-04 03:07:18,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-02-04 03:07:18,277 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:18,277 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:18,277 INFO L371 AbstractCegarLoop]: === Iteration 59 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:18,278 INFO L82 PathProgramCache]: Analyzing trace with hash -2088439763, now seen corresponding path program 1 times [2018-02-04 03:07:18,278 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:18,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:18,288 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:18,350 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-04 03:07:18,350 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:18,350 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:07:18,350 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:18,351 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-02-04 03:07:18,351 INFO L182 omatonBuilderFactory]: Interpolants [58768#(= 1 (select |#valid| |alloc_12_#t~ret48.base|)), 58769#(= 1 (select |#valid| alloc_12_~priv~0.base)), 58764#true, 58765#false, 58766#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 58767#(= 1 (select |#valid| |ldv_malloc_#res.base|))] [2018-02-04 03:07:18,351 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-04 03:07:18,351 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:07:18,351 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:07:18,351 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:07:18,351 INFO L87 Difference]: Start difference. First operand 437 states and 489 transitions. Second operand 6 states. [2018-02-04 03:07:18,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:18,608 INFO L93 Difference]: Finished difference Result 436 states and 488 transitions. [2018-02-04 03:07:18,609 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:07:18,609 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 77 [2018-02-04 03:07:18,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:18,610 INFO L225 Difference]: With dead ends: 436 [2018-02-04 03:07:18,610 INFO L226 Difference]: Without dead ends: 436 [2018-02-04 03:07:18,610 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:18,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 436 states. [2018-02-04 03:07:18,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 436 to 435. [2018-02-04 03:07:18,614 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 435 states. [2018-02-04 03:07:18,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 435 states to 435 states and 487 transitions. [2018-02-04 03:07:18,615 INFO L78 Accepts]: Start accepts. Automaton has 435 states and 487 transitions. Word has length 77 [2018-02-04 03:07:18,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:18,616 INFO L432 AbstractCegarLoop]: Abstraction has 435 states and 487 transitions. [2018-02-04 03:07:18,616 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:07:18,616 INFO L276 IsEmpty]: Start isEmpty. Operand 435 states and 487 transitions. [2018-02-04 03:07:18,617 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-02-04 03:07:18,617 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:18,617 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:18,617 INFO L371 AbstractCegarLoop]: === Iteration 60 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:18,617 INFO L82 PathProgramCache]: Analyzing trace with hash -2088439761, now seen corresponding path program 1 times [2018-02-04 03:07:18,618 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:18,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:18,632 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:18,723 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-02-04 03:07:18,723 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:18,723 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:07:18,723 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:18,724 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:07:18,724 INFO L182 omatonBuilderFactory]: Interpolants [59648#(and (= 0 |alloc_12_#t~ret48.offset|) (<= 8 (select |#length| |alloc_12_#t~ret48.base|))), 59649#(and (= alloc_12_~priv~0.offset 0) (<= 8 (select |#length| alloc_12_~priv~0.base))), 59643#true, 59644#false, 59645#(or (= ldv_malloc_~size 8) (= |ldv_malloc_#in~size| ldv_malloc_~size)), 59646#(and (or (not (= |ldv_malloc_#in~size| 8)) (<= 8 (select |#length| |ldv_malloc_#t~malloc4.base|))) (= 0 |ldv_malloc_#t~malloc4.offset|)), 59647#(and (= 0 |ldv_malloc_#res.offset|) (or (<= 8 (select |#length| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#in~size| 8))))] [2018-02-04 03:07:18,724 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 25 proven. 0 refuted. 0 times theorem prover too weak. 65 trivial. 0 not checked. [2018-02-04 03:07:18,724 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:07:18,724 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:07:18,724 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:18,724 INFO L87 Difference]: Start difference. First operand 435 states and 487 transitions. Second operand 7 states. [2018-02-04 03:07:19,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:19,023 INFO L93 Difference]: Finished difference Result 439 states and 491 transitions. [2018-02-04 03:07:19,023 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:07:19,024 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 77 [2018-02-04 03:07:19,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:19,025 INFO L225 Difference]: With dead ends: 439 [2018-02-04 03:07:19,025 INFO L226 Difference]: Without dead ends: 439 [2018-02-04 03:07:19,025 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:07:19,025 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 439 states. [2018-02-04 03:07:19,030 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 439 to 433. [2018-02-04 03:07:19,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 433 states. [2018-02-04 03:07:19,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 433 states to 433 states and 485 transitions. [2018-02-04 03:07:19,030 INFO L78 Accepts]: Start accepts. Automaton has 433 states and 485 transitions. Word has length 77 [2018-02-04 03:07:19,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:19,031 INFO L432 AbstractCegarLoop]: Abstraction has 433 states and 485 transitions. [2018-02-04 03:07:19,031 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:07:19,031 INFO L276 IsEmpty]: Start isEmpty. Operand 433 states and 485 transitions. [2018-02-04 03:07:19,031 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-02-04 03:07:19,031 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:19,031 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:19,031 INFO L371 AbstractCegarLoop]: === Iteration 61 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:19,031 INFO L82 PathProgramCache]: Analyzing trace with hash -2088439760, now seen corresponding path program 1 times [2018-02-04 03:07:19,032 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:19,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:19,042 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:19,118 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-04 03:07:19,118 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:19,118 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:07:19,118 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:19,119 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 03:07:19,119 INFO L182 omatonBuilderFactory]: Interpolants [60528#(and (= (select |#valid| alloc_12_~cfg~0.base) 1) (<= (+ alloc_12_~cfg~0.offset 4) (select |#length| alloc_12_~cfg~0.base)) (< 0 (+ alloc_12_~cfg~0.offset 1))), 60529#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 60530#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 60531#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 60532#(and (<= (+ alloc_12_~cfg~0.offset 4) (select |#length| alloc_12_~cfg~0.base)) (< 0 (+ alloc_12_~cfg~0.offset 1))), 60526#true, 60527#false] [2018-02-04 03:07:19,119 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-02-04 03:07:19,119 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:07:19,119 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:07:19,119 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:19,120 INFO L87 Difference]: Start difference. First operand 433 states and 485 transitions. Second operand 7 states. [2018-02-04 03:07:19,840 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:19,840 INFO L93 Difference]: Finished difference Result 537 states and 613 transitions. [2018-02-04 03:07:19,840 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 03:07:19,840 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 77 [2018-02-04 03:07:19,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:19,841 INFO L225 Difference]: With dead ends: 537 [2018-02-04 03:07:19,841 INFO L226 Difference]: Without dead ends: 537 [2018-02-04 03:07:19,842 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:07:19,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 537 states. [2018-02-04 03:07:19,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 537 to 432. [2018-02-04 03:07:19,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 432 states. [2018-02-04 03:07:19,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 432 states to 432 states and 484 transitions. [2018-02-04 03:07:19,846 INFO L78 Accepts]: Start accepts. Automaton has 432 states and 484 transitions. Word has length 77 [2018-02-04 03:07:19,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:19,847 INFO L432 AbstractCegarLoop]: Abstraction has 432 states and 484 transitions. [2018-02-04 03:07:19,847 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:07:19,847 INFO L276 IsEmpty]: Start isEmpty. Operand 432 states and 484 transitions. [2018-02-04 03:07:19,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-04 03:07:19,848 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:19,848 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:19,848 INFO L371 AbstractCegarLoop]: === Iteration 62 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:19,848 INFO L82 PathProgramCache]: Analyzing trace with hash -1421195722, now seen corresponding path program 1 times [2018-02-04 03:07:19,849 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:19,859 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:19,859 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:19,936 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 12 proven. 2 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-02-04 03:07:19,936 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:19,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:07:19,936 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:19,937 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 03:07:19,937 INFO L182 omatonBuilderFactory]: Interpolants [61506#true, 61507#false, 61508#(= 0 |ldv_malloc_#t~malloc4.offset|), 61509#(= 0 |ldv_malloc_#res.offset|), 61510#(= 0 |entry_point_#t~ret66.offset|), 61511#(= 0 entry_point_~adapter~0.offset)] [2018-02-04 03:07:19,937 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 12 proven. 2 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-02-04 03:07:19,937 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:07:19,938 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:07:19,938 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:07:19,938 INFO L87 Difference]: Start difference. First operand 432 states and 484 transitions. Second operand 6 states. [2018-02-04 03:07:19,962 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:19,962 INFO L93 Difference]: Finished difference Result 431 states and 483 transitions. [2018-02-04 03:07:19,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:07:19,963 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 83 [2018-02-04 03:07:19,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:19,964 INFO L225 Difference]: With dead ends: 431 [2018-02-04 03:07:19,964 INFO L226 Difference]: Without dead ends: 431 [2018-02-04 03:07:19,964 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:19,965 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431 states. [2018-02-04 03:07:19,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431 to 431. [2018-02-04 03:07:19,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 431 states. [2018-02-04 03:07:19,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 431 states to 431 states and 483 transitions. [2018-02-04 03:07:19,970 INFO L78 Accepts]: Start accepts. Automaton has 431 states and 483 transitions. Word has length 83 [2018-02-04 03:07:19,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:19,970 INFO L432 AbstractCegarLoop]: Abstraction has 431 states and 483 transitions. [2018-02-04 03:07:19,970 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:07:19,970 INFO L276 IsEmpty]: Start isEmpty. Operand 431 states and 483 transitions. [2018-02-04 03:07:19,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-04 03:07:19,970 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:19,971 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:19,971 INFO L371 AbstractCegarLoop]: === Iteration 63 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:19,971 INFO L82 PathProgramCache]: Analyzing trace with hash -1421195721, now seen corresponding path program 1 times [2018-02-04 03:07:19,972 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:19,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:19,981 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:20,084 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 30 proven. 2 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:07:20,084 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:20,084 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 03:07:20,084 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:20,084 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:07:20,084 INFO L182 omatonBuilderFactory]: Interpolants [62384#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 62385#(and (= 0 |alloc_12_#t~ret48.base|) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= (select |old(#valid)| |alloc_12_~#chip_id~0.base|) 0)), 62386#(and (= alloc_12_~priv~0.base 0) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= (select |old(#valid)| |alloc_12_~#chip_id~0.base|) 0)), 62376#true, 62377#false, 62378#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 62379#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 62380#(= 1 (select |#valid| |entry_point_#t~ret66.base|)), 62381#(= 1 (select |#valid| entry_point_~adapter~0.base)), 62382#(= |#valid| |old(#valid)|), 62383#(and (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= (select |old(#valid)| |alloc_12_~#chip_id~0.base|) 0))] [2018-02-04 03:07:20,085 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 30 proven. 2 refuted. 0 times theorem prover too weak. 48 trivial. 0 not checked. [2018-02-04 03:07:20,085 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:07:20,085 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:07:20,085 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=88, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:07:20,085 INFO L87 Difference]: Start difference. First operand 431 states and 483 transitions. Second operand 11 states. [2018-02-04 03:07:20,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:20,892 INFO L93 Difference]: Finished difference Result 498 states and 566 transitions. [2018-02-04 03:07:20,892 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 03:07:20,893 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 83 [2018-02-04 03:07:20,893 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:20,894 INFO L225 Difference]: With dead ends: 498 [2018-02-04 03:07:20,894 INFO L226 Difference]: Without dead ends: 498 [2018-02-04 03:07:20,894 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:07:20,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 498 states. [2018-02-04 03:07:20,897 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 498 to 443. [2018-02-04 03:07:20,897 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 443 states. [2018-02-04 03:07:20,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 498 transitions. [2018-02-04 03:07:20,898 INFO L78 Accepts]: Start accepts. Automaton has 443 states and 498 transitions. Word has length 83 [2018-02-04 03:07:20,898 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:20,898 INFO L432 AbstractCegarLoop]: Abstraction has 443 states and 498 transitions. [2018-02-04 03:07:20,898 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:07:20,898 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 498 transitions. [2018-02-04 03:07:20,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-02-04 03:07:20,898 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:20,898 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:20,899 INFO L371 AbstractCegarLoop]: === Iteration 64 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:20,899 INFO L82 PathProgramCache]: Analyzing trace with hash -1107394187, now seen corresponding path program 1 times [2018-02-04 03:07:20,899 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:20,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:20,909 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:21,077 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 7 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2018-02-04 03:07:21,077 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:21,077 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 03:07:21,077 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:21,078 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 3 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-02-04 03:07:21,078 INFO L182 omatonBuilderFactory]: Interpolants [63332#true, 63333#false, 63334#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 63335#(= (select |#valid| |ldv_malloc_#res.base|) 1), 63336#(= (select |#valid| |entry_point_#t~ret64.base|) 1), 63337#(= (select |#valid| entry_point_~addr~0.base) 1), 63338#(= |#valid| |old(#valid)|), 63339#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 63340#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 63341#(and (not (= entry_point_~addr~0.base |entry_point_#t~ret66.base|)) (= (select |#valid| entry_point_~addr~0.base) 1) (not (= |entry_point_#t~ret66.base| 0))), 63342#(and (= (select |#valid| entry_point_~addr~0.base) 1) (not (= entry_point_~adapter~0.base entry_point_~addr~0.base)) (not (= entry_point_~adapter~0.base 0))), 63343#(and (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 63344#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 63345#(and (= 0 |alloc_12_#t~ret48.base|) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 63346#(and (= alloc_12_~priv~0.base 0) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 63347#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 03:07:21,078 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 44 proven. 7 refuted. 0 times theorem prover too weak. 29 trivial. 0 not checked. [2018-02-04 03:07:21,078 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 03:07:21,078 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 03:07:21,078 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=199, Unknown=0, NotChecked=0, Total=240 [2018-02-04 03:07:21,079 INFO L87 Difference]: Start difference. First operand 443 states and 498 transitions. Second operand 16 states. [2018-02-04 03:07:22,205 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:22,206 INFO L93 Difference]: Finished difference Result 527 states and 606 transitions. [2018-02-04 03:07:22,206 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 03:07:22,206 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 84 [2018-02-04 03:07:22,206 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:22,207 INFO L225 Difference]: With dead ends: 527 [2018-02-04 03:07:22,207 INFO L226 Difference]: Without dead ends: 527 [2018-02-04 03:07:22,207 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 5 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 34 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=60, Invalid=282, Unknown=0, NotChecked=0, Total=342 [2018-02-04 03:07:22,207 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2018-02-04 03:07:22,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 444. [2018-02-04 03:07:22,210 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 444 states. [2018-02-04 03:07:22,211 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 444 states to 444 states and 499 transitions. [2018-02-04 03:07:22,211 INFO L78 Accepts]: Start accepts. Automaton has 444 states and 499 transitions. Word has length 84 [2018-02-04 03:07:22,211 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:22,211 INFO L432 AbstractCegarLoop]: Abstraction has 444 states and 499 transitions. [2018-02-04 03:07:22,211 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 03:07:22,211 INFO L276 IsEmpty]: Start isEmpty. Operand 444 states and 499 transitions. [2018-02-04 03:07:22,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 03:07:22,211 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:22,212 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:22,212 INFO L371 AbstractCegarLoop]: === Iteration 65 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:22,212 INFO L82 PathProgramCache]: Analyzing trace with hash 30705212, now seen corresponding path program 1 times [2018-02-04 03:07:22,212 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:22,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:22,218 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:22,240 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-02-04 03:07:22,240 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:22,240 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 03:07:22,241 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:22,241 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-02-04 03:07:22,241 INFO L182 omatonBuilderFactory]: Interpolants [64325#true, 64326#false, 64327#(<= 3 alloc_12_~ret~2), 64328#(<= 3 |alloc_12_#res|), 64329#(<= 3 |entry_point_#t~ret69|)] [2018-02-04 03:07:22,241 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-02-04 03:07:22,241 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:07:22,241 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:07:22,241 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:07:22,241 INFO L87 Difference]: Start difference. First operand 444 states and 499 transitions. Second operand 5 states. [2018-02-04 03:07:22,260 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:22,260 INFO L93 Difference]: Finished difference Result 450 states and 502 transitions. [2018-02-04 03:07:22,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 03:07:22,260 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 85 [2018-02-04 03:07:22,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:22,261 INFO L225 Difference]: With dead ends: 450 [2018-02-04 03:07:22,261 INFO L226 Difference]: Without dead ends: 450 [2018-02-04 03:07:22,261 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:07:22,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-02-04 03:07:22,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 448. [2018-02-04 03:07:22,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 448 states. [2018-02-04 03:07:22,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 448 states to 448 states and 500 transitions. [2018-02-04 03:07:22,265 INFO L78 Accepts]: Start accepts. Automaton has 448 states and 500 transitions. Word has length 85 [2018-02-04 03:07:22,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:22,265 INFO L432 AbstractCegarLoop]: Abstraction has 448 states and 500 transitions. [2018-02-04 03:07:22,265 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:07:22,265 INFO L276 IsEmpty]: Start isEmpty. Operand 448 states and 500 transitions. [2018-02-04 03:07:22,265 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 03:07:22,265 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:22,265 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:22,266 INFO L371 AbstractCegarLoop]: === Iteration 66 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:22,266 INFO L82 PathProgramCache]: Analyzing trace with hash -722003495, now seen corresponding path program 1 times [2018-02-04 03:07:22,266 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:22,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:22,272 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:22,291 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-04 03:07:22,291 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:22,291 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 03:07:22,291 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:22,291 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-02-04 03:07:22,291 INFO L182 omatonBuilderFactory]: Interpolants [65232#(not (= |ldv_malloc_#t~malloc4.base| 0)), 65233#(not (= |ldv_malloc_#res.base| 0)), 65234#(not (= |alloc_12_#t~ret48.base| 0)), 65235#(not (= alloc_12_~priv~0.base 0)), 65230#true, 65231#false] [2018-02-04 03:07:22,292 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-04 03:07:22,292 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:07:22,292 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:07:22,292 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:07:22,292 INFO L87 Difference]: Start difference. First operand 448 states and 500 transitions. Second operand 6 states. [2018-02-04 03:07:22,313 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:22,314 INFO L93 Difference]: Finished difference Result 440 states and 491 transitions. [2018-02-04 03:07:22,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 03:07:22,314 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 85 [2018-02-04 03:07:22,314 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:22,315 INFO L225 Difference]: With dead ends: 440 [2018-02-04 03:07:22,315 INFO L226 Difference]: Without dead ends: 440 [2018-02-04 03:07:22,315 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:22,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 440 states. [2018-02-04 03:07:22,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 440 to 440. [2018-02-04 03:07:22,317 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 440 states. [2018-02-04 03:07:22,318 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 491 transitions. [2018-02-04 03:07:22,318 INFO L78 Accepts]: Start accepts. Automaton has 440 states and 491 transitions. Word has length 85 [2018-02-04 03:07:22,318 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:22,318 INFO L432 AbstractCegarLoop]: Abstraction has 440 states and 491 transitions. [2018-02-04 03:07:22,318 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:07:22,318 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 491 transitions. [2018-02-04 03:07:22,319 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 03:07:22,319 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:22,319 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:22,319 INFO L371 AbstractCegarLoop]: === Iteration 67 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:22,319 INFO L82 PathProgramCache]: Analyzing trace with hash 30518779, now seen corresponding path program 1 times [2018-02-04 03:07:22,319 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:22,332 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:22,333 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:22,705 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 48 proven. 12 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:07:22,705 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:22,705 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-04 03:07:22,706 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:22,706 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 10 proven. 6 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 03:07:22,706 INFO L182 omatonBuilderFactory]: Interpolants [66119#false, 66118#true, 66121#(= (select |#valid| |ldv_malloc_#res.base|) 1), 66120#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 66123#(= 1 (select |#valid| entry_point_~fe~2.base)), 66122#(= (select |#valid| |entry_point_#t~ret62.base|) 1), 66125#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 66124#(= |#valid| |old(#valid)|), 66127#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~fe~2.base |entry_point_#t~ret64.base|)) (= 1 (select |#valid| entry_point_~fe~2.base))), 66126#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 66129#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 66128#(and (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 66131#(and (not (= entry_point_~adapter~0.base entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~adapter~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 66130#(and (not (= entry_point_~fe~2.base |entry_point_#t~ret66.base|)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0)) (not (= entry_point_~addr~0.base entry_point_~fe~2.base))), 66133#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 66132#(and (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 66135#(and (= alloc_12_~priv~0.base 0) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 66134#(and (= 0 |alloc_12_#t~ret48.base|) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 66136#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 03:07:22,706 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 48 proven. 12 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 03:07:22,707 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 03:07:22,707 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 03:07:22,707 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=289, Unknown=0, NotChecked=0, Total=342 [2018-02-04 03:07:22,707 INFO L87 Difference]: Start difference. First operand 440 states and 491 transitions. Second operand 19 states. [2018-02-04 03:07:23,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:23,999 INFO L93 Difference]: Finished difference Result 526 states and 601 transitions. [2018-02-04 03:07:23,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 03:07:23,999 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 85 [2018-02-04 03:07:24,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:24,000 INFO L225 Difference]: With dead ends: 526 [2018-02-04 03:07:24,000 INFO L226 Difference]: Without dead ends: 526 [2018-02-04 03:07:24,000 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 29 GetRequests, 6 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=73, Invalid=389, Unknown=0, NotChecked=0, Total=462 [2018-02-04 03:07:24,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 526 states. [2018-02-04 03:07:24,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 526 to 441. [2018-02-04 03:07:24,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 441 states. [2018-02-04 03:07:24,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 492 transitions. [2018-02-04 03:07:24,005 INFO L78 Accepts]: Start accepts. Automaton has 441 states and 492 transitions. Word has length 85 [2018-02-04 03:07:24,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:24,005 INFO L432 AbstractCegarLoop]: Abstraction has 441 states and 492 transitions. [2018-02-04 03:07:24,005 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 03:07:24,005 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 492 transitions. [2018-02-04 03:07:24,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-02-04 03:07:24,006 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:24,006 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:24,006 INFO L371 AbstractCegarLoop]: === Iteration 68 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:24,006 INFO L82 PathProgramCache]: Analyzing trace with hash 946082361, now seen corresponding path program 1 times [2018-02-04 03:07:24,007 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:24,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:24,013 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:24,392 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 17 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 03:07:24,393 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:24,393 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-04 03:07:24,393 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:24,393 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 03:07:24,394 INFO L182 omatonBuilderFactory]: Interpolants [67111#false, 67110#true, 67113#(= 1 (select |#valid| |ldv_malloc_#res.base|)), 67112#(= 1 (select |#valid| |ldv_malloc_#t~malloc4.base|)), 67115#(= 1 (select |#valid| entry_point_~cfg~2.base)), 67114#(= 1 (select |#valid| |entry_point_#t~ret60.base|)), 67117#(and (= (select |old(#valid)| |ldv_malloc_#t~malloc4.base|) 0) (not (= |ldv_malloc_#t~malloc4.base| 0))), 67116#(= |#valid| |old(#valid)|), 67119#(and (not (= entry_point_~cfg~2.base |entry_point_#t~ret62.base|)) (not (= |entry_point_#t~ret62.base| 0))), 67118#(and (= (select |old(#valid)| |ldv_malloc_#res.base|) 0) (not (= |ldv_malloc_#res.base| 0))), 67121#(and (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 67120#(and (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base))), 67123#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 67122#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 67125#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 67124#(and (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret64.base|))), 67127#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~adapter~0.base)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~adapter~0.base 0)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base))), 67126#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~fe~2.base)) (not (= entry_point_~cfg~2.base |entry_point_#t~ret66.base|)) (not (= entry_point_~cfg~2.base entry_point_~addr~0.base)) (= (select |#valid| entry_point_~cfg~2.base) 1) (not (= 0 entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0))), 67129#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 67128#(and (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 67131#(and (= alloc_12_~priv~0.base 0) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 67130#(and (= 0 |alloc_12_#t~ret48.base|) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 67132#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 03:07:24,394 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 42 proven. 17 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 03:07:24,394 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 03:07:24,394 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 03:07:24,394 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=435, Unknown=0, NotChecked=0, Total=506 [2018-02-04 03:07:24,394 INFO L87 Difference]: Start difference. First operand 441 states and 492 transitions. Second operand 23 states. [2018-02-04 03:07:25,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:25,374 INFO L93 Difference]: Finished difference Result 527 states and 602 transitions. [2018-02-04 03:07:25,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 03:07:25,374 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 86 [2018-02-04 03:07:25,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:25,375 INFO L225 Difference]: With dead ends: 527 [2018-02-04 03:07:25,375 INFO L226 Difference]: Without dead ends: 527 [2018-02-04 03:07:25,376 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 8 SyntacticMatches, 5 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=97, Invalid=605, Unknown=0, NotChecked=0, Total=702 [2018-02-04 03:07:25,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 527 states. [2018-02-04 03:07:25,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 527 to 442. [2018-02-04 03:07:25,379 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 442 states. [2018-02-04 03:07:25,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 442 states to 442 states and 493 transitions. [2018-02-04 03:07:25,379 INFO L78 Accepts]: Start accepts. Automaton has 442 states and 493 transitions. Word has length 86 [2018-02-04 03:07:25,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:25,379 INFO L432 AbstractCegarLoop]: Abstraction has 442 states and 493 transitions. [2018-02-04 03:07:25,379 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 03:07:25,379 INFO L276 IsEmpty]: Start isEmpty. Operand 442 states and 493 transitions. [2018-02-04 03:07:25,380 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-04 03:07:25,380 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:25,380 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:25,380 INFO L371 AbstractCegarLoop]: === Iteration 69 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:25,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1050442937, now seen corresponding path program 1 times [2018-02-04 03:07:25,381 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:25,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:25,391 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:25,409 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:25,409 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:25,409 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 03:07:25,410 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:25,410 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:25,410 INFO L182 omatonBuilderFactory]: Interpolants [68112#(= 1 (select |#valid| |ldv_m88ts2022_rd_reg_~#reg.base|)), 68111#false, 68110#true] [2018-02-04 03:07:25,410 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:25,410 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 03:07:25,410 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 03:07:25,411 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:25,411 INFO L87 Difference]: Start difference. First operand 442 states and 493 transitions. Second operand 3 states. [2018-02-04 03:07:25,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:25,505 INFO L93 Difference]: Finished difference Result 441 states and 492 transitions. [2018-02-04 03:07:25,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 03:07:25,506 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 89 [2018-02-04 03:07:25,506 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:25,507 INFO L225 Difference]: With dead ends: 441 [2018-02-04 03:07:25,507 INFO L226 Difference]: Without dead ends: 441 [2018-02-04 03:07:25,507 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:25,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 441 states. [2018-02-04 03:07:25,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 441 to 441. [2018-02-04 03:07:25,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 441 states. [2018-02-04 03:07:25,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 441 states to 441 states and 492 transitions. [2018-02-04 03:07:25,512 INFO L78 Accepts]: Start accepts. Automaton has 441 states and 492 transitions. Word has length 89 [2018-02-04 03:07:25,512 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:25,512 INFO L432 AbstractCegarLoop]: Abstraction has 441 states and 492 transitions. [2018-02-04 03:07:25,512 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 03:07:25,512 INFO L276 IsEmpty]: Start isEmpty. Operand 441 states and 492 transitions. [2018-02-04 03:07:25,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-04 03:07:25,513 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:25,513 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:25,513 INFO L371 AbstractCegarLoop]: === Iteration 70 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:25,514 INFO L82 PathProgramCache]: Analyzing trace with hash 1050442938, now seen corresponding path program 1 times [2018-02-04 03:07:25,514 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:25,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:25,525 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:25,562 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:25,562 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:25,562 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 03:07:25,563 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:25,563 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:25,563 INFO L182 omatonBuilderFactory]: Interpolants [68995#true, 68997#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 68996#false, 68998#(<= |#Ultimate.C_memcpy_size| 0)] [2018-02-04 03:07:25,563 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:25,564 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 03:07:25,564 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 03:07:25,564 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 03:07:25,564 INFO L87 Difference]: Start difference. First operand 441 states and 492 transitions. Second operand 4 states. [2018-02-04 03:07:25,583 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:25,583 INFO L93 Difference]: Finished difference Result 447 states and 499 transitions. [2018-02-04 03:07:25,584 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 03:07:25,584 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 89 [2018-02-04 03:07:25,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:25,584 INFO L225 Difference]: With dead ends: 447 [2018-02-04 03:07:25,585 INFO L226 Difference]: Without dead ends: 445 [2018-02-04 03:07:25,585 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:07:25,585 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 445 states. [2018-02-04 03:07:25,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 445 to 445. [2018-02-04 03:07:25,588 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 445 states. [2018-02-04 03:07:25,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 445 states to 445 states and 497 transitions. [2018-02-04 03:07:25,588 INFO L78 Accepts]: Start accepts. Automaton has 445 states and 497 transitions. Word has length 89 [2018-02-04 03:07:25,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:25,588 INFO L432 AbstractCegarLoop]: Abstraction has 445 states and 497 transitions. [2018-02-04 03:07:25,588 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 03:07:25,589 INFO L276 IsEmpty]: Start isEmpty. Operand 445 states and 497 transitions. [2018-02-04 03:07:25,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-04 03:07:25,589 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:25,589 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:25,589 INFO L371 AbstractCegarLoop]: === Iteration 71 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:25,589 INFO L82 PathProgramCache]: Analyzing trace with hash -736217665, now seen corresponding path program 1 times [2018-02-04 03:07:25,590 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:25,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:25,599 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:26,283 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 17 proven. 28 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-04 03:07:26,283 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:26,283 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-02-04 03:07:26,283 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:26,284 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 3 proven. 9 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 03:07:26,284 INFO L182 omatonBuilderFactory]: Interpolants [69893#true, 69895#(= (select |#valid| 0) 0), 69894#false, 69897#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1)), 69896#(= (select |old(#valid)| 0) (select |#valid| 0)), 69899#(and (= (select |#valid| 0) 0) (= (select |#valid| |entry_point_#t~ret59.base|) 1)), 69898#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= (select |#valid| |ldv_malloc_#res.base|) 1)), 69901#(= |#valid| |old(#valid)|), 69900#(and (= (select |#valid| entry_point_~client~0.base) 1) (= (select |#valid| 0) 0)), 69903#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 69902#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 69905#(and (= (select |#valid| 0) 0) (not (= entry_point_~cfg~2.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base))), 69904#(and (not (= |entry_point_#t~ret60.base| 0)) (not (= entry_point_~client~0.base |entry_point_#t~ret60.base|)) (= (select |#valid| 0) 0)), 69907#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 69906#(and (= 1 (select |#valid| entry_point_~client~0.base)) (= (select |#valid| 0) 0) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69909#(and (not (= entry_point_~client~0.base |entry_point_#t~ret62.base|)) (= 1 (select |#valid| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69908#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 69911#(and (not (= entry_point_~client~0.base |entry_point_#t~ret64.base|)) (not (= |entry_point_#t~ret64.base| 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69910#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~fe~2.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69913#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69912#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69915#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69914#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base |entry_point_#t~ret66.base|)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0)) (not (= 0 entry_point_~cfg~2.base))), 69917#(and (= |#valid| |old(#valid)|) (= alloc_12_~client.base |alloc_12_#in~client.base|)), 69916#(and (= 1 (select |#valid| entry_point_~client~0.base)) (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~client~0.base entry_point_~fe~2.base)) (= 0 (select |#valid| 0)) (not (= entry_point_~client~0.base entry_point_~adapter~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~client~0.base entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base entry_point_~addr~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69919#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (or (and (= 1 (select |#valid| |alloc_12_#in~client.base|)) (not (= |alloc_12_~#chip_id~0.base| |alloc_12_#in~client.base|))) (= 0 (select |old(#valid)| |alloc_12_#in~client.base|)))), 69918#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= alloc_12_~client.base |alloc_12_#in~client.base|) (or (not (= alloc_12_~client.base |alloc_12_~#chip_id~0.base|)) (= 0 (select |old(#valid)| |alloc_12_#in~client.base|)))), 69921#(and (= 0 |alloc_12_#t~ret48.base|) (= (select |old(#valid)| 0) (select |#valid| 0)) (or (and (= 1 (select |#valid| |alloc_12_#in~client.base|)) (not (= |alloc_12_~#chip_id~0.base| |alloc_12_#in~client.base|))) (= 0 (select |old(#valid)| |alloc_12_#in~client.base|)))), 69920#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 69923#(or (= 0 (select |old(#valid)| |alloc_12_#in~client.base|)) (= (select |old(#valid)| 0) 1) (= 1 (select (store |#valid| |alloc_12_~#chip_id~0.base| 0) |alloc_12_#in~client.base|))), 69922#(and (= 0 alloc_12_~priv~0.base) (= (select |old(#valid)| 0) (select |#valid| 0)) (or (and (= 1 (select |#valid| |alloc_12_#in~client.base|)) (not (= |alloc_12_~#chip_id~0.base| |alloc_12_#in~client.base|))) (= 0 (select |old(#valid)| |alloc_12_#in~client.base|)))), 69925#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (not (= entry_point_~adapter~0.base 0)) (not (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= entry_point_~addr~0.base entry_point_~client~0.base)) (not (= 0 entry_point_~fe~2.base)) (= 1 (select (store |#valid| entry_point_~adapter~0.base 0) entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base))), 69924#(or (= 1 (select |#valid| |alloc_12_#in~client.base|)) (= 0 (select |old(#valid)| |alloc_12_#in~client.base|)) (= (select |old(#valid)| 0) 1)), 69927#(and (= 1 (select (store |#valid| entry_point_~fe~2.base 0) entry_point_~client~0.base)) (not (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base))), 69926#(and (not (= entry_point_~addr~0.base 0)) (not (= entry_point_~fe~2.base entry_point_~client~0.base)) (not (= entry_point_~cfg~2.base entry_point_~client~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (= 1 (select (store |#valid| entry_point_~addr~0.base 0) entry_point_~client~0.base))), 69929#(= (select |#valid| entry_point_~client~0.base) 1), 69928#(and (= 1 (select (store |#valid| entry_point_~cfg~2.base 0) entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base)))] [2018-02-04 03:07:26,284 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 17 proven. 28 refuted. 0 times theorem prover too weak. 35 trivial. 0 not checked. [2018-02-04 03:07:26,284 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-02-04 03:07:26,284 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-02-04 03:07:26,284 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=163, Invalid=1169, Unknown=0, NotChecked=0, Total=1332 [2018-02-04 03:07:26,284 INFO L87 Difference]: Start difference. First operand 445 states and 497 transitions. Second operand 37 states. [2018-02-04 03:07:28,498 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:28,498 INFO L93 Difference]: Finished difference Result 503 states and 569 transitions. [2018-02-04 03:07:28,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-04 03:07:28,499 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 87 [2018-02-04 03:07:28,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:28,500 INFO L225 Difference]: With dead ends: 503 [2018-02-04 03:07:28,500 INFO L226 Difference]: Without dead ends: 503 [2018-02-04 03:07:28,500 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 13 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 945 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=415, Invalid=3125, Unknown=0, NotChecked=0, Total=3540 [2018-02-04 03:07:28,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-04 03:07:28,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 446. [2018-02-04 03:07:28,506 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-02-04 03:07:28,506 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 498 transitions. [2018-02-04 03:07:28,507 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 498 transitions. Word has length 87 [2018-02-04 03:07:28,507 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:28,507 INFO L432 AbstractCegarLoop]: Abstraction has 446 states and 498 transitions. [2018-02-04 03:07:28,507 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-02-04 03:07:28,507 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 498 transitions. [2018-02-04 03:07:28,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-04 03:07:28,508 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:28,508 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:28,508 INFO L371 AbstractCegarLoop]: === Iteration 72 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:28,508 INFO L82 PathProgramCache]: Analyzing trace with hash -32348299, now seen corresponding path program 1 times [2018-02-04 03:07:28,509 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:28,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:28,519 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:28,553 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:28,553 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:28,553 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 03:07:28,553 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:28,554 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:28,554 INFO L182 omatonBuilderFactory]: Interpolants [70929#(<= |#Ultimate.C_memcpy_size| 1), 70928#(<= |#Ultimate.C_memcpy_#t~loopctr71| 1), 70925#true, 70927#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 70926#false] [2018-02-04 03:07:28,554 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:28,554 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 03:07:28,554 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 03:07:28,554 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-02-04 03:07:28,554 INFO L87 Difference]: Start difference. First operand 446 states and 498 transitions. Second operand 5 states. [2018-02-04 03:07:28,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:28,576 INFO L93 Difference]: Finished difference Result 453 states and 508 transitions. [2018-02-04 03:07:28,576 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 03:07:28,576 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 90 [2018-02-04 03:07:28,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:28,576 INFO L225 Difference]: With dead ends: 453 [2018-02-04 03:07:28,576 INFO L226 Difference]: Without dead ends: 453 [2018-02-04 03:07:28,577 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:28,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453 states. [2018-02-04 03:07:28,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453 to 453. [2018-02-04 03:07:28,579 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 453 states. [2018-02-04 03:07:28,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453 states to 453 states and 508 transitions. [2018-02-04 03:07:28,580 INFO L78 Accepts]: Start accepts. Automaton has 453 states and 508 transitions. Word has length 90 [2018-02-04 03:07:28,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:28,580 INFO L432 AbstractCegarLoop]: Abstraction has 453 states and 508 transitions. [2018-02-04 03:07:28,580 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 03:07:28,580 INFO L276 IsEmpty]: Start isEmpty. Operand 453 states and 508 transitions. [2018-02-04 03:07:28,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-02-04 03:07:28,581 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:28,581 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:28,581 INFO L371 AbstractCegarLoop]: === Iteration 73 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:28,581 INFO L82 PathProgramCache]: Analyzing trace with hash 760861722, now seen corresponding path program 2 times [2018-02-04 03:07:28,582 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:28,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:28,590 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:28,626 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:28,626 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:28,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6] total 6 [2018-02-04 03:07:28,627 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:28,627 INFO L182 omatonBuilderFactory]: Interpolants [71841#false, 71840#true, 71843#(<= |#Ultimate.C_memcpy_#t~loopctr71| 1), 71842#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 71845#(<= |#Ultimate.C_memcpy_size| 2), 71844#(<= |#Ultimate.C_memcpy_#t~loopctr71| 2)] [2018-02-04 03:07:28,627 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:28,627 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 03:07:28,628 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 03:07:28,628 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-02-04 03:07:28,628 INFO L87 Difference]: Start difference. First operand 453 states and 508 transitions. Second operand 6 states. [2018-02-04 03:07:28,685 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:28,686 INFO L93 Difference]: Finished difference Result 462 states and 520 transitions. [2018-02-04 03:07:28,686 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 03:07:28,686 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 91 [2018-02-04 03:07:28,686 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:28,687 INFO L225 Difference]: With dead ends: 462 [2018-02-04 03:07:28,687 INFO L226 Difference]: Without dead ends: 462 [2018-02-04 03:07:28,687 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=42, Unknown=0, NotChecked=0, Total=72 [2018-02-04 03:07:28,687 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 462 states. [2018-02-04 03:07:28,689 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 462 to 457. [2018-02-04 03:07:28,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 457 states. [2018-02-04 03:07:28,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 457 states to 457 states and 514 transitions. [2018-02-04 03:07:28,690 INFO L78 Accepts]: Start accepts. Automaton has 457 states and 514 transitions. Word has length 91 [2018-02-04 03:07:28,690 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:28,690 INFO L432 AbstractCegarLoop]: Abstraction has 457 states and 514 transitions. [2018-02-04 03:07:28,690 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 03:07:28,690 INFO L276 IsEmpty]: Start isEmpty. Operand 457 states and 514 transitions. [2018-02-04 03:07:28,690 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-04 03:07:28,690 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:28,690 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:28,691 INFO L371 AbstractCegarLoop]: === Iteration 74 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:28,691 INFO L82 PathProgramCache]: Analyzing trace with hash 1738003277, now seen corresponding path program 1 times [2018-02-04 03:07:28,691 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:28,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:28,699 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:29,598 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 4 proven. 18 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-04 03:07:29,598 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:29,598 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-04 03:07:29,598 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:29,599 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 03:07:29,599 INFO L182 omatonBuilderFactory]: Interpolants [72771#true, 72773#(= (select |#valid| 0) 0), 72772#false, 72775#(= |#valid| |old(#valid)|), 72774#(and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= (select |#valid| 0) 0)), 72777#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 72776#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 72779#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= (select |#valid| 0) 0) (not (= entry_point_~client~0.base 0))), 72778#(and (not (= |entry_point_#t~ret59.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 72781#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |entry_point_#t~ret60.base| 0)) (= 0 (select |#valid| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (not (= entry_point_~client~0.base 0))), 72780#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 72783#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |entry_point_#t~ret62.base| 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret62.base|)) (= 0 (select |#valid| 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72782#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= entry_point_~cfg~2.base 0)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72785#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |entry_point_#t~ret64.base| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72784#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~fe~2.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72787#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|)) (not (= 0 entry_point_~fe~2.base)) (not (= |entry_point_#t~ret66.base| 0)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72786#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72789#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 72788#(and (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (not (= entry_point_~addr~0.base 0)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select |#valid| 0)) (not (= entry_point_~adapter~0.base 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72791#(and (= 0 |alloc_12_#t~ret48.base|) (= (select |old(#valid)| 0) (select |#valid| 0)) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 72790#(and (= |#valid| |old(#valid)|) (= 0 |ldv_malloc_#res.base|)), 72793#(or (and (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))) (= (select |old(#valid)| 0) 1)), 72792#(and (= alloc_12_~priv~0.base 0) (= (select |old(#valid)| 0) (select |#valid| 0)) (= (store |old(#valid)| |alloc_12_~#chip_id~0.base| (select |#valid| |alloc_12_~#chip_id~0.base|)) |#valid|) (= 0 (select |old(#valid)| |alloc_12_~#chip_id~0.base|))), 72795#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~addr~0.base)) (not (= entry_point_~addr~0.base 0)) (= 1 (select (store |#valid| entry_point_~adapter~0.base 0) |~#ldv_global_msg_list.base|)) (not (= entry_point_~adapter~0.base 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0))), 72794#(or (and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))) (= (select |old(#valid)| 0) 1)), 72797#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)) (= 1 (select (store |#valid| entry_point_~fe~2.base 0) |~#ldv_global_msg_list.base|))), 72796#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~fe~2.base)) (not (= entry_point_~addr~0.base 0)) (not (= 0 entry_point_~fe~2.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (= 1 (select (store |#valid| entry_point_~addr~0.base 0) |~#ldv_global_msg_list.base|)) (not (= entry_point_~client~0.base 0))), 72799#(and (= 1 (select (store |#valid| entry_point_~client~0.base 0) |~#ldv_global_msg_list.base|)) (not (= entry_point_~client~0.base 0))), 72798#(and (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= 0 entry_point_~cfg~2.base)) (not (= entry_point_~client~0.base 0)) (= 1 (select (store |#valid| entry_point_~cfg~2.base 0) |~#ldv_global_msg_list.base|))), 72800#(= 1 (select |#valid| |~#ldv_global_msg_list.base|))] [2018-02-04 03:07:29,599 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 4 proven. 18 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-04 03:07:29,599 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-04 03:07:29,600 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-04 03:07:29,600 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=705, Unknown=0, NotChecked=0, Total=870 [2018-02-04 03:07:29,600 INFO L87 Difference]: Start difference. First operand 457 states and 514 transitions. Second operand 30 states. [2018-02-04 03:07:31,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:31,536 INFO L93 Difference]: Finished difference Result 571 states and 644 transitions. [2018-02-04 03:07:31,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-04 03:07:31,536 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 90 [2018-02-04 03:07:31,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:31,537 INFO L225 Difference]: With dead ends: 571 [2018-02-04 03:07:31,537 INFO L226 Difference]: Without dead ends: 571 [2018-02-04 03:07:31,537 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 11 SyntacticMatches, 9 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 494 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=272, Invalid=1450, Unknown=0, NotChecked=0, Total=1722 [2018-02-04 03:07:31,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-04 03:07:31,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 460. [2018-02-04 03:07:31,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-04 03:07:31,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 518 transitions. [2018-02-04 03:07:31,542 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 518 transitions. Word has length 90 [2018-02-04 03:07:31,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:31,542 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 518 transitions. [2018-02-04 03:07:31,542 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-04 03:07:31,542 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 518 transitions. [2018-02-04 03:07:31,542 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-04 03:07:31,542 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:31,542 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:31,542 INFO L371 AbstractCegarLoop]: === Iteration 75 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:31,543 INFO L82 PathProgramCache]: Analyzing trace with hash -419431403, now seen corresponding path program 3 times [2018-02-04 03:07:31,543 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:31,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:31,551 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:31,575 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:31,576 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:31,576 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-04 03:07:31,576 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:31,576 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:31,576 INFO L182 omatonBuilderFactory]: Interpolants [73857#false, 73856#true, 73859#(<= |#Ultimate.C_memcpy_#t~loopctr71| 1), 73858#(= |#Ultimate.C_memcpy_#t~loopctr71| 0), 73861#(<= |#Ultimate.C_memcpy_#t~loopctr71| 3), 73860#(<= |#Ultimate.C_memcpy_#t~loopctr71| 2), 73862#(<= |#Ultimate.C_memcpy_size| 3)] [2018-02-04 03:07:31,576 INFO L134 CoverageAnalysis]: Checked inductivity of 96 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 90 trivial. 0 not checked. [2018-02-04 03:07:31,577 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 03:07:31,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 03:07:31,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-02-04 03:07:31,577 INFO L87 Difference]: Start difference. First operand 460 states and 518 transitions. Second operand 7 states. [2018-02-04 03:07:31,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:31,633 INFO L93 Difference]: Finished difference Result 474 states and 536 transitions. [2018-02-04 03:07:31,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 03:07:31,633 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 92 [2018-02-04 03:07:31,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:31,634 INFO L225 Difference]: With dead ends: 474 [2018-02-04 03:07:31,634 INFO L226 Difference]: Without dead ends: 474 [2018-02-04 03:07:31,635 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=45, Invalid=65, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:07:31,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 474 states. [2018-02-04 03:07:31,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 474 to 461. [2018-02-04 03:07:31,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-04 03:07:31,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 520 transitions. [2018-02-04 03:07:31,640 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 520 transitions. Word has length 92 [2018-02-04 03:07:31,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:31,640 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 520 transitions. [2018-02-04 03:07:31,640 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 03:07:31,640 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 520 transitions. [2018-02-04 03:07:31,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-04 03:07:31,641 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:31,641 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:31,641 INFO L371 AbstractCegarLoop]: === Iteration 76 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:31,641 INFO L82 PathProgramCache]: Analyzing trace with hash 1646187386, now seen corresponding path program 4 times [2018-02-04 03:07:31,642 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:31,658 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:31,659 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:31,701 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-04 03:07:31,701 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:31,701 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 03:07:31,702 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:31,702 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:31,702 INFO L182 omatonBuilderFactory]: Interpolants [74807#false, 74806#true, 74808#(and (= |ldv_m88ts2022_rd_reg_~#reg.offset| 0) (= (select |#length| |ldv_m88ts2022_rd_reg_~#reg.base|) 1))] [2018-02-04 03:07:31,702 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-04 03:07:31,702 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 03:07:31,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 03:07:31,703 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:31,703 INFO L87 Difference]: Start difference. First operand 461 states and 520 transitions. Second operand 3 states. [2018-02-04 03:07:31,816 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:31,816 INFO L93 Difference]: Finished difference Result 460 states and 519 transitions. [2018-02-04 03:07:31,816 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 03:07:31,816 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 93 [2018-02-04 03:07:31,817 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:31,817 INFO L225 Difference]: With dead ends: 460 [2018-02-04 03:07:31,817 INFO L226 Difference]: Without dead ends: 460 [2018-02-04 03:07:31,817 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:31,818 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 460 states. [2018-02-04 03:07:31,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 460 to 460. [2018-02-04 03:07:31,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 460 states. [2018-02-04 03:07:31,820 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 460 states to 460 states and 519 transitions. [2018-02-04 03:07:31,821 INFO L78 Accepts]: Start accepts. Automaton has 460 states and 519 transitions. Word has length 93 [2018-02-04 03:07:31,821 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:31,821 INFO L432 AbstractCegarLoop]: Abstraction has 460 states and 519 transitions. [2018-02-04 03:07:31,821 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 03:07:31,821 INFO L276 IsEmpty]: Start isEmpty. Operand 460 states and 519 transitions. [2018-02-04 03:07:31,821 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-04 03:07:31,821 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:31,821 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:31,821 INFO L371 AbstractCegarLoop]: === Iteration 77 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:31,821 INFO L82 PathProgramCache]: Analyzing trace with hash -521120050, now seen corresponding path program 1 times [2018-02-04 03:07:31,822 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:31,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:31,833 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:32,538 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-02-04 03:07:32,538 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:32,538 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-04 03:07:32,539 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:32,539 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:07:32,539 INFO L182 omatonBuilderFactory]: Interpolants [75729#true, 75731#(= (select |#valid| |~#ldv_global_msg_list.base|) 1), 75730#false, 75733#(= |#valid| |old(#valid)|), 75732#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1)), 75735#(and (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 75734#(and (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 75737#(and (or (and (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75736#(and (or (and (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|)) (not (= |entry_point_#t~ret59.base| 0))), 75739#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 75738#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 75741#(and (or (and (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75740#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 75743#(and (or (= |~#ldv_global_msg_list.base| entry_point_~client~0.base) (and (= (select |#valid| entry_point_~cfg~2.base) (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)))) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (= (select |#valid| entry_point_~cfg~2.base) 1)), 75742#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 75745#(and (or (and (not (= entry_point_~addr~0.base 0)) (or (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75744#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (not (= |entry_point_#t~ret64.base| 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= |entry_point_#t~ret64.base| |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 75747#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 75746#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 75749#(and (or (and (or (not (= entry_point_~adapter~0.base entry_point_~addr~0.base)) (not (= entry_point_~adapter~0.base 0))) (or (and (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= entry_point_~adapter~0.base entry_point_~addr~0.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75748#(and (or (and (not (= entry_point_~addr~0.base 0)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |entry_point_#t~ret66.base| 0)) (or (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75751#(and (or (and (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (and (not (= entry_point_~addr~0.base 0)) (not (= 1 (select |#valid| entry_point_~addr~0.base)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75750#(= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|), 75753#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 75752#(and (or (and (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 75755#(= 1 (select |#valid| |ldv_destroy_msgs_#t~mem23.base|)), 75754#(or (not (= 1 (select |#valid| |~#ldv_global_msg_list.base|))) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))), 75756#(= 1 (select |#valid| ldv_destroy_msgs_~msg~1.base))] [2018-02-04 03:07:32,539 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-02-04 03:07:32,539 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 03:07:32,539 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 03:07:32,540 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=675, Unknown=0, NotChecked=0, Total=756 [2018-02-04 03:07:32,540 INFO L87 Difference]: Start difference. First operand 460 states and 519 transitions. Second operand 28 states. [2018-02-04 03:07:36,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:36,338 INFO L93 Difference]: Finished difference Result 711 states and 848 transitions. [2018-02-04 03:07:36,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 03:07:36,339 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 92 [2018-02-04 03:07:36,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:36,340 INFO L225 Difference]: With dead ends: 711 [2018-02-04 03:07:36,340 INFO L226 Difference]: Without dead ends: 711 [2018-02-04 03:07:36,340 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 81 GetRequests, 14 SyntacticMatches, 10 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 643 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=416, Invalid=3006, Unknown=0, NotChecked=0, Total=3422 [2018-02-04 03:07:36,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2018-02-04 03:07:36,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 469. [2018-02-04 03:07:36,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-04 03:07:36,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 530 transitions. [2018-02-04 03:07:36,348 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 530 transitions. Word has length 92 [2018-02-04 03:07:36,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:36,349 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 530 transitions. [2018-02-04 03:07:36,349 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 03:07:36,349 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 530 transitions. [2018-02-04 03:07:36,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-04 03:07:36,349 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:36,350 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:36,350 INFO L371 AbstractCegarLoop]: === Iteration 78 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:36,350 INFO L82 PathProgramCache]: Analyzing trace with hash -521120049, now seen corresponding path program 1 times [2018-02-04 03:07:36,351 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:36,372 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:36,373 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:37,494 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-02-04 03:07:37,494 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:37,494 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-02-04 03:07:37,494 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:37,494 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:07:37,495 INFO L182 omatonBuilderFactory]: Interpolants [77005#false, 77004#true, 77007#(and (= 0 |~#ldv_global_msg_list.offset|) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= (select |#valid| 0) 0)), 77006#(= (select |#valid| 0) 0), 77009#(= |#valid| |old(#valid)|), 77008#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= (select |#valid| 0) 0) (<= 0 |~#ldv_global_msg_list.offset|)), 77011#(and (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 77010#(and (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 77013#(and (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77012#(and (or (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|) (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|))) (not (= |entry_point_#t~ret59.base| 0)) (= (select |#valid| 0) 0)), 77015#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 77014#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 77017#(and (or (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77016#(and (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 77019#(and (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (not (= |entry_point_#t~ret64.base| 0)) (or (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 77018#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 77021#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 77020#(and (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (not (= entry_point_~addr~0.base 0)) (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (= 1 (select |#valid| |~#ldv_global_msg_list.base|)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (<= 0 |~#ldv_global_msg_list.offset|) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 77023#(and (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (not (= entry_point_~addr~0.base 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |entry_point_#t~ret66.base| 0)) (<= 0 |~#ldv_global_msg_list.offset|) (or (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 77022#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 77025#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 77024#(and (or (and (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (and (not (= entry_point_~adapter~0.base 0)) (= entry_point_~adapter~0.base entry_point_~addr~0.base))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base) (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (= 0 (select |#valid| 0)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77027#(and (= (select |old(#valid)| 0) (select |#valid| 0)) (= 0 |ldv_malloc_#res.base|)), 77026#(= (select |old(#valid)| 0) (select |#valid| 0)), 77029#(and (= 0 alloc_12_~priv~0.base) (= (select |old(#valid)| 0) (select |#valid| 0)) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 77028#(and (= 0 |alloc_12_#t~ret48.base|) (= (select |old(#valid)| 0) (select |#valid| 0)) (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 77031#(and (or (and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (and (not (= entry_point_~adapter~0.base 0)) (= entry_point_~adapter~0.base entry_point_~addr~0.base))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77030#(or (and (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)) (= (select |old(#valid)| 0) 1)), 77033#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77032#(and (or (and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (and (not (= entry_point_~addr~0.base 0)) (not (= 1 (select |#valid| entry_point_~addr~0.base))))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77035#(or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (not (= 1 (select |#valid| |~#ldv_global_msg_list.base|)))), 77034#(and (or (and (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (<= 0 |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 77037#(and (<= (+ ldv_destroy_msgs_~msg~1.offset 8) (select |#length| ldv_destroy_msgs_~msg~1.base)) (<= 0 (+ ldv_destroy_msgs_~msg~1.offset 4))), 77036#(and (<= 4 (select |#length| |ldv_destroy_msgs_#t~mem23.base|)) (= 0 |ldv_destroy_msgs_#t~mem23.offset|))] [2018-02-04 03:07:37,495 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 46 refuted. 0 times theorem prover too weak. 34 trivial. 0 not checked. [2018-02-04 03:07:37,495 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-02-04 03:07:37,495 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-02-04 03:07:37,495 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=1005, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 03:07:37,495 INFO L87 Difference]: Start difference. First operand 469 states and 530 transitions. Second operand 34 states. [2018-02-04 03:07:43,519 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:43,519 INFO L93 Difference]: Finished difference Result 700 states and 845 transitions. [2018-02-04 03:07:43,519 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-02-04 03:07:43,519 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 92 [2018-02-04 03:07:43,519 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:43,520 INFO L225 Difference]: With dead ends: 700 [2018-02-04 03:07:43,520 INFO L226 Difference]: Without dead ends: 700 [2018-02-04 03:07:43,521 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 9 SyntacticMatches, 11 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1462 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=808, Invalid=5512, Unknown=0, NotChecked=0, Total=6320 [2018-02-04 03:07:43,521 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 700 states. [2018-02-04 03:07:43,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 700 to 469. [2018-02-04 03:07:43,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-04 03:07:43,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 529 transitions. [2018-02-04 03:07:43,527 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 529 transitions. Word has length 92 [2018-02-04 03:07:43,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:43,527 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 529 transitions. [2018-02-04 03:07:43,527 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-02-04 03:07:43,527 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 529 transitions. [2018-02-04 03:07:43,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-02-04 03:07:43,528 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:43,528 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:43,528 INFO L371 AbstractCegarLoop]: === Iteration 79 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:43,528 INFO L82 PathProgramCache]: Analyzing trace with hash -953073477, now seen corresponding path program 1 times [2018-02-04 03:07:43,529 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:43,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:43,557 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:43,640 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-02-04 03:07:43,640 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:43,640 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 03:07:43,640 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:43,640 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-02-04 03:07:43,640 INFO L182 omatonBuilderFactory]: Interpolants [78305#(not (= (select |#valid| alloc_12_~priv~0.base) 0)), 78304#(not (= (select |#valid| |alloc_12_#t~ret48.base|) 0)), 78307#(= 1 (select |#valid| alloc_12_~priv~0.base)), 78306#(= 1 (select |#valid| |#Ultimate.C_memcpy_dest.base|)), 78309#(= 1 (select |#valid| ldv_m88ts2022_rd_reg_~priv.base)), 78308#(= 1 (select |#valid| |ldv_m88ts2022_rd_reg_#in~priv.base|)), 78299#true, 78301#(= (select |#valid| entry_point_~client~0.base) 1), 78300#false, 78303#(= (select |#valid| |ldv_malloc_#res.base|) 1), 78302#(= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1)] [2018-02-04 03:07:43,640 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-02-04 03:07:43,641 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:07:43,641 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:07:43,641 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:07:43,641 INFO L87 Difference]: Start difference. First operand 469 states and 529 transitions. Second operand 11 states. [2018-02-04 03:07:44,079 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:44,079 INFO L93 Difference]: Finished difference Result 466 states and 526 transitions. [2018-02-04 03:07:44,079 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 03:07:44,079 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 97 [2018-02-04 03:07:44,079 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:44,080 INFO L225 Difference]: With dead ends: 466 [2018-02-04 03:07:44,080 INFO L226 Difference]: Without dead ends: 466 [2018-02-04 03:07:44,080 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 6 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=128, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:07:44,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 466 states. [2018-02-04 03:07:44,083 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 466 to 466. [2018-02-04 03:07:44,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 466 states. [2018-02-04 03:07:44,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 466 states to 466 states and 526 transitions. [2018-02-04 03:07:44,084 INFO L78 Accepts]: Start accepts. Automaton has 466 states and 526 transitions. Word has length 97 [2018-02-04 03:07:44,084 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:44,084 INFO L432 AbstractCegarLoop]: Abstraction has 466 states and 526 transitions. [2018-02-04 03:07:44,084 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:07:44,084 INFO L276 IsEmpty]: Start isEmpty. Operand 466 states and 526 transitions. [2018-02-04 03:07:44,084 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-02-04 03:07:44,084 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:44,084 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:44,085 INFO L371 AbstractCegarLoop]: === Iteration 80 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:44,085 INFO L82 PathProgramCache]: Analyzing trace with hash -953073476, now seen corresponding path program 1 times [2018-02-04 03:07:44,085 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:44,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:44,108 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:44,298 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-02-04 03:07:44,298 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:44,298 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 03:07:44,298 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:44,298 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 33 trivial. 0 not checked. [2018-02-04 03:07:44,298 INFO L182 omatonBuilderFactory]: Interpolants [79249#(and (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1)), 79248#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 |ldv_malloc_#t~malloc4.offset|)), 79251#(and (= alloc_12_~priv~0.offset 0) (not (= (select |#valid| alloc_12_~priv~0.base) 0))), 79250#(and (not (= (select |#valid| |alloc_12_#t~ret48.base|) 0)) (= 0 |alloc_12_#t~ret48.offset|)), 79253#(and (= alloc_12_~priv~0.offset 0) (<= (+ alloc_12_~priv~0.offset 8) (select |#length| alloc_12_~priv~0.base)) (not (= (select |#valid| alloc_12_~priv~0.base) 0))), 79252#(= (select |#valid| |#Ultimate.C_memcpy_dest.base|) 1), 79255#(and (<= 8 (select |#length| ldv_m88ts2022_rd_reg_~priv.base)) (= ldv_m88ts2022_rd_reg_~priv.offset 0) (not (= (select |#valid| ldv_m88ts2022_rd_reg_~priv.base) 0))), 79254#(and (= 0 |ldv_m88ts2022_rd_reg_#in~priv.offset|) (<= 8 (select |#length| |ldv_m88ts2022_rd_reg_#in~priv.base|)) (not (= (select |#valid| |ldv_m88ts2022_rd_reg_#in~priv.base|) 0))), 79256#(and (<= 8 (select |#length| ldv_m88ts2022_rd_reg_~priv.base)) (= ldv_m88ts2022_rd_reg_~priv.offset 0)), 79247#false, 79246#true] [2018-02-04 03:07:44,298 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 15 proven. 0 refuted. 0 times theorem prover too weak. 85 trivial. 0 not checked. [2018-02-04 03:07:44,298 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 03:07:44,299 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 03:07:44,299 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=89, Unknown=0, NotChecked=0, Total=110 [2018-02-04 03:07:44,299 INFO L87 Difference]: Start difference. First operand 466 states and 526 transitions. Second operand 11 states. [2018-02-04 03:07:44,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:44,855 INFO L93 Difference]: Finished difference Result 463 states and 523 transitions. [2018-02-04 03:07:44,855 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 03:07:44,855 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 97 [2018-02-04 03:07:44,855 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:44,856 INFO L225 Difference]: With dead ends: 463 [2018-02-04 03:07:44,856 INFO L226 Difference]: Without dead ends: 463 [2018-02-04 03:07:44,856 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 5 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=30, Invalid=126, Unknown=0, NotChecked=0, Total=156 [2018-02-04 03:07:44,857 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 463 states. [2018-02-04 03:07:44,861 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 463 to 463. [2018-02-04 03:07:44,861 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 463 states. [2018-02-04 03:07:44,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 463 states to 463 states and 523 transitions. [2018-02-04 03:07:44,862 INFO L78 Accepts]: Start accepts. Automaton has 463 states and 523 transitions. Word has length 97 [2018-02-04 03:07:44,862 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:44,862 INFO L432 AbstractCegarLoop]: Abstraction has 463 states and 523 transitions. [2018-02-04 03:07:44,862 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 03:07:44,862 INFO L276 IsEmpty]: Start isEmpty. Operand 463 states and 523 transitions. [2018-02-04 03:07:44,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-02-04 03:07:44,863 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:44,863 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:44,863 INFO L371 AbstractCegarLoop]: === Iteration 81 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:44,863 INFO L82 PathProgramCache]: Analyzing trace with hash 519493314, now seen corresponding path program 1 times [2018-02-04 03:07:44,864 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:44,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:44,924 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:45,306 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-04 03:07:45,307 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:45,307 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-02-04 03:07:45,307 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:45,307 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 18 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 03:07:45,307 INFO L182 omatonBuilderFactory]: Interpolants [80193#(and (= (select |#valid| |alloc_12_#t~ret48.base|) 1) (= 1 (select |#valid| alloc_12_~client.base)) (= 0 |alloc_12_#t~ret48.offset|)), 80192#(and (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 80195#(and (= (select |#valid| alloc_12_~priv~0.base) 1) (= alloc_12_~priv~0.offset 0) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| alloc_12_~priv~0.base) (+ alloc_12_~priv~0.offset 4))))), 80194#(and (= 1 (select |#valid| alloc_12_~client.base)) (= (select |#valid| alloc_12_~priv~0.base) 1) (= alloc_12_~priv~0.offset 0)), 80197#(and (= 0 |ldv_m88ts2022_rd_reg_#in~priv.offset|) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| |ldv_m88ts2022_rd_reg_#in~priv.base|) (+ 0 4)))) (not (= |ldv_m88ts2022_rd_reg_~#reg.base| |ldv_m88ts2022_rd_reg_#in~priv.base|))), 80196#(and (= 0 |ldv_m88ts2022_rd_reg_#in~priv.offset|) (= (select |#valid| |ldv_m88ts2022_rd_reg_#in~priv.base|) 1) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| |ldv_m88ts2022_rd_reg_#in~priv.base|) (+ 0 4))))), 80199#(and (= ldv_m88ts2022_rd_reg_~priv.offset 0) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4))))), 80198#(and (= ldv_m88ts2022_rd_reg_~priv.offset 0) (= 1 (select |#valid| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4)))) (not (= |ldv_m88ts2022_rd_reg_~#reg.base| ldv_m88ts2022_rd_reg_~priv.base))), 80200#(= 1 (select |#valid| |ldv_m88ts2022_rd_reg_#t~mem38.base|)), 80187#true, 80189#(= 1 (select |#valid| alloc_12_~client.base)), 80188#false, 80191#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 80190#(= |#valid| |old(#valid)|)] [2018-02-04 03:07:45,308 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-02-04 03:07:45,308 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 03:07:45,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 03:07:45,308 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-02-04 03:07:45,308 INFO L87 Difference]: Start difference. First operand 463 states and 523 transitions. Second operand 14 states. [2018-02-04 03:07:46,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:46,578 INFO L93 Difference]: Finished difference Result 519 states and 595 transitions. [2018-02-04 03:07:46,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 03:07:46,578 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 98 [2018-02-04 03:07:46,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:46,580 INFO L225 Difference]: With dead ends: 519 [2018-02-04 03:07:46,580 INFO L226 Difference]: Without dead ends: 519 [2018-02-04 03:07:46,580 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 10 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=68, Invalid=352, Unknown=0, NotChecked=0, Total=420 [2018-02-04 03:07:46,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 519 states. [2018-02-04 03:07:46,585 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 519 to 462. [2018-02-04 03:07:46,585 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 462 states. [2018-02-04 03:07:46,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 462 states to 462 states and 522 transitions. [2018-02-04 03:07:46,586 INFO L78 Accepts]: Start accepts. Automaton has 462 states and 522 transitions. Word has length 98 [2018-02-04 03:07:46,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:46,586 INFO L432 AbstractCegarLoop]: Abstraction has 462 states and 522 transitions. [2018-02-04 03:07:46,586 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 03:07:46,586 INFO L276 IsEmpty]: Start isEmpty. Operand 462 states and 522 transitions. [2018-02-04 03:07:46,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-02-04 03:07:46,587 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:46,587 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:46,587 INFO L371 AbstractCegarLoop]: === Iteration 82 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:46,587 INFO L82 PathProgramCache]: Analyzing trace with hash 519493315, now seen corresponding path program 1 times [2018-02-04 03:07:46,588 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:46,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:46,642 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:47,471 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 38 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:07:47,471 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:47,471 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-04 03:07:47,471 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:47,472 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 20 proven. 9 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 03:07:47,472 INFO L182 omatonBuilderFactory]: Interpolants [81217#(and (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1) (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= 0 |ldv_malloc_#t~malloc4.offset|) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 81216#(and (= 0 alloc_12_~client.offset) (<= 20 (select |#length| alloc_12_~client.base))), 81219#(and (not (= (select |#valid| alloc_12_~client.base) 0)) (= 0 alloc_12_~client.offset) (= (select |#valid| |alloc_12_#t~ret48.base|) 1) (= 0 |alloc_12_#t~ret48.offset|) (<= 20 (select |#length| alloc_12_~client.base))), 81218#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (= 0 |ldv_malloc_#res.offset|) (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 81221#(and (= 0 (select (select |#memory_$Pointer$.offset| alloc_12_~priv~0.base) 4)) (= (select |#valid| alloc_12_~priv~0.base) 1) (= alloc_12_~priv~0.offset 0) (<= 20 (select |#length| (select (select |#memory_$Pointer$.base| alloc_12_~priv~0.base) (+ alloc_12_~priv~0.offset 4)))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| alloc_12_~priv~0.base) (+ alloc_12_~priv~0.offset 4))) 0))), 81220#(and (not (= (select |#valid| alloc_12_~client.base) 0)) (= 0 alloc_12_~client.offset) (= (select |#valid| alloc_12_~priv~0.base) 1) (= alloc_12_~priv~0.offset 0) (<= 20 (select |#length| alloc_12_~client.base))), 81223#(and (= 0 |ldv_m88ts2022_rd_reg_#in~priv.offset|) (<= 20 (select |#length| (select (select |#memory_$Pointer$.base| |ldv_m88ts2022_rd_reg_#in~priv.base|) 4))) (= 0 (select (select |#memory_$Pointer$.offset| |ldv_m88ts2022_rd_reg_#in~priv.base|) 4)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| |ldv_m88ts2022_rd_reg_#in~priv.base|) 4)) 0)) (not (= |ldv_m88ts2022_rd_reg_~#reg.base| |ldv_m88ts2022_rd_reg_#in~priv.base|))), 81222#(and (= 0 |ldv_m88ts2022_rd_reg_#in~priv.offset|) (= (select |#valid| |ldv_m88ts2022_rd_reg_#in~priv.base|) 1) (<= 20 (select |#length| (select (select |#memory_$Pointer$.base| |ldv_m88ts2022_rd_reg_#in~priv.base|) 4))) (= 0 (select (select |#memory_$Pointer$.offset| |ldv_m88ts2022_rd_reg_#in~priv.base|) 4)) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| |ldv_m88ts2022_rd_reg_#in~priv.base|) 4)) 0))), 81225#(and (<= 20 (select |#length| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4)))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4))) 0)) (= 0 (select (select |#memory_$Pointer$.offset| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4)))), 81224#(and (<= 20 (select |#length| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4)))) (not (= (select |#valid| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4))) 0)) (= 0 (select (select |#memory_$Pointer$.offset| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4))) (not (= |ldv_m88ts2022_rd_reg_~#reg.base| ldv_m88ts2022_rd_reg_~priv.base))), 81227#(and (= |ldv_m88ts2022_rd_reg_#t~mem38.offset| 0) (<= 20 (select |#length| |ldv_m88ts2022_rd_reg_#t~mem38.base|))), 81226#(and (<= 20 (select |#length| (select (select |#memory_$Pointer$.base| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| ldv_m88ts2022_rd_reg_~priv.base) (+ ldv_m88ts2022_rd_reg_~priv.offset 4)))), 81197#false, 81196#true, 81199#(= 0 |ldv_malloc_#res.offset|), 81198#(= 0 |ldv_malloc_#t~malloc4.offset|), 81201#(= 0 entry_point_~client~0.offset), 81200#(= 0 |entry_point_#t~ret59.offset|), 81203#(and (or (and (<= (select |#length| |ldv_malloc_#t~malloc4.base|) |ldv_malloc_#in~size|) (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#t~malloc4.base|))) (<= (+ |ldv_malloc_#in~size| 1) 0) (<= 4294967296 |ldv_malloc_#in~size|) (and (<= (+ (select |#length| |ldv_malloc_#t~malloc4.base|) 1) 0) (= 0 |ldv_malloc_#t~malloc4.offset|))) (= (select |#valid| |ldv_malloc_#t~malloc4.base|) 1)), 81202#(and (or (< 0 (div ldv_malloc_~size 4294967296)) (and (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (+ (div ldv_malloc_~size 4294967296) 1) 0)) (<= |ldv_malloc_#in~size| ldv_malloc_~size))) (or (<= ldv_malloc_~size |ldv_malloc_#in~size|) (<= (div ldv_malloc_~size 4294967296) 0))), 81205#(and (or (and (= 0 |entry_point_#t~ret60.offset|) (<= (+ (select |#length| |entry_point_#t~ret60.base|) 1) 0)) (and (= 0 entry_point_~client~0.offset) (<= (select |#length| |entry_point_#t~ret60.base|) 4) (<= 4 (select |#length| |entry_point_#t~ret60.base|)))) (= (select |#valid| |entry_point_#t~ret60.base|) 1)), 81204#(and (= (select |#valid| |ldv_malloc_#res.base|) 1) (or (<= (+ |ldv_malloc_#in~size| 1) 0) (and (= 0 |ldv_malloc_#res.offset|) (<= (+ (select |#length| |ldv_malloc_#res.base|) 1) 0)) (and (<= |ldv_malloc_#in~size| (select |#length| |ldv_malloc_#res.base|)) (<= (select |#length| |ldv_malloc_#res.base|) |ldv_malloc_#in~size|)) (<= 4294967296 |ldv_malloc_#in~size|))), 81207#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 81206#(and (or (and (<= (+ (select |#length| entry_point_~cfg~2.base) 1) 0) (= 0 entry_point_~cfg~2.offset)) (and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= 0 entry_point_~client~0.offset) (<= (select |#length| entry_point_~cfg~2.base) 4))) (= (select |#valid| entry_point_~cfg~2.base) 1)), 81209#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 81208#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= (store |old(#length)| |ldv_malloc_#t~malloc4.base| (select |#length| |ldv_malloc_#t~malloc4.base|)) |#length|)), 81211#(and (= (select |#valid| entry_point_~client~0.base) 1) (= 0 entry_point_~client~0.offset) (<= 20 (select |#length| entry_point_~client~0.base))), 81210#(or (and (= entry_point_~cfg~2.offset 0) (<= (select |#length| entry_point_~cfg~2.base) 3)) (and (<= 4 (select |#length| entry_point_~cfg~2.base)) (= 0 entry_point_~client~0.offset) (<= (select |#length| entry_point_~cfg~2.base) 4))), 81213#(and (= 0 entry_point_~client~0.offset) (<= 20 (select |#length| entry_point_~client~0.base)) (not (= (select |#valid| entry_point_~client~0.base) 0))), 81212#(and (= 0 entry_point_~client~0.offset) (<= 20 (select |#length| entry_point_~client~0.base))), 81215#(and (not (= (select |#valid| alloc_12_~client.base) 0)) (= 0 alloc_12_~client.offset) (<= 20 (select |#length| alloc_12_~client.base))), 81214#(and (not (= (select |#valid| |alloc_12_#in~client.base|) 0)) (= 0 |alloc_12_#in~client.offset|) (<= 20 (select |#length| |alloc_12_#in~client.base|)))] [2018-02-04 03:07:47,472 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 38 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 03:07:47,472 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-04 03:07:47,472 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-04 03:07:47,472 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=83, Invalid=909, Unknown=0, NotChecked=0, Total=992 [2018-02-04 03:07:47,472 INFO L87 Difference]: Start difference. First operand 462 states and 522 transitions. Second operand 32 states. [2018-02-04 03:07:51,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:51,057 INFO L93 Difference]: Finished difference Result 557 states and 644 transitions. [2018-02-04 03:07:51,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 03:07:51,057 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 98 [2018-02-04 03:07:51,057 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:51,058 INFO L225 Difference]: With dead ends: 557 [2018-02-04 03:07:51,058 INFO L226 Difference]: Without dead ends: 557 [2018-02-04 03:07:51,058 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 65 GetRequests, 7 SyntacticMatches, 5 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 557 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=239, Invalid=2731, Unknown=0, NotChecked=0, Total=2970 [2018-02-04 03:07:51,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-02-04 03:07:51,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 461. [2018-02-04 03:07:51,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-04 03:07:51,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 521 transitions. [2018-02-04 03:07:51,061 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 521 transitions. Word has length 98 [2018-02-04 03:07:51,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:51,062 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 521 transitions. [2018-02-04 03:07:51,062 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-04 03:07:51,062 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 521 transitions. [2018-02-04 03:07:51,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-02-04 03:07:51,062 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:51,062 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:51,062 INFO L371 AbstractCegarLoop]: === Iteration 83 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:51,062 INFO L82 PathProgramCache]: Analyzing trace with hash 1201435651, now seen corresponding path program 1 times [2018-02-04 03:07:51,063 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:51,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:51,073 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:52,079 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-02-04 03:07:52,079 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 03:07:52,079 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-04 03:07:52,079 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:52,080 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 03:07:52,080 INFO L182 omatonBuilderFactory]: Interpolants [82305#(and (or (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (not (= (select |#valid| |~#ldv_global_msg_list.base|) 0)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) entry_point_~client~0.offset entry_point_~cfg~2.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 82304#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (not (= (select |#valid| |~#ldv_global_msg_list.base|) 0)) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret60.base|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 82307#(and (or (= |#valid| |old(#valid)|) (and (= (@diff |old(#valid)| |#valid|) |ldv_malloc_#res.base|) (not (= |ldv_malloc_#res.base| 0)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 82306#(and (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 82309#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (or (and (not (= entry_point_~addr~0.base 0)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (not (= (select |#valid| |~#ldv_global_msg_list.base|) 0))) (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 16) entry_point_~addr~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 82308#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (or (not (= (select |#valid| |~#ldv_global_msg_list.base|) 0)) (and (not (= |entry_point_#t~ret64.base| 0)) (= |~#ldv_global_msg_list.base| |entry_point_#t~ret64.base|))) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 82311#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (not (= |ldv_malloc_#res.base| 0))), 82310#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (not (= |ldv_malloc_#t~malloc4.base| 0))), 82313#(and (or (and (or (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base) (and (= 0 (select (select (store |#memory_$Pointer$.offset| entry_point_~client~0.base (store (select |#memory_$Pointer$.offset| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.offset)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| (select (select (store |#memory_$Pointer$.base| entry_point_~client~0.base (store (select |#memory_$Pointer$.base| entry_point_~client~0.base) (+ entry_point_~client~0.offset 12) entry_point_~adapter~0.base)) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)))) (or (not (= |~#ldv_global_msg_list.base| entry_point_~adapter~0.base)) (and (not (= entry_point_~adapter~0.base 0)) (= entry_point_~adapter~0.base entry_point_~addr~0.base))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 82312#(and (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (or (and (not (= |entry_point_#t~ret66.base| 0)) (= entry_point_~addr~0.base |~#ldv_global_msg_list.base|)) (not (= |~#ldv_global_msg_list.base| |entry_point_#t~ret66.base|))) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0)))), 82315#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base)) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (and (not (= entry_point_~addr~0.base 0)) (not (= 1 (select |#valid| entry_point_~addr~0.base)))))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 82314#(and (= |#memory_$Pointer$.base| |old(#memory_$Pointer$.base)|) (= |#memory_$Pointer$.offset| |old(#memory_$Pointer$.offset)|)), 82317#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 82316#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (not (= |~#ldv_global_msg_list.base| entry_point_~cfg~2.base))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 82319#(and (= |~#ldv_global_msg_list.offset| 0) (= |~#ldv_global_msg_list.base| |ldv_destroy_msgs_#t~mem23.base|) (= 0 |ldv_destroy_msgs_#t~mem23.offset|)), 82318#(or (and (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= 0 (select |#valid| |~#ldv_global_msg_list.base|))), 82321#(and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)), 82320#(and (or (and (< (+ ldv_destroy_msgs_~msg~1.offset 3) |~#ldv_global_msg_list.offset|) (= ldv_destroy_msgs_~msg~1.base |~#ldv_global_msg_list.base|)) (< (+ ldv_destroy_msgs_~msg~1.offset 4) |~#ldv_global_msg_list.offset|)) (or (= |~#ldv_global_msg_list.offset| 0) (<= |~#ldv_global_msg_list.offset| (+ ldv_destroy_msgs_~msg~1.offset 4)))), 82293#true, 82295#(and (= 0 |~#ldv_global_msg_list.offset|) (= (select |#valid| |~#ldv_global_msg_list.base|) 1)), 82294#false, 82297#(= |#valid| |old(#valid)|), 82296#(and (= |~#ldv_global_msg_list.base| (select (store (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.offset| 0) (= 0 (select (store (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) (+ |~#ldv_global_msg_list.offset| 4) |~#ldv_global_msg_list.offset|) |~#ldv_global_msg_list.offset|)) (= (select |#valid| |~#ldv_global_msg_list.base|) 1)), 82299#(and (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (not (= |ldv_malloc_#res.base| 0)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 82298#(and (not (= |ldv_malloc_#t~malloc4.base| 0)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|)))), 82301#(and (or (not (= |~#ldv_global_msg_list.base| entry_point_~client~0.base)) (not (= entry_point_~client~0.base 0))) (or (and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| entry_point_~client~0.base))), 82300#(and (not (= |entry_point_#t~ret59.base| 0)) (or (and (= |~#ldv_global_msg_list.offset| 0) (= (select |#valid| |~#ldv_global_msg_list.base|) 1) (= 0 (select (select |#memory_$Pointer$.offset| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|)) (= |~#ldv_global_msg_list.base| (select (select |#memory_$Pointer$.base| |~#ldv_global_msg_list.base|) |~#ldv_global_msg_list.offset|))) (= |~#ldv_global_msg_list.base| |entry_point_#t~ret59.base|))), 82303#(and (= 0 (select |old(#valid)| |ldv_malloc_#res.base|)) (or (= |#valid| |old(#valid)|) (= |ldv_malloc_#res.base| (@diff |old(#valid)| |#valid|))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 82302#(and (= 0 (select |old(#valid)| |ldv_malloc_#t~malloc4.base|)) (= |#valid| (store |old(#valid)| |ldv_malloc_#t~malloc4.base| (select |#valid| |ldv_malloc_#t~malloc4.base|))))] [2018-02-04 03:07:52,080 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 0 proven. 48 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-02-04 03:07:52,080 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 03:07:52,080 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 03:07:52,080 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=81, Invalid=731, Unknown=0, NotChecked=0, Total=812 [2018-02-04 03:07:52,081 INFO L87 Difference]: Start difference. First operand 461 states and 521 transitions. Second operand 29 states. [2018-02-04 03:07:56,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:56,369 INFO L93 Difference]: Finished difference Result 678 states and 816 transitions. [2018-02-04 03:07:56,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 03:07:56,370 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 98 [2018-02-04 03:07:56,370 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:56,371 INFO L225 Difference]: With dead ends: 678 [2018-02-04 03:07:56,371 INFO L226 Difference]: Without dead ends: 678 [2018-02-04 03:07:56,371 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 14 SyntacticMatches, 11 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 525 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=390, Invalid=2802, Unknown=0, NotChecked=0, Total=3192 [2018-02-04 03:07:56,371 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678 states. [2018-02-04 03:07:56,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678 to 459. [2018-02-04 03:07:56,375 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 459 states. [2018-02-04 03:07:56,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 459 states to 459 states and 517 transitions. [2018-02-04 03:07:56,376 INFO L78 Accepts]: Start accepts. Automaton has 459 states and 517 transitions. Word has length 98 [2018-02-04 03:07:56,376 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:56,376 INFO L432 AbstractCegarLoop]: Abstraction has 459 states and 517 transitions. [2018-02-04 03:07:56,376 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 03:07:56,376 INFO L276 IsEmpty]: Start isEmpty. Operand 459 states and 517 transitions. [2018-02-04 03:07:56,376 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-02-04 03:07:56,376 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:56,376 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:56,376 INFO L371 AbstractCegarLoop]: === Iteration 84 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:56,376 INFO L82 PathProgramCache]: Analyzing trace with hash -1075576417, now seen corresponding path program 1 times [2018-02-04 03:07:56,377 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:56,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:56,386 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:56,410 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-04 03:07:56,411 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:56,411 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 03:07:56,411 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:56,411 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:56,411 INFO L182 omatonBuilderFactory]: Interpolants [83521#false, 83520#true, 83522#(and (= |ldv_m88ts2022_rd_reg_~#msg~2.offset| 0) (= (select |#length| |ldv_m88ts2022_rd_reg_~#msg~2.base|) 32))] [2018-02-04 03:07:56,411 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-04 03:07:56,411 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 03:07:56,411 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 03:07:56,411 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:56,412 INFO L87 Difference]: Start difference. First operand 459 states and 517 transitions. Second operand 3 states. [2018-02-04 03:07:56,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:56,493 INFO L93 Difference]: Finished difference Result 451 states and 509 transitions. [2018-02-04 03:07:56,493 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 03:07:56,494 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2018-02-04 03:07:56,494 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:56,494 INFO L225 Difference]: With dead ends: 451 [2018-02-04 03:07:56,494 INFO L226 Difference]: Without dead ends: 451 [2018-02-04 03:07:56,494 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:56,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 451 states. [2018-02-04 03:07:56,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 451 to 451. [2018-02-04 03:07:56,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 451 states. [2018-02-04 03:07:56,498 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 451 states to 451 states and 509 transitions. [2018-02-04 03:07:56,498 INFO L78 Accepts]: Start accepts. Automaton has 451 states and 509 transitions. Word has length 99 [2018-02-04 03:07:56,498 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:56,498 INFO L432 AbstractCegarLoop]: Abstraction has 451 states and 509 transitions. [2018-02-04 03:07:56,498 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 03:07:56,498 INFO L276 IsEmpty]: Start isEmpty. Operand 451 states and 509 transitions. [2018-02-04 03:07:56,498 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-02-04 03:07:56,498 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:56,499 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:56,499 INFO L371 AbstractCegarLoop]: === Iteration 85 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:56,499 INFO L82 PathProgramCache]: Analyzing trace with hash -1075576418, now seen corresponding path program 1 times [2018-02-04 03:07:56,500 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:56,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:56,512 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 03:07:56,543 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-04 03:07:56,543 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 03:07:56,544 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 03:07:56,544 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 03:07:56,544 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 42 trivial. 0 not checked. [2018-02-04 03:07:56,544 INFO L182 omatonBuilderFactory]: Interpolants [84425#true, 84427#(= 1 (select |#valid| |ldv_m88ts2022_rd_reg_~#msg~2.base|)), 84426#false] [2018-02-04 03:07:56,544 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-02-04 03:07:56,545 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 03:07:56,545 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 03:07:56,545 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:56,545 INFO L87 Difference]: Start difference. First operand 451 states and 509 transitions. Second operand 3 states. [2018-02-04 03:07:56,632 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 03:07:56,633 INFO L93 Difference]: Finished difference Result 443 states and 501 transitions. [2018-02-04 03:07:56,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 03:07:56,633 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 99 [2018-02-04 03:07:56,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 03:07:56,634 INFO L225 Difference]: With dead ends: 443 [2018-02-04 03:07:56,634 INFO L226 Difference]: Without dead ends: 443 [2018-02-04 03:07:56,634 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 03:07:56,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 443 states. [2018-02-04 03:07:56,637 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 443 to 443. [2018-02-04 03:07:56,637 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 443 states. [2018-02-04 03:07:56,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 443 states to 443 states and 501 transitions. [2018-02-04 03:07:56,638 INFO L78 Accepts]: Start accepts. Automaton has 443 states and 501 transitions. Word has length 99 [2018-02-04 03:07:56,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 03:07:56,638 INFO L432 AbstractCegarLoop]: Abstraction has 443 states and 501 transitions. [2018-02-04 03:07:56,638 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 03:07:56,638 INFO L276 IsEmpty]: Start isEmpty. Operand 443 states and 501 transitions. [2018-02-04 03:07:56,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-02-04 03:07:56,639 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 03:07:56,639 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 03:07:56,639 INFO L371 AbstractCegarLoop]: === Iteration 86 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 03:07:56,639 INFO L82 PathProgramCache]: Analyzing trace with hash -1017819762, now seen corresponding path program 1 times [2018-02-04 03:07:56,640 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 03:07:56,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 03:07:56,666 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. Received shutdown request... [2018-02-04 03:09:14,561 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: Timeout exceeded at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkResolutionNode(Interpolator.java:235) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.access$0(Interpolator.java:233) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator$ProofTreeWalker.walk(Interpolator.java:130) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.interpolate(Interpolator.java:220) at de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.getInterpolants(Interpolator.java:201) at de.uni_freiburg.informatik.ultimate.smtinterpol.smtlib2.SMTInterpol.getInterpolants(SMTInterpol.java:915) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.managedscript.ManagedScript.getInterpolants(ManagedScript.java:192) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.computeCraigInterpolants(NestedInterpolantsBuilder.java:281) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.NestedInterpolantsBuilder.(NestedInterpolantsBuilder.java:164) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolantsTree(InterpolatingTraceCheckCraig.java:263) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.computeInterpolants(InterpolatingTraceCheckCraig.java:199) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.InterpolatingTraceCheckCraig.(InterpolatingTraceCheckCraig.java:106) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.constructCraig(TraceCheckConstructor.java:222) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceCheckConstructor.get(TraceCheckConstructor.java:179) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.FixedTraceAbstractionRefinementStrategy.getTraceCheck(FixedTraceAbstractionRefinementStrategy.java:131) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.checkFeasibility(BaseRefinementStrategy.java:231) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.BaseRefinementStrategy.executeStrategy(BaseRefinementStrategy.java:205) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.tracehandling.TraceAbstractionRefinementEngine.(TraceAbstractionRefinementEngine.java:68) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.isCounterexampleFeasible(BasicCegarLoop.java:397) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:381) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:316) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:292) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:147) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:115) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:119) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) [2018-02-04 03:09:14,564 INFO L168 Benchmark]: Toolchain (without parser) took 168567.81 ms. Allocated memory was 410.0 MB in the beginning and 2.9 GB in the end (delta: 2.5 GB). Free memory was 366.9 MB in the beginning and 1.8 GB in the end (delta: -1.5 GB). Peak memory consumption was 2.9 GB. Max. memory is 5.3 GB. [2018-02-04 03:09:14,565 INFO L168 Benchmark]: CDTParser took 0.13 ms. Allocated memory is still 410.0 MB. Free memory is still 373.5 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 03:09:14,565 INFO L168 Benchmark]: CACSL2BoogieTranslator took 233.97 ms. Allocated memory is still 410.0 MB. Free memory was 366.9 MB in the beginning and 349.5 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. [2018-02-04 03:09:14,565 INFO L168 Benchmark]: Boogie Preprocessor took 45.44 ms. Allocated memory is still 410.0 MB. Free memory was 349.5 MB in the beginning and 346.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-04 03:09:14,565 INFO L168 Benchmark]: RCFGBuilder took 652.20 ms. Allocated memory was 410.0 MB in the beginning and 428.9 MB in the end (delta: 18.9 MB). Free memory was 346.8 MB in the beginning and 388.1 MB in the end (delta: -41.3 MB). Peak memory consumption was 100.9 MB. Max. memory is 5.3 GB. [2018-02-04 03:09:14,566 INFO L168 Benchmark]: TraceAbstraction took 167633.51 ms. Allocated memory was 428.9 MB in the beginning and 2.9 GB in the end (delta: 2.5 GB). Free memory was 386.2 MB in the beginning and 1.8 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.9 GB. Max. memory is 5.3 GB. [2018-02-04 03:09:14,567 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.13 ms. Allocated memory is still 410.0 MB. Free memory is still 373.5 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 233.97 ms. Allocated memory is still 410.0 MB. Free memory was 366.9 MB in the beginning and 349.5 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 45.44 ms. Allocated memory is still 410.0 MB. Free memory was 349.5 MB in the beginning and 346.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 652.20 ms. Allocated memory was 410.0 MB in the beginning and 428.9 MB in the end (delta: 18.9 MB). Free memory was 346.8 MB in the beginning and 388.1 MB in the end (delta: -41.3 MB). Peak memory consumption was 100.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 167633.51 ms. Allocated memory was 428.9 MB in the beginning and 2.9 GB in the end (delta: 2.5 GB). Free memory was 386.2 MB in the beginning and 1.8 GB in the end (delta: -1.4 GB). Peak memory consumption was 2.9 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: Timeout exceeded de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: Timeout exceeded: de.uni_freiburg.informatik.ultimate.smtinterpol.interpolate.Interpolator.walkResolutionNode(Interpolator.java:235) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_03-09-14-573.csv Completed graceful shutdown