java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_false-valid-free.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 13:40:49,993 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 13:40:49,994 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 13:40:50,006 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 13:40:50,006 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 13:40:50,006 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 13:40:50,007 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 13:40:50,009 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 13:40:50,010 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 13:40:50,011 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 13:40:50,011 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 13:40:50,011 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 13:40:50,012 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 13:40:50,013 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 13:40:50,014 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 13:40:50,015 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 13:40:50,017 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 13:40:50,018 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 13:40:50,019 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 13:40:50,020 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 13:40:50,022 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 13:40:50,022 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 13:40:50,022 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 13:40:50,023 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 13:40:50,024 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 13:40:50,025 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 13:40:50,025 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 13:40:50,025 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 13:40:50,025 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 13:40:50,025 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 13:40:50,026 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 13:40:50,026 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-02-04 13:40:50,034 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 13:40:50,035 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 13:40:50,035 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 13:40:50,035 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 13:40:50,036 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 13:40:50,036 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 13:40:50,037 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 13:40:50,037 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 13:40:50,037 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 13:40:50,038 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 13:40:50,038 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-02-04 13:40:50,062 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 13:40:50,069 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 13:40:50,072 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 13:40:50,072 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 13:40:50,073 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 13:40:50,073 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_false-valid-free.i [2018-02-04 13:40:50,230 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 13:40:50,231 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 13:40:50,232 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 13:40:50,232 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 13:40:50,238 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 13:40:50,238 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,241 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@2da7cdee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50, skipping insertion in model container [2018-02-04 13:40:50,241 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,255 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 13:40:50,294 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 13:40:50,395 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 13:40:50,423 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 13:40:50,434 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50 WrapperNode [2018-02-04 13:40:50,434 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 13:40:50,435 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 13:40:50,435 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 13:40:50,435 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 13:40:50,444 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,444 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,454 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,454 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,464 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,472 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,475 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... [2018-02-04 13:40:50,479 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 13:40:50,479 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 13:40:50,480 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 13:40:50,480 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 13:40:50,480 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-02-04 13:40:50,521 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_get_clientdata [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_set_clientdata [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure master_xfer [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_transfer [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_m88ts2022_rd_reg [2018-02-04 13:40:50,522 INFO L136 BoogieDeclarations]: Found implementation of procedure alloc_12 [2018-02-04 13:40:50,523 INFO L136 BoogieDeclarations]: Found implementation of procedure free_12 [2018-02-04 13:40:50,523 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 13:40:50,523 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 13:40:50,523 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-02-04 13:40:50,524 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-02-04 13:40:50,524 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 13:40:50,524 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 13:40:50,524 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 13:40:50,524 INFO L128 BoogieDeclarations]: Found specification of procedure memcpy [2018-02-04 13:40:50,524 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 13:40:50,524 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-02-04 13:40:50,525 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_get_clientdata [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_set_clientdata [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure master_xfer [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_transfer [2018-02-04 13:40:50,526 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_m88ts2022_rd_reg [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure alloc_12 [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure free_12 [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 13:40:50,527 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 13:40:51,104 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-04 13:40:51,195 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 13:40:51,195 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 01:40:51 BoogieIcfgContainer [2018-02-04 13:40:51,195 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 13:40:51,196 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 13:40:51,196 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 13:40:51,197 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 13:40:51,197 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 01:40:50" (1/3) ... [2018-02-04 13:40:51,198 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6c834ba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 01:40:51, skipping insertion in model container [2018-02-04 13:40:51,198 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:40:50" (2/3) ... [2018-02-04 13:40:51,198 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@6c834ba3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 01:40:51, skipping insertion in model container [2018-02-04 13:40:51,198 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 01:40:51" (3/3) ... [2018-02-04 13:40:51,199 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test12_false-valid-free.i [2018-02-04 13:40:51,204 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 13:40:51,209 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 141 error locations. [2018-02-04 13:40:51,230 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 13:40:51,230 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 13:40:51,231 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 13:40:51,231 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 13:40:51,231 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 13:40:51,231 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 13:40:51,231 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 13:40:51,231 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 13:40:51,231 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 13:40:51,249 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states. [2018-02-04 13:40:51,256 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-04 13:40:51,256 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:51,257 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-04 13:40:51,257 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:51,261 INFO L82 PathProgramCache]: Analyzing trace with hash 18685926, now seen corresponding path program 1 times [2018-02-04 13:40:51,263 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:51,263 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:51,301 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:51,301 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:51,301 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:51,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:51,390 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:51,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:51,421 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:51,421 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 13:40:51,422 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 13:40:51,430 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 13:40:51,430 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:40:51,431 INFO L87 Difference]: Start difference. First operand 398 states. Second operand 3 states. [2018-02-04 13:40:51,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:51,723 INFO L93 Difference]: Finished difference Result 487 states and 527 transitions. [2018-02-04 13:40:51,723 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 13:40:51,724 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-04 13:40:51,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:51,735 INFO L225 Difference]: With dead ends: 487 [2018-02-04 13:40:51,736 INFO L226 Difference]: Without dead ends: 481 [2018-02-04 13:40:51,737 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:40:51,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-04 13:40:51,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 436. [2018-02-04 13:40:51,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-02-04 13:40:51,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 491 transitions. [2018-02-04 13:40:51,783 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 491 transitions. Word has length 4 [2018-02-04 13:40:51,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:51,783 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 491 transitions. [2018-02-04 13:40:51,783 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 13:40:51,783 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 491 transitions. [2018-02-04 13:40:51,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-04 13:40:51,783 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:51,783 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-04 13:40:51,783 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:51,784 INFO L82 PathProgramCache]: Analyzing trace with hash 18685927, now seen corresponding path program 1 times [2018-02-04 13:40:51,784 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:51,784 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:51,785 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:51,786 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:51,786 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:51,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:51,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:51,825 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:51,826 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:51,826 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 13:40:51,827 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 13:40:51,827 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 13:40:51,827 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:40:51,827 INFO L87 Difference]: Start difference. First operand 436 states and 491 transitions. Second operand 3 states. [2018-02-04 13:40:51,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:51,978 INFO L93 Difference]: Finished difference Result 567 states and 652 transitions. [2018-02-04 13:40:51,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 13:40:51,978 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-04 13:40:51,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:51,980 INFO L225 Difference]: With dead ends: 567 [2018-02-04 13:40:51,981 INFO L226 Difference]: Without dead ends: 567 [2018-02-04 13:40:51,981 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:40:51,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-02-04 13:40:51,997 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 497. [2018-02-04 13:40:51,997 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 497 states. [2018-02-04 13:40:51,999 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 497 states to 497 states and 602 transitions. [2018-02-04 13:40:51,999 INFO L78 Accepts]: Start accepts. Automaton has 497 states and 602 transitions. Word has length 4 [2018-02-04 13:40:51,999 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:51,999 INFO L432 AbstractCegarLoop]: Abstraction has 497 states and 602 transitions. [2018-02-04 13:40:51,999 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 13:40:51,999 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 602 transitions. [2018-02-04 13:40:52,000 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 13:40:52,000 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:52,000 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:52,000 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:52,000 INFO L82 PathProgramCache]: Analyzing trace with hash -2098584656, now seen corresponding path program 1 times [2018-02-04 13:40:52,000 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:52,001 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:52,002 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:52,002 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:52,002 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:52,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:52,022 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:52,063 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:52,063 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:52,063 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:40:52,064 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:40:52,064 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:40:52,064 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:40:52,064 INFO L87 Difference]: Start difference. First operand 497 states and 602 transitions. Second operand 6 states. [2018-02-04 13:40:52,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:52,154 INFO L93 Difference]: Finished difference Result 543 states and 666 transitions. [2018-02-04 13:40:52,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:40:52,154 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-04 13:40:52,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:52,156 INFO L225 Difference]: With dead ends: 543 [2018-02-04 13:40:52,156 INFO L226 Difference]: Without dead ends: 543 [2018-02-04 13:40:52,157 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:40:52,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-02-04 13:40:52,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 496. [2018-02-04 13:40:52,166 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 496 states. [2018-02-04 13:40:52,167 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 604 transitions. [2018-02-04 13:40:52,167 INFO L78 Accepts]: Start accepts. Automaton has 496 states and 604 transitions. Word has length 21 [2018-02-04 13:40:52,167 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:52,167 INFO L432 AbstractCegarLoop]: Abstraction has 496 states and 604 transitions. [2018-02-04 13:40:52,168 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:40:52,168 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 604 transitions. [2018-02-04 13:40:52,168 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 13:40:52,168 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:52,168 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:52,168 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:52,168 INFO L82 PathProgramCache]: Analyzing trace with hash -1744465714, now seen corresponding path program 1 times [2018-02-04 13:40:52,168 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:52,169 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:52,170 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:52,170 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:52,170 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:52,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:52,190 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:52,248 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:52,249 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:52,249 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 13:40:52,249 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:40:52,249 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:40:52,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:40:52,249 INFO L87 Difference]: Start difference. First operand 496 states and 604 transitions. Second operand 5 states. [2018-02-04 13:40:52,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:52,543 INFO L93 Difference]: Finished difference Result 571 states and 703 transitions. [2018-02-04 13:40:52,543 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:40:52,543 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2018-02-04 13:40:52,544 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:52,546 INFO L225 Difference]: With dead ends: 571 [2018-02-04 13:40:52,546 INFO L226 Difference]: Without dead ends: 571 [2018-02-04 13:40:52,546 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:40:52,547 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-04 13:40:52,559 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 538. [2018-02-04 13:40:52,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-04 13:40:52,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 661 transitions. [2018-02-04 13:40:52,562 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 661 transitions. Word has length 21 [2018-02-04 13:40:52,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:52,563 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 661 transitions. [2018-02-04 13:40:52,563 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:40:52,563 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 661 transitions. [2018-02-04 13:40:52,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 13:40:52,563 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:52,564 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:52,564 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:52,564 INFO L82 PathProgramCache]: Analyzing trace with hash -1744465713, now seen corresponding path program 1 times [2018-02-04 13:40:52,564 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:52,564 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:52,565 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:52,566 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:52,566 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:52,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:52,580 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:52,700 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:52,700 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:52,700 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:40:52,700 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 13:40:52,701 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 13:40:52,701 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:40:52,701 INFO L87 Difference]: Start difference. First operand 538 states and 661 transitions. Second operand 7 states. [2018-02-04 13:40:53,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:53,525 INFO L93 Difference]: Finished difference Result 668 states and 771 transitions. [2018-02-04 13:40:53,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 13:40:53,526 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-02-04 13:40:53,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:53,528 INFO L225 Difference]: With dead ends: 668 [2018-02-04 13:40:53,528 INFO L226 Difference]: Without dead ends: 668 [2018-02-04 13:40:53,528 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-02-04 13:40:53,528 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states. [2018-02-04 13:40:53,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 538. [2018-02-04 13:40:53,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-04 13:40:53,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 660 transitions. [2018-02-04 13:40:53,537 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 660 transitions. Word has length 21 [2018-02-04 13:40:53,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:53,537 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 660 transitions. [2018-02-04 13:40:53,537 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 13:40:53,537 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 660 transitions. [2018-02-04 13:40:53,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 13:40:53,537 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:53,538 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:53,538 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:53,538 INFO L82 PathProgramCache]: Analyzing trace with hash -1603523080, now seen corresponding path program 1 times [2018-02-04 13:40:53,538 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:53,538 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:53,539 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:53,539 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:53,539 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:53,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:53,545 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:53,584 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:40:53,584 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:40:53,584 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:40:53,592 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:53,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:53,624 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:40:53,647 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:40:53,666 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:40:53,667 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 8 [2018-02-04 13:40:53,667 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 13:40:53,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 13:40:53,668 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:40:53,668 INFO L87 Difference]: Start difference. First operand 538 states and 660 transitions. Second operand 8 states. [2018-02-04 13:40:53,701 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:53,701 INFO L93 Difference]: Finished difference Result 503 states and 588 transitions. [2018-02-04 13:40:53,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:40:53,702 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-02-04 13:40:53,702 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:53,703 INFO L225 Difference]: With dead ends: 503 [2018-02-04 13:40:53,703 INFO L226 Difference]: Without dead ends: 503 [2018-02-04 13:40:53,703 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:40:53,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-04 13:40:53,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 495. [2018-02-04 13:40:53,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-02-04 13:40:53,713 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 574 transitions. [2018-02-04 13:40:53,714 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 574 transitions. Word has length 24 [2018-02-04 13:40:53,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:53,714 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 574 transitions. [2018-02-04 13:40:53,714 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 13:40:53,714 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 574 transitions. [2018-02-04 13:40:53,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 13:40:53,715 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:53,715 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:53,715 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:53,715 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705302, now seen corresponding path program 1 times [2018-02-04 13:40:53,715 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:53,715 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:53,716 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:53,716 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:53,716 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:53,725 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:53,725 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:53,751 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:40:53,752 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:40:53,752 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:40:53,763 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:53,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:53,782 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:40:53,797 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:40:53,825 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:40:53,825 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-02-04 13:40:53,825 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:40:53,825 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:40:53,826 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:40:53,826 INFO L87 Difference]: Start difference. First operand 495 states and 574 transitions. Second operand 6 states. [2018-02-04 13:40:53,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:53,867 INFO L93 Difference]: Finished difference Result 496 states and 579 transitions. [2018-02-04 13:40:53,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:40:53,868 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-02-04 13:40:53,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:53,870 INFO L225 Difference]: With dead ends: 496 [2018-02-04 13:40:53,870 INFO L226 Difference]: Without dead ends: 496 [2018-02-04 13:40:53,870 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 23 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:40:53,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-02-04 13:40:53,879 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 494. [2018-02-04 13:40:53,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 494 states. [2018-02-04 13:40:53,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 494 states to 494 states and 572 transitions. [2018-02-04 13:40:53,882 INFO L78 Accepts]: Start accepts. Automaton has 494 states and 572 transitions. Word has length 26 [2018-02-04 13:40:53,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:53,882 INFO L432 AbstractCegarLoop]: Abstraction has 494 states and 572 transitions. [2018-02-04 13:40:53,882 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:40:53,882 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 572 transitions. [2018-02-04 13:40:53,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 13:40:53,884 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:53,884 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:53,884 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:53,884 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705303, now seen corresponding path program 1 times [2018-02-04 13:40:53,884 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:53,884 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:53,885 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:53,886 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:53,886 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:53,897 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:53,898 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:53,952 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:53,952 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:40:53,953 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:40:53,961 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:53,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:53,983 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:40:54,009 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:40:54,011 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:54,031 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:40:54,032 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:40:54,040 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:54,058 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:40:54,058 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-02-04 13:40:54,058 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 13:40:54,058 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 13:40:54,058 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:40:54,058 INFO L87 Difference]: Start difference. First operand 494 states and 572 transitions. Second operand 7 states. [2018-02-04 13:40:54,778 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:54,778 INFO L93 Difference]: Finished difference Result 597 states and 705 transitions. [2018-02-04 13:40:54,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:40:54,803 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-02-04 13:40:54,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:54,805 INFO L225 Difference]: With dead ends: 597 [2018-02-04 13:40:54,805 INFO L226 Difference]: Without dead ends: 592 [2018-02-04 13:40:54,805 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 25 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:40:54,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2018-02-04 13:40:54,814 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 521. [2018-02-04 13:40:54,814 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-02-04 13:40:54,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 620 transitions. [2018-02-04 13:40:54,816 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 620 transitions. Word has length 26 [2018-02-04 13:40:54,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:54,817 INFO L432 AbstractCegarLoop]: Abstraction has 521 states and 620 transitions. [2018-02-04 13:40:54,817 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 13:40:54,817 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 620 transitions. [2018-02-04 13:40:54,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 13:40:54,818 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:54,818 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:54,818 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:54,818 INFO L82 PathProgramCache]: Analyzing trace with hash 1679705304, now seen corresponding path program 1 times [2018-02-04 13:40:54,818 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:54,818 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:54,819 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:54,820 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:54,820 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:54,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:54,828 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:54,855 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:40:54,855 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:54,855 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 13:40:54,855 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:40:54,855 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:40:54,855 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:40:54,855 INFO L87 Difference]: Start difference. First operand 521 states and 620 transitions. Second operand 5 states. [2018-02-04 13:40:54,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:54,868 INFO L93 Difference]: Finished difference Result 523 states and 619 transitions. [2018-02-04 13:40:54,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 13:40:54,868 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-02-04 13:40:54,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:54,870 INFO L225 Difference]: With dead ends: 523 [2018-02-04 13:40:54,870 INFO L226 Difference]: Without dead ends: 523 [2018-02-04 13:40:54,870 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:40:54,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-02-04 13:40:54,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 520. [2018-02-04 13:40:54,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-02-04 13:40:54,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 617 transitions. [2018-02-04 13:40:54,876 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 617 transitions. Word has length 26 [2018-02-04 13:40:54,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:54,876 INFO L432 AbstractCegarLoop]: Abstraction has 520 states and 617 transitions. [2018-02-04 13:40:54,876 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:40:54,876 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 617 transitions. [2018-02-04 13:40:54,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 13:40:54,877 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:54,877 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:54,877 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:54,877 INFO L82 PathProgramCache]: Analyzing trace with hash -1000460798, now seen corresponding path program 1 times [2018-02-04 13:40:54,877 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:54,877 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:54,878 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:54,878 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:54,878 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:54,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:54,886 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:54,909 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:54,909 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:54,909 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 13:40:54,909 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:40:54,910 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:40:54,910 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:40:54,910 INFO L87 Difference]: Start difference. First operand 520 states and 617 transitions. Second operand 5 states. [2018-02-04 13:40:55,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:55,126 INFO L93 Difference]: Finished difference Result 541 states and 644 transitions. [2018-02-04 13:40:55,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:40:55,126 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-02-04 13:40:55,126 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:55,127 INFO L225 Difference]: With dead ends: 541 [2018-02-04 13:40:55,127 INFO L226 Difference]: Without dead ends: 541 [2018-02-04 13:40:55,128 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:40:55,128 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-02-04 13:40:55,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 537. [2018-02-04 13:40:55,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-02-04 13:40:55,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 638 transitions. [2018-02-04 13:40:55,138 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 638 transitions. Word has length 27 [2018-02-04 13:40:55,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:55,139 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 638 transitions. [2018-02-04 13:40:55,139 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:40:55,139 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 638 transitions. [2018-02-04 13:40:55,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 13:40:55,139 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:55,139 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:55,140 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:55,140 INFO L82 PathProgramCache]: Analyzing trace with hash -1000460797, now seen corresponding path program 1 times [2018-02-04 13:40:55,140 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:55,140 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:55,141 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:55,141 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:55,141 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:55,149 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:55,150 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:55,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:55,302 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:55,302 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 13:40:55,303 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 13:40:55,303 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 13:40:55,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:40:55,303 INFO L87 Difference]: Start difference. First operand 537 states and 638 transitions. Second operand 8 states. [2018-02-04 13:40:55,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:55,627 INFO L93 Difference]: Finished difference Result 500 states and 568 transitions. [2018-02-04 13:40:55,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 13:40:55,627 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-02-04 13:40:55,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:55,629 INFO L225 Difference]: With dead ends: 500 [2018-02-04 13:40:55,629 INFO L226 Difference]: Without dead ends: 488 [2018-02-04 13:40:55,629 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-02-04 13:40:55,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2018-02-04 13:40:55,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 477. [2018-02-04 13:40:55,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 477 states. [2018-02-04 13:40:55,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 550 transitions. [2018-02-04 13:40:55,638 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 550 transitions. Word has length 27 [2018-02-04 13:40:55,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:55,638 INFO L432 AbstractCegarLoop]: Abstraction has 477 states and 550 transitions. [2018-02-04 13:40:55,638 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 13:40:55,638 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 550 transitions. [2018-02-04 13:40:55,639 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 13:40:55,639 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:55,639 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:55,639 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:55,639 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219079, now seen corresponding path program 1 times [2018-02-04 13:40:55,639 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:55,639 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:55,640 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:55,640 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:55,640 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:55,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:55,649 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:55,682 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 13:40:55,682 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:40:55,682 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:40:55,682 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:40:55,682 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:40:55,683 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:40:55,683 INFO L87 Difference]: Start difference. First operand 477 states and 550 transitions. Second operand 6 states. [2018-02-04 13:40:55,718 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:55,718 INFO L93 Difference]: Finished difference Result 478 states and 549 transitions. [2018-02-04 13:40:55,719 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:40:55,719 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-04 13:40:55,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:55,721 INFO L225 Difference]: With dead ends: 478 [2018-02-04 13:40:55,721 INFO L226 Difference]: Without dead ends: 478 [2018-02-04 13:40:55,722 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:40:55,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-04 13:40:55,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 476. [2018-02-04 13:40:55,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 476 states. [2018-02-04 13:40:55,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 476 states to 476 states and 547 transitions. [2018-02-04 13:40:55,731 INFO L78 Accepts]: Start accepts. Automaton has 476 states and 547 transitions. Word has length 28 [2018-02-04 13:40:55,731 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:55,731 INFO L432 AbstractCegarLoop]: Abstraction has 476 states and 547 transitions. [2018-02-04 13:40:55,732 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:40:55,732 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 547 transitions. [2018-02-04 13:40:55,732 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 13:40:55,732 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:55,732 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:55,732 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:55,733 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219079, now seen corresponding path program 1 times [2018-02-04 13:40:55,733 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:55,733 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:55,734 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:55,734 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:55,734 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:55,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:55,741 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:55,815 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:55,815 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:40:55,815 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:40:55,825 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:55,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:55,852 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:40:55,855 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:40:55,856 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:55,857 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:40:55,857 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:40:55,900 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:55,900 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:55,903 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:40:55,903 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:55,909 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:40:55,909 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-02-04 13:40:55,928 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:55,959 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:40:55,959 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-02-04 13:40:55,959 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 13:40:55,960 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 13:40:55,960 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2018-02-04 13:40:55,960 INFO L87 Difference]: Start difference. First operand 476 states and 547 transitions. Second operand 11 states. [2018-02-04 13:40:56,985 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:40:56,985 INFO L93 Difference]: Finished difference Result 582 states and 680 transitions. [2018-02-04 13:40:56,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 13:40:56,985 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 28 [2018-02-04 13:40:56,985 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:40:56,987 INFO L225 Difference]: With dead ends: 582 [2018-02-04 13:40:56,987 INFO L226 Difference]: Without dead ends: 582 [2018-02-04 13:40:56,988 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 25 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=162, Unknown=0, NotChecked=0, Total=210 [2018-02-04 13:40:56,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 582 states. [2018-02-04 13:40:56,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 582 to 461. [2018-02-04 13:40:56,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 461 states. [2018-02-04 13:40:56,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 461 states to 461 states and 518 transitions. [2018-02-04 13:40:56,993 INFO L78 Accepts]: Start accepts. Automaton has 461 states and 518 transitions. Word has length 28 [2018-02-04 13:40:56,993 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:40:56,993 INFO L432 AbstractCegarLoop]: Abstraction has 461 states and 518 transitions. [2018-02-04 13:40:56,993 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 13:40:56,993 INFO L276 IsEmpty]: Start isEmpty. Operand 461 states and 518 transitions. [2018-02-04 13:40:56,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 13:40:56,993 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:40:56,994 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:40:56,994 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:40:56,994 INFO L82 PathProgramCache]: Analyzing trace with hash -1378219078, now seen corresponding path program 1 times [2018-02-04 13:40:56,994 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:40:56,994 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:40:56,995 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:56,995 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:56,995 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:40:57,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:57,002 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:40:57,198 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:57,199 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:40:57,199 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:40:57,208 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:40:57,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:40:57,230 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:40:57,247 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 13:40:57,247 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,272 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 13:40:57,272 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,274 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 13:40:57,274 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,291 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 13:40:57,292 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,306 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 13:40:57,307 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 13:40:57,471 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:57,471 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:57,472 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 26 [2018-02-04 13:40:57,473 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,503 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 13:40:57,504 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,521 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:57,521 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:57,522 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 47 [2018-02-04 13:40:57,522 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,571 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:57,572 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:40:57,573 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 27 [2018-02-04 13:40:57,573 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:40:57,593 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 13:40:57,593 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-02-04 13:40:57,633 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:40:57,650 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:40:57,650 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-02-04 13:40:57,650 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 13:40:57,651 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 13:40:57,651 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=261, Unknown=1, NotChecked=0, Total=306 [2018-02-04 13:40:57,651 INFO L87 Difference]: Start difference. First operand 461 states and 518 transitions. Second operand 18 states. [2018-02-04 13:41:17,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:41:17,857 INFO L93 Difference]: Finished difference Result 655 states and 761 transitions. [2018-02-04 13:41:17,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 13:41:17,857 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 28 [2018-02-04 13:41:17,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:41:17,858 INFO L225 Difference]: With dead ends: 655 [2018-02-04 13:41:17,858 INFO L226 Difference]: Without dead ends: 655 [2018-02-04 13:41:17,859 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=96, Invalid=501, Unknown=3, NotChecked=0, Total=600 [2018-02-04 13:41:17,859 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 655 states. [2018-02-04 13:41:17,864 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 655 to 473. [2018-02-04 13:41:17,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-04 13:41:17,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 544 transitions. [2018-02-04 13:41:17,866 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 544 transitions. Word has length 28 [2018-02-04 13:41:17,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:41:17,866 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 544 transitions. [2018-02-04 13:41:17,866 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 13:41:17,866 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 544 transitions. [2018-02-04 13:41:17,866 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 13:41:17,866 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:41:17,867 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:41:17,867 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:41:17,867 INFO L82 PathProgramCache]: Analyzing trace with hash -562803403, now seen corresponding path program 1 times [2018-02-04 13:41:17,867 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:41:17,867 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:41:17,868 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:41:17,868 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:41:17,868 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:41:17,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:41:17,877 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:41:17,983 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:41:17,983 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:41:17,983 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:41:17,988 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:41:18,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:41:18,006 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:41:18,020 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:41:18,020 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,021 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,021 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:41:18,024 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:41:18,024 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,025 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,025 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:9, output treesize:3 [2018-02-04 13:41:18,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:18,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:18,045 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:41:18,045 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,049 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,049 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 13:41:18,124 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 12 [2018-02-04 13:41:18,124 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,137 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 8 [2018-02-04 13:41:18,138 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,146 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,146 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:41, output treesize:3 [2018-02-04 13:41:18,155 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:18,156 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:41:18,156 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:18,164 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:41:18,164 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:25, output treesize:15 [2018-02-04 13:41:18,184 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:41:18,202 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:41:18,202 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 9] total 13 [2018-02-04 13:41:18,202 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 13:41:18,203 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 13:41:18,203 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2018-02-04 13:41:18,203 INFO L87 Difference]: Start difference. First operand 473 states and 544 transitions. Second operand 14 states. [2018-02-04 13:41:19,408 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:41:19,408 INFO L93 Difference]: Finished difference Result 572 states and 640 transitions. [2018-02-04 13:41:19,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 13:41:19,409 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-02-04 13:41:19,409 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:41:19,410 INFO L225 Difference]: With dead ends: 572 [2018-02-04 13:41:19,411 INFO L226 Difference]: Without dead ends: 572 [2018-02-04 13:41:19,411 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 27 SyntacticMatches, 2 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=71, Invalid=349, Unknown=0, NotChecked=0, Total=420 [2018-02-04 13:41:19,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states. [2018-02-04 13:41:19,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 473. [2018-02-04 13:41:19,417 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-04 13:41:19,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 543 transitions. [2018-02-04 13:41:19,419 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 543 transitions. Word has length 29 [2018-02-04 13:41:19,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:41:19,419 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 543 transitions. [2018-02-04 13:41:19,419 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 13:41:19,419 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 543 transitions. [2018-02-04 13:41:19,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 13:41:19,420 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:41:19,420 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:41:19,420 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:41:19,420 INFO L82 PathProgramCache]: Analyzing trace with hash -562803402, now seen corresponding path program 1 times [2018-02-04 13:41:19,420 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:41:19,420 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:41:19,421 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:41:19,422 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:41:19,422 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:41:19,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:41:19,431 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:41:19,500 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:41:19,500 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:41:19,500 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:41:19,505 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:41:19,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:41:19,523 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:41:19,532 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:41:19,533 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,537 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:41:19,537 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,540 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,540 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-02-04 13:41:19,564 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:41:19,564 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,569 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:41:19,569 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,572 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,572 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:20, output treesize:10 [2018-02-04 13:41:19,630 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,631 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,632 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 47 [2018-02-04 13:41:19,632 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,660 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,661 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 27 [2018-02-04 13:41:19,662 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,683 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,684 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 35 [2018-02-04 13:41:19,685 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,707 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,707 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,708 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 25 [2018-02-04 13:41:19,708 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,721 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 13:41:19,722 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-02-04 13:41:19,756 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2018-02-04 13:41:19,757 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,769 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:41:19,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2018-02-04 13:41:19,770 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,783 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:41:19,784 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:55, output treesize:7 [2018-02-04 13:41:19,805 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:41:19,822 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:41:19,822 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 11 [2018-02-04 13:41:19,822 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 13:41:19,822 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 13:41:19,822 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2018-02-04 13:41:19,822 INFO L87 Difference]: Start difference. First operand 473 states and 543 transitions. Second operand 12 states. [2018-02-04 13:41:48,874 WARN L146 SmtUtils]: Spent 21288ms on a formula simplification. DAG size of input: 59 DAG size of output 56 [2018-02-04 13:42:09,162 WARN L146 SmtUtils]: Spent 20262ms on a formula simplification. DAG size of input: 57 DAG size of output 54 [2018-02-04 13:42:34,159 WARN L146 SmtUtils]: Spent 24576ms on a formula simplification. DAG size of input: 52 DAG size of output 50 [2018-02-04 13:42:56,345 WARN L146 SmtUtils]: Spent 20253ms on a formula simplification. DAG size of input: 48 DAG size of output 47 [2018-02-04 13:43:08,839 WARN L143 SmtUtils]: Spent 12053ms on a formula simplification that was a NOOP. DAG size: 43 [2018-02-04 13:43:09,812 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:09,812 INFO L93 Difference]: Finished difference Result 636 states and 719 transitions. [2018-02-04 13:43:09,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 13:43:09,812 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 29 [2018-02-04 13:43:09,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:09,814 INFO L225 Difference]: With dead ends: 636 [2018-02-04 13:43:09,814 INFO L226 Difference]: Without dead ends: 636 [2018-02-04 13:43:09,814 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 24 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 80 ImplicationChecksByTransitivity, 101.2s TimeCoverageRelationStatistics Valid=127, Invalid=321, Unknown=14, NotChecked=0, Total=462 [2018-02-04 13:43:09,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 636 states. [2018-02-04 13:43:09,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 636 to 472. [2018-02-04 13:43:09,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-04 13:43:09,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 541 transitions. [2018-02-04 13:43:09,823 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 541 transitions. Word has length 29 [2018-02-04 13:43:09,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:09,824 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 541 transitions. [2018-02-04 13:43:09,824 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 13:43:09,824 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 541 transitions. [2018-02-04 13:43:09,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-02-04 13:43:09,824 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:09,824 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:09,825 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:09,825 INFO L82 PathProgramCache]: Analyzing trace with hash 311817911, now seen corresponding path program 1 times [2018-02-04 13:43:09,825 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:09,825 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:09,826 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:09,826 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:09,826 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:09,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:09,834 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:09,897 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 13:43:09,897 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:43:09,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 13:43:09,898 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:43:09,898 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:43:09,898 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:43:09,898 INFO L87 Difference]: Start difference. First operand 472 states and 541 transitions. Second operand 6 states. [2018-02-04 13:43:10,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:10,191 INFO L93 Difference]: Finished difference Result 481 states and 550 transitions. [2018-02-04 13:43:10,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:43:10,192 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 31 [2018-02-04 13:43:10,192 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:10,193 INFO L225 Difference]: With dead ends: 481 [2018-02-04 13:43:10,193 INFO L226 Difference]: Without dead ends: 481 [2018-02-04 13:43:10,193 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 4 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-02-04 13:43:10,194 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-04 13:43:10,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 472. [2018-02-04 13:43:10,199 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 472 states. [2018-02-04 13:43:10,200 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 472 states to 472 states and 540 transitions. [2018-02-04 13:43:10,201 INFO L78 Accepts]: Start accepts. Automaton has 472 states and 540 transitions. Word has length 31 [2018-02-04 13:43:10,201 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:10,201 INFO L432 AbstractCegarLoop]: Abstraction has 472 states and 540 transitions. [2018-02-04 13:43:10,201 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:43:10,201 INFO L276 IsEmpty]: Start isEmpty. Operand 472 states and 540 transitions. [2018-02-04 13:43:10,201 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 13:43:10,201 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:10,202 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:10,202 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:10,202 INFO L82 PathProgramCache]: Analyzing trace with hash -156377544, now seen corresponding path program 1 times [2018-02-04 13:43:10,202 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:10,202 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:10,203 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:10,203 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:10,203 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:10,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:10,211 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:10,239 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 13:43:10,240 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:43:10,240 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 13:43:10,240 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:43:10,240 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:43:10,240 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:43:10,240 INFO L87 Difference]: Start difference. First operand 472 states and 540 transitions. Second operand 5 states. [2018-02-04 13:43:10,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:10,263 INFO L93 Difference]: Finished difference Result 478 states and 542 transitions. [2018-02-04 13:43:10,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 13:43:10,263 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 36 [2018-02-04 13:43:10,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:10,265 INFO L225 Difference]: With dead ends: 478 [2018-02-04 13:43:10,265 INFO L226 Difference]: Without dead ends: 478 [2018-02-04 13:43:10,265 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:43:10,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-04 13:43:10,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 470. [2018-02-04 13:43:10,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-04 13:43:10,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-04 13:43:10,273 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-04 13:43:10,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:10,273 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-04 13:43:10,273 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:43:10,273 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-04 13:43:10,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 13:43:10,273 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:10,274 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:10,274 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:10,274 INFO L82 PathProgramCache]: Analyzing trace with hash -156377559, now seen corresponding path program 1 times [2018-02-04 13:43:10,274 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:10,274 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:10,275 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:10,275 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:10,275 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:10,282 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:10,282 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:10,308 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 13:43:10,309 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:10,309 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:10,316 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:10,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:10,337 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:10,345 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 3 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 13:43:10,376 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:10,376 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-02-04 13:43:10,377 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:43:10,378 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:43:10,378 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:43:10,378 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 6 states. [2018-02-04 13:43:10,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:10,405 INFO L93 Difference]: Finished difference Result 469 states and 532 transitions. [2018-02-04 13:43:10,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:43:10,405 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 36 [2018-02-04 13:43:10,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:10,406 INFO L225 Difference]: With dead ends: 469 [2018-02-04 13:43:10,407 INFO L226 Difference]: Without dead ends: 469 [2018-02-04 13:43:10,407 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 41 GetRequests, 34 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:43:10,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 469 states. [2018-02-04 13:43:10,413 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 469 to 469. [2018-02-04 13:43:10,413 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-04 13:43:10,414 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 532 transitions. [2018-02-04 13:43:10,414 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 532 transitions. Word has length 36 [2018-02-04 13:43:10,414 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:10,414 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 532 transitions. [2018-02-04 13:43:10,415 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:43:10,415 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 532 transitions. [2018-02-04 13:43:10,415 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 13:43:10,415 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:10,415 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:10,415 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:10,415 INFO L82 PathProgramCache]: Analyzing trace with hash -156377558, now seen corresponding path program 1 times [2018-02-04 13:43:10,415 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:10,416 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:10,416 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:10,416 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:10,417 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:10,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:10,425 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:10,459 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 13:43:10,460 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:10,460 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:10,468 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:10,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:10,492 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:10,516 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:10,516 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:10,517 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:10,517 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:10,526 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 9 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 13:43:10,556 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:10,557 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-02-04 13:43:10,557 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 13:43:10,557 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 13:43:10,557 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:43:10,557 INFO L87 Difference]: Start difference. First operand 469 states and 532 transitions. Second operand 7 states. [2018-02-04 13:43:11,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:11,074 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-04 13:43:11,074 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:43:11,074 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 36 [2018-02-04 13:43:11,074 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:11,075 INFO L225 Difference]: With dead ends: 540 [2018-02-04 13:43:11,076 INFO L226 Difference]: Without dead ends: 540 [2018-02-04 13:43:11,076 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 35 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:43:11,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-04 13:43:11,079 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 470. [2018-02-04 13:43:11,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-04 13:43:11,080 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-04 13:43:11,080 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 36 [2018-02-04 13:43:11,080 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:11,080 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-04 13:43:11,080 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 13:43:11,080 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-04 13:43:11,081 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-02-04 13:43:11,081 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:11,081 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:11,081 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:11,081 INFO L82 PathProgramCache]: Analyzing trace with hash -552736786, now seen corresponding path program 1 times [2018-02-04 13:43:11,081 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:11,081 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:11,082 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:11,082 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:11,082 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:11,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:11,086 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:11,201 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:43:11,201 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:11,201 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:11,209 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:11,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:11,233 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:11,237 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:11,238 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:11,239 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:11,239 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:11,266 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:11,266 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:11,267 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 13:43:11,267 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:11,268 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:11,268 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:4 [2018-02-04 13:43:11,319 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:11,319 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-02-04 13:43:11,320 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:11,326 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:43:11,327 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:20, output treesize:15 [2018-02-04 13:43:11,341 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 5 proven. 7 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:43:11,372 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:11,372 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 13] total 18 [2018-02-04 13:43:11,373 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 13:43:11,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 13:43:11,373 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=292, Unknown=0, NotChecked=0, Total=342 [2018-02-04 13:43:11,373 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 19 states. [2018-02-04 13:43:12,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:12,425 INFO L93 Difference]: Finished difference Result 540 states and 618 transitions. [2018-02-04 13:43:12,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 13:43:12,425 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 37 [2018-02-04 13:43:12,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:12,426 INFO L225 Difference]: With dead ends: 540 [2018-02-04 13:43:12,426 INFO L226 Difference]: Without dead ends: 540 [2018-02-04 13:43:12,427 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 29 SyntacticMatches, 5 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=73, Invalid=389, Unknown=0, NotChecked=0, Total=462 [2018-02-04 13:43:12,427 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 540 states. [2018-02-04 13:43:12,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 540 to 471. [2018-02-04 13:43:12,432 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-04 13:43:12,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-04 13:43:12,433 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 37 [2018-02-04 13:43:12,433 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:12,433 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-04 13:43:12,433 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 13:43:12,434 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-04 13:43:12,434 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 13:43:12,434 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:12,434 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:12,434 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:12,435 INFO L82 PathProgramCache]: Analyzing trace with hash -689007910, now seen corresponding path program 1 times [2018-02-04 13:43:12,435 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:12,435 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:12,436 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:12,436 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:12,436 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:12,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:12,444 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:12,516 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 13 proven. 2 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 13:43:12,517 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:12,517 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:12,521 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:12,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:12,540 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:12,556 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:12,556 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:12,568 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:12,568 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:12,590 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:12,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:12,593 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:43:12,594 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:12,599 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:43:12,599 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-02-04 13:43:12,611 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 3 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 13:43:12,641 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:12,641 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-02-04 13:43:12,641 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 13:43:12,641 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 13:43:12,641 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2018-02-04 13:43:12,642 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 11 states. [2018-02-04 13:43:13,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:13,574 INFO L93 Difference]: Finished difference Result 577 states and 667 transitions. [2018-02-04 13:43:13,574 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 13:43:13,575 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-02-04 13:43:13,575 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:13,576 INFO L225 Difference]: With dead ends: 577 [2018-02-04 13:43:13,576 INFO L226 Difference]: Without dead ends: 577 [2018-02-04 13:43:13,576 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 35 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-02-04 13:43:13,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 577 states. [2018-02-04 13:43:13,581 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 577 to 471. [2018-02-04 13:43:13,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-04 13:43:13,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 534 transitions. [2018-02-04 13:43:13,582 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 534 transitions. Word has length 38 [2018-02-04 13:43:13,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:13,583 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 534 transitions. [2018-02-04 13:43:13,583 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 13:43:13,583 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 534 transitions. [2018-02-04 13:43:13,583 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 13:43:13,583 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:13,583 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:13,583 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:13,584 INFO L82 PathProgramCache]: Analyzing trace with hash -689007909, now seen corresponding path program 1 times [2018-02-04 13:43:13,584 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:13,584 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:13,585 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:13,585 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:13,585 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:13,595 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:13,596 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:13,746 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 13:43:13,746 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:13,746 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:13,752 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:13,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:13,769 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:13,778 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 13:43:13,779 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:13,790 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 13:43:13,791 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:13,795 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 13:43:13,795 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:13,811 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 13:43:13,811 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:13,821 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 13:43:13,821 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 13:43:13,930 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:13,931 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 15 [2018-02-04 13:43:13,931 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:13,940 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:13,940 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:13,941 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 13:43:13,941 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:13,945 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:43:13,946 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:25, output treesize:18 [2018-02-04 13:43:13,964 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 14 proven. 3 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-02-04 13:43:13,981 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:13,981 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 18 [2018-02-04 13:43:13,982 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 13:43:13,982 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 13:43:13,982 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=289, Unknown=3, NotChecked=0, Total=342 [2018-02-04 13:43:13,982 INFO L87 Difference]: Start difference. First operand 471 states and 534 transitions. Second operand 19 states. [2018-02-04 13:43:16,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:16,253 INFO L93 Difference]: Finished difference Result 633 states and 732 transitions. [2018-02-04 13:43:16,254 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 13:43:16,254 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 38 [2018-02-04 13:43:16,254 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:16,255 INFO L225 Difference]: With dead ends: 633 [2018-02-04 13:43:16,255 INFO L226 Difference]: Without dead ends: 633 [2018-02-04 13:43:16,255 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 30 SyntacticMatches, 1 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 64 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=77, Invalid=382, Unknown=3, NotChecked=0, Total=462 [2018-02-04 13:43:16,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states. [2018-02-04 13:43:16,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 470. [2018-02-04 13:43:16,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 470 states. [2018-02-04 13:43:16,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 470 states to 470 states and 533 transitions. [2018-02-04 13:43:16,260 INFO L78 Accepts]: Start accepts. Automaton has 470 states and 533 transitions. Word has length 38 [2018-02-04 13:43:16,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:16,260 INFO L432 AbstractCegarLoop]: Abstraction has 470 states and 533 transitions. [2018-02-04 13:43:16,260 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 13:43:16,260 INFO L276 IsEmpty]: Start isEmpty. Operand 470 states and 533 transitions. [2018-02-04 13:43:16,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 13:43:16,260 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:16,260 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:16,260 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:16,261 INFO L82 PathProgramCache]: Analyzing trace with hash 115591052, now seen corresponding path program 1 times [2018-02-04 13:43:16,261 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:16,261 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:16,261 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:16,261 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:16,261 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:16,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:16,266 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:16,325 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 13:43:16,325 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:43:16,325 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:43:16,325 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:43:16,325 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:43:16,325 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:43:16,326 INFO L87 Difference]: Start difference. First operand 470 states and 533 transitions. Second operand 6 states. [2018-02-04 13:43:16,342 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:16,342 INFO L93 Difference]: Finished difference Result 472 states and 535 transitions. [2018-02-04 13:43:16,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:43:16,342 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 39 [2018-02-04 13:43:16,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:16,343 INFO L225 Difference]: With dead ends: 472 [2018-02-04 13:43:16,343 INFO L226 Difference]: Without dead ends: 472 [2018-02-04 13:43:16,344 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:43:16,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 472 states. [2018-02-04 13:43:16,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 472 to 469. [2018-02-04 13:43:16,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 469 states. [2018-02-04 13:43:16,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 469 states to 469 states and 531 transitions. [2018-02-04 13:43:16,349 INFO L78 Accepts]: Start accepts. Automaton has 469 states and 531 transitions. Word has length 39 [2018-02-04 13:43:16,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:16,349 INFO L432 AbstractCegarLoop]: Abstraction has 469 states and 531 transitions. [2018-02-04 13:43:16,349 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:43:16,349 INFO L276 IsEmpty]: Start isEmpty. Operand 469 states and 531 transitions. [2018-02-04 13:43:16,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-04 13:43:16,350 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:16,350 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:16,350 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:16,350 INFO L82 PathProgramCache]: Analyzing trace with hash 323501758, now seen corresponding path program 1 times [2018-02-04 13:43:16,350 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:16,351 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:16,351 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:16,352 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:16,352 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:16,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:16,362 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:16,551 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 13:43:16,551 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:16,551 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:16,564 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:16,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:16,592 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:16,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:16,598 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,599 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,599 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:16,607 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:43:16,608 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,609 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,609 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:9, output treesize:3 [2018-02-04 13:43:16,647 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,647 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,648 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:43:16,648 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,654 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,654 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 13:43:16,712 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 8 [2018-02-04 13:43:16,713 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,724 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 12 [2018-02-04 13:43:16,724 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,731 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,731 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:41, output treesize:3 [2018-02-04 13:43:16,738 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,738 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,739 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,740 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 38 [2018-02-04 13:43:16,740 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,742 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,743 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,743 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:16,744 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 38 [2018-02-04 13:43:16,744 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,769 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 13:43:16,769 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:61, output treesize:65 [2018-02-04 13:43:16,926 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 3 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 16 [2018-02-04 13:43:16,927 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,957 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 20 [2018-02-04 13:43:16,957 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:16,982 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 28 [2018-02-04 13:43:16,983 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:17,006 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 35 treesize of output 20 [2018-02-04 13:43:17,006 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:17,025 INFO L267 ElimStorePlain]: Start of recursive call 1: 8 dim-0 vars, 4 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:17,025 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 12 variables, input treesize:141, output treesize:3 [2018-02-04 13:43:17,031 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:17,031 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 45 [2018-02-04 13:43:17,032 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:17,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:17,054 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 5 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 45 [2018-02-04 13:43:17,055 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:17,072 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 13:43:17,072 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:91, output treesize:63 [2018-02-04 13:43:17,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:17,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:17,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:17,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 36 [2018-02-04 13:43:17,116 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:17,124 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 13:43:17,124 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:34, output treesize:28 [2018-02-04 13:43:17,152 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 13:43:17,175 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:17,175 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 14] total 21 [2018-02-04 13:43:17,175 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 13:43:17,175 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 13:43:17,175 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=395, Unknown=0, NotChecked=0, Total=462 [2018-02-04 13:43:17,175 INFO L87 Difference]: Start difference. First operand 469 states and 531 transitions. Second operand 22 states. [2018-02-04 13:43:19,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:19,487 INFO L93 Difference]: Finished difference Result 623 states and 693 transitions. [2018-02-04 13:43:19,488 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 13:43:19,488 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 40 [2018-02-04 13:43:19,488 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:19,489 INFO L225 Difference]: With dead ends: 623 [2018-02-04 13:43:19,489 INFO L226 Difference]: Without dead ends: 623 [2018-02-04 13:43:19,489 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 34 SyntacticMatches, 7 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 133 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=153, Invalid=903, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 13:43:19,490 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 623 states. [2018-02-04 13:43:19,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 623 to 512. [2018-02-04 13:43:19,494 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 512 states. [2018-02-04 13:43:19,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 512 states to 512 states and 593 transitions. [2018-02-04 13:43:19,495 INFO L78 Accepts]: Start accepts. Automaton has 512 states and 593 transitions. Word has length 40 [2018-02-04 13:43:19,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:19,496 INFO L432 AbstractCegarLoop]: Abstraction has 512 states and 593 transitions. [2018-02-04 13:43:19,496 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 13:43:19,496 INFO L276 IsEmpty]: Start isEmpty. Operand 512 states and 593 transitions. [2018-02-04 13:43:19,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 13:43:19,496 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:19,496 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:19,497 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:19,497 INFO L82 PathProgramCache]: Analyzing trace with hash 1592821110, now seen corresponding path program 1 times [2018-02-04 13:43:19,497 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:19,497 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:19,498 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:19,498 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:19,498 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:19,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:19,505 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:19,598 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:43:19,598 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:19,598 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:19,607 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:19,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:19,627 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:19,723 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:43:19,754 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:19,754 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 8] total 12 [2018-02-04 13:43:19,754 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 13:43:19,754 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 13:43:19,755 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=122, Unknown=9, NotChecked=0, Total=156 [2018-02-04 13:43:19,755 INFO L87 Difference]: Start difference. First operand 512 states and 593 transitions. Second operand 13 states. [2018-02-04 13:43:21,147 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:21,147 INFO L93 Difference]: Finished difference Result 570 states and 663 transitions. [2018-02-04 13:43:21,147 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 13:43:21,147 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 39 [2018-02-04 13:43:21,147 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:21,148 INFO L225 Difference]: With dead ends: 570 [2018-02-04 13:43:21,148 INFO L226 Difference]: Without dead ends: 552 [2018-02-04 13:43:21,149 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 57 GetRequests, 38 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=50, Invalid=247, Unknown=9, NotChecked=0, Total=306 [2018-02-04 13:43:21,149 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 552 states. [2018-02-04 13:43:21,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 552 to 495. [2018-02-04 13:43:21,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-02-04 13:43:21,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 575 transitions. [2018-02-04 13:43:21,153 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 575 transitions. Word has length 39 [2018-02-04 13:43:21,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:21,153 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 575 transitions. [2018-02-04 13:43:21,153 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 13:43:21,153 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 575 transitions. [2018-02-04 13:43:21,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 13:43:21,153 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:21,154 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:21,154 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:21,154 INFO L82 PathProgramCache]: Analyzing trace with hash 1647553023, now seen corresponding path program 1 times [2018-02-04 13:43:21,154 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:21,154 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:21,155 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:21,155 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:21,155 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:21,164 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:21,165 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:21,299 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 13:43:21,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:21,300 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:21,310 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:21,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:21,346 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:21,348 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:21,348 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,350 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,350 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:21,378 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 13:43:21,381 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:21,381 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,391 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,397 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,397 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-02-04 13:43:21,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-02-04 13:43:21,446 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:21,447 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-02-04 13:43:21,447 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,464 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,473 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,473 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:22 [2018-02-04 13:43:21,507 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:43:21,507 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,513 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,513 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:25, output treesize:20 [2018-02-04 13:43:21,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:21,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:21,624 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 13:43:21,624 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,627 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,627 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:27, output treesize:21 [2018-02-04 13:43:21,672 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 29 [2018-02-04 13:43:21,673 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:21,674 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,678 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,683 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,683 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:17 [2018-02-04 13:43:21,686 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-02-04 13:43:21,688 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:21,688 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-02-04 13:43:21,689 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,691 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,693 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:21,693 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:5 [2018-02-04 13:43:21,697 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 13:43:21,715 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:21,715 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 12] total 18 [2018-02-04 13:43:21,715 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 13:43:21,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 13:43:21,715 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=278, Unknown=0, NotChecked=0, Total=342 [2018-02-04 13:43:21,716 INFO L87 Difference]: Start difference. First operand 495 states and 575 transitions. Second operand 19 states. [2018-02-04 13:43:22,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:22,825 INFO L93 Difference]: Finished difference Result 553 states and 617 transitions. [2018-02-04 13:43:22,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 13:43:22,825 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 42 [2018-02-04 13:43:22,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:22,826 INFO L225 Difference]: With dead ends: 553 [2018-02-04 13:43:22,826 INFO L226 Difference]: Without dead ends: 553 [2018-02-04 13:43:22,826 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 36 SyntacticMatches, 4 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=156, Invalid=656, Unknown=0, NotChecked=0, Total=812 [2018-02-04 13:43:22,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 553 states. [2018-02-04 13:43:22,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 553 to 503. [2018-02-04 13:43:22,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 503 states. [2018-02-04 13:43:22,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 503 states to 503 states and 581 transitions. [2018-02-04 13:43:22,830 INFO L78 Accepts]: Start accepts. Automaton has 503 states and 581 transitions. Word has length 42 [2018-02-04 13:43:22,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:22,830 INFO L432 AbstractCegarLoop]: Abstraction has 503 states and 581 transitions. [2018-02-04 13:43:22,831 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 13:43:22,831 INFO L276 IsEmpty]: Start isEmpty. Operand 503 states and 581 transitions. [2018-02-04 13:43:22,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 13:43:22,831 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:22,831 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:22,831 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:22,831 INFO L82 PathProgramCache]: Analyzing trace with hash 1647553024, now seen corresponding path program 1 times [2018-02-04 13:43:22,831 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:22,831 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:22,832 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:22,832 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:22,832 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:22,839 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:22,840 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:23,052 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 13:43:23,053 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:23,053 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:23,068 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:23,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:23,097 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:23,100 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:23,100 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,105 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,105 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-02-04 13:43:23,120 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 13:43:23,121 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:23,121 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,123 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 13:43:23,134 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:23,134 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,136 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,140 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,140 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:31, output treesize:23 [2018-02-04 13:43:23,155 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-02-04 13:43:23,179 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:23,180 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-02-04 13:43:23,180 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,193 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,203 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-02-04 13:43:23,207 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:23,207 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-02-04 13:43:23,207 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,210 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,215 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,216 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:49, output treesize:41 [2018-02-04 13:43:23,233 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:43:23,233 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,238 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,238 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:44, output treesize:39 [2018-02-04 13:43:23,291 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:23,291 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:23,292 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 13:43:23,292 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,297 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,298 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:46, output treesize:40 [2018-02-04 13:43:23,366 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 29 [2018-02-04 13:43:23,368 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:23,368 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,372 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,385 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 29 [2018-02-04 13:43:23,387 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:23,387 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,390 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,398 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,398 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:62, output treesize:36 [2018-02-04 13:43:23,405 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-02-04 13:43:23,407 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:23,408 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-02-04 13:43:23,408 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,420 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,428 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-02-04 13:43:23,430 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:23,430 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-02-04 13:43:23,431 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,433 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,437 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:23,441 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:57, output treesize:11 [2018-02-04 13:43:23,466 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 13:43:23,483 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:23,483 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 12] total 20 [2018-02-04 13:43:23,484 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 13:43:23,484 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 13:43:23,484 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=368, Unknown=0, NotChecked=0, Total=420 [2018-02-04 13:43:23,484 INFO L87 Difference]: Start difference. First operand 503 states and 581 transitions. Second operand 21 states. [2018-02-04 13:43:25,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:25,156 INFO L93 Difference]: Finished difference Result 557 states and 621 transitions. [2018-02-04 13:43:25,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 13:43:25,156 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 42 [2018-02-04 13:43:25,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:25,157 INFO L225 Difference]: With dead ends: 557 [2018-02-04 13:43:25,157 INFO L226 Difference]: Without dead ends: 557 [2018-02-04 13:43:25,158 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 36 SyntacticMatches, 4 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=227, Invalid=1105, Unknown=0, NotChecked=0, Total=1332 [2018-02-04 13:43:25,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-02-04 13:43:25,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 503. [2018-02-04 13:43:25,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 503 states. [2018-02-04 13:43:25,162 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 503 states to 503 states and 580 transitions. [2018-02-04 13:43:25,162 INFO L78 Accepts]: Start accepts. Automaton has 503 states and 580 transitions. Word has length 42 [2018-02-04 13:43:25,163 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:25,163 INFO L432 AbstractCegarLoop]: Abstraction has 503 states and 580 transitions. [2018-02-04 13:43:25,163 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 13:43:25,163 INFO L276 IsEmpty]: Start isEmpty. Operand 503 states and 580 transitions. [2018-02-04 13:43:25,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-04 13:43:25,163 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:25,163 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:25,163 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:25,164 INFO L82 PathProgramCache]: Analyzing trace with hash -824107646, now seen corresponding path program 1 times [2018-02-04 13:43:25,164 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:25,164 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:25,164 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:25,165 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:25,165 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:25,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:25,170 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:25,187 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-04 13:43:25,187 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:25,187 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:25,193 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:25,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:25,213 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:25,221 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 6 proven. 2 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-04 13:43:25,247 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:25,247 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-02-04 13:43:25,247 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:43:25,247 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:43:25,247 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:43:25,247 INFO L87 Difference]: Start difference. First operand 503 states and 580 transitions. Second operand 6 states. [2018-02-04 13:43:25,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:25,264 INFO L93 Difference]: Finished difference Result 502 states and 579 transitions. [2018-02-04 13:43:25,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:43:25,265 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 46 [2018-02-04 13:43:25,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:25,266 INFO L225 Difference]: With dead ends: 502 [2018-02-04 13:43:25,266 INFO L226 Difference]: Without dead ends: 502 [2018-02-04 13:43:25,266 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 43 SyntacticMatches, 3 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:43:25,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 502 states. [2018-02-04 13:43:25,271 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 502 to 502. [2018-02-04 13:43:25,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 502 states. [2018-02-04 13:43:25,272 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 502 states to 502 states and 579 transitions. [2018-02-04 13:43:25,272 INFO L78 Accepts]: Start accepts. Automaton has 502 states and 579 transitions. Word has length 46 [2018-02-04 13:43:25,272 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:25,272 INFO L432 AbstractCegarLoop]: Abstraction has 502 states and 579 transitions. [2018-02-04 13:43:25,273 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:43:25,273 INFO L276 IsEmpty]: Start isEmpty. Operand 502 states and 579 transitions. [2018-02-04 13:43:25,273 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-04 13:43:25,273 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:25,273 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:25,273 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:25,274 INFO L82 PathProgramCache]: Analyzing trace with hash -824107645, now seen corresponding path program 1 times [2018-02-04 13:43:25,274 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:25,274 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:25,275 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:25,275 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:25,275 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:25,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:25,282 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:25,318 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 13:43:25,318 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:25,319 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:25,326 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:25,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:25,355 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:25,358 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:25,358 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:25,361 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:25,362 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:25,366 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 13:43:25,397 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:25,398 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-02-04 13:43:25,398 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 13:43:25,398 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 13:43:25,398 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:43:25,398 INFO L87 Difference]: Start difference. First operand 502 states and 579 transitions. Second operand 7 states. [2018-02-04 13:43:25,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:25,877 INFO L93 Difference]: Finished difference Result 568 states and 660 transitions. [2018-02-04 13:43:25,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:43:25,877 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 46 [2018-02-04 13:43:25,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:25,879 INFO L225 Difference]: With dead ends: 568 [2018-02-04 13:43:25,879 INFO L226 Difference]: Without dead ends: 568 [2018-02-04 13:43:25,879 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 46 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:43:25,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 568 states. [2018-02-04 13:43:25,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 568 to 503. [2018-02-04 13:43:25,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 503 states. [2018-02-04 13:43:25,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 503 states to 503 states and 580 transitions. [2018-02-04 13:43:25,883 INFO L78 Accepts]: Start accepts. Automaton has 503 states and 580 transitions. Word has length 46 [2018-02-04 13:43:25,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:25,884 INFO L432 AbstractCegarLoop]: Abstraction has 503 states and 580 transitions. [2018-02-04 13:43:25,884 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 13:43:25,884 INFO L276 IsEmpty]: Start isEmpty. Operand 503 states and 580 transitions. [2018-02-04 13:43:25,884 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 13:43:25,884 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:25,884 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:25,884 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:25,884 INFO L82 PathProgramCache]: Analyzing trace with hash 222466993, now seen corresponding path program 1 times [2018-02-04 13:43:25,884 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:25,884 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:25,885 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:25,885 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:25,885 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:25,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:25,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:25,999 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 13:43:25,999 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:25,999 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:26,007 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:26,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:26,047 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:26,052 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:26,052 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:26,053 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:26,053 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:43:26,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:26,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:26,086 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 13:43:26,087 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:26,088 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:26,088 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:4 [2018-02-04 13:43:26,149 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:26,149 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 3 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-02-04 13:43:26,150 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:26,156 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:43:26,157 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:20, output treesize:15 [2018-02-04 13:43:26,177 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 18 proven. 7 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-02-04 13:43:26,207 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:26,208 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 13] total 18 [2018-02-04 13:43:26,208 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 13:43:26,208 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 13:43:26,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=50, Invalid=292, Unknown=0, NotChecked=0, Total=342 [2018-02-04 13:43:26,208 INFO L87 Difference]: Start difference. First operand 503 states and 580 transitions. Second operand 19 states. [2018-02-04 13:43:27,129 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:27,129 INFO L93 Difference]: Finished difference Result 571 states and 663 transitions. [2018-02-04 13:43:27,129 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 13:43:27,129 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 47 [2018-02-04 13:43:27,130 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:27,131 INFO L225 Difference]: With dead ends: 571 [2018-02-04 13:43:27,131 INFO L226 Difference]: Without dead ends: 571 [2018-02-04 13:43:27,131 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 40 SyntacticMatches, 4 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 42 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=73, Invalid=389, Unknown=0, NotChecked=0, Total=462 [2018-02-04 13:43:27,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-04 13:43:27,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 504. [2018-02-04 13:43:27,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 504 states. [2018-02-04 13:43:27,134 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 581 transitions. [2018-02-04 13:43:27,135 INFO L78 Accepts]: Start accepts. Automaton has 504 states and 581 transitions. Word has length 47 [2018-02-04 13:43:27,135 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:27,135 INFO L432 AbstractCegarLoop]: Abstraction has 504 states and 581 transitions. [2018-02-04 13:43:27,135 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 13:43:27,135 INFO L276 IsEmpty]: Start isEmpty. Operand 504 states and 581 transitions. [2018-02-04 13:43:27,135 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 13:43:27,135 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:27,135 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:27,135 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:27,135 INFO L82 PathProgramCache]: Analyzing trace with hash 1340530292, now seen corresponding path program 1 times [2018-02-04 13:43:27,135 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:27,136 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:27,136 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:27,136 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:27,136 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:27,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:27,146 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:27,357 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-02-04 13:43:27,357 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:27,357 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:27,362 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:27,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:27,380 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:27,381 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:43:27,381 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,383 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,383 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-02-04 13:43:27,392 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 13:43:27,393 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:27,393 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,394 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,399 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 8 [2018-02-04 13:43:27,400 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:27,400 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,401 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,405 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,405 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:31, output treesize:23 [2018-02-04 13:43:27,417 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-02-04 13:43:27,418 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:27,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-02-04 13:43:27,419 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,422 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,430 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 16 [2018-02-04 13:43:27,431 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:27,432 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-02-04 13:43:27,432 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,435 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,440 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,440 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:49, output treesize:41 [2018-02-04 13:43:27,460 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:43:27,461 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,466 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,466 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:44, output treesize:39 [2018-02-04 13:43:27,512 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:27,513 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:27,514 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-02-04 13:43:27,514 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,520 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,520 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:46, output treesize:40 [2018-02-04 13:43:27,594 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 29 [2018-02-04 13:43:27,596 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:27,596 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,601 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,614 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 29 [2018-02-04 13:43:27,615 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-02-04 13:43:27,615 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,620 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,628 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,629 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:62, output treesize:36 [2018-02-04 13:43:27,633 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-02-04 13:43:27,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:27,635 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-02-04 13:43:27,635 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,637 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,643 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-02-04 13:43:27,645 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:27,645 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 10 [2018-02-04 13:43:27,645 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,648 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,651 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:43:27,651 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 2 variables, input treesize:50, output treesize:10 [2018-02-04 13:43:27,708 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 13:43:27,724 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:43:27,724 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 14] total 24 [2018-02-04 13:43:27,724 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 13:43:27,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 13:43:27,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=486, Unknown=0, NotChecked=0, Total=552 [2018-02-04 13:43:27,725 INFO L87 Difference]: Start difference. First operand 504 states and 581 transitions. Second operand 24 states. [2018-02-04 13:43:29,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:29,467 INFO L93 Difference]: Finished difference Result 511 states and 556 transitions. [2018-02-04 13:43:29,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 13:43:29,467 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 48 [2018-02-04 13:43:29,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:29,468 INFO L225 Difference]: With dead ends: 511 [2018-02-04 13:43:29,468 INFO L226 Difference]: Without dead ends: 511 [2018-02-04 13:43:29,468 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 41 SyntacticMatches, 4 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 212 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=241, Invalid=1241, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 13:43:29,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 511 states. [2018-02-04 13:43:29,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 511 to 471. [2018-02-04 13:43:29,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-04 13:43:29,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 531 transitions. [2018-02-04 13:43:29,472 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 531 transitions. Word has length 48 [2018-02-04 13:43:29,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:29,472 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 531 transitions. [2018-02-04 13:43:29,472 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 13:43:29,472 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 531 transitions. [2018-02-04 13:43:29,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 13:43:29,472 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:29,472 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:29,472 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:29,473 INFO L82 PathProgramCache]: Analyzing trace with hash 1800754789, now seen corresponding path program 1 times [2018-02-04 13:43:29,473 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:29,473 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:29,473 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:29,473 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:29,473 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:29,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:29,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:29,506 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 9 proven. 0 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-02-04 13:43:29,506 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:43:29,506 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:43:29,506 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:43:29,506 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:43:29,507 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:43:29,507 INFO L87 Difference]: Start difference. First operand 471 states and 531 transitions. Second operand 6 states. [2018-02-04 13:43:29,525 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:43:29,525 INFO L93 Difference]: Finished difference Result 492 states and 556 transitions. [2018-02-04 13:43:29,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:43:29,526 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 48 [2018-02-04 13:43:29,526 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:43:29,527 INFO L225 Difference]: With dead ends: 492 [2018-02-04 13:43:29,527 INFO L226 Difference]: Without dead ends: 492 [2018-02-04 13:43:29,527 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:43:29,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 492 states. [2018-02-04 13:43:29,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 492 to 471. [2018-02-04 13:43:29,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 471 states. [2018-02-04 13:43:29,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 471 states to 471 states and 530 transitions. [2018-02-04 13:43:29,532 INFO L78 Accepts]: Start accepts. Automaton has 471 states and 530 transitions. Word has length 48 [2018-02-04 13:43:29,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:43:29,532 INFO L432 AbstractCegarLoop]: Abstraction has 471 states and 530 transitions. [2018-02-04 13:43:29,532 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:43:29,532 INFO L276 IsEmpty]: Start isEmpty. Operand 471 states and 530 transitions. [2018-02-04 13:43:29,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 13:43:29,532 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:43:29,533 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:43:29,533 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, alloc_12Err2RequiresViolation, alloc_12Err13RequiresViolation, alloc_12Err14RequiresViolation, alloc_12Err6RequiresViolation, alloc_12Err7RequiresViolation, alloc_12Err4RequiresViolation, alloc_12Err11RequiresViolation, alloc_12Err0RequiresViolation, alloc_12Err9RequiresViolation, alloc_12Err5RequiresViolation, alloc_12Err15RequiresViolation, alloc_12Err1RequiresViolation, alloc_12Err10RequiresViolation, alloc_12Err8RequiresViolation, alloc_12Err3RequiresViolation, alloc_12Err12RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:43:29,533 INFO L82 PathProgramCache]: Analyzing trace with hash 1800754818, now seen corresponding path program 1 times [2018-02-04 13:43:29,533 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:43:29,533 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:43:29,533 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:29,533 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:29,534 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:43:29,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:29,541 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:43:29,849 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 18 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 13:43:29,850 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:43:29,850 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:43:29,857 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:43:29,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:43:29,888 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:43:29,900 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 13:43:29,901 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:29,902 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 13:43:29,903 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:29,918 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 13:43:29,919 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:29,932 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 13:43:29,933 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:29,944 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 13:43:29,945 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 13:43:30,098 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,099 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,099 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 44 [2018-02-04 13:43:30,099 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,118 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 47 [2018-02-04 13:43:30,119 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,138 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,138 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,139 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 42 [2018-02-04 13:43:30,139 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,173 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 35 [2018-02-04 13:43:30,173 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,189 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 4 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 13:43:30,189 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:79, output treesize:69 [2018-02-04 13:43:30,339 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,340 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,342 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,342 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 88 [2018-02-04 13:43:30,343 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,433 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,433 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,434 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,434 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 68 [2018-02-04 13:43:30,435 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,524 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,525 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,525 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,526 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,527 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,528 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 88 [2018-02-04 13:43:30,528 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,639 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 66 [2018-02-04 13:43:30,639 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,715 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,716 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,717 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,717 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,718 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,719 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 84 [2018-02-04 13:43:30,720 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,798 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,799 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,799 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,800 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,800 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 68 [2018-02-04 13:43:30,801 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,895 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,896 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,897 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,898 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:30,899 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 70 [2018-02-04 13:43:30,899 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:30,997 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:31,003 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:31,004 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:31,004 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 66 [2018-02-04 13:43:31,004 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:31,070 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 8 dim-1 vars, End of recursive call: 16 dim-0 vars, and 4 xjuncts. [2018-02-04 13:43:31,070 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 24 variables, input treesize:237, output treesize:225 [2018-02-04 13:43:38,013 WARN L146 SmtUtils]: Spent 6896ms on a formula simplification. DAG size of input: 111 DAG size of output 87 [2018-02-04 13:43:38,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,083 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 76 treesize of output 76 [2018-02-04 13:43:38,083 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:38,275 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,276 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,277 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,279 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,281 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 9 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 101 [2018-02-04 13:43:38,281 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:38,548 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,549 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,549 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,550 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,550 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 80 treesize of output 72 [2018-02-04 13:43:38,551 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:38,758 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,758 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,759 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,760 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,760 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,761 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,762 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,765 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 10 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 129 [2018-02-04 13:43:38,765 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:38,961 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,964 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,964 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:38,964 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 72 treesize of output 72 [2018-02-04 13:43:38,965 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:39,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,122 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,123 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 70 [2018-02-04 13:43:39,123 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:39,273 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,274 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,275 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,275 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,276 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,278 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 9 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 64 treesize of output 95 [2018-02-04 13:43:39,279 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:39,439 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 70 treesize of output 69 [2018-02-04 13:43:39,439 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:39,580 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,581 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,582 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,583 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 9 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 72 treesize of output 101 [2018-02-04 13:43:39,583 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:39,724 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,724 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,725 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,725 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,726 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,726 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,727 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,728 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,729 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,730 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 10 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 74 treesize of output 129 [2018-02-04 13:43:39,730 INFO L267 ElimStorePlain]: Start of recursive call 11: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:39,874 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,875 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,875 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,883 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,884 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,884 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:39,885 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 73 treesize of output 73 [2018-02-04 13:43:39,885 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:40,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:40,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:40,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:40,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:40,017 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:40,017 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:43:40,018 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 7 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 73 treesize of output 73 [2018-02-04 13:43:40,018 INFO L267 ElimStorePlain]: Start of recursive call 13: End of recursive call: and 1 xjuncts. [2018-02-04 13:43:40,134 INFO L267 ElimStorePlain]: Start of recursive call 1: 36 dim-0 vars, 12 dim-1 vars, End of recursive call: 36 dim-0 vars, and 6 xjuncts. [2018-02-04 13:43:40,134 INFO L202 ElimStorePlain]: Needed 13 recursive calls to eliminate 48 variables, input treesize:455, output treesize:365 Received shutdown request... [2018-02-04 13:44:16,752 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-02-04 13:44:16,752 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 13:44:16,756 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 13:44:16,756 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 01:44:16 BoogieIcfgContainer [2018-02-04 13:44:16,756 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 13:44:16,757 INFO L168 Benchmark]: Toolchain (without parser) took 206526.21 ms. Allocated memory was 407.4 MB in the beginning and 714.6 MB in the end (delta: 307.2 MB). Free memory was 364.2 MB in the beginning and 668.3 MB in the end (delta: -304.1 MB). Peak memory consumption was 311.1 MB. Max. memory is 5.3 GB. [2018-02-04 13:44:16,757 INFO L168 Benchmark]: CDTParser took 0.09 ms. Allocated memory is still 407.4 MB. Free memory is still 370.9 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 13:44:16,757 INFO L168 Benchmark]: CACSL2BoogieTranslator took 202.73 ms. Allocated memory is still 407.4 MB. Free memory was 364.2 MB in the beginning and 346.8 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. [2018-02-04 13:44:16,758 INFO L168 Benchmark]: Boogie Preprocessor took 44.21 ms. Allocated memory is still 407.4 MB. Free memory was 346.8 MB in the beginning and 344.2 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-04 13:44:16,758 INFO L168 Benchmark]: RCFGBuilder took 715.81 ms. Allocated memory was 407.4 MB in the beginning and 424.7 MB in the end (delta: 17.3 MB). Free memory was 344.2 MB in the beginning and 384.0 MB in the end (delta: -39.8 MB). Peak memory consumption was 100.9 MB. Max. memory is 5.3 GB. [2018-02-04 13:44:16,758 INFO L168 Benchmark]: TraceAbstraction took 205560.63 ms. Allocated memory was 424.7 MB in the beginning and 714.6 MB in the end (delta: 289.9 MB). Free memory was 382.0 MB in the beginning and 668.3 MB in the end (delta: -286.3 MB). Peak memory consumption was 311.6 MB. Max. memory is 5.3 GB. [2018-02-04 13:44:16,759 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.09 ms. Allocated memory is still 407.4 MB. Free memory is still 370.9 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 202.73 ms. Allocated memory is still 407.4 MB. Free memory was 364.2 MB in the beginning and 346.8 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 44.21 ms. Allocated memory is still 407.4 MB. Free memory was 346.8 MB in the beginning and 344.2 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 715.81 ms. Allocated memory was 407.4 MB in the beginning and 424.7 MB in the end (delta: 17.3 MB). Free memory was 344.2 MB in the beginning and 384.0 MB in the end (delta: -39.8 MB). Peak memory consumption was 100.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 205560.63 ms. Allocated memory was 424.7 MB in the beginning and 714.6 MB in the end (delta: 289.9 MB). Free memory was 382.0 MB in the beginning and 668.3 MB in the end (delta: -286.3 MB). Peak memory consumption was 311.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1121). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1179). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1157). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1156). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1559). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1563). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1545). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1563). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1541). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1551). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1546). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1542). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1559). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1115). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1116). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1164). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1163). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1619]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1619). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1131). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1522). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1515). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1530). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1512). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1110). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1107). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1109). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1108). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1135). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1508). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1569). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1574). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1570). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1569). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1574). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1571). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1592). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1609). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1613). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1584). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1584). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1607). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1613). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1597). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1599). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1605). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1588). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1611). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1597). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1607). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1609). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1611). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1592). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1588). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1599). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1605). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1146). Cancelled while BasicCegarLoop was analyzing trace of length 49 with TraceHistMax 4, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 192. - StatisticsResult: Ultimate Automizer benchmark data CFG has 28 procedures, 416 locations, 141 error locations. TIMEOUT Result, 205.5s OverallTime, 34 OverallIterations, 4 TraceHistogramMax, 150.3s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 12078 SDtfs, 9688 SDslu, 49871 SDs, 0 SdLazy, 42836 SolverSat, 2420 SolverUnsat, 120 SolverUnknown, 0 SolverNotchecked, 39.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1135 GetRequests, 667 SyntacticMatches, 71 SemanticMatches, 397 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1036 ImplicationChecksByTransitivity, 110.5s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=538occurred in iteration=4, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 33 MinimizatonAttempts, 1885 StatesRemovedByMinimization, 31 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 6.0s InterpolantComputationTime, 1783 NumberOfCodeBlocks, 1783 NumberOfCodeBlocksAsserted, 53 NumberOfCheckSat, 1730 ConstructedInterpolants, 49 QuantifiedInterpolants, 517589 SizeOfPredicates, 105 NumberOfNonLiveVariables, 3672 ConjunctsInSsa, 439 ConjunctsInUnsatCore, 53 InterpolantComputations, 13 PerfectInterpolantSequences, 451/602 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_13-44-16-767.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_false-valid-free.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_13-44-16-767.csv Completed graceful shutdown