java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_true-valid-memsafety.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 13:57:51,093 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 13:57:51,095 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 13:57:51,108 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 13:57:51,108 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 13:57:51,109 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 13:57:51,110 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 13:57:51,112 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 13:57:51,114 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 13:57:51,114 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 13:57:51,115 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 13:57:51,115 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 13:57:51,116 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 13:57:51,117 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 13:57:51,118 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 13:57:51,119 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 13:57:51,121 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 13:57:51,123 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 13:57:51,124 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 13:57:51,125 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 13:57:51,126 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 13:57:51,127 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 13:57:51,127 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 13:57:51,128 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 13:57:51,129 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 13:57:51,130 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 13:57:51,130 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 13:57:51,130 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 13:57:51,131 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 13:57:51,131 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 13:57:51,131 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 13:57:51,132 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-02-04 13:57:51,142 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 13:57:51,142 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 13:57:51,143 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 13:57:51,143 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 13:57:51,144 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 13:57:51,144 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 13:57:51,144 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 13:57:51,144 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 13:57:51,144 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 13:57:51,144 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 13:57:51,145 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 13:57:51,145 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 13:57:51,145 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 13:57:51,145 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 13:57:51,145 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 13:57:51,145 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 13:57:51,146 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 13:57:51,146 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 13:57:51,146 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 13:57:51,146 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 13:57:51,146 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 13:57:51,146 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 13:57:51,147 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 13:57:51,147 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL [2018-02-04 13:57:51,174 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 13:57:51,185 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 13:57:51,188 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 13:57:51,189 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 13:57:51,189 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 13:57:51,190 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test12_true-valid-memsafety.i [2018-02-04 13:57:51,337 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 13:57:51,338 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 13:57:51,338 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 13:57:51,338 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 13:57:51,343 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 13:57:51,343 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,346 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@63bdc3e5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51, skipping insertion in model container [2018-02-04 13:57:51,346 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,356 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 13:57:51,398 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 13:57:51,525 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 13:57:51,560 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 13:57:51,575 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51 WrapperNode [2018-02-04 13:57:51,575 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 13:57:51,576 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 13:57:51,576 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 13:57:51,576 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 13:57:51,585 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,586 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,595 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,595 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,602 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,605 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,607 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... [2018-02-04 13:57:51,610 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 13:57:51,611 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 13:57:51,611 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 13:57:51,611 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 13:57:51,612 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_add [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure __ldv_list_del [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_add [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_list_del [2018-02-04 13:57:51,649 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_alloc [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_fill [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_msg_free [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_submit_msg [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_destroy_msgs [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_get_clientdata [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_set_clientdata [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure master_xfer [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_i2c_transfer [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_m88ts2022_rd_reg [2018-02-04 13:57:51,650 INFO L136 BoogieDeclarations]: Found implementation of procedure alloc_fix_12 [2018-02-04 13:57:51,651 INFO L136 BoogieDeclarations]: Found implementation of procedure free_12 [2018-02-04 13:57:51,651 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 13:57:51,651 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 13:57:51,651 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memcpy [2018-02-04 13:57:51,652 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memcpy [2018-02-04 13:57:51,652 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 13:57:51,652 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 13:57:51,652 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 13:57:51,652 INFO L128 BoogieDeclarations]: Found specification of procedure memcpy [2018-02-04 13:57:51,652 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 13:57:51,652 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_add [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure __ldv_list_del [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_add [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_list_del [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_alloc [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_fill [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_msg_free [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_submit_msg [2018-02-04 13:57:51,653 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_destroy_msgs [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_get_clientdata [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_set_clientdata [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure master_xfer [2018-02-04 13:57:51,654 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_i2c_transfer [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~X~$Pointer$~X~int~TO~int [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_m88ts2022_rd_reg [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure alloc_fix_12 [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure free_12 [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 13:57:51,655 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 13:57:52,229 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-04 13:57:52,335 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 13:57:52,336 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 01:57:52 BoogieIcfgContainer [2018-02-04 13:57:52,336 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 13:57:52,336 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 13:57:52,337 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 13:57:52,339 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 13:57:52,339 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 01:57:51" (1/3) ... [2018-02-04 13:57:52,340 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4db8ddb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 01:57:52, skipping insertion in model container [2018-02-04 13:57:52,340 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 01:57:51" (2/3) ... [2018-02-04 13:57:52,340 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@4db8ddb1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 01:57:52, skipping insertion in model container [2018-02-04 13:57:52,340 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 01:57:52" (3/3) ... [2018-02-04 13:57:52,342 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test12_true-valid-memsafety.i [2018-02-04 13:57:52,349 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 13:57:52,355 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 141 error locations. [2018-02-04 13:57:52,387 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 13:57:52,387 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 13:57:52,387 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 13:57:52,387 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 13:57:52,388 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 13:57:52,388 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 13:57:52,388 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 13:57:52,388 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 13:57:52,388 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 13:57:52,407 INFO L276 IsEmpty]: Start isEmpty. Operand 398 states. [2018-02-04 13:57:52,414 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-04 13:57:52,414 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:52,415 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-04 13:57:52,415 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:52,419 INFO L82 PathProgramCache]: Analyzing trace with hash 18685926, now seen corresponding path program 1 times [2018-02-04 13:57:52,420 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:52,421 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:52,470 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:52,470 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:52,470 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:52,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:52,497 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:52,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:52,595 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:52,595 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 13:57:52,597 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 13:57:52,608 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 13:57:52,609 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:57:52,611 INFO L87 Difference]: Start difference. First operand 398 states. Second operand 3 states. [2018-02-04 13:57:52,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:52,922 INFO L93 Difference]: Finished difference Result 487 states and 527 transitions. [2018-02-04 13:57:52,922 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 13:57:52,923 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-04 13:57:52,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:52,938 INFO L225 Difference]: With dead ends: 487 [2018-02-04 13:57:52,938 INFO L226 Difference]: Without dead ends: 481 [2018-02-04 13:57:52,939 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:57:52,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 481 states. [2018-02-04 13:57:52,980 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 481 to 436. [2018-02-04 13:57:52,981 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 436 states. [2018-02-04 13:57:52,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 436 states to 436 states and 491 transitions. [2018-02-04 13:57:52,984 INFO L78 Accepts]: Start accepts. Automaton has 436 states and 491 transitions. Word has length 4 [2018-02-04 13:57:52,984 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:52,984 INFO L432 AbstractCegarLoop]: Abstraction has 436 states and 491 transitions. [2018-02-04 13:57:52,984 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 13:57:52,984 INFO L276 IsEmpty]: Start isEmpty. Operand 436 states and 491 transitions. [2018-02-04 13:57:52,984 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 5 [2018-02-04 13:57:52,985 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:52,985 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1] [2018-02-04 13:57:52,985 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:52,985 INFO L82 PathProgramCache]: Analyzing trace with hash 18685927, now seen corresponding path program 1 times [2018-02-04 13:57:52,985 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:52,985 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:52,987 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:52,987 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:52,987 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:52,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:52,999 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:53,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:53,030 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:53,030 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 13:57:53,031 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 13:57:53,031 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 13:57:53,031 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:57:53,032 INFO L87 Difference]: Start difference. First operand 436 states and 491 transitions. Second operand 3 states. [2018-02-04 13:57:53,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:53,212 INFO L93 Difference]: Finished difference Result 567 states and 652 transitions. [2018-02-04 13:57:53,212 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 13:57:53,212 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 4 [2018-02-04 13:57:53,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:53,215 INFO L225 Difference]: With dead ends: 567 [2018-02-04 13:57:53,215 INFO L226 Difference]: Without dead ends: 567 [2018-02-04 13:57:53,216 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 13:57:53,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 567 states. [2018-02-04 13:57:53,236 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 567 to 497. [2018-02-04 13:57:53,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 497 states. [2018-02-04 13:57:53,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 497 states to 497 states and 602 transitions. [2018-02-04 13:57:53,241 INFO L78 Accepts]: Start accepts. Automaton has 497 states and 602 transitions. Word has length 4 [2018-02-04 13:57:53,241 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:53,241 INFO L432 AbstractCegarLoop]: Abstraction has 497 states and 602 transitions. [2018-02-04 13:57:53,241 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 13:57:53,241 INFO L276 IsEmpty]: Start isEmpty. Operand 497 states and 602 transitions. [2018-02-04 13:57:53,242 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 13:57:53,242 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:53,242 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:53,243 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:53,243 INFO L82 PathProgramCache]: Analyzing trace with hash -769194584, now seen corresponding path program 1 times [2018-02-04 13:57:53,243 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:53,243 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:53,245 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:53,245 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:53,245 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:53,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:53,272 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:53,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:53,327 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:53,328 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:57:53,328 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:57:53,328 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:57:53,328 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:57:53,329 INFO L87 Difference]: Start difference. First operand 497 states and 602 transitions. Second operand 6 states. [2018-02-04 13:57:53,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:53,411 INFO L93 Difference]: Finished difference Result 543 states and 666 transitions. [2018-02-04 13:57:53,413 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:57:53,413 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 21 [2018-02-04 13:57:53,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:53,416 INFO L225 Difference]: With dead ends: 543 [2018-02-04 13:57:53,416 INFO L226 Difference]: Without dead ends: 543 [2018-02-04 13:57:53,416 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:57:53,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 543 states. [2018-02-04 13:57:53,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 543 to 496. [2018-02-04 13:57:53,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 496 states. [2018-02-04 13:57:53,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 496 states to 496 states and 604 transitions. [2018-02-04 13:57:53,430 INFO L78 Accepts]: Start accepts. Automaton has 496 states and 604 transitions. Word has length 21 [2018-02-04 13:57:53,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:53,431 INFO L432 AbstractCegarLoop]: Abstraction has 496 states and 604 transitions. [2018-02-04 13:57:53,431 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:57:53,431 INFO L276 IsEmpty]: Start isEmpty. Operand 496 states and 604 transitions. [2018-02-04 13:57:53,431 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 13:57:53,431 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:53,431 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:53,432 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:53,432 INFO L82 PathProgramCache]: Analyzing trace with hash 976272294, now seen corresponding path program 1 times [2018-02-04 13:57:53,432 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:53,432 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:53,433 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:53,433 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:53,433 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:53,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:53,451 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:53,521 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:53,522 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:53,522 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 13:57:53,522 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:57:53,522 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:57:53,522 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:57:53,523 INFO L87 Difference]: Start difference. First operand 496 states and 604 transitions. Second operand 5 states. [2018-02-04 13:57:53,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:53,774 INFO L93 Difference]: Finished difference Result 571 states and 703 transitions. [2018-02-04 13:57:53,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:57:53,774 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 21 [2018-02-04 13:57:53,774 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:53,776 INFO L225 Difference]: With dead ends: 571 [2018-02-04 13:57:53,776 INFO L226 Difference]: Without dead ends: 571 [2018-02-04 13:57:53,776 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:57:53,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 571 states. [2018-02-04 13:57:53,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 571 to 538. [2018-02-04 13:57:53,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-04 13:57:53,796 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 661 transitions. [2018-02-04 13:57:53,796 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 661 transitions. Word has length 21 [2018-02-04 13:57:53,796 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:53,796 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 661 transitions. [2018-02-04 13:57:53,796 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:57:53,796 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 661 transitions. [2018-02-04 13:57:53,797 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-02-04 13:57:53,797 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:53,797 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:53,797 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:53,797 INFO L82 PathProgramCache]: Analyzing trace with hash 976272295, now seen corresponding path program 1 times [2018-02-04 13:57:53,797 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:53,797 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:53,798 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:53,799 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:53,799 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:53,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:53,812 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:53,911 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:53,912 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:53,912 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:57:53,912 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 13:57:53,912 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 13:57:53,913 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:57:53,913 INFO L87 Difference]: Start difference. First operand 538 states and 661 transitions. Second operand 7 states. [2018-02-04 13:57:54,900 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:54,900 INFO L93 Difference]: Finished difference Result 668 states and 771 transitions. [2018-02-04 13:57:54,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 13:57:54,900 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 21 [2018-02-04 13:57:54,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:54,903 INFO L225 Difference]: With dead ends: 668 [2018-02-04 13:57:54,903 INFO L226 Difference]: Without dead ends: 668 [2018-02-04 13:57:54,903 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 1 SyntacticMatches, 5 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-02-04 13:57:54,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 668 states. [2018-02-04 13:57:54,915 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 668 to 538. [2018-02-04 13:57:54,915 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 538 states. [2018-02-04 13:57:54,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 538 states to 538 states and 660 transitions. [2018-02-04 13:57:54,918 INFO L78 Accepts]: Start accepts. Automaton has 538 states and 660 transitions. Word has length 21 [2018-02-04 13:57:54,918 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:54,918 INFO L432 AbstractCegarLoop]: Abstraction has 538 states and 660 transitions. [2018-02-04 13:57:54,918 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 13:57:54,918 INFO L276 IsEmpty]: Start isEmpty. Operand 538 states and 660 transitions. [2018-02-04 13:57:54,919 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 13:57:54,919 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:54,919 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:54,920 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:54,920 INFO L82 PathProgramCache]: Analyzing trace with hash 886332479, now seen corresponding path program 1 times [2018-02-04 13:57:54,920 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:54,920 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:54,921 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:54,922 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:54,922 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:54,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:54,935 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:54,990 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:57:54,990 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:57:54,990 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:57:55,000 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:55,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:55,028 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:57:55,058 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:57:55,079 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:57:55,079 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 4] total 8 [2018-02-04 13:57:55,079 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 13:57:55,079 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 13:57:55,083 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:57:55,083 INFO L87 Difference]: Start difference. First operand 538 states and 660 transitions. Second operand 8 states. [2018-02-04 13:57:55,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:55,113 INFO L93 Difference]: Finished difference Result 503 states and 588 transitions. [2018-02-04 13:57:55,114 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:57:55,114 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-02-04 13:57:55,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:55,115 INFO L225 Difference]: With dead ends: 503 [2018-02-04 13:57:55,115 INFO L226 Difference]: Without dead ends: 503 [2018-02-04 13:57:55,115 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:57:55,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 503 states. [2018-02-04 13:57:55,125 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 503 to 495. [2018-02-04 13:57:55,125 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 495 states. [2018-02-04 13:57:55,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 495 states to 495 states and 574 transitions. [2018-02-04 13:57:55,127 INFO L78 Accepts]: Start accepts. Automaton has 495 states and 574 transitions. Word has length 24 [2018-02-04 13:57:55,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:55,127 INFO L432 AbstractCegarLoop]: Abstraction has 495 states and 574 transitions. [2018-02-04 13:57:55,127 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 13:57:55,128 INFO L276 IsEmpty]: Start isEmpty. Operand 495 states and 574 transitions. [2018-02-04 13:57:55,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 13:57:55,128 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:55,128 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:55,128 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:55,129 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343331, now seen corresponding path program 1 times [2018-02-04 13:57:55,129 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:55,129 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:55,130 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:55,130 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:55,130 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:55,140 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:55,141 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:55,167 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:57:55,167 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:57:55,167 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:57:55,172 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:55,190 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:55,192 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:57:55,203 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:57:55,224 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:57:55,224 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 5 [2018-02-04 13:57:55,224 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:57:55,224 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:57:55,224 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:57:55,225 INFO L87 Difference]: Start difference. First operand 495 states and 574 transitions. Second operand 6 states. [2018-02-04 13:57:55,269 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:55,269 INFO L93 Difference]: Finished difference Result 496 states and 579 transitions. [2018-02-04 13:57:55,270 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:57:55,271 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 26 [2018-02-04 13:57:55,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:55,273 INFO L225 Difference]: With dead ends: 496 [2018-02-04 13:57:55,273 INFO L226 Difference]: Without dead ends: 496 [2018-02-04 13:57:55,273 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 32 GetRequests, 23 SyntacticMatches, 4 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:57:55,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 496 states. [2018-02-04 13:57:55,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 496 to 494. [2018-02-04 13:57:55,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 494 states. [2018-02-04 13:57:55,284 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 494 states to 494 states and 572 transitions. [2018-02-04 13:57:55,284 INFO L78 Accepts]: Start accepts. Automaton has 494 states and 572 transitions. Word has length 26 [2018-02-04 13:57:55,284 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:55,284 INFO L432 AbstractCegarLoop]: Abstraction has 494 states and 572 transitions. [2018-02-04 13:57:55,284 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:57:55,285 INFO L276 IsEmpty]: Start isEmpty. Operand 494 states and 572 transitions. [2018-02-04 13:57:55,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 13:57:55,285 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:55,285 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:55,286 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:55,286 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343330, now seen corresponding path program 1 times [2018-02-04 13:57:55,286 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:55,286 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:55,287 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:55,287 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:55,287 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:55,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:55,297 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:55,341 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:55,341 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:57:55,342 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:57:55,349 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:55,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:55,372 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:57:55,397 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:57:55,399 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:55,400 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:57:55,400 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:57:55,410 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:55,436 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:57:55,436 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-02-04 13:57:55,436 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 13:57:55,436 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 13:57:55,437 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:57:55,437 INFO L87 Difference]: Start difference. First operand 494 states and 572 transitions. Second operand 7 states. [2018-02-04 13:57:56,154 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:56,154 INFO L93 Difference]: Finished difference Result 597 states and 705 transitions. [2018-02-04 13:57:56,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 13:57:56,154 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 26 [2018-02-04 13:57:56,154 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:56,156 INFO L225 Difference]: With dead ends: 597 [2018-02-04 13:57:56,156 INFO L226 Difference]: Without dead ends: 592 [2018-02-04 13:57:56,157 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 25 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=15, Invalid=41, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:57:56,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 592 states. [2018-02-04 13:57:56,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 592 to 521. [2018-02-04 13:57:56,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 521 states. [2018-02-04 13:57:56,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 521 states to 521 states and 620 transitions. [2018-02-04 13:57:56,166 INFO L78 Accepts]: Start accepts. Automaton has 521 states and 620 transitions. Word has length 26 [2018-02-04 13:57:56,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:56,166 INFO L432 AbstractCegarLoop]: Abstraction has 521 states and 620 transitions. [2018-02-04 13:57:56,166 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 13:57:56,166 INFO L276 IsEmpty]: Start isEmpty. Operand 521 states and 620 transitions. [2018-02-04 13:57:56,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-02-04 13:57:56,167 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:56,167 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:56,167 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:56,167 INFO L82 PathProgramCache]: Analyzing trace with hash -1359343329, now seen corresponding path program 1 times [2018-02-04 13:57:56,167 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:56,167 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:56,169 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:56,169 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:56,169 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:56,175 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:56,176 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:56,207 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:57:56,208 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:56,208 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 13:57:56,208 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:57:56,208 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:57:56,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:57:56,208 INFO L87 Difference]: Start difference. First operand 521 states and 620 transitions. Second operand 5 states. [2018-02-04 13:57:56,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:56,225 INFO L93 Difference]: Finished difference Result 523 states and 619 transitions. [2018-02-04 13:57:56,226 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 13:57:56,226 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 26 [2018-02-04 13:57:56,226 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:56,227 INFO L225 Difference]: With dead ends: 523 [2018-02-04 13:57:56,228 INFO L226 Difference]: Without dead ends: 523 [2018-02-04 13:57:56,228 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:57:56,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 523 states. [2018-02-04 13:57:56,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 523 to 520. [2018-02-04 13:57:56,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 520 states. [2018-02-04 13:57:56,236 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 520 states to 520 states and 617 transitions. [2018-02-04 13:57:56,236 INFO L78 Accepts]: Start accepts. Automaton has 520 states and 617 transitions. Word has length 26 [2018-02-04 13:57:56,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:56,236 INFO L432 AbstractCegarLoop]: Abstraction has 520 states and 617 transitions. [2018-02-04 13:57:56,236 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:57:56,236 INFO L276 IsEmpty]: Start isEmpty. Operand 520 states and 617 transitions. [2018-02-04 13:57:56,238 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 13:57:56,238 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:56,238 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:56,238 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:56,238 INFO L82 PathProgramCache]: Analyzing trace with hash -1082862565, now seen corresponding path program 1 times [2018-02-04 13:57:56,239 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:56,239 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:56,240 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:56,240 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:56,240 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:56,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:56,250 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:56,302 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:56,302 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:56,302 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 13:57:56,303 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 13:57:56,303 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 13:57:56,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 13:57:56,303 INFO L87 Difference]: Start difference. First operand 520 states and 617 transitions. Second operand 5 states. [2018-02-04 13:57:56,545 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:56,546 INFO L93 Difference]: Finished difference Result 541 states and 644 transitions. [2018-02-04 13:57:56,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:57:56,546 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 27 [2018-02-04 13:57:56,546 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:56,547 INFO L225 Difference]: With dead ends: 541 [2018-02-04 13:57:56,547 INFO L226 Difference]: Without dead ends: 541 [2018-02-04 13:57:56,548 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:57:56,548 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541 states. [2018-02-04 13:57:56,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541 to 537. [2018-02-04 13:57:56,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 537 states. [2018-02-04 13:57:56,562 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 537 states to 537 states and 638 transitions. [2018-02-04 13:57:56,562 INFO L78 Accepts]: Start accepts. Automaton has 537 states and 638 transitions. Word has length 27 [2018-02-04 13:57:56,562 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:56,562 INFO L432 AbstractCegarLoop]: Abstraction has 537 states and 638 transitions. [2018-02-04 13:57:56,562 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 13:57:56,562 INFO L276 IsEmpty]: Start isEmpty. Operand 537 states and 638 transitions. [2018-02-04 13:57:56,563 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-02-04 13:57:56,563 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:56,563 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:56,563 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:56,563 INFO L82 PathProgramCache]: Analyzing trace with hash -1082862564, now seen corresponding path program 1 times [2018-02-04 13:57:56,564 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:56,564 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:56,565 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:56,565 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:56,565 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:56,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:56,575 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:56,751 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:56,751 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:56,752 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 13:57:56,752 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 13:57:56,752 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 13:57:56,752 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-02-04 13:57:56,752 INFO L87 Difference]: Start difference. First operand 537 states and 638 transitions. Second operand 8 states. [2018-02-04 13:57:57,060 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:57,060 INFO L93 Difference]: Finished difference Result 500 states and 568 transitions. [2018-02-04 13:57:57,060 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 13:57:57,060 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 27 [2018-02-04 13:57:57,061 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:57,062 INFO L225 Difference]: With dead ends: 500 [2018-02-04 13:57:57,062 INFO L226 Difference]: Without dead ends: 488 [2018-02-04 13:57:57,062 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=92, Unknown=0, NotChecked=0, Total=132 [2018-02-04 13:57:57,063 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 488 states. [2018-02-04 13:57:57,069 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 488 to 477. [2018-02-04 13:57:57,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 477 states. [2018-02-04 13:57:57,070 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 477 states to 477 states and 550 transitions. [2018-02-04 13:57:57,070 INFO L78 Accepts]: Start accepts. Automaton has 477 states and 550 transitions. Word has length 27 [2018-02-04 13:57:57,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:57,070 INFO L432 AbstractCegarLoop]: Abstraction has 477 states and 550 transitions. [2018-02-04 13:57:57,070 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 13:57:57,071 INFO L276 IsEmpty]: Start isEmpty. Operand 477 states and 550 transitions. [2018-02-04 13:57:57,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 13:57:57,071 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:57,071 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:57,071 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:57,072 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671872, now seen corresponding path program 1 times [2018-02-04 13:57:57,072 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:57,072 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:57,073 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:57,073 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:57,073 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:57,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:57,080 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:57,103 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 13:57:57,103 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 13:57:57,103 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 13:57:57,103 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 13:57:57,104 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 13:57:57,104 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 13:57:57,104 INFO L87 Difference]: Start difference. First operand 477 states and 550 transitions. Second operand 6 states. [2018-02-04 13:57:57,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:57:57,136 INFO L93 Difference]: Finished difference Result 478 states and 549 transitions. [2018-02-04 13:57:57,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 13:57:57,136 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 28 [2018-02-04 13:57:57,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:57:57,138 INFO L225 Difference]: With dead ends: 478 [2018-02-04 13:57:57,138 INFO L226 Difference]: Without dead ends: 478 [2018-02-04 13:57:57,138 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 13:57:57,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 478 states. [2018-02-04 13:57:57,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 478 to 476. [2018-02-04 13:57:57,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 476 states. [2018-02-04 13:57:57,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 476 states to 476 states and 547 transitions. [2018-02-04 13:57:57,145 INFO L78 Accepts]: Start accepts. Automaton has 476 states and 547 transitions. Word has length 28 [2018-02-04 13:57:57,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:57:57,146 INFO L432 AbstractCegarLoop]: Abstraction has 476 states and 547 transitions. [2018-02-04 13:57:57,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 13:57:57,146 INFO L276 IsEmpty]: Start isEmpty. Operand 476 states and 547 transitions. [2018-02-04 13:57:57,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 13:57:57,146 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:57:57,146 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:57:57,147 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:57:57,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671871, now seen corresponding path program 1 times [2018-02-04 13:57:57,147 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:57:57,147 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:57:57,148 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:57,148 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:57,148 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:57:57,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:57,158 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:57:57,357 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:57,358 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:57:57,358 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:57:57,365 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:57:57,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:57:57,387 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:57:57,410 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 13:57:57,411 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,429 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 13:57:57,430 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 13:57:57,444 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,453 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 13:57:57,453 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,466 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 13:57:57,466 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 13:57:57,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:57:57,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:57:57,594 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-02-04 13:57:57,594 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:57:57,614 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 37 [2018-02-04 13:57:57,615 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:57:57,638 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 35 [2018-02-04 13:57:57,638 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:57:57,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:57:57,664 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 25 [2018-02-04 13:57:57,665 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:57:57,682 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 13:57:57,682 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-02-04 13:57:57,731 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 1 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:57:57,747 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:57:57,748 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-02-04 13:57:57,748 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 13:57:57,748 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 13:57:57,748 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=261, Unknown=1, NotChecked=0, Total=306 [2018-02-04 13:57:57,748 INFO L87 Difference]: Start difference. First operand 476 states and 547 transitions. Second operand 18 states. [2018-02-04 13:58:18,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:58:18,632 INFO L93 Difference]: Finished difference Result 663 states and 771 transitions. [2018-02-04 13:58:18,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 13:58:18,632 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 28 [2018-02-04 13:58:18,632 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:58:18,634 INFO L225 Difference]: With dead ends: 663 [2018-02-04 13:58:18,634 INFO L226 Difference]: Without dead ends: 663 [2018-02-04 13:58:18,634 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 22 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 88 ImplicationChecksByTransitivity, 4.5s TimeCoverageRelationStatistics Valid=96, Invalid=501, Unknown=3, NotChecked=0, Total=600 [2018-02-04 13:58:18,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 663 states. [2018-02-04 13:58:18,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 663 to 485. [2018-02-04 13:58:18,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 485 states. [2018-02-04 13:58:18,654 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 485 states to 485 states and 562 transitions. [2018-02-04 13:58:18,654 INFO L78 Accepts]: Start accepts. Automaton has 485 states and 562 transitions. Word has length 28 [2018-02-04 13:58:18,654 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:58:18,654 INFO L432 AbstractCegarLoop]: Abstraction has 485 states and 562 transitions. [2018-02-04 13:58:18,655 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 13:58:18,655 INFO L276 IsEmpty]: Start isEmpty. Operand 485 states and 562 transitions. [2018-02-04 13:58:18,655 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 13:58:18,655 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:58:18,655 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:58:18,655 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:58:18,656 INFO L82 PathProgramCache]: Analyzing trace with hash -1622671872, now seen corresponding path program 1 times [2018-02-04 13:58:18,656 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:58:18,656 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:58:18,657 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:58:18,658 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:58:18,658 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:58:18,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:58:18,663 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:58:18,723 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 4 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:58:18,723 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:58:18,723 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:58:18,728 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:58:18,742 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:58:18,743 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:58:18,745 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:58:18,745 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:18,746 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:18,746 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:58:18,762 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:18,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:18,764 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:58:18,764 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:18,768 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:58:18,769 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-02-04 13:58:18,781 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:58:18,802 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:58:18,802 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 10 [2018-02-04 13:58:18,802 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 13:58:18,802 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 13:58:18,802 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=86, Unknown=0, NotChecked=0, Total=110 [2018-02-04 13:58:18,803 INFO L87 Difference]: Start difference. First operand 485 states and 562 transitions. Second operand 11 states. [2018-02-04 13:58:19,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:58:19,662 INFO L93 Difference]: Finished difference Result 591 states and 693 transitions. [2018-02-04 13:58:19,662 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 13:58:19,662 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 28 [2018-02-04 13:58:19,662 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:58:19,664 INFO L225 Difference]: With dead ends: 591 [2018-02-04 13:58:19,664 INFO L226 Difference]: Without dead ends: 591 [2018-02-04 13:58:19,664 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 25 SyntacticMatches, 2 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=162, Unknown=0, NotChecked=0, Total=210 [2018-02-04 13:58:19,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 591 states. [2018-02-04 13:58:19,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 591 to 473. [2018-02-04 13:58:19,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-04 13:58:19,673 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 544 transitions. [2018-02-04 13:58:19,673 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 544 transitions. Word has length 28 [2018-02-04 13:58:19,673 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:58:19,674 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 544 transitions. [2018-02-04 13:58:19,674 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 13:58:19,674 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 544 transitions. [2018-02-04 13:58:19,674 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 13:58:19,674 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:58:19,674 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:58:19,674 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:58:19,675 INFO L82 PathProgramCache]: Analyzing trace with hash 1049980534, now seen corresponding path program 1 times [2018-02-04 13:58:19,675 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:58:19,675 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:58:19,676 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:58:19,676 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:58:19,676 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:58:19,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:58:19,684 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:58:19,792 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:58:19,792 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:58:19,792 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:58:19,801 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:58:19,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:58:19,821 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:58:19,823 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:58:19,823 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,824 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,824 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 13:58:19,827 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:58:19,827 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,828 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,828 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:9, output treesize:3 [2018-02-04 13:58:19,846 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:19,847 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:19,847 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:58:19,848 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,851 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,851 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 13:58:19,901 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 12 [2018-02-04 13:58:19,901 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,910 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 8 [2018-02-04 13:58:19,911 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,918 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,918 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:41, output treesize:3 [2018-02-04 13:58:19,927 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:19,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 13:58:19,928 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:19,933 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 13:58:19,933 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:25, output treesize:15 [2018-02-04 13:58:19,949 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 13:58:19,965 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:58:19,966 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 9] total 13 [2018-02-04 13:58:19,966 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 13:58:19,966 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 13:58:19,966 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=150, Unknown=0, NotChecked=0, Total=182 [2018-02-04 13:58:19,966 INFO L87 Difference]: Start difference. First operand 473 states and 544 transitions. Second operand 14 states. [2018-02-04 13:58:21,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 13:58:21,166 INFO L93 Difference]: Finished difference Result 572 states and 640 transitions. [2018-02-04 13:58:21,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 13:58:21,167 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-02-04 13:58:21,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 13:58:21,168 INFO L225 Difference]: With dead ends: 572 [2018-02-04 13:58:21,168 INFO L226 Difference]: Without dead ends: 572 [2018-02-04 13:58:21,168 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 28 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=71, Invalid=349, Unknown=0, NotChecked=0, Total=420 [2018-02-04 13:58:21,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 572 states. [2018-02-04 13:58:21,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 572 to 473. [2018-02-04 13:58:21,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 473 states. [2018-02-04 13:58:21,175 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 473 states to 473 states and 543 transitions. [2018-02-04 13:58:21,175 INFO L78 Accepts]: Start accepts. Automaton has 473 states and 543 transitions. Word has length 29 [2018-02-04 13:58:21,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 13:58:21,175 INFO L432 AbstractCegarLoop]: Abstraction has 473 states and 543 transitions. [2018-02-04 13:58:21,175 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 13:58:21,175 INFO L276 IsEmpty]: Start isEmpty. Operand 473 states and 543 transitions. [2018-02-04 13:58:21,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 13:58:21,176 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 13:58:21,176 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 13:58:21,176 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_list_addErr0RequiresViolation, ldv_list_addErr1RequiresViolation, ldv_destroy_msgsErr5RequiresViolation, ldv_destroy_msgsErr3RequiresViolation, ldv_destroy_msgsErr4RequiresViolation, ldv_destroy_msgsErr0RequiresViolation, ldv_destroy_msgsErr2RequiresViolation, ldv_destroy_msgsErr1RequiresViolation, ldv_msg_fillErr3RequiresViolation, ldv_msg_fillErr1RequiresViolation, ldv_msg_fillErr5RequiresViolation, ldv_msg_fillErr0RequiresViolation, ldv_msg_fillErr4RequiresViolation, ldv_msg_fillErr2RequiresViolation, __ldv_list_delErr2RequiresViolation, __ldv_list_delErr0RequiresViolation, __ldv_list_delErr1RequiresViolation, __ldv_list_delErr3RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, ldv_msg_freeErr5RequiresViolation, ldv_msg_freeErr3RequiresViolation, ldv_msg_freeErr1RequiresViolation, ldv_msg_freeErr0RequiresViolation, ldv_msg_freeErr4RequiresViolation, ldv_msg_freeErr2RequiresViolation, mainErr0EnsuresViolation, ldv_list_delErr3RequiresViolation, ldv_list_delErr1RequiresViolation, ldv_list_delErr0RequiresViolation, ldv_list_delErr2RequiresViolation, ldv_m88ts2022_rd_regErr30RequiresViolation, ldv_m88ts2022_rd_regErr25RequiresViolation, ldv_m88ts2022_rd_regErr20RequiresViolation, ldv_m88ts2022_rd_regErr15RequiresViolation, ldv_m88ts2022_rd_regErr2RequiresViolation, ldv_m88ts2022_rd_regErr10RequiresViolation, ldv_m88ts2022_rd_regErr17RequiresViolation, ldv_m88ts2022_rd_regErr22RequiresViolation, ldv_m88ts2022_rd_regErr12RequiresViolation, ldv_m88ts2022_rd_regErr8RequiresViolation, ldv_m88ts2022_rd_regErr31RequiresViolation, ldv_m88ts2022_rd_regErr28RequiresViolation, ldv_m88ts2022_rd_regErr18RequiresViolation, ldv_m88ts2022_rd_regErr21RequiresViolation, ldv_m88ts2022_rd_regErr5RequiresViolation, ldv_m88ts2022_rd_regErr1RequiresViolation, ldv_m88ts2022_rd_regErr11RequiresViolation, ldv_m88ts2022_rd_regErr29RequiresViolation, ldv_m88ts2022_rd_regErr16RequiresViolation, ldv_m88ts2022_rd_regErr24RequiresViolation, ldv_m88ts2022_rd_regErr4RequiresViolation, ldv_m88ts2022_rd_regErr14RequiresViolation, ldv_m88ts2022_rd_regErr6RequiresViolation, ldv_m88ts2022_rd_regErr9RequiresViolation, ldv_m88ts2022_rd_regErr19RequiresViolation, ldv_m88ts2022_rd_regErr27RequiresViolation, ldv_m88ts2022_rd_regErr13RequiresViolation, ldv_m88ts2022_rd_regErr3RequiresViolation, ldv_m88ts2022_rd_regErr23RequiresViolation, ldv_m88ts2022_rd_regErr32RequiresViolation, ldv_m88ts2022_rd_regErr7RequiresViolation, ldv_m88ts2022_rd_regErr33RequiresViolation, ldv_m88ts2022_rd_regErr0RequiresViolation, ldv_m88ts2022_rd_regErr26RequiresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation, __ldv_list_addErr6RequiresViolation, __ldv_list_addErr1RequiresViolation, __ldv_list_addErr7RequiresViolation, __ldv_list_addErr0RequiresViolation, __ldv_list_addErr2RequiresViolation, __ldv_list_addErr4RequiresViolation, __ldv_list_addErr5RequiresViolation, __ldv_list_addErr3RequiresViolation, alloc_fix_12Err4RequiresViolation, alloc_fix_12Err0RequiresViolation, alloc_fix_12Err5RequiresViolation, alloc_fix_12Err12RequiresViolation, alloc_fix_12Err3RequiresViolation, alloc_fix_12Err1RequiresViolation, alloc_fix_12Err13RequiresViolation, alloc_fix_12Err8RequiresViolation, alloc_fix_12Err15RequiresViolation, alloc_fix_12Err10RequiresViolation, alloc_fix_12Err6RequiresViolation, alloc_fix_12Err14RequiresViolation, alloc_fix_12Err11RequiresViolation, alloc_fix_12Err7RequiresViolation, alloc_fix_12Err9RequiresViolation, alloc_fix_12Err2RequiresViolation, master_xferErr0RequiresViolation, master_xferErr3RequiresViolation, master_xferErr1RequiresViolation, master_xferErr2RequiresViolation, ULTIMATE.initErr3RequiresViolation, ULTIMATE.initErr1RequiresViolation, ULTIMATE.initErr2RequiresViolation, ULTIMATE.initErr0RequiresViolation, ldv_i2c_transferErr0RequiresViolation, ldv_i2c_transferErr1RequiresViolation, ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, free_12Err1RequiresViolation, free_12Err6RequiresViolation, free_12Err3RequiresViolation, free_12Err2RequiresViolation, free_12Err0RequiresViolation, free_12Err7RequiresViolation, free_12Err4RequiresViolation, free_12Err5RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr18RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr19RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_msg_allocErr0RequiresViolation, ldv_msg_allocErr1RequiresViolation]=== [2018-02-04 13:58:21,176 INFO L82 PathProgramCache]: Analyzing trace with hash 1049980535, now seen corresponding path program 1 times [2018-02-04 13:58:21,176 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-02-04 13:58:21,176 INFO L67 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-02-04 13:58:21,177 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:58:21,177 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:58:21,177 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 13:58:21,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:58:21,184 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 13:58:21,252 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:58:21,252 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 13:58:21,252 INFO L213 onRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-02-04 13:58:21,260 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 13:58:21,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 13:58:21,297 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 13:58:21,300 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:58:21,300 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,305 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 13:58:21,305 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,308 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,308 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:16, output treesize:14 [2018-02-04 13:58:21,318 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:58:21,318 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,322 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 13:58:21,323 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,325 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,326 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:20, output treesize:10 [2018-02-04 13:58:21,364 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,365 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,366 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 47 [2018-02-04 13:58:21,366 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,396 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 27 [2018-02-04 13:58:21,396 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,418 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,420 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 35 [2018-02-04 13:58:21,420 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,445 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,445 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,446 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 25 [2018-02-04 13:58:21,446 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,465 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 13:58:21,465 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-02-04 13:58:21,514 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 16 [2018-02-04 13:58:21,514 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,528 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,529 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 13:58:21,529 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 24 [2018-02-04 13:58:21,530 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,541 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 13:58:21,541 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:55, output treesize:7 [2018-02-04 13:58:21,564 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 13:58:21,590 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 13:58:21,590 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 11 [2018-02-04 13:58:21,590 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 13:58:21,590 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 13:58:21,590 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=98, Unknown=0, NotChecked=0, Total=132 [2018-02-04 13:58:21,590 INFO L87 Difference]: Start difference. First operand 473 states and 543 transitions. Second operand 12 states. [2018-02-04 13:58:51,518 WARN L146 SmtUtils]: Spent 22226ms on a formula simplification. DAG size of input: 59 DAG size of output 56 [2018-02-04 13:59:11,733 WARN L146 SmtUtils]: Spent 20195ms on a formula simplification. DAG size of input: 57 DAG size of output 54 [2018-02-04 13:59:32,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 13:59:32,470 FATAL L265 ToolchainWalker]: An unrecoverable error occured during an interaction with an SMT solver: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. No stderr output. at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:209) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parseSuccess(Executor.java:222) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Scriptor.pop(Scriptor.java:139) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.arrays.DiffWrapperScript.pop(DiffWrapperScript.java:188) at de.uni_freiburg.informatik.ultimate.logic.Util.checkSat(Util.java:67) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.getRedundancy(SimplifyDDA.java:626) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getRedundancy(SimplifyDDAWithTimeout.java:135) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA$Simplifier.walk(SimplifyDDA.java:371) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:122) at de.uni_freiburg.informatik.ultimate.logic.NonRecursive.run(NonRecursive.java:113) at de.uni_freiburg.informatik.ultimate.logic.simplification.SimplifyDDA.simplifyOnce(SimplifyDDA.java:650) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SimplifyDDAWithTimeout.getSimplifiedTerm(SimplifyDDAWithTimeout.java:204) at de.uni_freiburg.informatik.ultimate.modelcheckerutils.smt.SmtUtils.simplify(SmtUtils.java:126) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.PredicateUnifier.getOrConstructPredicate(PredicateUnifier.java:370) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.PredicateUnifier.getOrConstructPredicateForConjunction(PredicateUnifier.java:398) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.singletracecheck.PredicateUnifier.getOrConstructPredicateForConjunction(PredicateUnifier.java:239) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.getOrConstructPredicate(DeterministicInterpolantAutomaton.java:261) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.DeterministicInterpolantAutomaton.constructSuccessorsAndTransitions(DeterministicInterpolantAutomaton.java:283) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:78) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.BasicAbstractInterpolantAutomaton.computeSuccs(BasicAbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:234) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.interpolantautomata.transitionappender.AbstractInterpolantAutomaton.internalSuccessors(AbstractInterpolantAutomaton.java:1) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.TotalizeNwa.internalSuccessors(TotalizeNwa.java:213) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ComplementDeterministicNwa.internalSuccessors(ComplementDeterministicNwa.java:121) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:216) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.ProductNwa.internalSuccessors(ProductNwa.java:208) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.addInternalsAndSuccessors(NestedWordAutomatonReachableStates.java:1054) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates$ReachableStatesComputation.(NestedWordAutomatonReachableStates.java:956) at de.uni_freiburg.informatik.ultimate.automata.nestedword.reachablestates.NestedWordAutomatonReachableStates.(NestedWordAutomatonReachableStates.java:185) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.computeDifference(Difference.java:137) at de.uni_freiburg.informatik.ultimate.automata.nestedword.operations.Difference.(Difference.java:90) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.computeAutomataDifference(BasicCegarLoop.java:581) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.BasicCegarLoop.refineAbstraction(BasicCegarLoop.java:551) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterateInternal(AbstractCegarLoop.java:420) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.AbstractCegarLoop.iterate(AbstractCegarLoop.java:316) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.iterate(TraceAbstractionStarter.java:292) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.runCegarLoops(TraceAbstractionStarter.java:147) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionStarter.(TraceAbstractionStarter.java:115) at de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver.finish(TraceAbstractionObserver.java:119) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runObserver(PluginConnector.java:168) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.runTool(PluginConnector.java:151) at de.uni_freiburg.informatik.ultimate.core.coreplugin.PluginConnector.run(PluginConnector.java:128) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.executePluginConnector(ToolchainWalker.java:232) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.processPlugin(ToolchainWalker.java:226) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walkUnprotected(ToolchainWalker.java:142) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainWalker.walk(ToolchainWalker.java:104) at de.uni_freiburg.informatik.ultimate.core.coreplugin.ToolchainManager$Toolchain.processToolchain(ToolchainManager.java:324) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.DefaultToolchainJob.runToolchainDefault(DefaultToolchainJob.java:221) at de.uni_freiburg.informatik.ultimate.core.coreplugin.toolchain.BasicToolchainJob.run(BasicToolchainJob.java:134) at org.eclipse.core.internal.jobs.Worker.run(Worker.java:55) Caused by: de.uni_freiburg.informatik.ultimate.logic.SMTLIBException: EOF at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser$Action$.CUP$do_action(Parser.java:1427) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Parser.do_action(Parser.java:630) at com.github.jhoenicke.javacup.runtime.LRParser.parse(LRParser.java:419) at de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:206) ... 49 more [2018-02-04 13:59:32,473 INFO L168 Benchmark]: Toolchain (without parser) took 101135.70 ms. Allocated memory was 407.9 MB in the beginning and 807.9 MB in the end (delta: 400.0 MB). Free memory was 361.9 MB in the beginning and 653.8 MB in the end (delta: -291.9 MB). Peak memory consumption was 108.1 MB. Max. memory is 5.3 GB. [2018-02-04 13:59:32,474 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 407.9 MB. Free memory is still 368.5 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 13:59:32,474 INFO L168 Benchmark]: CACSL2BoogieTranslator took 237.04 ms. Allocated memory is still 407.9 MB. Free memory was 361.9 MB in the beginning and 344.5 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. [2018-02-04 13:59:32,474 INFO L168 Benchmark]: Boogie Preprocessor took 34.88 ms. Allocated memory is still 407.9 MB. Free memory was 344.5 MB in the beginning and 341.9 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-04 13:59:32,474 INFO L168 Benchmark]: RCFGBuilder took 725.24 ms. Allocated memory was 407.9 MB in the beginning and 426.2 MB in the end (delta: 18.4 MB). Free memory was 341.9 MB in the beginning and 381.7 MB in the end (delta: -39.8 MB). Peak memory consumption was 97.9 MB. Max. memory is 5.3 GB. [2018-02-04 13:59:32,475 INFO L168 Benchmark]: TraceAbstraction took 100135.84 ms. Allocated memory was 426.2 MB in the beginning and 807.9 MB in the end (delta: 381.7 MB). Free memory was 381.7 MB in the beginning and 653.8 MB in the end (delta: -272.1 MB). Peak memory consumption was 109.6 MB. Max. memory is 5.3 GB. [2018-02-04 13:59:32,476 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 407.9 MB. Free memory is still 368.5 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 237.04 ms. Allocated memory is still 407.9 MB. Free memory was 361.9 MB in the beginning and 344.5 MB in the end (delta: 17.4 MB). Peak memory consumption was 17.4 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 34.88 ms. Allocated memory is still 407.9 MB. Free memory was 344.5 MB in the beginning and 341.9 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 725.24 ms. Allocated memory was 407.9 MB in the beginning and 426.2 MB in the end (delta: 18.4 MB). Free memory was 341.9 MB in the beginning and 381.7 MB in the end (delta: -39.8 MB). Peak memory consumption was 97.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 100135.84 ms. Allocated memory was 426.2 MB in the beginning and 807.9 MB in the end (delta: 381.7 MB). Free memory was 381.7 MB in the beginning and 653.8 MB in the end (delta: -272.1 MB). Peak memory consumption was 109.6 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - ExceptionOrErrorResult: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. No stderr output. de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: SMTLIBException: External (z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000)Received EOF on stdin. No stderr output.: de.uni_freiburg.informatik.ultimate.smtsolver.external.Executor.parse(Executor.java:209) RESULT: Ultimate could not prove your program: Toolchain returned no result. Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test12_true-valid-memsafety.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_13-59-32-482.csv Received shutdown request...