java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 16:22:19,199 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 16:22:19,200 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 16:22:19,213 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 16:22:19,213 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 16:22:19,214 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 16:22:19,215 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 16:22:19,216 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 16:22:19,218 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 16:22:19,219 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 16:22:19,219 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 16:22:19,220 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 16:22:19,220 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 16:22:19,221 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 16:22:19,222 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 16:22:19,224 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 16:22:19,225 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 16:22:19,227 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 16:22:19,227 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 16:22:19,228 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 16:22:19,230 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 16:22:19,230 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 16:22:19,230 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 16:22:19,231 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 16:22:19,232 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 16:22:19,232 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 16:22:19,233 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 16:22:19,234 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 16:22:19,234 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 16:22:19,234 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 16:22:19,235 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 16:22:19,235 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-04 16:22:19,243 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 16:22:19,243 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 16:22:19,244 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 16:22:19,244 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 16:22:19,244 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 16:22:19,244 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 16:22:19,244 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 16:22:19,244 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 16:22:19,245 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 16:22:19,245 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 16:22:19,246 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 16:22:19,246 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 16:22:19,246 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 16:22:19,246 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-04 16:22:19,279 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 16:22:19,288 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 16:22:19,292 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 16:22:19,293 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 16:22:19,293 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 16:22:19,294 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i [2018-02-04 16:22:19,469 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 16:22:19,471 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 16:22:19,471 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 16:22:19,471 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 16:22:19,477 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 16:22:19,478 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,480 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f13972f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19, skipping insertion in model container [2018-02-04 16:22:19,480 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,495 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 16:22:19,534 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 16:22:19,626 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 16:22:19,643 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 16:22:19,651 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19 WrapperNode [2018-02-04 16:22:19,651 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 16:22:19,651 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 16:22:19,651 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 16:22:19,651 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 16:22:19,662 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,663 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,675 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,676 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,683 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,686 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,687 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... [2018-02-04 16:22:19,690 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 16:22:19,691 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 16:22:19,691 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 16:22:19,691 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 16:22:19,692 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 16:22:19,730 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 16:22:19,730 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 16:22:19,730 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-02-04 16:22:19,730 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-02-04 16:22:19,730 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_get_drvdata [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_set_drvdata [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_arvo_device_struct [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_specials_unsafe [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure lvd_arvo_remove_specials [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_probe_unsafe [2018-02-04 16:22:19,731 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_remove [2018-02-04 16:22:19,732 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 16:22:19,732 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 16:22:19,732 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-02-04 16:22:19,733 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-04 16:22:19,733 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_get_drvdata [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_set_drvdata [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_arvo_device_struct [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_specials_unsafe [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure lvd_arvo_remove_specials [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_probe_unsafe [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_remove [2018-02-04 16:22:19,734 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 16:22:19,735 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 16:22:19,735 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 16:22:19,735 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 16:22:20,098 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 16:22:20,099 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 04:22:20 BoogieIcfgContainer [2018-02-04 16:22:20,099 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 16:22:20,100 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 16:22:20,100 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 16:22:20,102 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 16:22:20,103 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 04:22:19" (1/3) ... [2018-02-04 16:22:20,103 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@64fa4bb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 04:22:20, skipping insertion in model container [2018-02-04 16:22:20,103 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 04:22:19" (2/3) ... [2018-02-04 16:22:20,103 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@64fa4bb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 04:22:20, skipping insertion in model container [2018-02-04 16:22:20,103 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 04:22:20" (3/3) ... [2018-02-04 16:22:20,104 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test15_false-valid-memtrack.i [2018-02-04 16:22:20,110 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-04 16:22:20,116 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 45 error locations. [2018-02-04 16:22:20,144 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 16:22:20,144 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 16:22:20,144 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-04 16:22:20,144 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-04 16:22:20,144 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 16:22:20,144 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 16:22:20,144 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 16:22:20,144 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 16:22:20,145 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 16:22:20,155 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states. [2018-02-04 16:22:20,161 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-02-04 16:22:20,161 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:20,162 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:20,162 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:20,164 INFO L82 PathProgramCache]: Analyzing trace with hash 462743197, now seen corresponding path program 1 times [2018-02-04 16:22:20,203 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:20,244 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:20,253 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:20,363 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 16:22:20,366 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 16:22:20,366 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 16:22:20,367 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:20,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 16:22:20,368 INFO L182 omatonBuilderFactory]: Interpolants [168#true, 169#false, 170#(not (= 0 |ldv_zalloc_#t~malloc1.base|)), 171#(not (= 0 |ldv_zalloc_#res.base|)), 172#(not (= 0 |entry_point_#t~ret22.base|)), 173#(not (= 0 entry_point_~hdev~0.base))] [2018-02-04 16:22:20,369 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 16:22:20,431 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 16:22:20,442 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 16:22:20,443 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 16:22:20,444 INFO L87 Difference]: Start difference. First operand 165 states. Second operand 6 states. [2018-02-04 16:22:20,506 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:20,506 INFO L93 Difference]: Finished difference Result 165 states and 177 transitions. [2018-02-04 16:22:20,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 16:22:20,507 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-02-04 16:22:20,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:20,513 INFO L225 Difference]: With dead ends: 165 [2018-02-04 16:22:20,513 INFO L226 Difference]: Without dead ends: 162 [2018-02-04 16:22:20,514 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 16:22:20,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-04 16:22:20,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-04 16:22:20,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-04 16:22:20,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 174 transitions. [2018-02-04 16:22:20,543 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 174 transitions. Word has length 22 [2018-02-04 16:22:20,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:20,544 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 174 transitions. [2018-02-04 16:22:20,544 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 16:22:20,544 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 174 transitions. [2018-02-04 16:22:20,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-04 16:22:20,545 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:20,545 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:20,545 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:20,545 INFO L82 PathProgramCache]: Analyzing trace with hash -844495449, now seen corresponding path program 1 times [2018-02-04 16:22:20,546 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:20,568 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:20,569 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:20,631 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 16:22:20,632 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 16:22:20,632 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 16:22:20,632 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:20,633 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 16:22:20,633 INFO L182 omatonBuilderFactory]: Interpolants [503#true, 504#false, 505#(not (= 0 |ldv_zalloc_#t~malloc1.base|)), 506#(not (= 0 |ldv_zalloc_#res.base|)), 507#(not (= 0 |entry_point_#t~ret23.base|)), 508#(not (= 0 entry_point_~intf~2.base))] [2018-02-04 16:22:20,633 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 16:22:20,634 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 16:22:20,634 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 16:22:20,635 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 16:22:20,635 INFO L87 Difference]: Start difference. First operand 162 states and 174 transitions. Second operand 6 states. [2018-02-04 16:22:20,700 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:20,700 INFO L93 Difference]: Finished difference Result 162 states and 173 transitions. [2018-02-04 16:22:20,701 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 16:22:20,701 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-02-04 16:22:20,701 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:20,702 INFO L225 Difference]: With dead ends: 162 [2018-02-04 16:22:20,702 INFO L226 Difference]: Without dead ends: 162 [2018-02-04 16:22:20,703 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 16:22:20,703 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-04 16:22:20,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-04 16:22:20,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-04 16:22:20,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 173 transitions. [2018-02-04 16:22:20,713 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 173 transitions. Word has length 33 [2018-02-04 16:22:20,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:20,713 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 173 transitions. [2018-02-04 16:22:20,713 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 16:22:20,713 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 173 transitions. [2018-02-04 16:22:20,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-04 16:22:20,714 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:20,714 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:20,714 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:20,714 INFO L82 PathProgramCache]: Analyzing trace with hash 902320110, now seen corresponding path program 1 times [2018-02-04 16:22:20,716 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:20,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:20,739 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:20,869 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:20,870 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:20,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-04 16:22:20,870 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:20,870 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:20,871 INFO L182 omatonBuilderFactory]: Interpolants [835#true, 836#false, 837#(= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|)), 838#(= 1 (select |#valid| |ldv_zalloc_#res.base|)), 839#(= 1 (select |#valid| |entry_point_#t~ret23.base|)), 840#(= 1 (select |#valid| entry_point_~intf~2.base)), 841#(= |#valid| |old(#valid)|), 842#(and (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|))), 843#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 16:22:20,871 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 14 proven. 2 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:20,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 16:22:20,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 16:22:20,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=54, Unknown=0, NotChecked=0, Total=72 [2018-02-04 16:22:20,872 INFO L87 Difference]: Start difference. First operand 162 states and 173 transitions. Second operand 9 states. [2018-02-04 16:22:21,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:21,353 INFO L93 Difference]: Finished difference Result 184 states and 200 transitions. [2018-02-04 16:22:21,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 16:22:21,353 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 44 [2018-02-04 16:22:21,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:21,355 INFO L225 Difference]: With dead ends: 184 [2018-02-04 16:22:21,356 INFO L226 Difference]: Without dead ends: 184 [2018-02-04 16:22:21,356 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-02-04 16:22:21,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-02-04 16:22:21,361 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 175. [2018-02-04 16:22:21,361 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-04 16:22:21,362 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 192 transitions. [2018-02-04 16:22:21,362 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 192 transitions. Word has length 44 [2018-02-04 16:22:21,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:21,363 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 192 transitions. [2018-02-04 16:22:21,363 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 16:22:21,363 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 192 transitions. [2018-02-04 16:22:21,364 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-04 16:22:21,364 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:21,364 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:21,364 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:21,364 INFO L82 PathProgramCache]: Analyzing trace with hash 902320111, now seen corresponding path program 1 times [2018-02-04 16:22:21,365 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:21,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:21,385 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:21,539 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:21,539 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:21,539 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-04 16:22:21,539 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:21,540 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:21,540 INFO L182 omatonBuilderFactory]: Interpolants [1205#true, 1206#false, 1207#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 1208#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))) (< 0 (div ldv_zalloc_~size 4294967296)))), 1209#(= |#Ultimate.meminit_#t~loopctr33| 0), 1210#(<= |#Ultimate.meminit_#product| 0), 1211#(or (<= 2147483648 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 0))] [2018-02-04 16:22:21,540 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 16 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:21,540 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 16:22:21,541 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 16:22:21,541 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-04 16:22:21,541 INFO L87 Difference]: Start difference. First operand 175 states and 192 transitions. Second operand 7 states. [2018-02-04 16:22:21,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:21,614 INFO L93 Difference]: Finished difference Result 181 states and 198 transitions. [2018-02-04 16:22:21,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 16:22:21,615 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 44 [2018-02-04 16:22:21,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:21,615 INFO L225 Difference]: With dead ends: 181 [2018-02-04 16:22:21,616 INFO L226 Difference]: Without dead ends: 176 [2018-02-04 16:22:21,616 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-04 16:22:21,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-02-04 16:22:21,622 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 176. [2018-02-04 16:22:21,623 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 176 states. [2018-02-04 16:22:21,624 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 176 states to 176 states and 193 transitions. [2018-02-04 16:22:21,624 INFO L78 Accepts]: Start accepts. Automaton has 176 states and 193 transitions. Word has length 44 [2018-02-04 16:22:21,624 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:21,624 INFO L432 AbstractCegarLoop]: Abstraction has 176 states and 193 transitions. [2018-02-04 16:22:21,624 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 16:22:21,624 INFO L276 IsEmpty]: Start isEmpty. Operand 176 states and 193 transitions. [2018-02-04 16:22:21,625 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 16:22:21,625 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:21,625 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:21,625 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:21,626 INFO L82 PathProgramCache]: Analyzing trace with hash -506792821, now seen corresponding path program 1 times [2018-02-04 16:22:21,627 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:21,646 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:21,647 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:21,746 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-04 16:22:21,746 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:21,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-04 16:22:21,746 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:21,747 INFO L134 CoverageAnalysis]: Checked inductivity of 33 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 16:22:21,747 INFO L182 omatonBuilderFactory]: Interpolants [1573#true, 1574#false, 1575#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 1576#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 1577#(= |#Ultimate.meminit_#t~loopctr33| 0), 1578#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 1 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|))), 1579#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 1 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| |#Ultimate.meminit_#sizeOfFields|))), 1580#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 1))] [2018-02-04 16:22:21,747 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 23 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-04 16:22:21,747 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 16:22:21,747 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 16:22:21,747 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-02-04 16:22:21,748 INFO L87 Difference]: Start difference. First operand 176 states and 193 transitions. Second operand 8 states. [2018-02-04 16:22:21,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:21,824 INFO L93 Difference]: Finished difference Result 182 states and 199 transitions. [2018-02-04 16:22:21,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 16:22:21,824 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 47 [2018-02-04 16:22:21,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:21,825 INFO L225 Difference]: With dead ends: 182 [2018-02-04 16:22:21,825 INFO L226 Difference]: Without dead ends: 177 [2018-02-04 16:22:21,825 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 16:22:21,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-02-04 16:22:21,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-02-04 16:22:21,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-02-04 16:22:21,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 194 transitions. [2018-02-04 16:22:21,830 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 194 transitions. Word has length 47 [2018-02-04 16:22:21,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:21,831 INFO L432 AbstractCegarLoop]: Abstraction has 177 states and 194 transitions. [2018-02-04 16:22:21,831 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 16:22:21,831 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 194 transitions. [2018-02-04 16:22:21,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-04 16:22:21,831 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:21,832 INFO L351 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:21,832 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:21,832 INFO L82 PathProgramCache]: Analyzing trace with hash -1284083601, now seen corresponding path program 2 times [2018-02-04 16:22:21,832 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:21,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:21,856 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:21,995 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 16:22:21,995 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:21,995 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-04 16:22:21,995 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:21,996 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-02-04 16:22:21,996 INFO L182 omatonBuilderFactory]: Interpolants [1952#(or (<= |ldv_zalloc_#in~size| 2) (<= 4294967296 |ldv_zalloc_#in~size|)), 1944#true, 1945#false, 1946#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 1947#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 1948#(= |#Ultimate.meminit_#t~loopctr33| 0), 1949#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 1950#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ |#Ultimate.meminit_#t~loopctr33| 2) (* 2 |#Ultimate.meminit_#product|)))), 1951#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#product| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= 2 |#Ultimate.meminit_#product|)))] [2018-02-04 16:22:21,996 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 35 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 16:22:21,996 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 16:22:21,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 16:22:21,996 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-02-04 16:22:21,997 INFO L87 Difference]: Start difference. First operand 177 states and 194 transitions. Second operand 9 states. [2018-02-04 16:22:22,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:22,126 INFO L93 Difference]: Finished difference Result 183 states and 200 transitions. [2018-02-04 16:22:22,126 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 16:22:22,126 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 50 [2018-02-04 16:22:22,127 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:22,128 INFO L225 Difference]: With dead ends: 183 [2018-02-04 16:22:22,128 INFO L226 Difference]: Without dead ends: 178 [2018-02-04 16:22:22,128 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-02-04 16:22:22,129 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-02-04 16:22:22,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 178. [2018-02-04 16:22:22,135 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-02-04 16:22:22,136 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 195 transitions. [2018-02-04 16:22:22,137 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 195 transitions. Word has length 50 [2018-02-04 16:22:22,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:22,137 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 195 transitions. [2018-02-04 16:22:22,137 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 16:22:22,137 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 195 transitions. [2018-02-04 16:22:22,138 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-04 16:22:22,138 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:22,138 INFO L351 BasicCegarLoop]: trace histogram [9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:22,138 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:22,139 INFO L82 PathProgramCache]: Analyzing trace with hash -202175989, now seen corresponding path program 3 times [2018-02-04 16:22:22,139 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:22,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:22,159 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:22,326 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-04 16:22:22,326 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:22,326 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10] total 10 [2018-02-04 16:22:22,327 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:22,327 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 17 trivial. 0 not checked. [2018-02-04 16:22:22,327 INFO L182 omatonBuilderFactory]: Interpolants [2320#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 2321#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 2322#(= |#Ultimate.meminit_#t~loopctr33| 0), 2323#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 2324#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 2325#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (+ (* 2 |#Ultimate.meminit_#t~loopctr33|) 3) (* 3 |#Ultimate.meminit_#product|))), 2326#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= 3 |#Ultimate.meminit_#product|)), 2327#(or (<= |ldv_zalloc_#in~size| 3) (<= 4294967296 |ldv_zalloc_#in~size|)), 2318#true, 2319#false] [2018-02-04 16:22:22,327 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-04 16:22:22,328 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 16:22:22,328 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 16:22:22,328 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=18, Invalid=72, Unknown=0, NotChecked=0, Total=90 [2018-02-04 16:22:22,328 INFO L87 Difference]: Start difference. First operand 178 states and 195 transitions. Second operand 10 states. [2018-02-04 16:22:22,470 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:22,470 INFO L93 Difference]: Finished difference Result 184 states and 201 transitions. [2018-02-04 16:22:22,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 16:22:22,470 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 53 [2018-02-04 16:22:22,471 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:22,472 INFO L225 Difference]: With dead ends: 184 [2018-02-04 16:22:22,472 INFO L226 Difference]: Without dead ends: 179 [2018-02-04 16:22:22,474 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=27, Invalid=105, Unknown=0, NotChecked=0, Total=132 [2018-02-04 16:22:22,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-02-04 16:22:22,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2018-02-04 16:22:22,479 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-02-04 16:22:22,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 196 transitions. [2018-02-04 16:22:22,480 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 196 transitions. Word has length 53 [2018-02-04 16:22:22,480 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:22,480 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 196 transitions. [2018-02-04 16:22:22,480 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 16:22:22,480 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 196 transitions. [2018-02-04 16:22:22,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 16:22:22,481 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:22,481 INFO L351 BasicCegarLoop]: trace histogram [12, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:22,482 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:22,482 INFO L82 PathProgramCache]: Analyzing trace with hash -734121745, now seen corresponding path program 4 times [2018-02-04 16:22:22,483 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:22,507 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:22,508 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:22,669 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-04 16:22:22,669 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:22,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-04 16:22:22,670 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:22,670 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 24 proven. 0 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-02-04 16:22:22,670 INFO L182 omatonBuilderFactory]: Interpolants [2704#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 4 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 2705#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 4)), 2695#true, 2696#false, 2697#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 2698#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 2699#(= |#Ultimate.meminit_#t~loopctr33| 0), 2700#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 2701#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 2702#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 2703#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 3 |#Ultimate.meminit_#t~loopctr33|) 4) (* 4 |#Ultimate.meminit_#product|))))] [2018-02-04 16:22:22,670 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-04 16:22:22,670 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 16:22:22,670 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 16:22:22,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=90, Unknown=0, NotChecked=0, Total=110 [2018-02-04 16:22:22,671 INFO L87 Difference]: Start difference. First operand 179 states and 196 transitions. Second operand 11 states. [2018-02-04 16:22:22,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:22,834 INFO L93 Difference]: Finished difference Result 185 states and 202 transitions. [2018-02-04 16:22:22,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 16:22:22,835 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 56 [2018-02-04 16:22:22,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:22,836 INFO L225 Difference]: With dead ends: 185 [2018-02-04 16:22:22,836 INFO L226 Difference]: Without dead ends: 180 [2018-02-04 16:22:22,836 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 16:22:22,836 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-02-04 16:22:22,838 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-02-04 16:22:22,838 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-02-04 16:22:22,839 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 197 transitions. [2018-02-04 16:22:22,839 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 197 transitions. Word has length 56 [2018-02-04 16:22:22,839 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:22,839 INFO L432 AbstractCegarLoop]: Abstraction has 180 states and 197 transitions. [2018-02-04 16:22:22,839 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 16:22:22,839 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 197 transitions. [2018-02-04 16:22:22,840 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 16:22:22,840 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:22,840 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:22,840 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:22,841 INFO L82 PathProgramCache]: Analyzing trace with hash 1514307467, now seen corresponding path program 5 times [2018-02-04 16:22:22,842 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:22,865 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:22,866 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:23,209 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 50 proven. 58 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-02-04 16:22:23,209 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:23,209 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-04 16:22:23,210 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:23,210 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 20 proven. 13 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-02-04 16:22:23,210 INFO L182 omatonBuilderFactory]: Interpolants [3075#true, 3076#false, 3077#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 3078#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296) ldv_zalloc_~size) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3079#(= |#Ultimate.meminit_#t~loopctr33| 0), 3080#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 3081#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 3082#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 3083#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 3084#(<= (+ (* 4 |#Ultimate.meminit_#t~loopctr33|) 5) (* 5 |#Ultimate.meminit_#product|)), 3085#(<= 5 |#Ultimate.meminit_#product|), 3086#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|)))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3087#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|)))) (= 0 |ldv_zalloc_#res.offset|)), 3088#(and (= 0 |entry_point_#t~ret23.offset|) (<= 20 (select |#length| |entry_point_#t~ret23.base|)) (= (select |#valid| |entry_point_#t~ret23.base|) 1)), 3089#(and (= (select |#valid| entry_point_~intf~2.base) 1) (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base))), 3090#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 3091#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 3092#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 3093#(and (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base)))] [2018-02-04 16:22:23,210 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 50 proven. 58 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-02-04 16:22:23,211 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 16:22:23,211 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 16:22:23,211 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=304, Unknown=0, NotChecked=0, Total=342 [2018-02-04 16:22:23,211 INFO L87 Difference]: Start difference. First operand 180 states and 197 transitions. Second operand 19 states. [2018-02-04 16:22:24,460 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:24,460 INFO L93 Difference]: Finished difference Result 235 states and 272 transitions. [2018-02-04 16:22:24,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 16:22:24,462 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-02-04 16:22:24,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:24,463 INFO L225 Difference]: With dead ends: 235 [2018-02-04 16:22:24,464 INFO L226 Difference]: Without dead ends: 235 [2018-02-04 16:22:24,464 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 52 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=104, Invalid=766, Unknown=0, NotChecked=0, Total=870 [2018-02-04 16:22:24,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-02-04 16:22:24,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 211. [2018-02-04 16:22:24,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 211 states. [2018-02-04 16:22:24,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 211 states to 211 states and 251 transitions. [2018-02-04 16:22:24,471 INFO L78 Accepts]: Start accepts. Automaton has 211 states and 251 transitions. Word has length 59 [2018-02-04 16:22:24,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:24,472 INFO L432 AbstractCegarLoop]: Abstraction has 211 states and 251 transitions. [2018-02-04 16:22:24,472 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 16:22:24,472 INFO L276 IsEmpty]: Start isEmpty. Operand 211 states and 251 transitions. [2018-02-04 16:22:24,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-04 16:22:24,473 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:24,473 INFO L351 BasicCegarLoop]: trace histogram [17, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:24,473 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:24,473 INFO L82 PathProgramCache]: Analyzing trace with hash -986148649, now seen corresponding path program 6 times [2018-02-04 16:22:24,474 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:24,491 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:24,492 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:24,770 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-02-04 16:22:24,770 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:24,770 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11] total 11 [2018-02-04 16:22:24,771 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:24,771 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 6 proven. 5 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-02-04 16:22:24,771 INFO L182 omatonBuilderFactory]: Interpolants [3568#(and (= 0 |entry_point_#t~ret23.offset|) (<= 20 (select |#length| |entry_point_#t~ret23.base|)) (= (select |#valid| |entry_point_#t~ret23.base|) 1)), 3569#(and (= (select |#valid| entry_point_~intf~2.base) 1) (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base))), 3570#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 3571#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 3572#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 3573#(and (= entry_point_~intf~2.offset 0) (<= 20 (select |#length| entry_point_~intf~2.base))), 3562#true, 3563#false, 3564#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 3565#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)) (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296) ldv_zalloc_~size) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3566#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 3567#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|))))) (= 0 |ldv_zalloc_#res.offset|))] [2018-02-04 16:22:24,771 INFO L134 CoverageAnalysis]: Checked inductivity of 217 backedges. 12 proven. 5 refuted. 0 times theorem prover too weak. 200 trivial. 0 not checked. [2018-02-04 16:22:24,772 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 16:22:24,772 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 16:22:24,772 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=107, Unknown=0, NotChecked=0, Total=132 [2018-02-04 16:22:24,772 INFO L87 Difference]: Start difference. First operand 211 states and 251 transitions. Second operand 12 states. [2018-02-04 16:22:25,553 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:25,558 INFO L93 Difference]: Finished difference Result 221 states and 267 transitions. [2018-02-04 16:22:25,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 16:22:25,559 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 61 [2018-02-04 16:22:25,559 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:25,560 INFO L225 Difference]: With dead ends: 221 [2018-02-04 16:22:25,560 INFO L226 Difference]: Without dead ends: 221 [2018-02-04 16:22:25,560 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=46, Invalid=164, Unknown=0, NotChecked=0, Total=210 [2018-02-04 16:22:25,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 221 states. [2018-02-04 16:22:25,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 221 to 175. [2018-02-04 16:22:25,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-04 16:22:25,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 190 transitions. [2018-02-04 16:22:25,567 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 190 transitions. Word has length 61 [2018-02-04 16:22:25,567 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:25,567 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 190 transitions. [2018-02-04 16:22:25,567 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 16:22:25,567 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 190 transitions. [2018-02-04 16:22:25,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 16:22:25,568 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:25,568 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:25,568 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:25,568 INFO L82 PathProgramCache]: Analyzing trace with hash 1708156291, now seen corresponding path program 1 times [2018-02-04 16:22:25,569 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:25,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:25,585 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:25,628 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 16:22:25,629 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:25,629 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5] total 5 [2018-02-04 16:22:25,629 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:25,629 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-04 16:22:25,629 INFO L182 omatonBuilderFactory]: Interpolants [3976#true, 3977#false, 3978#(= 0 |ldv_zalloc_#t~malloc1.offset|), 3979#(= 0 |ldv_zalloc_#res.offset|), 3980#(= 0 |entry_point_#t~ret22.offset|), 3981#(= 0 entry_point_~hdev~0.offset)] [2018-02-04 16:22:25,630 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 16:22:25,630 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 16:22:25,630 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 16:22:25,630 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 16:22:25,630 INFO L87 Difference]: Start difference. First operand 175 states and 190 transitions. Second operand 6 states. [2018-02-04 16:22:25,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:25,649 INFO L93 Difference]: Finished difference Result 174 states and 189 transitions. [2018-02-04 16:22:25,650 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 16:22:25,650 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 64 [2018-02-04 16:22:25,650 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:25,651 INFO L225 Difference]: With dead ends: 174 [2018-02-04 16:22:25,651 INFO L226 Difference]: Without dead ends: 174 [2018-02-04 16:22:25,651 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 16:22:25,651 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-04 16:22:25,654 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-04 16:22:25,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 16:22:25,657 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 189 transitions. [2018-02-04 16:22:25,657 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 189 transitions. Word has length 64 [2018-02-04 16:22:25,657 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:25,657 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 189 transitions. [2018-02-04 16:22:25,657 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 16:22:25,658 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 189 transitions. [2018-02-04 16:22:25,658 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 16:22:25,658 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:25,658 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:25,658 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:25,659 INFO L82 PathProgramCache]: Analyzing trace with hash 1708156292, now seen corresponding path program 1 times [2018-02-04 16:22:25,659 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:25,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:25,676 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:25,730 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 16:22:25,730 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 16:22:25,731 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 16:22:25,731 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:25,731 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-04 16:22:25,731 INFO L182 omatonBuilderFactory]: Interpolants [4336#(not (= 0 |entry_point_#t~ret24.base|)), 4337#(not (= 0 (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 4338#(not (= 0 |entry_point_#t~mem26.base|)), 4332#true, 4333#false, 4334#(not (= 0 |ldv_zalloc_#t~malloc1.base|)), 4335#(not (= 0 |ldv_zalloc_#res.base|))] [2018-02-04 16:22:25,731 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 16:22:25,732 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 16:22:25,732 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 16:22:25,732 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 16:22:25,732 INFO L87 Difference]: Start difference. First operand 174 states and 189 transitions. Second operand 7 states. [2018-02-04 16:22:25,798 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:25,798 INFO L93 Difference]: Finished difference Result 173 states and 187 transitions. [2018-02-04 16:22:25,798 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 16:22:25,798 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 64 [2018-02-04 16:22:25,799 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:25,799 INFO L225 Difference]: With dead ends: 173 [2018-02-04 16:22:25,799 INFO L226 Difference]: Without dead ends: 173 [2018-02-04 16:22:25,800 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 16:22:25,800 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-02-04 16:22:25,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2018-02-04 16:22:25,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-04 16:22:25,803 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 187 transitions. [2018-02-04 16:22:25,804 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 187 transitions. Word has length 64 [2018-02-04 16:22:25,804 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:25,804 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 187 transitions. [2018-02-04 16:22:25,804 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 16:22:25,804 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 187 transitions. [2018-02-04 16:22:25,804 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-04 16:22:25,805 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:25,805 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:25,805 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:25,805 INFO L82 PathProgramCache]: Analyzing trace with hash 1413269325, now seen corresponding path program 1 times [2018-02-04 16:22:25,806 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:25,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:25,822 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:25,870 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 16:22:25,870 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 16:22:25,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 16:22:25,870 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:25,870 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-04 16:22:25,871 INFO L182 omatonBuilderFactory]: Interpolants [4691#true, 4692#false, 4693#(= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|)), 4694#(= 1 (select |#valid| |ldv_zalloc_#res.base|)), 4695#(= 1 (select |#valid| |entry_point_#t~ret24.base|)), 4696#(= 1 (select |#valid| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 4697#(= 1 (select |#valid| |entry_point_#t~mem27.base|))] [2018-02-04 16:22:25,871 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 16:22:25,871 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 16:22:25,871 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 16:22:25,871 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 16:22:25,871 INFO L87 Difference]: Start difference. First operand 173 states and 187 transitions. Second operand 7 states. [2018-02-04 16:22:26,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:26,051 INFO L93 Difference]: Finished difference Result 172 states and 186 transitions. [2018-02-04 16:22:26,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 16:22:26,053 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 65 [2018-02-04 16:22:26,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:26,054 INFO L225 Difference]: With dead ends: 172 [2018-02-04 16:22:26,054 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 16:22:26,054 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 16:22:26,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 16:22:26,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 172. [2018-02-04 16:22:26,058 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-02-04 16:22:26,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 186 transitions. [2018-02-04 16:22:26,059 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 186 transitions. Word has length 65 [2018-02-04 16:22:26,059 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:26,059 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 186 transitions. [2018-02-04 16:22:26,059 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 16:22:26,060 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 186 transitions. [2018-02-04 16:22:26,060 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-02-04 16:22:26,061 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:26,061 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:26,061 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:26,061 INFO L82 PathProgramCache]: Analyzing trace with hash 1413269326, now seen corresponding path program 1 times [2018-02-04 16:22:26,062 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:26,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:26,090 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:26,266 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 101 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-02-04 16:22:26,267 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:26,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 16:22:26,267 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:26,267 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 19 trivial. 0 not checked. [2018-02-04 16:22:26,268 INFO L182 omatonBuilderFactory]: Interpolants [5056#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 5057#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 4 |#Ultimate.meminit_#t~loopctr33|) 5) (* 5 |#Ultimate.meminit_#product|)))), 5058#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 5 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 5059#(or (<= |ldv_zalloc_#in~size| 5) (<= 4294967296 |ldv_zalloc_#in~size|)), 5048#true, 5049#false, 5050#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 5051#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 5052#(= |#Ultimate.meminit_#t~loopctr33| 0), 5053#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 5054#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 5055#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:22:26,268 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 101 refuted. 0 times theorem prover too weak. 79 trivial. 0 not checked. [2018-02-04 16:22:26,268 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 16:22:26,268 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 16:22:26,268 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=110, Unknown=0, NotChecked=0, Total=132 [2018-02-04 16:22:26,269 INFO L87 Difference]: Start difference. First operand 172 states and 186 transitions. Second operand 12 states. [2018-02-04 16:22:26,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:26,450 INFO L93 Difference]: Finished difference Result 178 states and 192 transitions. [2018-02-04 16:22:26,451 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 16:22:26,451 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 65 [2018-02-04 16:22:26,451 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:26,452 INFO L225 Difference]: With dead ends: 178 [2018-02-04 16:22:26,452 INFO L226 Difference]: Without dead ends: 173 [2018-02-04 16:22:26,453 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=31, Invalid=151, Unknown=0, NotChecked=0, Total=182 [2018-02-04 16:22:26,453 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 173 states. [2018-02-04 16:22:26,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 173 to 173. [2018-02-04 16:22:26,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-04 16:22:26,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 187 transitions. [2018-02-04 16:22:26,477 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 187 transitions. Word has length 65 [2018-02-04 16:22:26,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:26,477 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 187 transitions. [2018-02-04 16:22:26,477 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 16:22:26,477 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 187 transitions. [2018-02-04 16:22:26,478 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-02-04 16:22:26,478 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:26,478 INFO L351 BasicCegarLoop]: trace histogram [18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:26,478 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:26,479 INFO L82 PathProgramCache]: Analyzing trace with hash 342744626, now seen corresponding path program 2 times [2018-02-04 16:22:26,479 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:26,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:26,506 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:26,672 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 0 proven. 133 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-02-04 16:22:26,672 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:26,673 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 16:22:26,673 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:26,673 INFO L134 CoverageAnalysis]: Checked inductivity of 48 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-02-04 16:22:26,673 INFO L182 omatonBuilderFactory]: Interpolants [5415#true, 5416#false, 5417#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 5418#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 5419#(= |#Ultimate.meminit_#t~loopctr33| 0), 5420#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 5421#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 5422#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 5423#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 5424#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 5425#(and (<= (+ (* 5 |#Ultimate.meminit_#t~loopctr33|) 6) (* 6 |#Ultimate.meminit_#product|)) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 5426#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 6 |#Ultimate.meminit_#sizeOfFields|))) (<= 6 |#Ultimate.meminit_#product|)), 5427#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 6))] [2018-02-04 16:22:26,674 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 0 proven. 133 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-02-04 16:22:26,674 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 16:22:26,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 16:22:26,674 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=132, Unknown=0, NotChecked=0, Total=156 [2018-02-04 16:22:26,675 INFO L87 Difference]: Start difference. First operand 173 states and 187 transitions. Second operand 13 states. [2018-02-04 16:22:26,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:26,860 INFO L93 Difference]: Finished difference Result 179 states and 193 transitions. [2018-02-04 16:22:26,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 16:22:26,861 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2018-02-04 16:22:26,861 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:26,862 INFO L225 Difference]: With dead ends: 179 [2018-02-04 16:22:26,862 INFO L226 Difference]: Without dead ends: 174 [2018-02-04 16:22:26,862 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=177, Unknown=0, NotChecked=0, Total=210 [2018-02-04 16:22:26,862 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-04 16:22:26,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-04 16:22:26,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 16:22:26,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-04 16:22:26,866 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 68 [2018-02-04 16:22:26,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:26,866 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-04 16:22:26,866 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 16:22:26,866 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-04 16:22:26,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-02-04 16:22:26,867 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:26,867 INFO L351 BasicCegarLoop]: trace histogram [21, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:26,867 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:26,867 INFO L82 PathProgramCache]: Analyzing trace with hash 1946516686, now seen corresponding path program 3 times [2018-02-04 16:22:26,868 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:26,892 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:26,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:27,109 INFO L134 CoverageAnalysis]: Checked inductivity of 303 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-02-04 16:22:27,110 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:27,110 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-02-04 16:22:27,110 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:27,110 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 16:22:27,110 INFO L182 omatonBuilderFactory]: Interpolants [5792#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 5793#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 5794#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 5795#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 5796#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (+ (* 6 |#Ultimate.meminit_#t~loopctr33|) 7) (* 7 |#Ultimate.meminit_#product|))), 5797#(and (<= 7 |#Ultimate.meminit_#product|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 5798#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 7)), 5785#true, 5786#false, 5787#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 5788#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 5789#(= |#Ultimate.meminit_#t~loopctr33| 0), 5790#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 5791#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:22:27,110 INFO L134 CoverageAnalysis]: Checked inductivity of 303 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-02-04 16:22:27,110 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 16:22:27,111 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 16:22:27,111 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=156, Unknown=0, NotChecked=0, Total=182 [2018-02-04 16:22:27,111 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 14 states. [2018-02-04 16:22:27,271 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:27,271 INFO L93 Difference]: Finished difference Result 180 states and 194 transitions. [2018-02-04 16:22:27,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 16:22:27,271 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-02-04 16:22:27,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:27,272 INFO L225 Difference]: With dead ends: 180 [2018-02-04 16:22:27,272 INFO L226 Difference]: Without dead ends: 175 [2018-02-04 16:22:27,272 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 16 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=205, Unknown=0, NotChecked=0, Total=240 [2018-02-04 16:22:27,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-02-04 16:22:27,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 175. [2018-02-04 16:22:27,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 175 states. [2018-02-04 16:22:27,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 175 states to 175 states and 189 transitions. [2018-02-04 16:22:27,275 INFO L78 Accepts]: Start accepts. Automaton has 175 states and 189 transitions. Word has length 71 [2018-02-04 16:22:27,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:27,276 INFO L432 AbstractCegarLoop]: Abstraction has 175 states and 189 transitions. [2018-02-04 16:22:27,276 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 16:22:27,276 INFO L276 IsEmpty]: Start isEmpty. Operand 175 states and 189 transitions. [2018-02-04 16:22:27,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-04 16:22:27,276 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:27,276 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:27,277 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:27,277 INFO L82 PathProgramCache]: Analyzing trace with hash 395214514, now seen corresponding path program 4 times [2018-02-04 16:22:27,277 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:27,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:27,292 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:27,533 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 174 proven. 36 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-04 16:22:27,533 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:27,534 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-04 16:22:27,534 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:27,535 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 30 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 16:22:27,535 INFO L182 omatonBuilderFactory]: Interpolants [6158#true, 6159#false, 6160#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6161#(= |#Ultimate.meminit_#t~loopctr33| 0), 6162#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 6163#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6164#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6165#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6166#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6167#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6168#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6169#(<= (+ (* 7 |#Ultimate.meminit_#t~loopctr33|) 8) (* 8 |#Ultimate.meminit_#product|)), 6170#(<= 8 |#Ultimate.meminit_#product|), 6171#(and (<= 8 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6172#(and (<= 8 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 6173#(and (= 0 |entry_point_#t~ret24.offset|) (<= 8 (select |#length| |entry_point_#t~ret24.base|))), 6174#(and (<= 8 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 6175#(and (= |entry_point_#t~mem27.offset| 0) (<= 8 (select |#length| |entry_point_#t~mem27.base|)))] [2018-02-04 16:22:27,535 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 174 proven. 36 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-04 16:22:27,536 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 16:22:27,536 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 16:22:27,536 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=273, Unknown=0, NotChecked=0, Total=306 [2018-02-04 16:22:27,536 INFO L87 Difference]: Start difference. First operand 175 states and 189 transitions. Second operand 18 states. [2018-02-04 16:22:27,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:27,922 INFO L93 Difference]: Finished difference Result 189 states and 207 transitions. [2018-02-04 16:22:27,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 16:22:27,923 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 74 [2018-02-04 16:22:27,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:27,924 INFO L225 Difference]: With dead ends: 189 [2018-02-04 16:22:27,924 INFO L226 Difference]: Without dead ends: 189 [2018-02-04 16:22:27,924 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=451, Unknown=0, NotChecked=0, Total=506 [2018-02-04 16:22:27,924 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-02-04 16:22:27,928 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 188. [2018-02-04 16:22:27,928 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 188 states. [2018-02-04 16:22:27,929 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 188 states to 188 states and 206 transitions. [2018-02-04 16:22:27,929 INFO L78 Accepts]: Start accepts. Automaton has 188 states and 206 transitions. Word has length 74 [2018-02-04 16:22:27,929 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:27,929 INFO L432 AbstractCegarLoop]: Abstraction has 188 states and 206 transitions. [2018-02-04 16:22:27,929 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 16:22:27,929 INFO L276 IsEmpty]: Start isEmpty. Operand 188 states and 206 transitions. [2018-02-04 16:22:27,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-04 16:22:27,930 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:27,930 INFO L351 BasicCegarLoop]: trace histogram [25, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:27,930 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:27,931 INFO L82 PathProgramCache]: Analyzing trace with hash -1901565606, now seen corresponding path program 5 times [2018-02-04 16:22:27,931 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:27,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:27,954 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:28,190 INFO L134 CoverageAnalysis]: Checked inductivity of 405 backedges. 192 proven. 45 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-04 16:22:28,191 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:28,191 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-04 16:22:28,191 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:28,191 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-02-04 16:22:28,191 INFO L182 omatonBuilderFactory]: Interpolants [6563#true, 6564#false, 6565#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6566#(= |#Ultimate.meminit_#t~loopctr33| 0), 6567#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 6568#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6569#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6570#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6571#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6572#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6573#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6574#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 6575#(<= (+ (* 8 |#Ultimate.meminit_#t~loopctr33|) 9) (* 9 |#Ultimate.meminit_#product|)), 6576#(<= 9 |#Ultimate.meminit_#product|), 6577#(and (<= 9 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6578#(and (<= 9 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 6579#(and (<= 9 (select |#length| |entry_point_#t~ret24.base|)) (= 0 |entry_point_#t~ret24.offset|)), 6580#(and (<= 9 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 6581#(and (= |entry_point_#t~mem27.offset| 0) (<= 9 (select |#length| |entry_point_#t~mem27.base|)))] [2018-02-04 16:22:28,191 INFO L134 CoverageAnalysis]: Checked inductivity of 405 backedges. 192 proven. 45 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-04 16:22:28,191 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 16:22:28,192 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 16:22:28,192 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=307, Unknown=0, NotChecked=0, Total=342 [2018-02-04 16:22:28,192 INFO L87 Difference]: Start difference. First operand 188 states and 206 transitions. Second operand 19 states. [2018-02-04 16:22:28,620 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:28,620 INFO L93 Difference]: Finished difference Result 202 states and 224 transitions. [2018-02-04 16:22:28,620 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-04 16:22:28,620 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 75 [2018-02-04 16:22:28,621 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:28,621 INFO L225 Difference]: With dead ends: 202 [2018-02-04 16:22:28,621 INFO L226 Difference]: Without dead ends: 202 [2018-02-04 16:22:28,621 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=57, Invalid=495, Unknown=0, NotChecked=0, Total=552 [2018-02-04 16:22:28,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-02-04 16:22:28,625 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 189. [2018-02-04 16:22:28,625 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-02-04 16:22:28,626 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 208 transitions. [2018-02-04 16:22:28,626 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 208 transitions. Word has length 75 [2018-02-04 16:22:28,626 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:28,626 INFO L432 AbstractCegarLoop]: Abstraction has 189 states and 208 transitions. [2018-02-04 16:22:28,626 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 16:22:28,626 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 208 transitions. [2018-02-04 16:22:28,628 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 79 [2018-02-04 16:22:28,628 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:28,628 INFO L351 BasicCegarLoop]: trace histogram [28, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:28,628 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:28,628 INFO L82 PathProgramCache]: Analyzing trace with hash -781159886, now seen corresponding path program 6 times [2018-02-04 16:22:28,629 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:28,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:28,658 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:28,943 INFO L134 CoverageAnalysis]: Checked inductivity of 492 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 482 trivial. 0 not checked. [2018-02-04 16:22:28,944 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 16:22:28,944 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 16:22:28,944 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:28,944 INFO L134 CoverageAnalysis]: Checked inductivity of 46 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2018-02-04 16:22:28,944 INFO L182 omatonBuilderFactory]: Interpolants [6983#true, 6984#false, 6985#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 6986#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6987#(and (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 6988#(and (= 0 |ldv_zalloc_#res.offset|) (or (<= 2147483648 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|)))), 6989#(and (<= 9 (select |#length| |entry_point_#t~ret24.base|)) (= 0 |entry_point_#t~ret24.offset|)), 6990#(and (<= 9 (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))) (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4)))), 6991#(and (= |entry_point_#t~mem27.offset| 0) (<= 9 (select |#length| |entry_point_#t~mem27.base|)))] [2018-02-04 16:22:28,945 INFO L134 CoverageAnalysis]: Checked inductivity of 492 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 482 trivial. 0 not checked. [2018-02-04 16:22:28,945 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 16:22:28,945 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 16:22:28,945 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=56, Unknown=0, NotChecked=0, Total=72 [2018-02-04 16:22:28,945 INFO L87 Difference]: Start difference. First operand 189 states and 208 transitions. Second operand 9 states. [2018-02-04 16:22:29,180 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 51 DAG size of output 42 [2018-02-04 16:22:29,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:29,373 INFO L93 Difference]: Finished difference Result 188 states and 207 transitions. [2018-02-04 16:22:29,373 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 16:22:29,373 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 78 [2018-02-04 16:22:29,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:29,374 INFO L225 Difference]: With dead ends: 188 [2018-02-04 16:22:29,374 INFO L226 Difference]: Without dead ends: 188 [2018-02-04 16:22:29,375 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-04 16:22:29,375 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-02-04 16:22:29,378 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 174. [2018-02-04 16:22:29,378 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 16:22:29,379 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-04 16:22:29,379 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 78 [2018-02-04 16:22:29,379 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:29,379 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-04 16:22:29,379 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 16:22:29,379 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-04 16:22:29,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-04 16:22:29,380 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:29,380 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:29,380 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:29,380 INFO L82 PathProgramCache]: Analyzing trace with hash 1844027634, now seen corresponding path program 1 times [2018-02-04 16:22:29,381 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:29,408 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:29,409 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:29,564 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2018-02-04 16:22:29,564 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:29,564 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12] total 12 [2018-02-04 16:22:29,564 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:29,565 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 38 trivial. 0 not checked. [2018-02-04 16:22:29,565 INFO L182 omatonBuilderFactory]: Interpolants [7362#true, 7363#false, 7364#(= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|)), 7365#(= 1 (select |#valid| |ldv_zalloc_#res.base|)), 7366#(= 1 (select |#valid| |entry_point_#t~ret22.base|)), 7367#(= 1 (select |#valid| entry_point_~hdev~0.base)), 7368#(= |#valid| |old(#valid)|), 7369#(= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))), 7370#(and (or (= |ldv_zalloc_#res.base| (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 7371#(or (= entry_point_~hdev~0.base |entry_point_#t~ret23.base|) (= 1 (select |#valid| entry_point_~hdev~0.base))), 7372#(or (= entry_point_~hdev~0.base entry_point_~intf~2.base) (= 1 (select |#valid| entry_point_~hdev~0.base))), 7373#(and (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= 1 (select |#valid| |ldv_zalloc_#t~malloc1.base|))), 7374#(and (or (= 1 (select |#valid| (@diff |old(#valid)| |#valid|))) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 16:22:29,565 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 8 proven. 8 refuted. 0 times theorem prover too weak. 362 trivial. 0 not checked. [2018-02-04 16:22:29,565 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 16:22:29,565 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 16:22:29,566 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=125, Unknown=0, NotChecked=0, Total=156 [2018-02-04 16:22:29,566 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 13 states. [2018-02-04 16:22:30,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:30,109 INFO L93 Difference]: Finished difference Result 183 states and 198 transitions. [2018-02-04 16:22:30,109 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 16:22:30,109 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 76 [2018-02-04 16:22:30,109 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:30,110 INFO L225 Difference]: With dead ends: 183 [2018-02-04 16:22:30,110 INFO L226 Difference]: Without dead ends: 183 [2018-02-04 16:22:30,110 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=49, Invalid=191, Unknown=0, NotChecked=0, Total=240 [2018-02-04 16:22:30,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-02-04 16:22:30,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 173. [2018-02-04 16:22:30,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 173 states. [2018-02-04 16:22:30,114 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 173 states to 173 states and 187 transitions. [2018-02-04 16:22:30,114 INFO L78 Accepts]: Start accepts. Automaton has 173 states and 187 transitions. Word has length 76 [2018-02-04 16:22:30,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:30,114 INFO L432 AbstractCegarLoop]: Abstraction has 173 states and 187 transitions. [2018-02-04 16:22:30,114 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 16:22:30,115 INFO L276 IsEmpty]: Start isEmpty. Operand 173 states and 187 transitions. [2018-02-04 16:22:30,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-04 16:22:30,115 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:30,115 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:30,115 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:30,116 INFO L82 PathProgramCache]: Analyzing trace with hash 1844027635, now seen corresponding path program 1 times [2018-02-04 16:22:30,116 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:30,143 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:30,144 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:30,365 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 166 trivial. 0 not checked. [2018-02-04 16:22:30,365 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:30,365 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 16:22:30,365 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:30,366 INFO L134 CoverageAnalysis]: Checked inductivity of 54 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-02-04 16:22:30,366 INFO L182 omatonBuilderFactory]: Interpolants [7744#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 7745#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 7746#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 7747#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 7748#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 7749#(and (<= (+ (* 7 |#Ultimate.meminit_#t~loopctr33|) 8) (* 8 |#Ultimate.meminit_#product|)) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)))), 7750#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 8 |#Ultimate.meminit_#sizeOfFields|))) (<= 8 |#Ultimate.meminit_#product|)), 7751#(or (<= |ldv_zalloc_#in~size| 8) (<= 4294967296 |ldv_zalloc_#in~size|)), 7737#true, 7738#false, 7739#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 7740#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 7741#(= |#Ultimate.meminit_#t~loopctr33| 0), 7742#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 7743#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:22:30,366 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 0 proven. 212 refuted. 0 times theorem prover too weak. 166 trivial. 0 not checked. [2018-02-04 16:22:30,366 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 16:22:30,367 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 16:22:30,367 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=182, Unknown=0, NotChecked=0, Total=210 [2018-02-04 16:22:30,367 INFO L87 Difference]: Start difference. First operand 173 states and 187 transitions. Second operand 15 states. [2018-02-04 16:22:30,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:30,562 INFO L93 Difference]: Finished difference Result 179 states and 193 transitions. [2018-02-04 16:22:30,563 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 16:22:30,563 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 76 [2018-02-04 16:22:30,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:30,564 INFO L225 Difference]: With dead ends: 179 [2018-02-04 16:22:30,564 INFO L226 Difference]: Without dead ends: 174 [2018-02-04 16:22:30,564 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=37, Invalid=235, Unknown=0, NotChecked=0, Total=272 [2018-02-04 16:22:30,564 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-02-04 16:22:30,567 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-02-04 16:22:30,567 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-02-04 16:22:30,568 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 188 transitions. [2018-02-04 16:22:30,568 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 188 transitions. Word has length 76 [2018-02-04 16:22:30,568 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:30,568 INFO L432 AbstractCegarLoop]: Abstraction has 174 states and 188 transitions. [2018-02-04 16:22:30,568 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 16:22:30,568 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 188 transitions. [2018-02-04 16:22:30,568 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-02-04 16:22:30,569 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:30,569 INFO L351 BasicCegarLoop]: trace histogram [27, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:30,569 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:30,569 INFO L82 PathProgramCache]: Analyzing trace with hash 10632591, now seen corresponding path program 2 times [2018-02-04 16:22:30,570 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:30,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:30,624 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:30,889 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 107 proven. 152 refuted. 0 times theorem prover too weak. 203 trivial. 0 not checked. [2018-02-04 16:22:30,889 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:30,889 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-04 16:22:30,889 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:30,890 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 17 proven. 17 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-02-04 16:22:30,890 INFO L182 omatonBuilderFactory]: Interpolants [8109#true, 8110#false, 8111#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 8112#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 8113#(= |#Ultimate.meminit_#t~loopctr33| 0), 8114#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 8115#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8116#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 8117#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 8118#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 8119#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8120#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 8121#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8122#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 8 |#Ultimate.meminit_#t~loopctr33|) 9) (* 9 |#Ultimate.meminit_#product|)))), 8123#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 9 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 9 |#Ultimate.meminit_#sizeOfFields|)))), 8124#(or (<= |ldv_zalloc_#in~size| 9) (<= 4294967296 |ldv_zalloc_#in~size|))] [2018-02-04 16:22:30,890 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 107 proven. 152 refuted. 0 times theorem prover too weak. 203 trivial. 0 not checked. [2018-02-04 16:22:30,890 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 16:22:30,891 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 16:22:30,891 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=210, Unknown=0, NotChecked=0, Total=240 [2018-02-04 16:22:30,891 INFO L87 Difference]: Start difference. First operand 174 states and 188 transitions. Second operand 16 states. [2018-02-04 16:22:31,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:31,191 INFO L93 Difference]: Finished difference Result 183 states and 199 transitions. [2018-02-04 16:22:31,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 16:22:31,191 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 79 [2018-02-04 16:22:31,191 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:31,192 INFO L225 Difference]: With dead ends: 183 [2018-02-04 16:22:31,193 INFO L226 Difference]: Without dead ends: 183 [2018-02-04 16:22:31,193 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=39, Invalid=267, Unknown=0, NotChecked=0, Total=306 [2018-02-04 16:22:31,193 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-02-04 16:22:31,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 183. [2018-02-04 16:22:31,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-02-04 16:22:31,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 199 transitions. [2018-02-04 16:22:31,195 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 199 transitions. Word has length 79 [2018-02-04 16:22:31,195 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:31,195 INFO L432 AbstractCegarLoop]: Abstraction has 183 states and 199 transitions. [2018-02-04 16:22:31,195 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 16:22:31,195 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 199 transitions. [2018-02-04 16:22:31,196 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-04 16:22:31,196 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:31,196 INFO L351 BasicCegarLoop]: trace histogram [29, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:31,196 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:31,196 INFO L82 PathProgramCache]: Analyzing trace with hash 826541595, now seen corresponding path program 3 times [2018-02-04 16:22:31,196 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:31,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:31,225 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:31,565 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 223 trivial. 0 not checked. [2018-02-04 16:22:31,565 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:31,565 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-04 16:22:31,565 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:31,566 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:31,566 INFO L182 omatonBuilderFactory]: Interpolants [8495#true, 8496#false, 8497#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 8498#(or (and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))) (and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))), 8499#(= |#Ultimate.meminit_#t~loopctr33| 0), 8500#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 8501#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8502#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 8503#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 8504#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 8505#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8506#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 8507#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8508#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 8509#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)) (<= (+ (* 9 |#Ultimate.meminit_#t~loopctr33|) 10) (* 10 |#Ultimate.meminit_#product|)))), 8510#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 10 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 8511#(or (<= 2147483648 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 10))] [2018-02-04 16:22:31,566 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 223 trivial. 0 not checked. [2018-02-04 16:22:31,566 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 16:22:31,567 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 16:22:31,567 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=32, Invalid=240, Unknown=0, NotChecked=0, Total=272 [2018-02-04 16:22:31,567 INFO L87 Difference]: Start difference. First operand 183 states and 199 transitions. Second operand 17 states. [2018-02-04 16:22:31,884 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:31,884 INFO L93 Difference]: Finished difference Result 192 states and 208 transitions. [2018-02-04 16:22:31,884 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 16:22:31,884 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 81 [2018-02-04 16:22:31,884 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:31,885 INFO L225 Difference]: With dead ends: 192 [2018-02-04 16:22:31,885 INFO L226 Difference]: Without dead ends: 186 [2018-02-04 16:22:31,885 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 19 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=41, Invalid=301, Unknown=0, NotChecked=0, Total=342 [2018-02-04 16:22:31,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-02-04 16:22:31,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 184. [2018-02-04 16:22:31,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 184 states. [2018-02-04 16:22:31,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 184 states to 184 states and 200 transitions. [2018-02-04 16:22:31,889 INFO L78 Accepts]: Start accepts. Automaton has 184 states and 200 transitions. Word has length 81 [2018-02-04 16:22:31,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:31,889 INFO L432 AbstractCegarLoop]: Abstraction has 184 states and 200 transitions. [2018-02-04 16:22:31,889 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 16:22:31,889 INFO L276 IsEmpty]: Start isEmpty. Operand 184 states and 200 transitions. [2018-02-04 16:22:31,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-04 16:22:31,890 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:31,890 INFO L351 BasicCegarLoop]: trace histogram [31, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:31,891 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:31,891 INFO L82 PathProgramCache]: Analyzing trace with hash 132830479, now seen corresponding path program 4 times [2018-02-04 16:22:31,892 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:31,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:31,927 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:32,287 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 0 proven. 344 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2018-02-04 16:22:32,287 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:32,287 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18] total 18 [2018-02-04 16:22:32,287 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:32,288 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:32,288 INFO L182 omatonBuilderFactory]: Interpolants [8896#(= |#Ultimate.meminit_#t~loopctr33| 0), 8897#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 8898#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 8899#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 8900#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 8901#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 8902#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 8903#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 8904#(and (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)))), 8905#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 8906#(and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 8907#(and (<= (+ (* 10 |#Ultimate.meminit_#t~loopctr33|) 11) (* 11 |#Ultimate.meminit_#product|)) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 8908#(and (<= 11 |#Ultimate.meminit_#product|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 8909#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 11)), 8892#true, 8893#false, 8894#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 8895#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)))] [2018-02-04 16:22:32,288 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 0 proven. 344 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2018-02-04 16:22:32,289 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 16:22:32,289 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 16:22:32,289 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=34, Invalid=272, Unknown=0, NotChecked=0, Total=306 [2018-02-04 16:22:32,289 INFO L87 Difference]: Start difference. First operand 184 states and 200 transitions. Second operand 18 states. [2018-02-04 16:22:32,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:32,666 INFO L93 Difference]: Finished difference Result 192 states and 209 transitions. [2018-02-04 16:22:32,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 16:22:32,667 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 83 [2018-02-04 16:22:32,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:32,667 INFO L225 Difference]: With dead ends: 192 [2018-02-04 16:22:32,668 INFO L226 Difference]: Without dead ends: 189 [2018-02-04 16:22:32,668 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 20 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=43, Invalid=337, Unknown=0, NotChecked=0, Total=380 [2018-02-04 16:22:32,668 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-02-04 16:22:32,670 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 185. [2018-02-04 16:22:32,670 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-02-04 16:22:32,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 202 transitions. [2018-02-04 16:22:32,671 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 202 transitions. Word has length 83 [2018-02-04 16:22:32,671 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:32,671 INFO L432 AbstractCegarLoop]: Abstraction has 185 states and 202 transitions. [2018-02-04 16:22:32,671 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 16:22:32,671 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 202 transitions. [2018-02-04 16:22:32,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 16:22:32,671 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:32,671 INFO L351 BasicCegarLoop]: trace histogram [33, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:32,672 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:32,672 INFO L82 PathProgramCache]: Analyzing trace with hash 1935927963, now seen corresponding path program 5 times [2018-02-04 16:22:32,672 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:32,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:32,696 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:33,241 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 4 proven. 393 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2018-02-04 16:22:33,242 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:33,242 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-04 16:22:33,242 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:33,242 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 2 proven. 29 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:33,242 INFO L182 omatonBuilderFactory]: Interpolants [9291#true, 9292#false, 9293#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 9294#(= |#Ultimate.meminit_#t~loopctr33| 0), 9295#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 9296#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9297#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9298#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9299#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9300#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9301#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9302#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9303#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9304#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9305#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 9306#(<= (+ (* 11 |#Ultimate.meminit_#t~loopctr33|) 12) (* 12 |#Ultimate.meminit_#product|)), 9307#(<= 12 |#Ultimate.meminit_#product|), 9308#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 12 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 9309#(and (<= 12 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 9310#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 12 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 9311#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 9312#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 9313#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 9314#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 9315#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 9316#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 9317#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:22:33,242 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 4 proven. 393 refuted. 0 times theorem prover too weak. 260 trivial. 0 not checked. [2018-02-04 16:22:33,243 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 16:22:33,243 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 16:22:33,243 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=643, Unknown=0, NotChecked=0, Total=702 [2018-02-04 16:22:33,243 INFO L87 Difference]: Start difference. First operand 185 states and 202 transitions. Second operand 27 states. [2018-02-04 16:22:35,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:35,017 INFO L93 Difference]: Finished difference Result 243 states and 278 transitions. [2018-02-04 16:22:35,018 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 16:22:35,018 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 85 [2018-02-04 16:22:35,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:35,019 INFO L225 Difference]: With dead ends: 243 [2018-02-04 16:22:35,019 INFO L226 Difference]: Without dead ends: 243 [2018-02-04 16:22:35,019 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 171 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=183, Invalid=1887, Unknown=0, NotChecked=0, Total=2070 [2018-02-04 16:22:35,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-02-04 16:22:35,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 206. [2018-02-04 16:22:35,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-02-04 16:22:35,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 230 transitions. [2018-02-04 16:22:35,024 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 230 transitions. Word has length 85 [2018-02-04 16:22:35,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:35,025 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 230 transitions. [2018-02-04 16:22:35,025 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 16:22:35,025 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 230 transitions. [2018-02-04 16:22:35,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-02-04 16:22:35,025 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:35,025 INFO L351 BasicCegarLoop]: trace histogram [35, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:35,025 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:35,026 INFO L82 PathProgramCache]: Analyzing trace with hash -1427501937, now seen corresponding path program 6 times [2018-02-04 16:22:35,026 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:35,055 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:35,056 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:35,431 INFO L134 CoverageAnalysis]: Checked inductivity of 730 backedges. 203 proven. 238 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-04 16:22:35,432 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:35,432 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-04 16:22:35,432 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:35,432 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 21 proven. 10 refuted. 0 times theorem prover too weak. 14 trivial. 0 not checked. [2018-02-04 16:22:35,432 INFO L182 omatonBuilderFactory]: Interpolants [9824#(or (<= |ldv_zalloc_#in~size| 13) (<= 4294967296 |ldv_zalloc_#in~size|)), 9805#true, 9806#false, 9807#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 9808#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 9809#(= |#Ultimate.meminit_#t~loopctr33| 0), 9810#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 9811#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9812#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 9813#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 9814#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 9815#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9816#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 9817#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9818#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 9819#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 9820#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 9821#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 9822#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (+ (* 12 |#Ultimate.meminit_#t~loopctr33|) 13) (* 13 |#Ultimate.meminit_#product|)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|)))), 9823#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= 13 |#Ultimate.meminit_#product|) (<= |#Ultimate.meminit_#product| (* 13 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:22:35,433 INFO L134 CoverageAnalysis]: Checked inductivity of 730 backedges. 203 proven. 238 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-04 16:22:35,433 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 16:22:35,433 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 16:22:35,433 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=342, Unknown=0, NotChecked=0, Total=380 [2018-02-04 16:22:35,433 INFO L87 Difference]: Start difference. First operand 206 states and 230 transitions. Second operand 20 states. [2018-02-04 16:22:35,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:35,848 INFO L93 Difference]: Finished difference Result 222 states and 249 transitions. [2018-02-04 16:22:35,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 16:22:35,883 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 87 [2018-02-04 16:22:35,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:35,884 INFO L225 Difference]: With dead ends: 222 [2018-02-04 16:22:35,884 INFO L226 Difference]: Without dead ends: 222 [2018-02-04 16:22:35,884 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=47, Invalid=415, Unknown=0, NotChecked=0, Total=462 [2018-02-04 16:22:35,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-02-04 16:22:35,887 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 215. [2018-02-04 16:22:35,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-02-04 16:22:35,888 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 241 transitions. [2018-02-04 16:22:35,888 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 241 transitions. Word has length 87 [2018-02-04 16:22:35,888 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:35,888 INFO L432 AbstractCegarLoop]: Abstraction has 215 states and 241 transitions. [2018-02-04 16:22:35,888 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 16:22:35,888 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 241 transitions. [2018-02-04 16:22:35,889 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-02-04 16:22:35,889 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:35,889 INFO L351 BasicCegarLoop]: trace histogram [34, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:35,889 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:35,889 INFO L82 PathProgramCache]: Analyzing trace with hash -586112205, now seen corresponding path program 7 times [2018-02-04 16:22:35,890 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:35,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:35,923 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:36,246 INFO L134 CoverageAnalysis]: Checked inductivity of 693 backedges. 189 proven. 215 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-04 16:22:36,247 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:36,247 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-04 16:22:36,247 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:36,247 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 13 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:36,247 INFO L182 omatonBuilderFactory]: Interpolants [10272#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10273#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 10274#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 10275#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 10276#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10277#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 10278#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10279#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 10280#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 10281#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 10282#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (+ (* 11 |#Ultimate.meminit_#t~loopctr33|) 12) (* 12 |#Ultimate.meminit_#product|)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 10283#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#product| (* 12 |#Ultimate.meminit_#sizeOfFields|)) (<= 12 |#Ultimate.meminit_#product|))), 10284#(or (<= |ldv_zalloc_#in~size| 12) (<= 4294967296 |ldv_zalloc_#in~size|)), 10266#true, 10267#false, 10268#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 10269#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 10270#(= |#Ultimate.meminit_#t~loopctr33| 0), 10271#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1)))] [2018-02-04 16:22:36,248 INFO L134 CoverageAnalysis]: Checked inductivity of 693 backedges. 189 proven. 215 refuted. 0 times theorem prover too weak. 289 trivial. 0 not checked. [2018-02-04 16:22:36,248 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 16:22:36,248 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 16:22:36,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=306, Unknown=0, NotChecked=0, Total=342 [2018-02-04 16:22:36,249 INFO L87 Difference]: Start difference. First operand 215 states and 241 transitions. Second operand 19 states. [2018-02-04 16:22:36,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:36,598 INFO L93 Difference]: Finished difference Result 225 states and 249 transitions. [2018-02-04 16:22:36,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 16:22:36,603 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 86 [2018-02-04 16:22:36,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:36,603 INFO L225 Difference]: With dead ends: 225 [2018-02-04 16:22:36,603 INFO L226 Difference]: Without dead ends: 219 [2018-02-04 16:22:36,604 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=375, Unknown=0, NotChecked=0, Total=420 [2018-02-04 16:22:36,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-02-04 16:22:36,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 215. [2018-02-04 16:22:36,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 215 states. [2018-02-04 16:22:36,607 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 215 states to 215 states and 239 transitions. [2018-02-04 16:22:36,607 INFO L78 Accepts]: Start accepts. Automaton has 215 states and 239 transitions. Word has length 86 [2018-02-04 16:22:36,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:36,608 INFO L432 AbstractCegarLoop]: Abstraction has 215 states and 239 transitions. [2018-02-04 16:22:36,608 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 16:22:36,608 INFO L276 IsEmpty]: Start isEmpty. Operand 215 states and 239 transitions. [2018-02-04 16:22:36,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-02-04 16:22:36,608 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:36,608 INFO L351 BasicCegarLoop]: trace histogram [36, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:36,608 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:36,609 INFO L82 PathProgramCache]: Analyzing trace with hash -1740779853, now seen corresponding path program 8 times [2018-02-04 16:22:36,609 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:36,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:36,640 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:36,888 INFO L134 CoverageAnalysis]: Checked inductivity of 768 backedges. 0 proven. 455 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-04 16:22:36,889 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:36,889 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-04 16:22:36,889 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:36,889 INFO L134 CoverageAnalysis]: Checked inductivity of 37 backedges. 0 proven. 24 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:36,889 INFO L182 omatonBuilderFactory]: Interpolants [10729#true, 10730#false, 10731#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 10732#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 10733#(= |#Ultimate.meminit_#t~loopctr33| 0), 10734#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 10735#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10736#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10737#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10738#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10739#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10740#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10741#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10742#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10743#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10744#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10745#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 10746#(<= (+ (* 12 |#Ultimate.meminit_#t~loopctr33|) 13) (* 13 |#Ultimate.meminit_#product|)), 10747#(<= 13 |#Ultimate.meminit_#product|), 10748#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 13 |ldv_zalloc_#in~size|))] [2018-02-04 16:22:36,890 INFO L134 CoverageAnalysis]: Checked inductivity of 768 backedges. 0 proven. 455 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-04 16:22:36,890 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 16:22:36,890 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 16:22:36,890 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=342, Unknown=0, NotChecked=0, Total=380 [2018-02-04 16:22:36,890 INFO L87 Difference]: Start difference. First operand 215 states and 239 transitions. Second operand 20 states. [2018-02-04 16:22:37,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:37,271 INFO L93 Difference]: Finished difference Result 225 states and 247 transitions. [2018-02-04 16:22:37,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 16:22:37,271 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 88 [2018-02-04 16:22:37,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:37,272 INFO L225 Difference]: With dead ends: 225 [2018-02-04 16:22:37,272 INFO L226 Difference]: Without dead ends: 217 [2018-02-04 16:22:37,272 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 22 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=47, Invalid=415, Unknown=0, NotChecked=0, Total=462 [2018-02-04 16:22:37,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-02-04 16:22:37,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 213. [2018-02-04 16:22:37,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-02-04 16:22:37,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 235 transitions. [2018-02-04 16:22:37,275 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 235 transitions. Word has length 88 [2018-02-04 16:22:37,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:37,275 INFO L432 AbstractCegarLoop]: Abstraction has 213 states and 235 transitions. [2018-02-04 16:22:37,275 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 16:22:37,275 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 235 transitions. [2018-02-04 16:22:37,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-04 16:22:37,275 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:37,276 INFO L351 BasicCegarLoop]: trace histogram [37, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:37,276 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:37,276 INFO L82 PathProgramCache]: Analyzing trace with hash 318451483, now seen corresponding path program 9 times [2018-02-04 16:22:37,277 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:37,327 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:37,328 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:37,741 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 232 proven. 262 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-04 16:22:37,741 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:37,741 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21] total 21 [2018-02-04 16:22:37,742 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:37,742 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:37,742 INFO L182 omatonBuilderFactory]: Interpolants [11200#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 11201#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11202#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|)))), 11203#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11204#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11205#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 11206#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 11207#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 11208#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|)))), 11209#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (+ (* 13 |#Ultimate.meminit_#t~loopctr33|) 14) (* 14 |#Ultimate.meminit_#product|)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|)))), 11210#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#product| (* 14 |#Ultimate.meminit_#sizeOfFields|)) (<= 14 |#Ultimate.meminit_#product|))), 11211#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 14)), 11191#true, 11192#false, 11193#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 11194#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 11195#(= |#Ultimate.meminit_#t~loopctr33| 0), 11196#(or (and (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 11197#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))), 11198#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|)))), 11199#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:22:37,743 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 232 proven. 262 refuted. 0 times theorem prover too weak. 313 trivial. 0 not checked. [2018-02-04 16:22:37,743 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 16:22:37,743 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 16:22:37,744 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=380, Unknown=0, NotChecked=0, Total=420 [2018-02-04 16:22:37,744 INFO L87 Difference]: Start difference. First operand 213 states and 235 transitions. Second operand 21 states. [2018-02-04 16:22:38,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:38,149 INFO L93 Difference]: Finished difference Result 223 states and 247 transitions. [2018-02-04 16:22:38,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-02-04 16:22:38,149 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 89 [2018-02-04 16:22:38,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:38,149 INFO L225 Difference]: With dead ends: 223 [2018-02-04 16:22:38,150 INFO L226 Difference]: Without dead ends: 220 [2018-02-04 16:22:38,150 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=49, Invalid=457, Unknown=0, NotChecked=0, Total=506 [2018-02-04 16:22:38,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 220 states. [2018-02-04 16:22:38,152 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 220 to 216. [2018-02-04 16:22:38,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-02-04 16:22:38,153 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 240 transitions. [2018-02-04 16:22:38,153 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 240 transitions. Word has length 89 [2018-02-04 16:22:38,153 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:38,154 INFO L432 AbstractCegarLoop]: Abstraction has 216 states and 240 transitions. [2018-02-04 16:22:38,154 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 16:22:38,154 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 240 transitions. [2018-02-04 16:22:38,154 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-04 16:22:38,154 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:38,154 INFO L351 BasicCegarLoop]: trace histogram [38, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:38,154 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:38,155 INFO L82 PathProgramCache]: Analyzing trace with hash 844168615, now seen corresponding path program 10 times [2018-02-04 16:22:38,155 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:38,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:38,193 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:38,737 INFO L134 CoverageAnalysis]: Checked inductivity of 847 backedges. 4 proven. 511 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:38,737 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:38,737 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-04 16:22:38,737 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:38,738 INFO L134 CoverageAnalysis]: Checked inductivity of 38 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:38,738 INFO L182 omatonBuilderFactory]: Interpolants [11655#true, 11656#false, 11657#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 11658#(= |#Ultimate.meminit_#t~loopctr33| 0), 11659#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 11660#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11661#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11662#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11663#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11664#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11665#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11666#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11667#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11668#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11669#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11670#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11671#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 11672#(<= (+ (* 13 |#Ultimate.meminit_#t~loopctr33|) 14) (* 14 |#Ultimate.meminit_#product|)), 11673#(<= 14 |#Ultimate.meminit_#product|), 11674#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 14 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 11675#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 14 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 11676#(and (<= 14 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 11677#(and (<= 14 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 11678#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 11679#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 11680#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 11681#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 11682#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 11683#(and (<= 14 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:22:38,738 INFO L134 CoverageAnalysis]: Checked inductivity of 847 backedges. 4 proven. 511 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:38,738 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 16:22:38,738 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 16:22:38,738 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=749, Unknown=0, NotChecked=0, Total=812 [2018-02-04 16:22:38,738 INFO L87 Difference]: Start difference. First operand 216 states and 240 transitions. Second operand 29 states. [2018-02-04 16:22:40,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:40,633 INFO L93 Difference]: Finished difference Result 271 states and 310 transitions. [2018-02-04 16:22:40,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-04 16:22:40,633 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 90 [2018-02-04 16:22:40,634 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:40,634 INFO L225 Difference]: With dead ends: 271 [2018-02-04 16:22:40,634 INFO L226 Difference]: Without dead ends: 271 [2018-02-04 16:22:40,635 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 210 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=199, Invalid=2251, Unknown=0, NotChecked=0, Total=2450 [2018-02-04 16:22:40,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-02-04 16:22:40,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 214. [2018-02-04 16:22:40,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-02-04 16:22:40,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 237 transitions. [2018-02-04 16:22:40,639 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 237 transitions. Word has length 90 [2018-02-04 16:22:40,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:40,640 INFO L432 AbstractCegarLoop]: Abstraction has 214 states and 237 transitions. [2018-02-04 16:22:40,640 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 16:22:40,640 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 237 transitions. [2018-02-04 16:22:40,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-02-04 16:22:40,640 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:40,640 INFO L351 BasicCegarLoop]: trace histogram [39, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:40,641 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:40,641 INFO L82 PathProgramCache]: Analyzing trace with hash -214440945, now seen corresponding path program 11 times [2018-02-04 16:22:40,642 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:40,686 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:40,687 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:41,265 INFO L134 CoverageAnalysis]: Checked inductivity of 888 backedges. 4 proven. 552 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:41,265 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:41,265 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29] total 29 [2018-02-04 16:22:41,265 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:41,266 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:41,266 INFO L182 omatonBuilderFactory]: Interpolants [12224#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12225#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12226#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12227#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12228#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12229#(<= (+ (* 14 |#Ultimate.meminit_#t~loopctr33|) 15) (* 15 |#Ultimate.meminit_#product|)), 12230#(<= 15 |#Ultimate.meminit_#product|), 12231#(and (<= 15 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 12232#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 15 (select |#length| |ldv_zalloc_#res.base|))), 12233#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 15 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 12234#(and (<= 15 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 12235#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 12236#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 12237#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 12238#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 12239#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 12240#(and (<= 15 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 12211#true, 12212#false, 12213#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 12214#(= |#Ultimate.meminit_#t~loopctr33| 0), 12215#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 12216#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12217#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12218#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12219#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12220#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12221#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12222#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12223#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:22:41,266 INFO L134 CoverageAnalysis]: Checked inductivity of 888 backedges. 4 proven. 552 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:41,266 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-04 16:22:41,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-04 16:22:41,266 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=805, Unknown=0, NotChecked=0, Total=870 [2018-02-04 16:22:41,266 INFO L87 Difference]: Start difference. First operand 214 states and 237 transitions. Second operand 30 states. [2018-02-04 16:22:43,139 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:43,139 INFO L93 Difference]: Finished difference Result 277 states and 321 transitions. [2018-02-04 16:22:43,139 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 16:22:43,139 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 91 [2018-02-04 16:22:43,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:43,140 INFO L225 Difference]: With dead ends: 277 [2018-02-04 16:22:43,140 INFO L226 Difference]: Without dead ends: 277 [2018-02-04 16:22:43,140 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 231 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=207, Invalid=2445, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 16:22:43,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-02-04 16:22:43,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 217. [2018-02-04 16:22:43,145 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-02-04 16:22:43,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 243 transitions. [2018-02-04 16:22:43,145 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 243 transitions. Word has length 91 [2018-02-04 16:22:43,146 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:43,146 INFO L432 AbstractCegarLoop]: Abstraction has 217 states and 243 transitions. [2018-02-04 16:22:43,146 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-04 16:22:43,146 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 243 transitions. [2018-02-04 16:22:43,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-04 16:22:43,147 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:43,147 INFO L351 BasicCegarLoop]: trace histogram [40, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:43,147 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:43,147 INFO L82 PathProgramCache]: Analyzing trace with hash 1328401063, now seen corresponding path program 12 times [2018-02-04 16:22:43,148 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:43,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:43,200 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:43,552 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 592 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-04 16:22:43,552 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:43,552 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-04 16:22:43,552 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:43,552 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:43,552 INFO L182 omatonBuilderFactory]: Interpolants [12800#(<= 16 |#Ultimate.meminit_#product|), 12801#(or (<= 16 |ldv_zalloc_#in~size|) (<= (+ |ldv_zalloc_#in~size| 1) 0)), 12779#true, 12780#false, 12781#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 12782#(and (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)) (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1)))), 12783#(= |#Ultimate.meminit_#t~loopctr33| 0), 12784#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 12785#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12786#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12787#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12788#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12789#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12790#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12791#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12792#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12793#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12794#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12795#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12796#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12797#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12798#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 12799#(<= (+ (* 15 |#Ultimate.meminit_#t~loopctr33|) 16) (* 16 |#Ultimate.meminit_#product|))] [2018-02-04 16:22:43,553 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 0 proven. 592 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-04 16:22:43,553 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 16:22:43,553 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 16:22:43,553 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=462, Unknown=0, NotChecked=0, Total=506 [2018-02-04 16:22:43,553 INFO L87 Difference]: Start difference. First operand 217 states and 243 transitions. Second operand 23 states. [2018-02-04 16:22:43,949 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:43,949 INFO L93 Difference]: Finished difference Result 232 states and 260 transitions. [2018-02-04 16:22:43,949 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-04 16:22:43,949 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 92 [2018-02-04 16:22:43,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:43,950 INFO L225 Difference]: With dead ends: 232 [2018-02-04 16:22:43,950 INFO L226 Difference]: Without dead ends: 226 [2018-02-04 16:22:43,950 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=53, Invalid=547, Unknown=0, NotChecked=0, Total=600 [2018-02-04 16:22:43,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226 states. [2018-02-04 16:22:43,953 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226 to 220. [2018-02-04 16:22:43,953 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 220 states. [2018-02-04 16:22:43,953 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 220 states to 220 states and 247 transitions. [2018-02-04 16:22:43,953 INFO L78 Accepts]: Start accepts. Automaton has 220 states and 247 transitions. Word has length 92 [2018-02-04 16:22:43,954 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:43,954 INFO L432 AbstractCegarLoop]: Abstraction has 220 states and 247 transitions. [2018-02-04 16:22:43,954 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 16:22:43,954 INFO L276 IsEmpty]: Start isEmpty. Operand 220 states and 247 transitions. [2018-02-04 16:22:43,954 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-04 16:22:43,954 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:43,954 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:43,955 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:43,955 INFO L82 PathProgramCache]: Analyzing trace with hash 1911863055, now seen corresponding path program 13 times [2018-02-04 16:22:43,956 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:43,978 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:43,979 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:44,615 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 4 proven. 637 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:44,615 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:44,615 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-04 16:22:44,615 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:44,616 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:44,616 INFO L182 omatonBuilderFactory]: Interpolants [13258#true, 13259#false, 13260#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13261#(= |#Ultimate.meminit_#t~loopctr33| 0), 13262#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 13263#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13264#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13265#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13266#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13267#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13268#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13269#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13270#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13271#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13272#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13273#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13274#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13275#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13276#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13277#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13278#(<= (+ (* 16 |#Ultimate.meminit_#t~loopctr33|) 17) (* 17 |#Ultimate.meminit_#product|)), 13279#(<= 17 |#Ultimate.meminit_#product|), 13280#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 17 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13281#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 17 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 13282#(and (<= 17 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 13283#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 17 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 13284#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 13285#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13286#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 13287#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13288#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 13289#(and (= entry_point_~hdev~0.offset 0) (<= 17 (select |#length| entry_point_~hdev~0.base)))] [2018-02-04 16:22:44,616 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 4 proven. 637 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:44,616 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-04 16:22:44,617 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-04 16:22:44,617 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=69, Invalid=923, Unknown=0, NotChecked=0, Total=992 [2018-02-04 16:22:44,617 INFO L87 Difference]: Start difference. First operand 220 states and 247 transitions. Second operand 32 states. [2018-02-04 16:22:46,754 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:46,754 INFO L93 Difference]: Finished difference Result 283 states and 331 transitions. [2018-02-04 16:22:46,755 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-04 16:22:46,755 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 93 [2018-02-04 16:22:46,755 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:46,756 INFO L225 Difference]: With dead ends: 283 [2018-02-04 16:22:46,756 INFO L226 Difference]: Without dead ends: 283 [2018-02-04 16:22:46,758 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 276 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=223, Invalid=2857, Unknown=0, NotChecked=0, Total=3080 [2018-02-04 16:22:46,758 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283 states. [2018-02-04 16:22:46,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283 to 221. [2018-02-04 16:22:46,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 221 states. [2018-02-04 16:22:46,762 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 221 states to 221 states and 249 transitions. [2018-02-04 16:22:46,762 INFO L78 Accepts]: Start accepts. Automaton has 221 states and 249 transitions. Word has length 93 [2018-02-04 16:22:46,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:46,763 INFO L432 AbstractCegarLoop]: Abstraction has 221 states and 249 transitions. [2018-02-04 16:22:46,763 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-04 16:22:46,763 INFO L276 IsEmpty]: Start isEmpty. Operand 221 states and 249 transitions. [2018-02-04 16:22:46,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-02-04 16:22:46,764 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:46,764 INFO L351 BasicCegarLoop]: trace histogram [42, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:46,764 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:46,764 INFO L82 PathProgramCache]: Analyzing trace with hash -1475651673, now seen corresponding path program 14 times [2018-02-04 16:22:46,765 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:46,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:46,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:47,371 INFO L134 CoverageAnalysis]: Checked inductivity of 1017 backedges. 4 proven. 681 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:47,372 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:47,372 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-04 16:22:47,372 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:47,372 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:47,372 INFO L182 omatonBuilderFactory]: Interpolants [13842#true, 13843#false, 13844#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13845#(= |#Ultimate.meminit_#t~loopctr33| 0), 13846#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 13847#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13848#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13849#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13850#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13851#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13852#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13853#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13854#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13855#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13856#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13857#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13858#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13859#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13860#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13861#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13862#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 13863#(<= (+ (* 17 |#Ultimate.meminit_#t~loopctr33|) 18) (* 18 |#Ultimate.meminit_#product|)), 13864#(<= 18 |#Ultimate.meminit_#product|), 13865#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 18 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 13866#(and (<= 18 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 13867#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 18 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 13868#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 18 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 13869#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 13870#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13871#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 13872#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 13873#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 13874#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:22:47,373 INFO L134 CoverageAnalysis]: Checked inductivity of 1017 backedges. 4 proven. 681 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:47,373 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 16:22:47,373 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 16:22:47,373 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=985, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 16:22:47,373 INFO L87 Difference]: Start difference. First operand 221 states and 249 transitions. Second operand 33 states. [2018-02-04 16:22:49,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:49,604 INFO L93 Difference]: Finished difference Result 286 states and 337 transitions. [2018-02-04 16:22:49,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 16:22:49,604 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 94 [2018-02-04 16:22:49,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:49,605 INFO L225 Difference]: With dead ends: 286 [2018-02-04 16:22:49,605 INFO L226 Difference]: Without dead ends: 286 [2018-02-04 16:22:49,606 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 300 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=231, Invalid=3075, Unknown=0, NotChecked=0, Total=3306 [2018-02-04 16:22:49,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 286 states. [2018-02-04 16:22:49,609 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 286 to 222. [2018-02-04 16:22:49,609 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-02-04 16:22:49,610 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 251 transitions. [2018-02-04 16:22:49,610 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 251 transitions. Word has length 94 [2018-02-04 16:22:49,610 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:49,610 INFO L432 AbstractCegarLoop]: Abstraction has 222 states and 251 transitions. [2018-02-04 16:22:49,610 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 16:22:49,610 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 251 transitions. [2018-02-04 16:22:49,611 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-02-04 16:22:49,611 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:49,611 INFO L351 BasicCegarLoop]: trace histogram [43, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:49,611 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:49,611 INFO L82 PathProgramCache]: Analyzing trace with hash 885574159, now seen corresponding path program 15 times [2018-02-04 16:22:49,612 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:49,656 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:49,657 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:50,218 INFO L134 CoverageAnalysis]: Checked inductivity of 1062 backedges. 4 proven. 726 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:50,218 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:50,218 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-02-04 16:22:50,219 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:50,219 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:50,219 INFO L182 omatonBuilderFactory]: Interpolants [14464#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 14465#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 14466#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 14433#true, 14434#false, 14435#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 14436#(= |#Ultimate.meminit_#t~loopctr33| 0), 14437#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 14438#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14439#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14440#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14441#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14442#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14443#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14444#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14445#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14446#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14447#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14448#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14449#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14450#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14451#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14452#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14453#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14454#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 14455#(<= (+ (* 18 |#Ultimate.meminit_#t~loopctr33|) 19) (* 19 |#Ultimate.meminit_#product|)), 14456#(<= 19 |#Ultimate.meminit_#product|), 14457#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 19 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 14458#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 19 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 14459#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 19 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 14460#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 19 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 14461#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 14462#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 14463#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 16:22:50,219 INFO L134 CoverageAnalysis]: Checked inductivity of 1062 backedges. 4 proven. 726 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:50,219 INFO L409 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-02-04 16:22:50,219 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-02-04 16:22:50,219 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=1049, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 16:22:50,220 INFO L87 Difference]: Start difference. First operand 222 states and 251 transitions. Second operand 34 states. [2018-02-04 16:22:52,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:52,483 INFO L93 Difference]: Finished difference Result 289 states and 343 transitions. [2018-02-04 16:22:52,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-02-04 16:22:52,484 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 95 [2018-02-04 16:22:52,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:52,485 INFO L225 Difference]: With dead ends: 289 [2018-02-04 16:22:52,485 INFO L226 Difference]: Without dead ends: 289 [2018-02-04 16:22:52,485 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 325 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=239, Invalid=3301, Unknown=0, NotChecked=0, Total=3540 [2018-02-04 16:22:52,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2018-02-04 16:22:52,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 223. [2018-02-04 16:22:52,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 223 states. [2018-02-04 16:22:52,488 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 223 states to 223 states and 253 transitions. [2018-02-04 16:22:52,488 INFO L78 Accepts]: Start accepts. Automaton has 223 states and 253 transitions. Word has length 95 [2018-02-04 16:22:52,488 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:52,489 INFO L432 AbstractCegarLoop]: Abstraction has 223 states and 253 transitions. [2018-02-04 16:22:52,489 INFO L433 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-02-04 16:22:52,489 INFO L276 IsEmpty]: Start isEmpty. Operand 223 states and 253 transitions. [2018-02-04 16:22:52,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-02-04 16:22:52,489 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:52,489 INFO L351 BasicCegarLoop]: trace histogram [44, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:52,489 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:52,489 INFO L82 PathProgramCache]: Analyzing trace with hash 1069130919, now seen corresponding path program 16 times [2018-02-04 16:22:52,490 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:52,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:52,516 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:53,359 INFO L134 CoverageAnalysis]: Checked inductivity of 1108 backedges. 4 proven. 772 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:53,360 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:53,360 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-02-04 16:22:53,360 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:53,360 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:53,360 INFO L182 omatonBuilderFactory]: Interpolants [15040#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15041#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15042#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15043#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15044#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15045#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15046#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15047#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15048#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15049#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15050#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15051#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15052#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15053#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15054#(<= (+ (* 19 |#Ultimate.meminit_#t~loopctr33|) 20) (* 20 |#Ultimate.meminit_#product|)), 15055#(<= 20 |#Ultimate.meminit_#product|), 15056#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 20 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15057#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 20 (select |#length| |ldv_zalloc_#res.base|))), 15058#(and (<= 20 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 15059#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset) (<= 20 (select |#length| entry_point_~hdev~0.base))), 15060#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 15061#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15062#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15063#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15064#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 15065#(and (= entry_point_~hdev~0.offset 0) (<= 20 (select |#length| entry_point_~hdev~0.base))), 15031#true, 15032#false, 15033#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15034#(= |#Ultimate.meminit_#t~loopctr33| 0), 15035#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 15036#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15037#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15038#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15039#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:22:53,360 INFO L134 CoverageAnalysis]: Checked inductivity of 1108 backedges. 4 proven. 772 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:53,361 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-02-04 16:22:53,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-02-04 16:22:53,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=1115, Unknown=0, NotChecked=0, Total=1190 [2018-02-04 16:22:53,361 INFO L87 Difference]: Start difference. First operand 223 states and 253 transitions. Second operand 35 states. [2018-02-04 16:22:55,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:55,859 INFO L93 Difference]: Finished difference Result 292 states and 349 transitions. [2018-02-04 16:22:55,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-04 16:22:55,859 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 96 [2018-02-04 16:22:55,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:55,860 INFO L225 Difference]: With dead ends: 292 [2018-02-04 16:22:55,860 INFO L226 Difference]: Without dead ends: 292 [2018-02-04 16:22:55,861 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 351 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=247, Invalid=3535, Unknown=0, NotChecked=0, Total=3782 [2018-02-04 16:22:55,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 292 states. [2018-02-04 16:22:55,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 292 to 224. [2018-02-04 16:22:55,864 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-02-04 16:22:55,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 255 transitions. [2018-02-04 16:22:55,864 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 255 transitions. Word has length 96 [2018-02-04 16:22:55,864 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:55,864 INFO L432 AbstractCegarLoop]: Abstraction has 224 states and 255 transitions. [2018-02-04 16:22:55,865 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-02-04 16:22:55,865 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 255 transitions. [2018-02-04 16:22:55,865 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-02-04 16:22:55,865 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:55,865 INFO L351 BasicCegarLoop]: trace histogram [45, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:55,865 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:55,865 INFO L82 PathProgramCache]: Analyzing trace with hash -1830544113, now seen corresponding path program 17 times [2018-02-04 16:22:55,866 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:55,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:55,890 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:22:56,526 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 4 proven. 819 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:56,526 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:22:56,526 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-04 16:22:56,527 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:22:56,527 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:22:56,527 INFO L182 omatonBuilderFactory]: Interpolants [15636#true, 15637#false, 15638#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15639#(= |#Ultimate.meminit_#t~loopctr33| 0), 15640#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 15641#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15642#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15643#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15644#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15645#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15646#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15647#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15648#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15649#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15650#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15651#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15652#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15653#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15654#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15655#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15656#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15657#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15658#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15659#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 15660#(<= (+ (* 20 |#Ultimate.meminit_#t~loopctr33|) 21) (* 21 |#Ultimate.meminit_#product|)), 15661#(<= 21 |#Ultimate.meminit_#product|), 15662#(and (<= 21 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 15663#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 21 (select |#length| |ldv_zalloc_#res.base|))), 15664#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 21 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 15665#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 21 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 15666#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 15667#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15668#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 15669#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 15670#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 15671#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:22:56,527 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 4 proven. 819 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:22:56,527 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 16:22:56,528 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 16:22:56,528 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=1183, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 16:22:56,528 INFO L87 Difference]: Start difference. First operand 224 states and 255 transitions. Second operand 36 states. [2018-02-04 16:22:59,255 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:22:59,255 INFO L93 Difference]: Finished difference Result 295 states and 355 transitions. [2018-02-04 16:22:59,255 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-04 16:22:59,255 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 97 [2018-02-04 16:22:59,255 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:22:59,256 INFO L225 Difference]: With dead ends: 295 [2018-02-04 16:22:59,256 INFO L226 Difference]: Without dead ends: 295 [2018-02-04 16:22:59,257 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 66 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 378 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=255, Invalid=3777, Unknown=0, NotChecked=0, Total=4032 [2018-02-04 16:22:59,257 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 295 states. [2018-02-04 16:22:59,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 295 to 225. [2018-02-04 16:22:59,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-02-04 16:22:59,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 257 transitions. [2018-02-04 16:22:59,259 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 257 transitions. Word has length 97 [2018-02-04 16:22:59,259 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:22:59,259 INFO L432 AbstractCegarLoop]: Abstraction has 225 states and 257 transitions. [2018-02-04 16:22:59,260 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 16:22:59,260 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 257 transitions. [2018-02-04 16:22:59,260 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-02-04 16:22:59,260 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:22:59,260 INFO L351 BasicCegarLoop]: trace histogram [46, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:22:59,260 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:22:59,261 INFO L82 PathProgramCache]: Analyzing trace with hash -1526156889, now seen corresponding path program 18 times [2018-02-04 16:22:59,261 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:22:59,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:22:59,289 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:00,007 INFO L134 CoverageAnalysis]: Checked inductivity of 1203 backedges. 4 proven. 867 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:23:00,008 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:00,008 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-02-04 16:23:00,008 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:00,008 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:00,008 INFO L182 omatonBuilderFactory]: Interpolants [16256#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16257#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16258#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16259#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16260#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16261#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16262#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16263#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16264#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16265#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16266#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16267#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16268#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16269#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16270#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16271#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16272#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16273#(<= (+ (* 21 |#Ultimate.meminit_#t~loopctr33|) 22) (* 22 |#Ultimate.meminit_#product|)), 16274#(<= 22 |#Ultimate.meminit_#product|), 16275#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|) (<= 22 (select |#length| |ldv_zalloc_#t~malloc1.base|))), 16276#(and (<= 22 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 16277#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 22 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 16278#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 22 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 16279#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16280#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16281#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 16282#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16283#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16284#(and (= entry_point_~hdev~0.offset 0) (<= 22 (select |#length| entry_point_~hdev~0.base))), 16248#true, 16249#false, 16250#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 16251#(= |#Ultimate.meminit_#t~loopctr33| 0), 16252#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 16253#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16254#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16255#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:23:00,008 INFO L134 CoverageAnalysis]: Checked inductivity of 1203 backedges. 4 proven. 867 refuted. 0 times theorem prover too weak. 332 trivial. 0 not checked. [2018-02-04 16:23:00,009 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-02-04 16:23:00,009 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-02-04 16:23:00,009 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=1253, Unknown=0, NotChecked=0, Total=1332 [2018-02-04 16:23:00,009 INFO L87 Difference]: Start difference. First operand 225 states and 257 transitions. Second operand 37 states. [2018-02-04 16:23:03,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:03,211 INFO L93 Difference]: Finished difference Result 298 states and 361 transitions. [2018-02-04 16:23:03,211 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 16:23:03,211 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 98 [2018-02-04 16:23:03,212 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:03,212 INFO L225 Difference]: With dead ends: 298 [2018-02-04 16:23:03,212 INFO L226 Difference]: Without dead ends: 298 [2018-02-04 16:23:03,213 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 406 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=263, Invalid=4027, Unknown=0, NotChecked=0, Total=4290 [2018-02-04 16:23:03,213 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 298 states. [2018-02-04 16:23:03,216 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 298 to 226. [2018-02-04 16:23:03,216 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 226 states. [2018-02-04 16:23:03,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 226 states to 226 states and 259 transitions. [2018-02-04 16:23:03,217 INFO L78 Accepts]: Start accepts. Automaton has 226 states and 259 transitions. Word has length 98 [2018-02-04 16:23:03,217 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:03,217 INFO L432 AbstractCegarLoop]: Abstraction has 226 states and 259 transitions. [2018-02-04 16:23:03,217 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-02-04 16:23:03,217 INFO L276 IsEmpty]: Start isEmpty. Operand 226 states and 259 transitions. [2018-02-04 16:23:03,218 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-02-04 16:23:03,218 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:03,218 INFO L351 BasicCegarLoop]: trace histogram [47, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:03,218 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:03,218 INFO L82 PathProgramCache]: Analyzing trace with hash -680087537, now seen corresponding path program 19 times [2018-02-04 16:23:03,219 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:03,266 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:03,267 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:04,457 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 166 proven. 960 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-02-04 16:23:04,457 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:04,457 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51] total 51 [2018-02-04 16:23:04,458 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:04,458 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 10 proven. 25 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 16:23:04,458 INFO L182 omatonBuilderFactory]: Interpolants [16896#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 23 (select |#length| |ldv_zalloc_#res.base|))), 16897#(and (<= 23 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 16898#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 23 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 16899#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 16900#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16901#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 16902#(and (or (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (and (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296) ldv_zalloc_~size) (= 0 |ldv_zalloc_#t~malloc1.offset|))) (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16903#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)), 16904#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))), 16905#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))), 16906#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))), 16907#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|))), 16908#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|))), 16909#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))), 16910#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|))), 16911#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= (+ (* 10 |#Ultimate.meminit_#t~loopctr33|) 9) (+ (* 18 |#Ultimate.meminit_#sizeOfFields|) (* 9 |#Ultimate.meminit_#product|)))), 16912#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= (+ |#Ultimate.meminit_#product| 9) (* 18 |#Ultimate.meminit_#sizeOfFields|))), 16913#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 16914#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 16915#(and (= entry_point_~hdev~0.offset 0) (or (<= 14 (select |#length| entry_point_~hdev~0.base)) (and (= 0 |entry_point_#t~ret24.offset|) (<= (select |#length| |entry_point_#t~ret24.base|) 7)))), 16916#(and (= entry_point_~hdev~0.offset 0) (or (<= 14 (select |#length| entry_point_~hdev~0.base)) (and (= 0 (select (select |#memory_$Pointer$.offset| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4))) (<= (select |#length| (select (select |#memory_$Pointer$.base| entry_point_~intf~2.base) (+ entry_point_~intf~2.offset 4))) 7)))), 16917#(and (or (and (= |entry_point_#t~mem27.offset| 0) (<= (select |#length| |entry_point_#t~mem27.base|) 7)) (<= 14 (select |#length| entry_point_~hdev~0.base))) (= entry_point_~hdev~0.offset 0)), 16918#(and (<= 14 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 16867#true, 16868#false, 16869#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 16870#(= |#Ultimate.meminit_#t~loopctr33| 0), 16871#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 16872#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16873#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16874#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16875#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16876#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16877#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16878#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16879#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16880#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16881#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16882#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16883#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16884#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16885#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16886#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16887#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16888#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16889#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16890#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16891#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16892#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 16893#(<= (+ (* 22 |#Ultimate.meminit_#t~loopctr33|) 23) (* 23 |#Ultimate.meminit_#product|)), 16894#(<= 23 |#Ultimate.meminit_#product|), 16895#(and (<= 23 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|))] [2018-02-04 16:23:04,458 INFO L134 CoverageAnalysis]: Checked inductivity of 1252 backedges. 166 proven. 960 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-02-04 16:23:04,458 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-02-04 16:23:04,458 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-02-04 16:23:04,459 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=2499, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 16:23:04,459 INFO L87 Difference]: Start difference. First operand 226 states and 259 transitions. Second operand 52 states. [2018-02-04 16:23:08,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:08,541 INFO L93 Difference]: Finished difference Result 301 states and 367 transitions. [2018-02-04 16:23:08,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 16:23:08,542 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 99 [2018-02-04 16:23:08,542 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:08,543 INFO L225 Difference]: With dead ends: 301 [2018-02-04 16:23:08,543 INFO L226 Difference]: Without dead ends: 301 [2018-02-04 16:23:08,544 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 3 SyntacticMatches, 2 SemanticMatches, 81 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 578 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=411, Invalid=6395, Unknown=0, NotChecked=0, Total=6806 [2018-02-04 16:23:08,544 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 301 states. [2018-02-04 16:23:08,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 301 to 227. [2018-02-04 16:23:08,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-02-04 16:23:08,546 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 261 transitions. [2018-02-04 16:23:08,546 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 261 transitions. Word has length 99 [2018-02-04 16:23:08,546 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:08,547 INFO L432 AbstractCegarLoop]: Abstraction has 227 states and 261 transitions. [2018-02-04 16:23:08,547 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-02-04 16:23:08,547 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 261 transitions. [2018-02-04 16:23:08,547 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-02-04 16:23:08,547 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:08,547 INFO L351 BasicCegarLoop]: trace histogram [48, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:08,547 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:08,547 INFO L82 PathProgramCache]: Analyzing trace with hash -221741401, now seen corresponding path program 20 times [2018-02-04 16:23:08,548 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:08,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:08,577 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:08,913 INFO L134 CoverageAnalysis]: Checked inductivity of 1302 backedges. 0 proven. 964 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-04 16:23:08,913 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:08,913 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-04 16:23:08,913 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:08,913 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:08,914 INFO L182 omatonBuilderFactory]: Interpolants [17536#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17537#(<= (+ (* 23 |#Ultimate.meminit_#t~loopctr33|) 24) (* 24 |#Ultimate.meminit_#product|)), 17538#(<= 24 |#Ultimate.meminit_#product|), 17539#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 24 |ldv_zalloc_#in~size|)), 17509#true, 17510#false, 17511#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 17512#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 17513#(= |#Ultimate.meminit_#t~loopctr33| 0), 17514#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 17515#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17516#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17517#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17518#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17519#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17520#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17521#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17522#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17523#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17524#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17525#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17526#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17527#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17528#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17529#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17530#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17531#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17532#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17533#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17534#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 17535#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:23:08,914 INFO L134 CoverageAnalysis]: Checked inductivity of 1302 backedges. 0 proven. 964 refuted. 0 times theorem prover too weak. 338 trivial. 0 not checked. [2018-02-04 16:23:08,914 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 16:23:08,914 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 16:23:08,914 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=870, Unknown=0, NotChecked=0, Total=930 [2018-02-04 16:23:08,914 INFO L87 Difference]: Start difference. First operand 227 states and 261 transitions. Second operand 31 states. [2018-02-04 16:23:09,698 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:09,699 INFO L93 Difference]: Finished difference Result 259 states and 308 transitions. [2018-02-04 16:23:09,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-04 16:23:09,699 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 100 [2018-02-04 16:23:09,699 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:09,700 INFO L225 Difference]: With dead ends: 259 [2018-02-04 16:23:09,700 INFO L226 Difference]: Without dead ends: 248 [2018-02-04 16:23:09,700 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=69, Invalid=987, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 16:23:09,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 248 states. [2018-02-04 16:23:09,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 248 to 228. [2018-02-04 16:23:09,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-02-04 16:23:09,702 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 262 transitions. [2018-02-04 16:23:09,702 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 262 transitions. Word has length 100 [2018-02-04 16:23:09,702 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:09,703 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 262 transitions. [2018-02-04 16:23:09,703 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 16:23:09,703 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 262 transitions. [2018-02-04 16:23:09,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-02-04 16:23:09,703 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:09,703 INFO L351 BasicCegarLoop]: trace histogram [49, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:09,703 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:09,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1102086927, now seen corresponding path program 21 times [2018-02-04 16:23:09,704 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:09,730 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:09,731 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:10,062 INFO L134 CoverageAnalysis]: Checked inductivity of 1353 backedges. 423 proven. 287 refuted. 0 times theorem prover too weak. 643 trivial. 0 not checked. [2018-02-04 16:23:10,062 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:10,062 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-04 16:23:10,062 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:10,063 INFO L134 CoverageAnalysis]: Checked inductivity of 39 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:10,063 INFO L182 omatonBuilderFactory]: Interpolants [18048#(and (<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|)))), 18049#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 18050#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 15 |#Ultimate.meminit_#sizeOfFields|))) (<= (+ (* 14 |#Ultimate.meminit_#t~loopctr33|) 15) (* 15 |#Ultimate.meminit_#product|))), 18051#(and (<= 15 |#Ultimate.meminit_#product|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 15 |#Ultimate.meminit_#sizeOfFields|)))), 18052#(or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 15)), 18031#true, 18032#false, 18033#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 18034#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 18035#(= |#Ultimate.meminit_#t~loopctr33| 0), 18036#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 18037#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 18038#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 18039#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 18040#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 18041#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 18042#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 18043#(and (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)))), 18044#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 18045#(and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 18046#(and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 18047#(and (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:23:10,063 INFO L134 CoverageAnalysis]: Checked inductivity of 1353 backedges. 423 proven. 287 refuted. 0 times theorem prover too weak. 643 trivial. 0 not checked. [2018-02-04 16:23:10,063 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 16:23:10,063 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 16:23:10,063 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=42, Invalid=420, Unknown=0, NotChecked=0, Total=462 [2018-02-04 16:23:10,063 INFO L87 Difference]: Start difference. First operand 228 states and 262 transitions. Second operand 22 states. [2018-02-04 16:23:10,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:10,467 INFO L93 Difference]: Finished difference Result 239 states and 275 transitions. [2018-02-04 16:23:10,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 16:23:10,467 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 101 [2018-02-04 16:23:10,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:10,468 INFO L225 Difference]: With dead ends: 239 [2018-02-04 16:23:10,468 INFO L226 Difference]: Without dead ends: 236 [2018-02-04 16:23:10,468 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=51, Invalid=501, Unknown=0, NotChecked=0, Total=552 [2018-02-04 16:23:10,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-02-04 16:23:10,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 228. [2018-02-04 16:23:10,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-02-04 16:23:10,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 262 transitions. [2018-02-04 16:23:10,471 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 262 transitions. Word has length 101 [2018-02-04 16:23:10,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:10,471 INFO L432 AbstractCegarLoop]: Abstraction has 228 states and 262 transitions. [2018-02-04 16:23:10,472 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 16:23:10,472 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 262 transitions. [2018-02-04 16:23:10,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-02-04 16:23:10,472 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:10,472 INFO L351 BasicCegarLoop]: trace histogram [50, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:10,472 INFO L371 AbstractCegarLoop]: === Iteration 42 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:10,472 INFO L82 PathProgramCache]: Analyzing trace with hash -632936397, now seen corresponding path program 22 times [2018-02-04 16:23:10,473 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:10,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:10,514 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:11,217 INFO L134 CoverageAnalysis]: Checked inductivity of 1405 backedges. 4 proven. 1043 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:11,217 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:11,217 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39] total 39 [2018-02-04 16:23:11,217 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:11,217 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:11,217 INFO L182 omatonBuilderFactory]: Interpolants [18560#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 18561#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 18562#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 18563#(and (<= 25 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 18524#true, 18525#false, 18526#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 18527#(= |#Ultimate.meminit_#t~loopctr33| 0), 18528#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 18529#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18530#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18531#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18532#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18533#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18534#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18535#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18536#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18537#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18538#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18539#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18540#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18541#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18542#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18543#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18544#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18545#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18546#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18547#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18548#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18549#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18550#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18551#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 18552#(<= (+ (* 24 |#Ultimate.meminit_#t~loopctr33|) 25) (* 25 |#Ultimate.meminit_#product|)), 18553#(<= 25 |#Ultimate.meminit_#product|), 18554#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 25 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 18555#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 25 (select |#length| |ldv_zalloc_#res.base|))), 18556#(and (<= 25 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 18557#(and (<= 25 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 18558#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 18559#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|))))] [2018-02-04 16:23:11,218 INFO L134 CoverageAnalysis]: Checked inductivity of 1405 backedges. 4 proven. 1043 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:11,218 INFO L409 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-02-04 16:23:11,218 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-02-04 16:23:11,218 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=85, Invalid=1475, Unknown=0, NotChecked=0, Total=1560 [2018-02-04 16:23:11,218 INFO L87 Difference]: Start difference. First operand 228 states and 262 transitions. Second operand 40 states. [2018-02-04 16:23:14,310 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:14,310 INFO L93 Difference]: Finished difference Result 305 states and 373 transitions. [2018-02-04 16:23:14,310 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-02-04 16:23:14,310 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 102 [2018-02-04 16:23:14,311 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:14,312 INFO L225 Difference]: With dead ends: 305 [2018-02-04 16:23:14,312 INFO L226 Difference]: Without dead ends: 305 [2018-02-04 16:23:14,312 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 74 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 496 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=287, Invalid=4825, Unknown=0, NotChecked=0, Total=5112 [2018-02-04 16:23:14,313 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 305 states. [2018-02-04 16:23:14,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 305 to 229. [2018-02-04 16:23:14,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2018-02-04 16:23:14,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 264 transitions. [2018-02-04 16:23:14,317 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 264 transitions. Word has length 102 [2018-02-04 16:23:14,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:14,317 INFO L432 AbstractCegarLoop]: Abstraction has 229 states and 264 transitions. [2018-02-04 16:23:14,317 INFO L433 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-02-04 16:23:14,318 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 264 transitions. [2018-02-04 16:23:14,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 104 [2018-02-04 16:23:14,318 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:14,318 INFO L351 BasicCegarLoop]: trace histogram [51, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:14,318 INFO L371 AbstractCegarLoop]: === Iteration 43 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:14,319 INFO L82 PathProgramCache]: Analyzing trace with hash 255767195, now seen corresponding path program 23 times [2018-02-04 16:23:14,319 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:14,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:14,362 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:15,178 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 4 proven. 1096 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:15,178 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:15,178 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40] total 40 [2018-02-04 16:23:15,178 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:15,179 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:15,179 INFO L182 omatonBuilderFactory]: Interpolants [19200#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 19201#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 19202#(and (= entry_point_~hdev~0.offset 0) (<= 26 (select |#length| entry_point_~hdev~0.base))), 19162#true, 19163#false, 19164#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 19165#(= |#Ultimate.meminit_#t~loopctr33| 0), 19166#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 19167#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19168#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19169#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19170#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19171#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19172#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19173#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19174#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19175#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19176#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19177#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19178#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19179#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19180#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19181#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19182#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19183#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19184#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19185#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19186#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19187#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19188#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19189#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19190#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19191#(<= (+ (* 25 |#Ultimate.meminit_#t~loopctr33|) 26) (* 26 |#Ultimate.meminit_#product|)), 19192#(<= 26 |#Ultimate.meminit_#product|), 19193#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|) (<= 26 (select |#length| |ldv_zalloc_#t~malloc1.base|))), 19194#(and (<= 26 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 19195#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 26 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 19196#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 26 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 19197#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 19198#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 19199#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|)))))] [2018-02-04 16:23:15,179 INFO L134 CoverageAnalysis]: Checked inductivity of 1458 backedges. 4 proven. 1096 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:15,179 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-02-04 16:23:15,179 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-02-04 16:23:15,179 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=87, Invalid=1553, Unknown=0, NotChecked=0, Total=1640 [2018-02-04 16:23:15,179 INFO L87 Difference]: Start difference. First operand 229 states and 264 transitions. Second operand 41 states. [2018-02-04 16:23:18,289 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:18,290 INFO L93 Difference]: Finished difference Result 308 states and 379 transitions. [2018-02-04 16:23:18,290 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-02-04 16:23:18,290 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 103 [2018-02-04 16:23:18,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:18,291 INFO L225 Difference]: With dead ends: 308 [2018-02-04 16:23:18,291 INFO L226 Difference]: Without dead ends: 308 [2018-02-04 16:23:18,291 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 528 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=295, Invalid=5107, Unknown=0, NotChecked=0, Total=5402 [2018-02-04 16:23:18,292 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states. [2018-02-04 16:23:18,294 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 230. [2018-02-04 16:23:18,294 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-02-04 16:23:18,294 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 266 transitions. [2018-02-04 16:23:18,294 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 266 transitions. Word has length 103 [2018-02-04 16:23:18,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:18,294 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 266 transitions. [2018-02-04 16:23:18,294 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-02-04 16:23:18,294 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 266 transitions. [2018-02-04 16:23:18,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-02-04 16:23:18,295 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:18,295 INFO L351 BasicCegarLoop]: trace histogram [52, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:18,295 INFO L371 AbstractCegarLoop]: === Iteration 44 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:18,295 INFO L82 PathProgramCache]: Analyzing trace with hash 2035774771, now seen corresponding path program 24 times [2018-02-04 16:23:18,296 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:18,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:18,323 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:19,152 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 4 proven. 1150 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:19,152 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:19,152 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41] total 41 [2018-02-04 16:23:19,152 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:19,153 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:19,153 INFO L182 omatonBuilderFactory]: Interpolants [19840#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 27 (select |#length| |ldv_zalloc_#res.base|))), 19841#(and (<= 27 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 19842#(and (<= 27 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 19843#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 19844#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 19845#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 19846#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 19847#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 19848#(and (<= 27 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 19807#true, 19808#false, 19809#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 19810#(= |#Ultimate.meminit_#t~loopctr33| 0), 19811#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 19812#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19813#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19814#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19815#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19816#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19817#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19818#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19819#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19820#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19821#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19822#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19823#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19824#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19825#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19826#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19827#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19828#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19829#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19830#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19831#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19832#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19833#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19834#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19835#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19836#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 19837#(<= (+ (* 26 |#Ultimate.meminit_#t~loopctr33|) 27) (* 27 |#Ultimate.meminit_#product|)), 19838#(<= 27 |#Ultimate.meminit_#product|), 19839#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 27 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|))] [2018-02-04 16:23:19,153 INFO L134 CoverageAnalysis]: Checked inductivity of 1512 backedges. 4 proven. 1150 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:19,153 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-02-04 16:23:19,153 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-02-04 16:23:19,153 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=89, Invalid=1633, Unknown=0, NotChecked=0, Total=1722 [2018-02-04 16:23:19,154 INFO L87 Difference]: Start difference. First operand 230 states and 266 transitions. Second operand 42 states. [2018-02-04 16:23:22,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:22,742 INFO L93 Difference]: Finished difference Result 311 states and 385 transitions. [2018-02-04 16:23:22,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-02-04 16:23:22,743 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 104 [2018-02-04 16:23:22,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:22,744 INFO L225 Difference]: With dead ends: 311 [2018-02-04 16:23:22,744 INFO L226 Difference]: Without dead ends: 311 [2018-02-04 16:23:22,745 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 78 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 561 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=303, Invalid=5397, Unknown=0, NotChecked=0, Total=5700 [2018-02-04 16:23:22,745 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 311 states. [2018-02-04 16:23:22,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 311 to 231. [2018-02-04 16:23:22,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2018-02-04 16:23:22,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 268 transitions. [2018-02-04 16:23:22,750 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 268 transitions. Word has length 104 [2018-02-04 16:23:22,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:22,750 INFO L432 AbstractCegarLoop]: Abstraction has 231 states and 268 transitions. [2018-02-04 16:23:22,750 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-02-04 16:23:22,750 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 268 transitions. [2018-02-04 16:23:22,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 106 [2018-02-04 16:23:22,751 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:22,751 INFO L351 BasicCegarLoop]: trace histogram [53, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:22,751 INFO L371 AbstractCegarLoop]: === Iteration 45 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:22,751 INFO L82 PathProgramCache]: Analyzing trace with hash 1381434779, now seen corresponding path program 25 times [2018-02-04 16:23:22,752 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:22,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:22,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:23,669 INFO L134 CoverageAnalysis]: Checked inductivity of 1567 backedges. 4 proven. 1205 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:23,669 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:23,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42] total 42 [2018-02-04 16:23:23,669 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:23,669 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 27 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:23,669 INFO L182 omatonBuilderFactory]: Interpolants [20480#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20481#(or (<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20482#(or (<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20483#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20484#(or (<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20485#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20486#(or (<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20487#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20488#(or (<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20489#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20490#(or (<= (+ (* 27 |#Ultimate.meminit_#t~loopctr33|) 28) (* 28 |#Ultimate.meminit_#product|)) (< 27 |#Ultimate.meminit_#product|)), 20491#(< 27 |#Ultimate.meminit_#product|), 20492#(and (<= 28 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 20493#(and (<= 28 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 20494#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 28 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 20495#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset) (<= 28 (select |#length| entry_point_~hdev~0.base))), 20496#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 20497#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 20498#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 20499#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 20500#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 20501#(and (= entry_point_~hdev~0.offset 0) (<= 28 (select |#length| entry_point_~hdev~0.base))), 20459#true, 20460#false, 20461#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 20462#(= |#Ultimate.meminit_#t~loopctr33| 0), 20463#(or (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20464#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20465#(or (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20466#(or (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20467#(or (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20468#(or (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20469#(or (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20470#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20471#(or (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20472#(or (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20473#(or (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20474#(or (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (< 27 |#Ultimate.meminit_#product|)), 20475#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20476#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20477#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20478#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 20479#(or (< 27 |#Ultimate.meminit_#product|) (<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|))] [2018-02-04 16:23:23,669 INFO L134 CoverageAnalysis]: Checked inductivity of 1567 backedges. 4 proven. 1205 refuted. 0 times theorem prover too weak. 358 trivial. 0 not checked. [2018-02-04 16:23:23,669 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-02-04 16:23:23,670 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-02-04 16:23:23,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=119, Invalid=1687, Unknown=0, NotChecked=0, Total=1806 [2018-02-04 16:23:23,670 INFO L87 Difference]: Start difference. First operand 231 states and 268 transitions. Second operand 43 states. [2018-02-04 16:23:27,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:27,490 INFO L93 Difference]: Finished difference Result 314 states and 391 transitions. [2018-02-04 16:23:27,490 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-02-04 16:23:27,490 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 105 [2018-02-04 16:23:27,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:27,491 INFO L225 Difference]: With dead ends: 314 [2018-02-04 16:23:27,491 INFO L226 Difference]: Without dead ends: 314 [2018-02-04 16:23:27,492 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 614 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=393, Invalid=5613, Unknown=0, NotChecked=0, Total=6006 [2018-02-04 16:23:27,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 314 states. [2018-02-04 16:23:27,495 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 314 to 232. [2018-02-04 16:23:27,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-02-04 16:23:27,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 270 transitions. [2018-02-04 16:23:27,495 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 270 transitions. Word has length 105 [2018-02-04 16:23:27,495 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:27,495 INFO L432 AbstractCegarLoop]: Abstraction has 232 states and 270 transitions. [2018-02-04 16:23:27,495 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-02-04 16:23:27,496 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 270 transitions. [2018-02-04 16:23:27,496 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-02-04 16:23:27,496 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:27,496 INFO L351 BasicCegarLoop]: trace histogram [54, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:27,496 INFO L371 AbstractCegarLoop]: === Iteration 46 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:27,496 INFO L82 PathProgramCache]: Analyzing trace with hash -1723235789, now seen corresponding path program 26 times [2018-02-04 16:23:27,497 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:27,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:27,525 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:27,957 INFO L134 CoverageAnalysis]: Checked inductivity of 1623 backedges. 524 proven. 313 refuted. 0 times theorem prover too weak. 786 trivial. 0 not checked. [2018-02-04 16:23:27,957 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:27,957 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-02-04 16:23:27,957 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:27,957 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 17 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:27,957 INFO L182 omatonBuilderFactory]: Interpolants [21120#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 21121#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (= 0 |ldv_zalloc_#t~malloc1.offset|)))))), 21122#(= |#Ultimate.meminit_#t~loopctr33| 0), 21123#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)), 21124#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))), 21125#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))), 21126#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))), 21127#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|))), 21128#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|))), 21129#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))), 21130#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|))), 21131#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))), 21132#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|))), 21133#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|))), 21134#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|))), 21135#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|))), 21136#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|))), 21137#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 15 |#Ultimate.meminit_#sizeOfFields|))), 21138#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 16 |#Ultimate.meminit_#sizeOfFields|))), 21139#(or (<= |#Ultimate.meminit_#product| (* 16 |#Ultimate.meminit_#sizeOfFields|)) (not (= |#Ultimate.meminit_#sizeOfFields| 1))), 21140#(or (and (<= (select |#length| |ldv_zalloc_#t~malloc1.base|) 7) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)) (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 16)), 21141#(or (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= (select |#length| |ldv_zalloc_#res.base|) 7) (= 0 |ldv_zalloc_#res.offset|)) (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 16)), 21142#(and (= 0 |entry_point_#t~ret23.offset|) (<= (select |#length| |entry_point_#t~ret23.base|) 7) (= (select |#valid| |entry_point_#t~ret23.base|) 1)), 21143#(and (= (select |#valid| entry_point_~intf~2.base) 1) (<= (select |#length| entry_point_~intf~2.base) 7) (= entry_point_~intf~2.offset 0)), 21144#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 21145#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 21146#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 21147#(and (<= (select |#length| entry_point_~intf~2.base) 7) (= entry_point_~intf~2.offset 0)), 21118#true, 21119#false] [2018-02-04 16:23:27,958 INFO L134 CoverageAnalysis]: Checked inductivity of 1623 backedges. 524 proven. 313 refuted. 0 times theorem prover too weak. 786 trivial. 0 not checked. [2018-02-04 16:23:27,958 INFO L409 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-02-04 16:23:27,958 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-02-04 16:23:27,958 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=196, Invalid=674, Unknown=0, NotChecked=0, Total=870 [2018-02-04 16:23:27,958 INFO L87 Difference]: Start difference. First operand 232 states and 270 transitions. Second operand 30 states. [2018-02-04 16:23:29,724 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:29,724 INFO L93 Difference]: Finished difference Result 264 states and 310 transitions. [2018-02-04 16:23:29,724 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 16:23:29,724 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 106 [2018-02-04 16:23:29,724 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:29,725 INFO L225 Difference]: With dead ends: 264 [2018-02-04 16:23:29,725 INFO L226 Difference]: Without dead ends: 251 [2018-02-04 16:23:29,725 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 620 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=726, Invalid=2934, Unknown=0, NotChecked=0, Total=3660 [2018-02-04 16:23:29,726 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 251 states. [2018-02-04 16:23:29,728 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 251 to 230. [2018-02-04 16:23:29,728 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-02-04 16:23:29,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 267 transitions. [2018-02-04 16:23:29,728 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 267 transitions. Word has length 106 [2018-02-04 16:23:29,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:29,728 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 267 transitions. [2018-02-04 16:23:29,729 INFO L433 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-02-04 16:23:29,729 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 267 transitions. [2018-02-04 16:23:29,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-02-04 16:23:29,729 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:29,729 INFO L351 BasicCegarLoop]: trace histogram [55, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:29,729 INFO L371 AbstractCegarLoop]: === Iteration 47 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:29,729 INFO L82 PathProgramCache]: Analyzing trace with hash 1976372623, now seen corresponding path program 27 times [2018-02-04 16:23:29,730 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:29,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:29,772 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:30,082 INFO L134 CoverageAnalysis]: Checked inductivity of 1680 backedges. 547 proven. 340 refuted. 0 times theorem prover too weak. 793 trivial. 0 not checked. [2018-02-04 16:23:30,083 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:30,083 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24] total 24 [2018-02-04 16:23:30,083 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:30,083 INFO L134 CoverageAnalysis]: Checked inductivity of 41 backedges. 18 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:30,083 INFO L182 omatonBuilderFactory]: Interpolants [21728#(or (<= |ldv_zalloc_#in~size| 17) (<= 4294967296 |ldv_zalloc_#in~size|)), 21705#true, 21706#false, 21707#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 21708#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|))), 21709#(= |#Ultimate.meminit_#t~loopctr33| 0), 21710#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)) (<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|)), 21711#(and (<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|)))), 21712#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 21713#(and (<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|)))), 21714#(and (<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|)))), 21715#(and (<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|)))), 21716#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 21717#(and (<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|)))), 21718#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 21719#(and (<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|)))), 21720#(and (<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|)))), 21721#(and (<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|)))), 21722#(and (<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|)))), 21723#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 21724#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 15 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 21725#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 16 |#Ultimate.meminit_#sizeOfFields|))) (<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)), 21726#(and (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 17 |#Ultimate.meminit_#sizeOfFields|))) (<= (+ (* 16 |#Ultimate.meminit_#t~loopctr33|) 17) (* 17 |#Ultimate.meminit_#product|))), 21727#(and (<= 17 |#Ultimate.meminit_#product|) (or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 17 |#Ultimate.meminit_#sizeOfFields|))))] [2018-02-04 16:23:30,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1680 backedges. 547 proven. 340 refuted. 0 times theorem prover too weak. 793 trivial. 0 not checked. [2018-02-04 16:23:30,084 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 16:23:30,084 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 16:23:30,084 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=506, Unknown=0, NotChecked=0, Total=552 [2018-02-04 16:23:30,084 INFO L87 Difference]: Start difference. First operand 230 states and 267 transitions. Second operand 24 states. [2018-02-04 16:23:30,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:30,562 INFO L93 Difference]: Finished difference Result 243 states and 283 transitions. [2018-02-04 16:23:30,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 16:23:30,562 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 107 [2018-02-04 16:23:30,562 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:30,563 INFO L225 Difference]: With dead ends: 243 [2018-02-04 16:23:30,563 INFO L226 Difference]: Without dead ends: 240 [2018-02-04 16:23:30,563 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 26 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=55, Invalid=595, Unknown=0, NotChecked=0, Total=650 [2018-02-04 16:23:30,563 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-02-04 16:23:30,565 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 230. [2018-02-04 16:23:30,565 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-02-04 16:23:30,566 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 267 transitions. [2018-02-04 16:23:30,566 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 267 transitions. Word has length 107 [2018-02-04 16:23:30,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:30,566 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 267 transitions. [2018-02-04 16:23:30,566 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 16:23:30,566 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 267 transitions. [2018-02-04 16:23:30,567 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 109 [2018-02-04 16:23:30,567 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:30,567 INFO L351 BasicCegarLoop]: trace histogram [56, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:30,567 INFO L371 AbstractCegarLoop]: === Iteration 48 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:30,567 INFO L82 PathProgramCache]: Analyzing trace with hash 700116403, now seen corresponding path program 28 times [2018-02-04 16:23:30,568 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:30,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:30,601 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:31,067 INFO L134 CoverageAnalysis]: Checked inductivity of 1738 backedges. 0 proven. 1319 refuted. 0 times theorem prover too weak. 419 trivial. 0 not checked. [2018-02-04 16:23:31,067 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:31,068 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36] total 36 [2018-02-04 16:23:31,068 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:31,068 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:31,068 INFO L182 omatonBuilderFactory]: Interpolants [22208#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 22209#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 22210#(= |#Ultimate.meminit_#t~loopctr33| 0), 22211#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 22212#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22213#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22214#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22215#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22216#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22217#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22218#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22219#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22220#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22221#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22222#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22223#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22224#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22225#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22226#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22227#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22228#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22229#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22230#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22231#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22232#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22233#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22234#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22235#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22236#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22237#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22238#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22239#(<= (+ (* 28 |#Ultimate.meminit_#t~loopctr33|) 29) (* 29 |#Ultimate.meminit_#product|)), 22240#(<= 29 |#Ultimate.meminit_#product|), 22241#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 29 |ldv_zalloc_#in~size|)), 22206#true, 22207#false] [2018-02-04 16:23:31,068 INFO L134 CoverageAnalysis]: Checked inductivity of 1738 backedges. 0 proven. 1319 refuted. 0 times theorem prover too weak. 419 trivial. 0 not checked. [2018-02-04 16:23:31,068 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 16:23:31,069 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 16:23:31,069 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=1190, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 16:23:31,069 INFO L87 Difference]: Start difference. First operand 230 states and 267 transitions. Second operand 36 states. [2018-02-04 16:23:32,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:32,123 INFO L93 Difference]: Finished difference Result 270 states and 328 transitions. [2018-02-04 16:23:32,123 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-04 16:23:32,123 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 108 [2018-02-04 16:23:32,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:32,124 INFO L225 Difference]: With dead ends: 270 [2018-02-04 16:23:32,124 INFO L226 Difference]: Without dead ends: 259 [2018-02-04 16:23:32,124 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 33 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=79, Invalid=1327, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 16:23:32,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2018-02-04 16:23:32,126 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 231. [2018-02-04 16:23:32,126 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2018-02-04 16:23:32,127 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 268 transitions. [2018-02-04 16:23:32,127 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 268 transitions. Word has length 108 [2018-02-04 16:23:32,127 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:32,128 INFO L432 AbstractCegarLoop]: Abstraction has 231 states and 268 transitions. [2018-02-04 16:23:32,128 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 16:23:32,128 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 268 transitions. [2018-02-04 16:23:32,128 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 110 [2018-02-04 16:23:32,128 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:32,128 INFO L351 BasicCegarLoop]: trace histogram [57, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:32,129 INFO L371 AbstractCegarLoop]: === Iteration 49 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:32,129 INFO L82 PathProgramCache]: Analyzing trace with hash 1579944475, now seen corresponding path program 29 times [2018-02-04 16:23:32,129 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:32,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:32,173 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:33,047 INFO L134 CoverageAnalysis]: Checked inductivity of 1797 backedges. 4 proven. 1380 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2018-02-04 16:23:33,047 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:33,047 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44] total 44 [2018-02-04 16:23:33,048 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:33,048 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:33,048 INFO L182 omatonBuilderFactory]: Interpolants [22784#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 30 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 22785#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 30 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 22786#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 22787#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 22788#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 22789#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 22790#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 22791#(and (= entry_point_~hdev~0.offset 0) (<= 30 (select |#length| entry_point_~hdev~0.base))), 22747#true, 22748#false, 22749#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 22750#(= |#Ultimate.meminit_#t~loopctr33| 0), 22751#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 22752#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22753#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22754#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22755#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22756#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22757#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22758#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22759#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22760#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22761#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22762#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22763#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22764#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22765#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22766#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22767#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22768#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22769#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22770#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22771#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22772#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22773#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22774#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22775#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22776#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22777#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22778#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22779#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 22780#(<= (+ (* 29 |#Ultimate.meminit_#t~loopctr33|) 30) (* 30 |#Ultimate.meminit_#product|)), 22781#(<= 30 |#Ultimate.meminit_#product|), 22782#(and (<= 30 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 22783#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 30 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|))] [2018-02-04 16:23:33,048 INFO L134 CoverageAnalysis]: Checked inductivity of 1797 backedges. 4 proven. 1380 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2018-02-04 16:23:33,049 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-02-04 16:23:33,049 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-02-04 16:23:33,049 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=1885, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 16:23:33,049 INFO L87 Difference]: Start difference. First operand 231 states and 268 transitions. Second operand 45 states. [2018-02-04 16:23:37,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:37,020 INFO L93 Difference]: Finished difference Result 316 states and 394 transitions. [2018-02-04 16:23:37,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-02-04 16:23:37,020 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 109 [2018-02-04 16:23:37,020 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:37,021 INFO L225 Difference]: With dead ends: 316 [2018-02-04 16:23:37,021 INFO L226 Difference]: Without dead ends: 316 [2018-02-04 16:23:37,022 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 666 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=327, Invalid=6315, Unknown=0, NotChecked=0, Total=6642 [2018-02-04 16:23:37,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 316 states. [2018-02-04 16:23:37,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 316 to 232. [2018-02-04 16:23:37,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-02-04 16:23:37,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 270 transitions. [2018-02-04 16:23:37,025 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 270 transitions. Word has length 109 [2018-02-04 16:23:37,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:37,025 INFO L432 AbstractCegarLoop]: Abstraction has 232 states and 270 transitions. [2018-02-04 16:23:37,025 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-02-04 16:23:37,025 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 270 transitions. [2018-02-04 16:23:37,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-02-04 16:23:37,026 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:37,026 INFO L351 BasicCegarLoop]: trace histogram [58, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:37,026 INFO L371 AbstractCegarLoop]: === Iteration 50 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:37,026 INFO L82 PathProgramCache]: Analyzing trace with hash -1210156365, now seen corresponding path program 30 times [2018-02-04 16:23:37,027 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:37,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:37,060 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:37,902 INFO L134 CoverageAnalysis]: Checked inductivity of 1857 backedges. 4 proven. 1440 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2018-02-04 16:23:37,902 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:37,902 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45] total 45 [2018-02-04 16:23:37,903 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:37,903 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 29 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:37,903 INFO L182 omatonBuilderFactory]: Interpolants [23424#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23425#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23426#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23427#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23428#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23429#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23430#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23431#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23432#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23433#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23434#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23435#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23436#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23437#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23438#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23439#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23440#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23441#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23442#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23443#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23444#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23445#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23446#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23447#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23448#(<= (+ (* 30 |#Ultimate.meminit_#t~loopctr33|) 31) (* 31 |#Ultimate.meminit_#product|)), 23449#(<= 31 |#Ultimate.meminit_#product|), 23450#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 31 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 23451#(and (<= 31 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 23452#(and (<= 31 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 23453#(and (<= 31 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 23454#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 23455#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 23456#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 23457#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 23458#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 23459#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 23414#true, 23415#false, 23416#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 23417#(= |#Ultimate.meminit_#t~loopctr33| 0), 23418#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 23419#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23420#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23421#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23422#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 23423#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:23:37,903 INFO L134 CoverageAnalysis]: Checked inductivity of 1857 backedges. 4 proven. 1440 refuted. 0 times theorem prover too weak. 413 trivial. 0 not checked. [2018-02-04 16:23:37,903 INFO L409 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-02-04 16:23:37,904 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-02-04 16:23:37,904 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=1973, Unknown=0, NotChecked=0, Total=2070 [2018-02-04 16:23:37,904 INFO L87 Difference]: Start difference. First operand 232 states and 270 transitions. Second operand 46 states. [2018-02-04 16:23:41,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:41,928 INFO L93 Difference]: Finished difference Result 319 states and 400 transitions. [2018-02-04 16:23:41,928 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-02-04 16:23:41,928 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 110 [2018-02-04 16:23:41,928 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:41,929 INFO L225 Difference]: With dead ends: 319 [2018-02-04 16:23:41,929 INFO L226 Difference]: Without dead ends: 319 [2018-02-04 16:23:41,930 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 703 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=335, Invalid=6637, Unknown=0, NotChecked=0, Total=6972 [2018-02-04 16:23:41,930 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2018-02-04 16:23:41,932 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 233. [2018-02-04 16:23:41,932 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-02-04 16:23:41,933 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 272 transitions. [2018-02-04 16:23:41,933 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 272 transitions. Word has length 110 [2018-02-04 16:23:41,933 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:41,933 INFO L432 AbstractCegarLoop]: Abstraction has 233 states and 272 transitions. [2018-02-04 16:23:41,934 INFO L433 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-02-04 16:23:41,934 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 272 transitions. [2018-02-04 16:23:41,934 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 112 [2018-02-04 16:23:41,934 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:41,934 INFO L351 BasicCegarLoop]: trace histogram [59, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:41,935 INFO L371 AbstractCegarLoop]: === Iteration 51 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:41,935 INFO L82 PathProgramCache]: Analyzing trace with hash -1803936485, now seen corresponding path program 31 times [2018-02-04 16:23:41,935 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:41,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:41,972 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:42,247 INFO L134 CoverageAnalysis]: Checked inductivity of 1918 backedges. 634 proven. 368 refuted. 0 times theorem prover too weak. 916 trivial. 0 not checked. [2018-02-04 16:23:42,247 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:42,248 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25] total 25 [2018-02-04 16:23:42,248 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:42,248 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 19 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:42,248 INFO L182 omatonBuilderFactory]: Interpolants [24088#true, 24089#false, 24090#(and (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0)))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 24091#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483648) |ldv_zalloc_#in~size|) (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))) (< 0 (div ldv_zalloc_~size 4294967296)))), 24092#(= |#Ultimate.meminit_#t~loopctr33| 0), 24093#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)), 24094#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))), 24095#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))), 24096#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))), 24097#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|))), 24098#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|))), 24099#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))), 24100#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|))), 24101#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))), 24102#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|))), 24103#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|))), 24104#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|))), 24105#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|))), 24106#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|))), 24107#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 15 |#Ultimate.meminit_#sizeOfFields|))), 24108#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 16 |#Ultimate.meminit_#sizeOfFields|))), 24109#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 17 |#Ultimate.meminit_#sizeOfFields|))), 24110#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 18 |#Ultimate.meminit_#sizeOfFields|))), 24111#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 18 |#Ultimate.meminit_#sizeOfFields|))), 24112#(or (<= 2147483648 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| 18))] [2018-02-04 16:23:42,248 INFO L134 CoverageAnalysis]: Checked inductivity of 1918 backedges. 634 proven. 368 refuted. 0 times theorem prover too weak. 916 trivial. 0 not checked. [2018-02-04 16:23:42,248 INFO L409 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-02-04 16:23:42,249 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-02-04 16:23:42,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=219, Invalid=381, Unknown=0, NotChecked=0, Total=600 [2018-02-04 16:23:42,249 INFO L87 Difference]: Start difference. First operand 233 states and 272 transitions. Second operand 25 states. [2018-02-04 16:23:42,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:42,509 INFO L93 Difference]: Finished difference Result 248 states and 291 transitions. [2018-02-04 16:23:42,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 16:23:42,509 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 111 [2018-02-04 16:23:42,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:42,510 INFO L225 Difference]: With dead ends: 248 [2018-02-04 16:23:42,510 INFO L226 Difference]: Without dead ends: 245 [2018-02-04 16:23:42,510 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 34 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 93 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=322, Invalid=800, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 16:23:42,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-02-04 16:23:42,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 233. [2018-02-04 16:23:42,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-02-04 16:23:42,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 272 transitions. [2018-02-04 16:23:42,513 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 272 transitions. Word has length 111 [2018-02-04 16:23:42,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:42,513 INFO L432 AbstractCegarLoop]: Abstraction has 233 states and 272 transitions. [2018-02-04 16:23:42,513 INFO L433 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-02-04 16:23:42,513 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 272 transitions. [2018-02-04 16:23:42,513 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 113 [2018-02-04 16:23:42,513 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:42,513 INFO L351 BasicCegarLoop]: trace histogram [60, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:42,514 INFO L371 AbstractCegarLoop]: === Iteration 52 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:42,514 INFO L82 PathProgramCache]: Analyzing trace with hash -525348953, now seen corresponding path program 32 times [2018-02-04 16:23:42,514 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:42,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:42,578 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:43,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1980 backedges. 4 proven. 1534 refuted. 0 times theorem prover too weak. 442 trivial. 0 not checked. [2018-02-04 16:23:43,563 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:43,563 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46] total 46 [2018-02-04 16:23:43,563 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:43,563 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:43,563 INFO L182 omatonBuilderFactory]: Interpolants [24640#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24641#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24642#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24643#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24644#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24645#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24646#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24647#(<= (+ (* 31 |#Ultimate.meminit_#t~loopctr33|) 32) (* 32 |#Ultimate.meminit_#product|)), 24648#(<= 32 |#Ultimate.meminit_#product|), 24649#(and (<= 32 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 24650#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 32 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 24651#(and (<= 32 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 24652#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 32 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 24653#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 24654#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 24655#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 24656#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 24657#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 24658#(and (= entry_point_~hdev~0.offset 0) (<= 32 (select |#length| entry_point_~hdev~0.base))), 24612#true, 24613#false, 24614#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 24615#(= |#Ultimate.meminit_#t~loopctr33| 0), 24616#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 24617#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24618#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24619#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24620#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24621#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24622#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24623#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24624#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24625#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24626#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24627#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24628#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24629#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24630#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24631#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24632#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24633#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24634#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24635#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24636#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24637#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24638#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 24639#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:23:43,563 INFO L134 CoverageAnalysis]: Checked inductivity of 1980 backedges. 4 proven. 1534 refuted. 0 times theorem prover too weak. 442 trivial. 0 not checked. [2018-02-04 16:23:43,564 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-02-04 16:23:43,564 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-02-04 16:23:43,564 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=99, Invalid=2063, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 16:23:43,564 INFO L87 Difference]: Start difference. First operand 233 states and 272 transitions. Second operand 47 states. [2018-02-04 16:23:47,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:47,749 INFO L93 Difference]: Finished difference Result 322 states and 405 transitions. [2018-02-04 16:23:47,749 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-02-04 16:23:47,749 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 112 [2018-02-04 16:23:47,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:47,750 INFO L225 Difference]: With dead ends: 322 [2018-02-04 16:23:47,750 INFO L226 Difference]: Without dead ends: 322 [2018-02-04 16:23:47,750 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 741 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=343, Invalid=6967, Unknown=0, NotChecked=0, Total=7310 [2018-02-04 16:23:47,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 322 states. [2018-02-04 16:23:47,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 322 to 234. [2018-02-04 16:23:47,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-02-04 16:23:47,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 274 transitions. [2018-02-04 16:23:47,754 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 274 transitions. Word has length 112 [2018-02-04 16:23:47,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:47,754 INFO L432 AbstractCegarLoop]: Abstraction has 234 states and 274 transitions. [2018-02-04 16:23:47,754 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-02-04 16:23:47,754 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 274 transitions. [2018-02-04 16:23:47,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-02-04 16:23:47,755 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:47,755 INFO L351 BasicCegarLoop]: trace histogram [61, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:47,755 INFO L371 AbstractCegarLoop]: === Iteration 53 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:47,756 INFO L82 PathProgramCache]: Analyzing trace with hash 82606095, now seen corresponding path program 33 times [2018-02-04 16:23:47,756 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:47,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:47,797 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:48,304 INFO L134 CoverageAnalysis]: Checked inductivity of 2043 backedges. 694 proven. 397 refuted. 0 times theorem prover too weak. 952 trivial. 0 not checked. [2018-02-04 16:23:48,304 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:48,304 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33] total 33 [2018-02-04 16:23:48,304 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:48,304 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 20 proven. 10 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:48,304 INFO L182 omatonBuilderFactory]: Interpolants [25293#true, 25294#false, 25295#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 25296#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (or (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (= 0 |ldv_zalloc_#t~malloc1.offset|)))))), 25297#(= |#Ultimate.meminit_#t~loopctr33| 0), 25298#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| |#Ultimate.meminit_#sizeOfFields|)), 25299#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 2 |#Ultimate.meminit_#sizeOfFields|))), 25300#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 3 |#Ultimate.meminit_#sizeOfFields|))), 25301#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 4 |#Ultimate.meminit_#sizeOfFields|))), 25302#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 5 |#Ultimate.meminit_#sizeOfFields|))), 25303#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 6 |#Ultimate.meminit_#sizeOfFields|))), 25304#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 7 |#Ultimate.meminit_#sizeOfFields|))), 25305#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 8 |#Ultimate.meminit_#sizeOfFields|))), 25306#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 9 |#Ultimate.meminit_#sizeOfFields|))), 25307#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 10 |#Ultimate.meminit_#sizeOfFields|))), 25308#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 11 |#Ultimate.meminit_#sizeOfFields|))), 25309#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 12 |#Ultimate.meminit_#sizeOfFields|))), 25310#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 13 |#Ultimate.meminit_#sizeOfFields|))), 25311#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 14 |#Ultimate.meminit_#sizeOfFields|))), 25312#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 15 |#Ultimate.meminit_#sizeOfFields|))), 25313#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 16 |#Ultimate.meminit_#sizeOfFields|))), 25314#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 17 |#Ultimate.meminit_#sizeOfFields|))), 25315#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 18 |#Ultimate.meminit_#sizeOfFields|))), 25316#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#t~loopctr33| (* 19 |#Ultimate.meminit_#sizeOfFields|))), 25317#(or (not (= |#Ultimate.meminit_#sizeOfFields| 1)) (<= |#Ultimate.meminit_#product| (* 19 |#Ultimate.meminit_#sizeOfFields|))), 25318#(or (and (<= (select |#length| |ldv_zalloc_#t~malloc1.base|) 7) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)) (<= |ldv_zalloc_#in~size| 19) (<= 4294967296 |ldv_zalloc_#in~size|)), 25319#(or (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= (select |#length| |ldv_zalloc_#res.base|) 7) (= 0 |ldv_zalloc_#res.offset|)) (<= |ldv_zalloc_#in~size| 19) (<= 4294967296 |ldv_zalloc_#in~size|)), 25320#(and (= 0 |entry_point_#t~ret23.offset|) (<= (select |#length| |entry_point_#t~ret23.base|) 7) (= (select |#valid| |entry_point_#t~ret23.base|) 1)), 25321#(and (= (select |#valid| entry_point_~intf~2.base) 1) (<= (select |#length| entry_point_~intf~2.base) 7) (= entry_point_~intf~2.offset 0)), 25322#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 25323#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 25324#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 25325#(and (<= (select |#length| entry_point_~intf~2.base) 7) (= entry_point_~intf~2.offset 0))] [2018-02-04 16:23:48,305 INFO L134 CoverageAnalysis]: Checked inductivity of 2043 backedges. 694 proven. 397 refuted. 0 times theorem prover too weak. 952 trivial. 0 not checked. [2018-02-04 16:23:48,305 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 16:23:48,305 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 16:23:48,305 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=256, Invalid=800, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 16:23:48,305 INFO L87 Difference]: Start difference. First operand 234 states and 274 transitions. Second operand 33 states. [2018-02-04 16:23:50,336 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:50,336 INFO L93 Difference]: Finished difference Result 272 states and 324 transitions. [2018-02-04 16:23:50,336 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-02-04 16:23:50,336 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 113 [2018-02-04 16:23:50,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:50,337 INFO L225 Difference]: With dead ends: 272 [2018-02-04 16:23:50,337 INFO L226 Difference]: Without dead ends: 261 [2018-02-04 16:23:50,337 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 4 SyntacticMatches, 1 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 829 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=980, Invalid=3712, Unknown=0, NotChecked=0, Total=4692 [2018-02-04 16:23:50,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-02-04 16:23:50,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 234. [2018-02-04 16:23:50,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-02-04 16:23:50,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 274 transitions. [2018-02-04 16:23:50,339 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 274 transitions. Word has length 113 [2018-02-04 16:23:50,339 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:50,339 INFO L432 AbstractCegarLoop]: Abstraction has 234 states and 274 transitions. [2018-02-04 16:23:50,339 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 16:23:50,339 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 274 transitions. [2018-02-04 16:23:50,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-02-04 16:23:50,340 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:50,340 INFO L351 BasicCegarLoop]: trace histogram [62, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:50,340 INFO L371 AbstractCegarLoop]: === Iteration 54 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:50,340 INFO L82 PathProgramCache]: Analyzing trace with hash 2122896179, now seen corresponding path program 34 times [2018-02-04 16:23:50,341 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:50,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:50,375 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:51,293 INFO L134 CoverageAnalysis]: Checked inductivity of 2107 backedges. 4 proven. 1631 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:23:51,294 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:51,294 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47] total 47 [2018-02-04 16:23:51,294 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:51,294 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:51,294 INFO L182 omatonBuilderFactory]: Interpolants [25920#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25921#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25922#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25923#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25924#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25925#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25926#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25927#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25928#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25929#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25930#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25931#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25932#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25933#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25934#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25935#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25936#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25937#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25938#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25939#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25940#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25941#(<= (+ (* 32 |#Ultimate.meminit_#t~loopctr33|) 33) (* 33 |#Ultimate.meminit_#product|)), 25942#(<= 33 |#Ultimate.meminit_#product|), 25943#(and (<= 33 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 25944#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 33 (select |#length| |ldv_zalloc_#res.base|))), 25945#(and (<= 33 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 25946#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 33 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 25947#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 25948#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 25949#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 25950#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 25951#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 25952#(and (= entry_point_~hdev~0.offset 0) (<= 33 (select |#length| entry_point_~hdev~0.base))), 25905#true, 25906#false, 25907#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 25908#(= |#Ultimate.meminit_#t~loopctr33| 0), 25909#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 25910#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25911#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25912#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25913#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25914#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25915#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25916#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25917#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25918#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 25919#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:23:51,294 INFO L134 CoverageAnalysis]: Checked inductivity of 2107 backedges. 4 proven. 1631 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:23:51,294 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-02-04 16:23:51,294 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-02-04 16:23:51,295 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=2155, Unknown=0, NotChecked=0, Total=2256 [2018-02-04 16:23:51,295 INFO L87 Difference]: Start difference. First operand 234 states and 274 transitions. Second operand 48 states. [2018-02-04 16:23:55,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:23:55,703 INFO L93 Difference]: Finished difference Result 325 states and 410 transitions. [2018-02-04 16:23:55,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-02-04 16:23:55,703 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 114 [2018-02-04 16:23:55,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:23:55,704 INFO L225 Difference]: With dead ends: 325 [2018-02-04 16:23:55,704 INFO L226 Difference]: Without dead ends: 325 [2018-02-04 16:23:55,704 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 90 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 780 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=351, Invalid=7305, Unknown=0, NotChecked=0, Total=7656 [2018-02-04 16:23:55,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 325 states. [2018-02-04 16:23:55,706 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 325 to 235. [2018-02-04 16:23:55,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235 states. [2018-02-04 16:23:55,707 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 276 transitions. [2018-02-04 16:23:55,707 INFO L78 Accepts]: Start accepts. Automaton has 235 states and 276 transitions. Word has length 114 [2018-02-04 16:23:55,707 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:23:55,707 INFO L432 AbstractCegarLoop]: Abstraction has 235 states and 276 transitions. [2018-02-04 16:23:55,707 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-02-04 16:23:55,707 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 276 transitions. [2018-02-04 16:23:55,707 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 116 [2018-02-04 16:23:55,708 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:23:55,708 INFO L351 BasicCegarLoop]: trace histogram [63, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:23:55,708 INFO L371 AbstractCegarLoop]: === Iteration 55 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:23:55,708 INFO L82 PathProgramCache]: Analyzing trace with hash -2042822245, now seen corresponding path program 35 times [2018-02-04 16:23:55,708 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:23:55,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:23:55,742 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:23:56,798 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 4 proven. 1696 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:23:56,798 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:23:56,798 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50] total 50 [2018-02-04 16:23:56,799 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:23:56,799 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:23:56,799 INFO L182 omatonBuilderFactory]: Interpolants [26624#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26625#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26626#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26627#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26628#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26629#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26630#(<= (+ (* 33 |#Ultimate.meminit_#t~loopctr33|) 34) (* 34 |#Ultimate.meminit_#product|)), 26631#(<= 34 |#Ultimate.meminit_#product|), 26632#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 34 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 26633#(and (<= 34 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 26634#(and (<= 34 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 26635#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 34 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 26636#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 26637#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 26638#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (or (= |ldv_zalloc_#res.base| (@diff |old(#valid)| |#valid|)) (= |#valid| |old(#valid)|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 26639#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (= entry_point_~hdev~0.offset 0) (= (select |#valid| |entry_point_#t~ret23.base|) 1) (<= 34 (select |#length| entry_point_~hdev~0.base))), 26640#(and (= (select |#valid| entry_point_~intf~2.base) 1) (= (select |#valid| entry_point_~hdev~0.base) 1) (= entry_point_~hdev~0.offset 0) (<= 34 (select |#length| entry_point_~hdev~0.base))), 26641#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 26642#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 26643#(and (= entry_point_~hdev~0.offset 0) (<= 34 (select |#length| entry_point_~hdev~0.base))), 26593#true, 26594#false, 26595#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 26596#(= |#Ultimate.meminit_#t~loopctr33| 0), 26597#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 26598#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26599#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26600#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26601#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26602#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26603#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26604#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26605#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26606#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26607#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26608#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26609#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26610#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26611#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26612#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26613#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26614#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26615#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26616#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26617#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26618#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26619#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26620#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26621#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26622#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 26623#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:23:56,799 INFO L134 CoverageAnalysis]: Checked inductivity of 2172 backedges. 4 proven. 1696 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:23:56,799 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-02-04 16:23:56,799 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-02-04 16:23:56,800 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=109, Invalid=2441, Unknown=0, NotChecked=0, Total=2550 [2018-02-04 16:23:56,800 INFO L87 Difference]: Start difference. First operand 235 states and 276 transitions. Second operand 51 states. [2018-02-04 16:24:01,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:01,587 INFO L93 Difference]: Finished difference Result 332 states and 423 transitions. [2018-02-04 16:24:01,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-02-04 16:24:01,587 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 115 [2018-02-04 16:24:01,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:01,588 INFO L225 Difference]: With dead ends: 332 [2018-02-04 16:24:01,588 INFO L226 Difference]: Without dead ends: 332 [2018-02-04 16:24:01,588 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 947 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=334, Invalid=8222, Unknown=0, NotChecked=0, Total=8556 [2018-02-04 16:24:01,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 332 states. [2018-02-04 16:24:01,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 332 to 236. [2018-02-04 16:24:01,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-02-04 16:24:01,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 278 transitions. [2018-02-04 16:24:01,592 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 278 transitions. Word has length 115 [2018-02-04 16:24:01,592 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:01,592 INFO L432 AbstractCegarLoop]: Abstraction has 236 states and 278 transitions. [2018-02-04 16:24:01,592 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-02-04 16:24:01,592 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 278 transitions. [2018-02-04 16:24:01,593 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-02-04 16:24:01,593 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:01,593 INFO L351 BasicCegarLoop]: trace histogram [64, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:01,593 INFO L371 AbstractCegarLoop]: === Iteration 56 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:01,593 INFO L82 PathProgramCache]: Analyzing trace with hash 1963892787, now seen corresponding path program 36 times [2018-02-04 16:24:01,594 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:01,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:01,635 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:03,066 INFO L134 CoverageAnalysis]: Checked inductivity of 2238 backedges. 4 proven. 1762 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:03,066 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:03,067 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49] total 49 [2018-02-04 16:24:03,067 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:03,067 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:03,067 INFO L182 omatonBuilderFactory]: Interpolants [27296#true, 27297#false, 27298#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 27299#(= |#Ultimate.meminit_#t~loopctr33| 0), 27300#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 27301#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27302#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27303#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27304#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27305#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27306#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27307#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27308#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27309#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27310#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27311#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27312#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27313#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27314#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27315#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27316#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27317#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27318#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27319#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27320#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27321#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27322#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27323#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27324#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27325#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27326#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27327#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27328#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27329#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27330#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27331#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27332#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27333#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 27334#(<= (+ (* 34 |#Ultimate.meminit_#t~loopctr33|) 35) (* 35 |#Ultimate.meminit_#product|)), 27335#(<= 35 |#Ultimate.meminit_#product|), 27336#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 35 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 27337#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 35 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 27338#(and (<= 35 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 27339#(and (<= 35 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 27340#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 27341#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 27342#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 27343#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 27344#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 27345#(and (<= 35 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:24:03,067 INFO L134 CoverageAnalysis]: Checked inductivity of 2238 backedges. 4 proven. 1762 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:03,067 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-02-04 16:24:03,068 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-02-04 16:24:03,068 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=2345, Unknown=0, NotChecked=0, Total=2450 [2018-02-04 16:24:03,068 INFO L87 Difference]: Start difference. First operand 236 states and 278 transitions. Second operand 50 states. [2018-02-04 16:24:07,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:07,802 INFO L93 Difference]: Finished difference Result 331 states and 422 transitions. [2018-02-04 16:24:07,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-02-04 16:24:07,803 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 116 [2018-02-04 16:24:07,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:07,804 INFO L225 Difference]: With dead ends: 331 [2018-02-04 16:24:07,804 INFO L226 Difference]: Without dead ends: 331 [2018-02-04 16:24:07,804 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 861 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=367, Invalid=8005, Unknown=0, NotChecked=0, Total=8372 [2018-02-04 16:24:07,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 331 states. [2018-02-04 16:24:07,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 331 to 237. [2018-02-04 16:24:07,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-02-04 16:24:07,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 280 transitions. [2018-02-04 16:24:07,807 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 280 transitions. Word has length 116 [2018-02-04 16:24:07,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:07,807 INFO L432 AbstractCegarLoop]: Abstraction has 237 states and 280 transitions. [2018-02-04 16:24:07,807 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-02-04 16:24:07,807 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 280 transitions. [2018-02-04 16:24:07,807 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 118 [2018-02-04 16:24:07,807 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:07,807 INFO L351 BasicCegarLoop]: trace histogram [65, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:07,807 INFO L371 AbstractCegarLoop]: === Iteration 57 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:07,807 INFO L82 PathProgramCache]: Analyzing trace with hash 1618007195, now seen corresponding path program 37 times [2018-02-04 16:24:07,808 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:07,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:07,841 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:08,841 INFO L134 CoverageAnalysis]: Checked inductivity of 2305 backedges. 4 proven. 1829 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:08,841 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:08,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50] total 50 [2018-02-04 16:24:08,841 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:08,842 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:08,842 INFO L182 omatonBuilderFactory]: Interpolants [28032#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28033#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28034#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28035#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28036#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28037#(<= (+ (* 35 |#Ultimate.meminit_#t~loopctr33|) 36) (* 36 |#Ultimate.meminit_#product|)), 28038#(<= 36 |#Ultimate.meminit_#product|), 28039#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 36 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 28040#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 36 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 28041#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 36 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 28042#(and (<= 36 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 28043#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 28044#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 28045#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 28046#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 28047#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 28048#(and (<= 36 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 27998#true, 27999#false, 28000#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 28001#(= |#Ultimate.meminit_#t~loopctr33| 0), 28002#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 28003#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28004#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28005#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28006#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28007#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28008#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28009#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28010#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28011#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28012#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28013#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28014#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28015#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28016#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28017#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28018#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28019#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28020#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28021#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28022#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28023#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28024#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28025#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28026#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28027#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28028#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28029#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28030#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28031#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:24:08,842 INFO L134 CoverageAnalysis]: Checked inductivity of 2305 backedges. 4 proven. 1829 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:08,842 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-02-04 16:24:08,842 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-02-04 16:24:08,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=2443, Unknown=0, NotChecked=0, Total=2550 [2018-02-04 16:24:08,842 INFO L87 Difference]: Start difference. First operand 237 states and 280 transitions. Second operand 51 states. [2018-02-04 16:24:13,706 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:13,706 INFO L93 Difference]: Finished difference Result 334 states and 428 transitions. [2018-02-04 16:24:13,706 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-02-04 16:24:13,706 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 117 [2018-02-04 16:24:13,706 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:13,707 INFO L225 Difference]: With dead ends: 334 [2018-02-04 16:24:13,707 INFO L226 Difference]: Without dead ends: 334 [2018-02-04 16:24:13,707 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 903 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=375, Invalid=8367, Unknown=0, NotChecked=0, Total=8742 [2018-02-04 16:24:13,707 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 334 states. [2018-02-04 16:24:13,710 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 334 to 238. [2018-02-04 16:24:13,710 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 238 states. [2018-02-04 16:24:13,710 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238 states to 238 states and 282 transitions. [2018-02-04 16:24:13,710 INFO L78 Accepts]: Start accepts. Automaton has 238 states and 282 transitions. Word has length 117 [2018-02-04 16:24:13,710 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:13,710 INFO L432 AbstractCegarLoop]: Abstraction has 238 states and 282 transitions. [2018-02-04 16:24:13,710 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-02-04 16:24:13,710 INFO L276 IsEmpty]: Start isEmpty. Operand 238 states and 282 transitions. [2018-02-04 16:24:13,711 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 119 [2018-02-04 16:24:13,711 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:13,711 INFO L351 BasicCegarLoop]: trace histogram [66, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:13,711 INFO L371 AbstractCegarLoop]: === Iteration 58 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:13,711 INFO L82 PathProgramCache]: Analyzing trace with hash -514511565, now seen corresponding path program 38 times [2018-02-04 16:24:13,711 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:13,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:13,741 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:14,778 INFO L134 CoverageAnalysis]: Checked inductivity of 2373 backedges. 4 proven. 1897 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:14,778 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:14,779 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51] total 51 [2018-02-04 16:24:14,779 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:14,779 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:14,779 INFO L182 omatonBuilderFactory]: Interpolants [28707#true, 28708#false, 28709#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 28710#(= |#Ultimate.meminit_#t~loopctr33| 0), 28711#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 28712#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28713#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28714#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28715#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28716#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28717#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28718#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28719#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28720#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28721#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28722#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28723#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28724#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28725#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28726#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28727#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28728#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28729#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28730#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28731#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28732#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28733#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28734#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28735#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28736#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28737#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28738#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28739#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28740#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28741#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28742#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28743#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28744#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28745#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28746#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 28747#(<= (+ (* 36 |#Ultimate.meminit_#t~loopctr33|) 37) (* 37 |#Ultimate.meminit_#product|)), 28748#(<= 37 |#Ultimate.meminit_#product|), 28749#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 37 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 28750#(and (<= 37 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 28751#(and (<= 37 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 28752#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset) (<= 37 (select |#length| entry_point_~hdev~0.base))), 28753#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 28754#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 28755#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 28756#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 28757#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 28758#(and (= entry_point_~hdev~0.offset 0) (<= 37 (select |#length| entry_point_~hdev~0.base)))] [2018-02-04 16:24:14,779 INFO L134 CoverageAnalysis]: Checked inductivity of 2373 backedges. 4 proven. 1897 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:14,779 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-02-04 16:24:14,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-02-04 16:24:14,779 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=109, Invalid=2543, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 16:24:14,780 INFO L87 Difference]: Start difference. First operand 238 states and 282 transitions. Second operand 52 states. [2018-02-04 16:24:19,699 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:19,699 INFO L93 Difference]: Finished difference Result 337 states and 434 transitions. [2018-02-04 16:24:19,699 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-02-04 16:24:19,699 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 118 [2018-02-04 16:24:19,700 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:19,700 INFO L225 Difference]: With dead ends: 337 [2018-02-04 16:24:19,700 INFO L226 Difference]: Without dead ends: 337 [2018-02-04 16:24:19,701 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 946 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=383, Invalid=8737, Unknown=0, NotChecked=0, Total=9120 [2018-02-04 16:24:19,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states. [2018-02-04 16:24:19,703 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 239. [2018-02-04 16:24:19,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-02-04 16:24:19,704 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 284 transitions. [2018-02-04 16:24:19,704 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 284 transitions. Word has length 118 [2018-02-04 16:24:19,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:19,704 INFO L432 AbstractCegarLoop]: Abstraction has 239 states and 284 transitions. [2018-02-04 16:24:19,704 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-02-04 16:24:19,704 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 284 transitions. [2018-02-04 16:24:19,704 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-02-04 16:24:19,704 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:19,704 INFO L351 BasicCegarLoop]: trace histogram [67, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:19,704 INFO L371 AbstractCegarLoop]: === Iteration 59 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:19,705 INFO L82 PathProgramCache]: Analyzing trace with hash 2096883611, now seen corresponding path program 39 times [2018-02-04 16:24:19,705 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:19,743 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:19,743 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:20,883 INFO L134 CoverageAnalysis]: Checked inductivity of 2442 backedges. 4 proven. 1966 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:20,883 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:20,884 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52] total 52 [2018-02-04 16:24:20,884 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:20,884 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:20,884 INFO L182 omatonBuilderFactory]: Interpolants [29440#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29441#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29442#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29443#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29444#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29445#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29446#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29447#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29448#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29449#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29450#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29451#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29452#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29453#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29454#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29455#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29456#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29457#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29458#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29459#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29460#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29461#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29462#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29463#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29464#(<= (+ (* 37 |#Ultimate.meminit_#t~loopctr33|) 38) (* 38 |#Ultimate.meminit_#product|)), 29465#(<= 38 |#Ultimate.meminit_#product|), 29466#(and (<= 38 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 29467#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 38 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 29468#(and (<= 38 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 29469#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 38 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 29470#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 29471#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 29472#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= (select |#valid| (@diff |old(#valid)| |#valid|)) 1) (= |#valid| |old(#valid)|)) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 29473#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 29474#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 29475#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 29423#true, 29424#false, 29425#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 29426#(= |#Ultimate.meminit_#t~loopctr33| 0), 29427#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 29428#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29429#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29430#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29431#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29432#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29433#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29434#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29435#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29436#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29437#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29438#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 29439#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:24:20,884 INFO L134 CoverageAnalysis]: Checked inductivity of 2442 backedges. 4 proven. 1966 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:20,884 INFO L409 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-02-04 16:24:20,884 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-02-04 16:24:20,885 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=2645, Unknown=0, NotChecked=0, Total=2756 [2018-02-04 16:24:20,885 INFO L87 Difference]: Start difference. First operand 239 states and 284 transitions. Second operand 53 states. [2018-02-04 16:24:25,978 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:25,978 INFO L93 Difference]: Finished difference Result 340 states and 440 transitions. [2018-02-04 16:24:25,978 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-02-04 16:24:25,978 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 119 [2018-02-04 16:24:25,979 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:25,979 INFO L225 Difference]: With dead ends: 340 [2018-02-04 16:24:25,979 INFO L226 Difference]: Without dead ends: 340 [2018-02-04 16:24:25,980 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 990 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=391, Invalid=9115, Unknown=0, NotChecked=0, Total=9506 [2018-02-04 16:24:25,980 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 340 states. [2018-02-04 16:24:25,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 340 to 240. [2018-02-04 16:24:25,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. [2018-02-04 16:24:25,982 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 286 transitions. [2018-02-04 16:24:25,982 INFO L78 Accepts]: Start accepts. Automaton has 240 states and 286 transitions. Word has length 119 [2018-02-04 16:24:25,982 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:25,983 INFO L432 AbstractCegarLoop]: Abstraction has 240 states and 286 transitions. [2018-02-04 16:24:25,983 INFO L433 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-02-04 16:24:25,983 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 286 transitions. [2018-02-04 16:24:25,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 121 [2018-02-04 16:24:25,983 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:25,983 INFO L351 BasicCegarLoop]: trace histogram [68, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:25,983 INFO L371 AbstractCegarLoop]: === Iteration 60 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:25,983 INFO L82 PathProgramCache]: Analyzing trace with hash 1445755443, now seen corresponding path program 40 times [2018-02-04 16:24:25,984 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:26,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:26,026 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:27,089 INFO L134 CoverageAnalysis]: Checked inductivity of 2512 backedges. 4 proven. 2036 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:27,090 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:27,090 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53] total 53 [2018-02-04 16:24:27,090 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:27,090 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:27,090 INFO L182 omatonBuilderFactory]: Interpolants [30146#true, 30147#false, 30148#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 30149#(= |#Ultimate.meminit_#t~loopctr33| 0), 30150#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 30151#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30152#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30153#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30154#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30155#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30156#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30157#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30158#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30159#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30160#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30161#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30162#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30163#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30164#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30165#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30166#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30167#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30168#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30169#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30170#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30171#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30172#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30173#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30174#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30175#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30176#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30177#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30178#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30179#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30180#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30181#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30182#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30183#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30184#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30185#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30186#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30187#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30188#(<= (+ (* 38 |#Ultimate.meminit_#t~loopctr33|) 39) (* 39 |#Ultimate.meminit_#product|)), 30189#(<= 39 |#Ultimate.meminit_#product|), 30190#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 39 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 30191#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 39 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 30192#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 39 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 30193#(and (<= 39 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 30194#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 30195#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 30196#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 30197#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 30198#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 30199#(and (<= 39 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:24:27,090 INFO L134 CoverageAnalysis]: Checked inductivity of 2512 backedges. 4 proven. 2036 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:27,090 INFO L409 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-02-04 16:24:27,091 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-02-04 16:24:27,091 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=2749, Unknown=0, NotChecked=0, Total=2862 [2018-02-04 16:24:27,091 INFO L87 Difference]: Start difference. First operand 240 states and 286 transitions. Second operand 54 states. [2018-02-04 16:24:32,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:32,352 INFO L93 Difference]: Finished difference Result 343 states and 446 transitions. [2018-02-04 16:24:32,352 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-02-04 16:24:32,352 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 120 [2018-02-04 16:24:32,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:32,353 INFO L225 Difference]: With dead ends: 343 [2018-02-04 16:24:32,353 INFO L226 Difference]: Without dead ends: 343 [2018-02-04 16:24:32,353 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1035 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=399, Invalid=9501, Unknown=0, NotChecked=0, Total=9900 [2018-02-04 16:24:32,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 343 states. [2018-02-04 16:24:32,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 343 to 241. [2018-02-04 16:24:32,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 241 states. [2018-02-04 16:24:32,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 241 states to 241 states and 288 transitions. [2018-02-04 16:24:32,357 INFO L78 Accepts]: Start accepts. Automaton has 241 states and 288 transitions. Word has length 120 [2018-02-04 16:24:32,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:32,357 INFO L432 AbstractCegarLoop]: Abstraction has 241 states and 288 transitions. [2018-02-04 16:24:32,357 INFO L433 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-02-04 16:24:32,357 INFO L276 IsEmpty]: Start isEmpty. Operand 241 states and 288 transitions. [2018-02-04 16:24:32,357 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 122 [2018-02-04 16:24:32,357 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:32,357 INFO L351 BasicCegarLoop]: trace histogram [69, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:32,357 INFO L371 AbstractCegarLoop]: === Iteration 61 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:32,358 INFO L82 PathProgramCache]: Analyzing trace with hash -1559348581, now seen corresponding path program 41 times [2018-02-04 16:24:32,358 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:32,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:32,408 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:33,587 INFO L134 CoverageAnalysis]: Checked inductivity of 2583 backedges. 4 proven. 2107 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:33,587 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:33,587 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54] total 54 [2018-02-04 16:24:33,587 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:33,587 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:33,587 INFO L182 omatonBuilderFactory]: Interpolants [30876#true, 30877#false, 30878#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 30879#(= |#Ultimate.meminit_#t~loopctr33| 0), 30880#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 30881#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30882#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30883#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30884#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30885#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30886#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30887#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30888#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30889#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30890#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30891#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30892#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30893#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30894#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30895#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30896#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30897#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30898#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30899#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30900#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30901#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30902#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30903#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30904#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30905#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30906#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30907#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30908#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30909#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30910#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30911#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30912#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30913#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30914#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30915#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30916#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30917#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30918#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 30919#(<= (+ (* 39 |#Ultimate.meminit_#t~loopctr33|) 40) (* 40 |#Ultimate.meminit_#product|)), 30920#(<= 40 |#Ultimate.meminit_#product|), 30921#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|) (<= 40 (select |#length| |ldv_zalloc_#t~malloc1.base|))), 30922#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 40 (select |#length| |ldv_zalloc_#res.base|))), 30923#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 40 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 30924#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 40 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 30925#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 30926#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 30927#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 30928#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 30929#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 30930#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0))] [2018-02-04 16:24:33,588 INFO L134 CoverageAnalysis]: Checked inductivity of 2583 backedges. 4 proven. 2107 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:33,588 INFO L409 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-02-04 16:24:33,588 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-02-04 16:24:33,588 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=115, Invalid=2855, Unknown=0, NotChecked=0, Total=2970 [2018-02-04 16:24:33,588 INFO L87 Difference]: Start difference. First operand 241 states and 288 transitions. Second operand 55 states. [2018-02-04 16:24:38,956 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:38,957 INFO L93 Difference]: Finished difference Result 346 states and 452 transitions. [2018-02-04 16:24:38,957 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-02-04 16:24:38,957 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 121 [2018-02-04 16:24:38,957 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:38,958 INFO L225 Difference]: With dead ends: 346 [2018-02-04 16:24:38,958 INFO L226 Difference]: Without dead ends: 346 [2018-02-04 16:24:38,958 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1081 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=407, Invalid=9895, Unknown=0, NotChecked=0, Total=10302 [2018-02-04 16:24:38,958 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 346 states. [2018-02-04 16:24:38,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 346 to 242. [2018-02-04 16:24:38,961 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-02-04 16:24:38,961 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 290 transitions. [2018-02-04 16:24:38,961 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 290 transitions. Word has length 121 [2018-02-04 16:24:38,961 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:38,961 INFO L432 AbstractCegarLoop]: Abstraction has 242 states and 290 transitions. [2018-02-04 16:24:38,961 INFO L433 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-02-04 16:24:38,961 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 290 transitions. [2018-02-04 16:24:38,962 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-02-04 16:24:38,962 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:38,962 INFO L351 BasicCegarLoop]: trace histogram [70, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:38,962 INFO L371 AbstractCegarLoop]: === Iteration 62 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:38,962 INFO L82 PathProgramCache]: Analyzing trace with hash -228292813, now seen corresponding path program 42 times [2018-02-04 16:24:38,962 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:38,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:39,000 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:40,144 INFO L134 CoverageAnalysis]: Checked inductivity of 2655 backedges. 4 proven. 2179 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:40,144 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:40,144 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55] total 55 [2018-02-04 16:24:40,144 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:40,144 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:40,144 INFO L182 omatonBuilderFactory]: Interpolants [31616#(= |#Ultimate.meminit_#t~loopctr33| 0), 31617#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 31618#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31619#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31620#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31621#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31622#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31623#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31624#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31625#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31626#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31627#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31628#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31629#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31630#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31631#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31632#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31633#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31634#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31635#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31636#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31637#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31638#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31639#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31640#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31641#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31642#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31643#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31644#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31645#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31646#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31647#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31648#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31649#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31650#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31651#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31652#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31653#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31654#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31655#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31656#(<= (* 40 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 31657#(<= (+ (* 40 |#Ultimate.meminit_#t~loopctr33|) 41) (* 41 |#Ultimate.meminit_#product|)), 31658#(<= 41 |#Ultimate.meminit_#product|), 31659#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 41 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 31660#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|) (<= 41 (select |#length| |ldv_zalloc_#res.base|))), 31661#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|) (<= 41 (select |#length| |entry_point_#t~ret22.base|))), 31662#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 41 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 31663#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 31664#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 31665#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 31666#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 31667#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 31668#(and (= entry_point_~hdev~0.offset 0) (<= 41 (select |#length| entry_point_~hdev~0.base))), 31613#true, 31614#false, 31615#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|))] [2018-02-04 16:24:40,145 INFO L134 CoverageAnalysis]: Checked inductivity of 2655 backedges. 4 proven. 2179 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:40,145 INFO L409 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-02-04 16:24:40,145 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-02-04 16:24:40,145 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=2963, Unknown=0, NotChecked=0, Total=3080 [2018-02-04 16:24:40,145 INFO L87 Difference]: Start difference. First operand 242 states and 290 transitions. Second operand 56 states. [2018-02-04 16:24:45,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:45,712 INFO L93 Difference]: Finished difference Result 349 states and 458 transitions. [2018-02-04 16:24:45,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-02-04 16:24:45,713 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 122 [2018-02-04 16:24:45,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:45,713 INFO L225 Difference]: With dead ends: 349 [2018-02-04 16:24:45,714 INFO L226 Difference]: Without dead ends: 349 [2018-02-04 16:24:45,714 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1128 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=415, Invalid=10297, Unknown=0, NotChecked=0, Total=10712 [2018-02-04 16:24:45,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states. [2018-02-04 16:24:45,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 243. [2018-02-04 16:24:45,716 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-02-04 16:24:45,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 292 transitions. [2018-02-04 16:24:45,717 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 292 transitions. Word has length 122 [2018-02-04 16:24:45,717 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:45,717 INFO L432 AbstractCegarLoop]: Abstraction has 243 states and 292 transitions. [2018-02-04 16:24:45,717 INFO L433 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-02-04 16:24:45,717 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 292 transitions. [2018-02-04 16:24:45,717 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-02-04 16:24:45,717 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:45,718 INFO L351 BasicCegarLoop]: trace histogram [71, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:45,718 INFO L371 AbstractCegarLoop]: === Iteration 63 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:45,718 INFO L82 PathProgramCache]: Analyzing trace with hash -1915236965, now seen corresponding path program 43 times [2018-02-04 16:24:45,718 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:45,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:45,780 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:47,126 INFO L134 CoverageAnalysis]: Checked inductivity of 2728 backedges. 2 proven. 2254 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:47,127 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:47,127 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57] total 57 [2018-02-04 16:24:47,127 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:47,127 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:47,127 INFO L182 omatonBuilderFactory]: Interpolants [32384#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32385#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32386#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32387#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32388#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32389#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32390#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32391#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32392#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32393#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32394#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32395#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32396#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32397#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32398#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32399#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32400#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32401#(<= (* 40 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32402#(<= (* 41 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32403#(<= (+ (* 41 |#Ultimate.meminit_#t~loopctr33|) 42) (* 42 |#Ultimate.meminit_#product|)), 32404#(<= 42 |#Ultimate.meminit_#product|), 32405#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (or (<= 4294967296 |ldv_zalloc_#in~size|) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#t~malloc1.base|))) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 32406#(and (or (<= 4294967296 |ldv_zalloc_#in~size|) (and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= |ldv_zalloc_#in~size| (select |#length| |ldv_zalloc_#res.base|)))) (= 0 |ldv_zalloc_#res.offset|)), 32407#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 12 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 32408#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset)), 32409#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 32410#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 32411#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 32412#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 32413#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 32414#(and (<= 12 (select |#length| entry_point_~hdev~0.base)) (= entry_point_~hdev~0.offset 0)), 32357#true, 32358#false, 32359#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (div ldv_zalloc_~size 4294967296))) (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= ldv_zalloc_~size |ldv_zalloc_#in~size|))), 32360#(and (or (<= (div ldv_zalloc_~size 4294967296) 0) (<= (* 4294967296 (div ldv_zalloc_~size 4294967296)) |ldv_zalloc_#in~size|)) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|) (or (< 0 (div ldv_zalloc_~size 4294967296)) (and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (<= |ldv_zalloc_#in~size| ldv_zalloc_~size)))), 32361#(= |#Ultimate.meminit_#t~loopctr33| 0), 32362#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 32363#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32364#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32365#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32366#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32367#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32368#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32369#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32370#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32371#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32372#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32373#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32374#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32375#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32376#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32377#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32378#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32379#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32380#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32381#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32382#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 32383#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:24:47,127 INFO L134 CoverageAnalysis]: Checked inductivity of 2728 backedges. 2 proven. 2254 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:47,128 INFO L409 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-02-04 16:24:47,128 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-02-04 16:24:47,128 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=121, Invalid=3185, Unknown=0, NotChecked=0, Total=3306 [2018-02-04 16:24:47,128 INFO L87 Difference]: Start difference. First operand 243 states and 292 transitions. Second operand 58 states. [2018-02-04 16:24:53,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:53,400 INFO L93 Difference]: Finished difference Result 352 states and 464 transitions. [2018-02-04 16:24:53,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-02-04 16:24:53,400 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 123 [2018-02-04 16:24:53,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:53,401 INFO L225 Difference]: With dead ends: 352 [2018-02-04 16:24:53,401 INFO L226 Difference]: Without dead ends: 352 [2018-02-04 16:24:53,402 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1225 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=434, Invalid=11122, Unknown=0, NotChecked=0, Total=11556 [2018-02-04 16:24:53,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 352 states. [2018-02-04 16:24:53,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 352 to 244. [2018-02-04 16:24:53,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 244 states. [2018-02-04 16:24:53,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 244 states to 244 states and 294 transitions. [2018-02-04 16:24:53,406 INFO L78 Accepts]: Start accepts. Automaton has 244 states and 294 transitions. Word has length 123 [2018-02-04 16:24:53,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:53,406 INFO L432 AbstractCegarLoop]: Abstraction has 244 states and 294 transitions. [2018-02-04 16:24:53,407 INFO L433 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-02-04 16:24:53,407 INFO L276 IsEmpty]: Start isEmpty. Operand 244 states and 294 transitions. [2018-02-04 16:24:53,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-02-04 16:24:53,407 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:53,407 INFO L351 BasicCegarLoop]: trace histogram [72, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:53,407 INFO L371 AbstractCegarLoop]: === Iteration 64 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:53,407 INFO L82 PathProgramCache]: Analyzing trace with hash 1624069171, now seen corresponding path program 44 times [2018-02-04 16:24:53,408 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:53,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:53,454 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:54,232 INFO L134 CoverageAnalysis]: Checked inductivity of 2802 backedges. 0 proven. 2324 refuted. 0 times theorem prover too weak. 478 trivial. 0 not checked. [2018-02-04 16:24:54,232 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:54,232 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50] total 50 [2018-02-04 16:24:54,232 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:54,233 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:54,233 INFO L182 omatonBuilderFactory]: Interpolants [33152#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33153#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33154#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33155#(<= (* 40 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33156#(<= (* 41 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33157#(<= (* 42 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33158#(<= (+ (* 42 |#Ultimate.meminit_#t~loopctr33|) 43) (* 43 |#Ultimate.meminit_#product|)), 33159#(<= 43 |#Ultimate.meminit_#product|), 33160#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 43 |ldv_zalloc_#in~size|)), 33111#true, 33112#false, 33113#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 33114#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 33115#(= |#Ultimate.meminit_#t~loopctr33| 0), 33116#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 33117#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33118#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33119#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33120#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33121#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33122#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33123#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33124#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33125#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33126#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33127#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33128#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33129#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33130#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33131#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33132#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33133#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33134#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33135#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33136#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33137#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33138#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33139#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33140#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33141#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33142#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33143#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33144#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33145#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33146#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33147#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33148#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33149#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33150#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33151#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|)] [2018-02-04 16:24:54,233 INFO L134 CoverageAnalysis]: Checked inductivity of 2802 backedges. 0 proven. 2324 refuted. 0 times theorem prover too weak. 478 trivial. 0 not checked. [2018-02-04 16:24:54,233 INFO L409 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-02-04 16:24:54,233 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-02-04 16:24:54,234 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=2352, Unknown=0, NotChecked=0, Total=2450 [2018-02-04 16:24:54,234 INFO L87 Difference]: Start difference. First operand 244 states and 294 transitions. Second operand 50 states. [2018-02-04 16:24:56,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:24:56,360 INFO L93 Difference]: Finished difference Result 310 states and 405 transitions. [2018-02-04 16:24:56,360 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-02-04 16:24:56,360 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 124 [2018-02-04 16:24:56,360 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:24:56,361 INFO L225 Difference]: With dead ends: 310 [2018-02-04 16:24:56,361 INFO L226 Difference]: Without dead ends: 299 [2018-02-04 16:24:56,361 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=107, Invalid=2545, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 16:24:56,361 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states. [2018-02-04 16:24:56,364 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 245. [2018-02-04 16:24:56,364 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-02-04 16:24:56,364 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 295 transitions. [2018-02-04 16:24:56,364 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 295 transitions. Word has length 124 [2018-02-04 16:24:56,364 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:24:56,364 INFO L432 AbstractCegarLoop]: Abstraction has 245 states and 295 transitions. [2018-02-04 16:24:56,364 INFO L433 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-02-04 16:24:56,364 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 295 transitions. [2018-02-04 16:24:56,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-02-04 16:24:56,365 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:24:56,365 INFO L351 BasicCegarLoop]: trace histogram [73, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:24:56,365 INFO L371 AbstractCegarLoop]: === Iteration 65 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:24:56,365 INFO L82 PathProgramCache]: Analyzing trace with hash -326590309, now seen corresponding path program 45 times [2018-02-04 16:24:56,365 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:24:56,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:24:56,411 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:24:57,681 INFO L134 CoverageAnalysis]: Checked inductivity of 2877 backedges. 4 proven. 2401 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:57,681 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:24:57,681 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58] total 58 [2018-02-04 16:24:57,681 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:24:57,681 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:24:57,681 INFO L182 omatonBuilderFactory]: Interpolants [33720#true, 33721#false, 33722#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 33723#(= |#Ultimate.meminit_#t~loopctr33| 0), 33724#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 33725#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33726#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33727#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33728#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33729#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33730#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33731#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33732#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33733#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33734#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33735#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33736#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33737#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33738#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33739#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33740#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33741#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33742#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33743#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33744#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33745#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33746#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33747#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33748#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33749#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33750#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33751#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33752#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33753#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33754#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33755#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33756#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33757#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33758#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33759#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33760#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33761#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33762#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33763#(<= (* 40 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33764#(<= (* 41 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33765#(<= (* 42 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33766#(<= (* 43 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 33767#(<= (+ (* 43 |#Ultimate.meminit_#t~loopctr33|) 44) (* 44 |#Ultimate.meminit_#product|)), 33768#(<= 44 |#Ultimate.meminit_#product|), 33769#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 44 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 33770#(and (= (select |#valid| |ldv_zalloc_#res.base|) 1) (<= 44 (select |#length| |ldv_zalloc_#res.base|)) (= 0 |ldv_zalloc_#res.offset|)), 33771#(and (<= 44 (select |#length| |entry_point_#t~ret22.base|)) (= (select |#valid| |entry_point_#t~ret22.base|) 1) (= 0 |entry_point_#t~ret22.offset|)), 33772#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (= 0 entry_point_~hdev~0.offset) (<= 44 (select |#length| entry_point_~hdev~0.base))), 33773#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 33774#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 33775#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 33776#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 33777#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 33778#(and (= entry_point_~hdev~0.offset 0) (<= 44 (select |#length| entry_point_~hdev~0.base)))] [2018-02-04 16:24:57,682 INFO L134 CoverageAnalysis]: Checked inductivity of 2877 backedges. 4 proven. 2401 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:24:57,682 INFO L409 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-02-04 16:24:57,682 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-02-04 16:24:57,682 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=123, Invalid=3299, Unknown=0, NotChecked=0, Total=3422 [2018-02-04 16:24:57,682 INFO L87 Difference]: Start difference. First operand 245 states and 295 transitions. Second operand 59 states. [2018-02-04 16:25:04,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:25:04,153 INFO L93 Difference]: Finished difference Result 356 states and 471 transitions. [2018-02-04 16:25:04,153 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-02-04 16:25:04,153 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 125 [2018-02-04 16:25:04,153 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:25:04,154 INFO L225 Difference]: With dead ends: 356 [2018-02-04 16:25:04,154 INFO L226 Difference]: Without dead ends: 356 [2018-02-04 16:25:04,155 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1275 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=439, Invalid=11551, Unknown=0, NotChecked=0, Total=11990 [2018-02-04 16:25:04,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 356 states. [2018-02-04 16:25:04,157 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 356 to 246. [2018-02-04 16:25:04,157 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2018-02-04 16:25:04,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 297 transitions. [2018-02-04 16:25:04,158 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 297 transitions. Word has length 125 [2018-02-04 16:25:04,158 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:25:04,158 INFO L432 AbstractCegarLoop]: Abstraction has 246 states and 297 transitions. [2018-02-04 16:25:04,158 INFO L433 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-02-04 16:25:04,158 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 297 transitions. [2018-02-04 16:25:04,158 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-02-04 16:25:04,158 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:25:04,158 INFO L351 BasicCegarLoop]: trace histogram [74, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:25:04,158 INFO L371 AbstractCegarLoop]: === Iteration 66 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:25:04,158 INFO L82 PathProgramCache]: Analyzing trace with hash -667492045, now seen corresponding path program 46 times [2018-02-04 16:25:04,159 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:25:04,205 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:25:04,206 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:25:05,071 INFO L134 CoverageAnalysis]: Checked inductivity of 2953 backedges. 0 proven. 2475 refuted. 0 times theorem prover too weak. 478 trivial. 0 not checked. [2018-02-04 16:25:05,071 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:25:05,071 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52] total 52 [2018-02-04 16:25:05,071 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:25:05,071 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:25:05,071 INFO L182 omatonBuilderFactory]: Interpolants [34483#true, 34484#false, 34485#(and (or (<= |ldv_zalloc_#in~size| ldv_zalloc_~size) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 34486#(and (or (<= |ldv_zalloc_#in~size| (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 4294967295)) (< 0 (+ (div ldv_zalloc_~size 4294967296) 1))) (or (<= ldv_zalloc_~size |ldv_zalloc_#in~size|) (<= (+ (div ldv_zalloc_~size 4294967296) 1) 0))), 34487#(= |#Ultimate.meminit_#t~loopctr33| 0), 34488#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 34489#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34490#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34491#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34492#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34493#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34494#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34495#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34496#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34497#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34498#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34499#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34500#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34501#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34502#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34503#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34504#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34505#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34506#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34507#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34508#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34509#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34510#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34511#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34512#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34513#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34514#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34515#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34516#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34517#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34518#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34519#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34520#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34521#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34522#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34523#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34524#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34525#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34526#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34527#(<= (* 40 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34528#(<= (* 41 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34529#(<= (* 42 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34530#(<= (* 43 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34531#(<= (* 44 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 34532#(<= (+ (* 44 |#Ultimate.meminit_#t~loopctr33|) 45) (* 45 |#Ultimate.meminit_#product|)), 34533#(<= 45 |#Ultimate.meminit_#product|), 34534#(or (<= (+ |ldv_zalloc_#in~size| 1) 0) (<= 45 |ldv_zalloc_#in~size|))] [2018-02-04 16:25:05,072 INFO L134 CoverageAnalysis]: Checked inductivity of 2953 backedges. 0 proven. 2475 refuted. 0 times theorem prover too weak. 478 trivial. 0 not checked. [2018-02-04 16:25:05,072 INFO L409 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-02-04 16:25:05,072 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-02-04 16:25:05,072 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=2550, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 16:25:05,072 INFO L87 Difference]: Start difference. First operand 246 states and 297 transitions. Second operand 52 states. [2018-02-04 16:25:07,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 16:25:07,384 INFO L93 Difference]: Finished difference Result 314 states and 412 transitions. [2018-02-04 16:25:07,384 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-02-04 16:25:07,385 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 126 [2018-02-04 16:25:07,385 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 16:25:07,385 INFO L225 Difference]: With dead ends: 314 [2018-02-04 16:25:07,385 INFO L226 Difference]: Without dead ends: 303 [2018-02-04 16:25:07,386 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 49 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=111, Invalid=2751, Unknown=0, NotChecked=0, Total=2862 [2018-02-04 16:25:07,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 303 states. [2018-02-04 16:25:07,388 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 303 to 247. [2018-02-04 16:25:07,388 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-02-04 16:25:07,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 298 transitions. [2018-02-04 16:25:07,389 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 298 transitions. Word has length 126 [2018-02-04 16:25:07,389 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 16:25:07,389 INFO L432 AbstractCegarLoop]: Abstraction has 247 states and 298 transitions. [2018-02-04 16:25:07,389 INFO L433 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-02-04 16:25:07,389 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 298 transitions. [2018-02-04 16:25:07,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-02-04 16:25:07,389 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 16:25:07,389 INFO L351 BasicCegarLoop]: trace histogram [75, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 16:25:07,389 INFO L371 AbstractCegarLoop]: === Iteration 67 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 16:25:07,389 INFO L82 PathProgramCache]: Analyzing trace with hash 1649456027, now seen corresponding path program 47 times [2018-02-04 16:25:07,390 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 16:25:07,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 16:25:07,433 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 16:25:08,764 INFO L134 CoverageAnalysis]: Checked inductivity of 3030 backedges. 4 proven. 2554 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:25:08,764 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 16:25:08,764 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60] total 60 [2018-02-04 16:25:08,765 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 16:25:08,765 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 0 proven. 31 refuted. 0 times theorem prover too weak. 13 trivial. 0 not checked. [2018-02-04 16:25:08,765 INFO L182 omatonBuilderFactory]: Interpolants [35100#true, 35101#false, 35102#(and (or (and (<= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647)) (= (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|)) ldv_zalloc_~size)) (and (= ldv_zalloc_~size (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) (select |#length| |ldv_zalloc_#t~malloc1.base|) 4294967296)) (< (+ (* 4294967296 (div ldv_zalloc_~size 4294967296)) 2147483647) ldv_zalloc_~size))) (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 35103#(= |#Ultimate.meminit_#t~loopctr33| 0), 35104#(<= |#Ultimate.meminit_#sizeOfFields| |#Ultimate.meminit_#t~loopctr33|), 35105#(<= (* 2 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35106#(<= (* 3 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35107#(<= (* 4 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35108#(<= (* 5 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35109#(<= (* 6 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35110#(<= (* 7 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35111#(<= (* 8 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35112#(<= (* 9 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35113#(<= (* 10 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35114#(<= (* 11 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35115#(<= (* 12 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35116#(<= (* 13 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35117#(<= (* 14 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35118#(<= (* 15 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35119#(<= (* 16 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35120#(<= (* 17 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35121#(<= (* 18 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35122#(<= (* 19 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35123#(<= (* 20 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35124#(<= (* 21 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35125#(<= (* 22 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35126#(<= (* 23 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35127#(<= (* 24 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35128#(<= (* 25 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35129#(<= (* 26 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35130#(<= (* 27 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35131#(<= (* 28 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35132#(<= (* 29 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35133#(<= (* 30 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35134#(<= (* 31 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35135#(<= (* 32 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35136#(<= (* 33 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35137#(<= (* 34 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35138#(<= (* 35 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35139#(<= (* 36 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35140#(<= (* 37 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35141#(<= (* 38 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35142#(<= (* 39 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35143#(<= (* 40 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35144#(<= (* 41 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35145#(<= (* 42 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35146#(<= (* 43 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35147#(<= (* 44 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35148#(<= (* 45 |#Ultimate.meminit_#sizeOfFields|) |#Ultimate.meminit_#t~loopctr33|), 35149#(<= (+ (* 45 |#Ultimate.meminit_#t~loopctr33|) 46) (* 46 |#Ultimate.meminit_#product|)), 35150#(<= 46 |#Ultimate.meminit_#product|), 35151#(and (= (select |#valid| |ldv_zalloc_#t~malloc1.base|) 1) (<= 46 (select |#length| |ldv_zalloc_#t~malloc1.base|)) (= 0 |ldv_zalloc_#t~malloc1.offset|)), 35152#(and (<= 46 (select |#length| |ldv_zalloc_#res.base|)) (= (select |#valid| |ldv_zalloc_#res.base|) 1) (= 0 |ldv_zalloc_#res.offset|)), 35153#(and (= (select |#valid| |entry_point_#t~ret22.base|) 1) (<= 46 (select |#length| |entry_point_#t~ret22.base|)) (= 0 |entry_point_#t~ret22.offset|)), 35154#(and (= (select |#valid| entry_point_~hdev~0.base) 1) (<= 46 (select |#length| entry_point_~hdev~0.base)) (= 0 entry_point_~hdev~0.offset)), 35155#(and (= |#valid| |old(#valid)|) (= |old(#length)| |#length|)), 35156#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#valid| (store |old(#valid)| |ldv_zalloc_#t~malloc1.base| (select |#valid| |ldv_zalloc_#t~malloc1.base|))) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 35157#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|)))) (or (= |#valid| |old(#valid)|) (= 0 (select |old(#valid)| (@diff |old(#valid)| |#valid|)))) (= |#valid| (store |old(#valid)| (@diff |old(#valid)| |#valid|) (select |#valid| (@diff |old(#valid)| |#valid|))))), 35158#(and (= 0 (select |old(#valid)| |ldv_zalloc_#t~malloc1.base|)) (= |#length| (store |old(#length)| |ldv_zalloc_#t~malloc1.base| (select |#length| |ldv_zalloc_#t~malloc1.base|)))), 35159#(and (or (= 0 (select |old(#valid)| (@diff |old(#length)| |#length|))) (= |old(#length)| |#length|)) (= |#length| (store |old(#length)| (@diff |old(#length)| |#length|) (select |#length| (@diff |old(#length)| |#length|))))), 35160#(and (= entry_point_~hdev~0.offset 0) (<= 46 (select |#length| entry_point_~hdev~0.base)))] [2018-02-04 16:25:08,765 INFO L134 CoverageAnalysis]: Checked inductivity of 3030 backedges. 4 proven. 2554 refuted. 0 times theorem prover too weak. 472 trivial. 0 not checked. [2018-02-04 16:25:08,765 INFO L409 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-02-04 16:25:08,765 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-02-04 16:25:08,766 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=127, Invalid=3533, Unknown=0, NotChecked=0, Total=3660 [2018-02-04 16:25:08,766 INFO L87 Difference]: Start difference. First operand 247 states and 298 transitions. Second operand 61 states. Received shutdown request... [2018-02-04 16:25:10,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-02-04 16:25:10,944 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 16:25:10,948 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 16:25:10,948 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 04:25:10 BoogieIcfgContainer [2018-02-04 16:25:10,948 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 16:25:10,949 INFO L168 Benchmark]: Toolchain (without parser) took 171479.10 ms. Allocated memory was 403.2 MB in the beginning and 1.3 GB in the end (delta: 879.8 MB). Free memory was 360.1 MB in the beginning and 791.5 MB in the end (delta: -431.4 MB). Peak memory consumption was 448.3 MB. Max. memory is 5.3 GB. [2018-02-04 16:25:10,950 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 403.2 MB. Free memory is still 366.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 16:25:10,950 INFO L168 Benchmark]: CACSL2BoogieTranslator took 179.74 ms. Allocated memory is still 403.2 MB. Free memory was 360.1 MB in the beginning and 345.3 MB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 5.3 GB. [2018-02-04 16:25:10,950 INFO L168 Benchmark]: Boogie Preprocessor took 39.54 ms. Allocated memory is still 403.2 MB. Free memory was 345.3 MB in the beginning and 343.9 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-04 16:25:10,950 INFO L168 Benchmark]: RCFGBuilder took 408.23 ms. Allocated memory is still 403.2 MB. Free memory was 342.6 MB in the beginning and 301.9 MB in the end (delta: 40.7 MB). Peak memory consumption was 40.7 MB. Max. memory is 5.3 GB. [2018-02-04 16:25:10,950 INFO L168 Benchmark]: TraceAbstraction took 170848.50 ms. Allocated memory was 403.2 MB in the beginning and 1.3 GB in the end (delta: 879.8 MB). Free memory was 301.9 MB in the beginning and 791.5 MB in the end (delta: -489.6 MB). Peak memory consumption was 390.1 MB. Max. memory is 5.3 GB. [2018-02-04 16:25:10,951 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 403.2 MB. Free memory is still 366.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 179.74 ms. Allocated memory is still 403.2 MB. Free memory was 360.1 MB in the beginning and 345.3 MB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 39.54 ms. Allocated memory is still 403.2 MB. Free memory was 345.3 MB in the beginning and 343.9 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 408.23 ms. Allocated memory is still 403.2 MB. Free memory was 342.6 MB in the beginning and 301.9 MB in the end (delta: 40.7 MB). Peak memory consumption was 40.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 170848.50 ms. Allocated memory was 403.2 MB in the beginning and 1.3 GB in the end (delta: 879.8 MB). Free memory was 301.9 MB in the beginning and 791.5 MB in the end (delta: -489.6 MB). Peak memory consumption was 390.1 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1533]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1533). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was constructing difference of abstraction (247states) and interpolant automaton (currently 34 states, 61 states before enhancement), while ReachableStatesComputation was computing reachable states (76 states constructedinput type IntersectNwa). - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 165 locations, 45 error locations. TIMEOUT Result, 170.8s OverallTime, 67 OverallIterations, 75 TraceHistogramMax, 130.7s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9456 SDtfs, 8012 SDslu, 169362 SDs, 0 SdLazy, 264510 SolverSat, 3679 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 89.1s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3236 GetRequests, 135 SyntacticMatches, 61 SemanticMatches, 3040 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21173 ImplicationChecksByTransitivity, 56.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=247occurred in iteration=66, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 26424/78761 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 66 MinimizatonAttempts, 2692 StatesRemovedByMinimization, 51 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 2.0s SatisfiabilityAnalysisTime, 36.7s InterpolantComputationTime, 6046 NumberOfCodeBlocks, 6046 NumberOfCodeBlocksAsserted, 67 NumberOfCheckSat, 5979 ConstructedInterpolants, 0 QuantifiedInterpolants, 3136075 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 67 InterpolantComputations, 5 PerfectInterpolantSequences, 26424/78761 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_false-valid-memtrack.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_16-25-10-956.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_false-valid-memtrack.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_16-25-10-956.csv Completed graceful shutdown