java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf -i ../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 15:00:40,400 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 15:00:40,401 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 15:00:40,413 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 15:00:40,413 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 15:00:40,414 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 15:00:40,414 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 15:00:40,415 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 15:00:40,417 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 15:00:40,418 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 15:00:40,418 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 15:00:40,419 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 15:00:40,419 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 15:00:40,420 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 15:00:40,421 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 15:00:40,423 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 15:00:40,424 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 15:00:40,426 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 15:00:40,427 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 15:00:40,428 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 15:00:40,429 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... 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[2018-02-04 15:00:40,433 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 15:00:40,433 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 15:00:40,433 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf [2018-02-04 15:00:40,443 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 15:00:40,443 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 15:00:40,444 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 15:00:40,444 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 15:00:40,445 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 15:00:40,445 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 15:00:40,445 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 15:00:40,445 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 15:00:40,445 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 15:00:40,445 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 15:00:40,446 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 15:00:40,446 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 15:00:40,446 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 15:00:40,446 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 15:00:40,446 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 15:00:40,446 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 15:00:40,447 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 15:00:40,447 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 15:00:40,447 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 15:00:40,447 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 15:00:40,447 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 15:00:40,447 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=Craig_TreeInterpolation [2018-02-04 15:00:40,476 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 15:00:40,486 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 15:00:40,489 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 15:00:40,490 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 15:00:40,491 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 15:00:40,491 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-02-04 15:00:40,628 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 15:00:40,629 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 15:00:40,630 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 15:00:40,630 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 15:00:40,634 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 15:00:40,635 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,637 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46667f30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40, skipping insertion in model container [2018-02-04 15:00:40,637 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,650 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 15:00:40,680 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 15:00:40,771 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 15:00:40,783 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 15:00:40,788 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40 WrapperNode [2018-02-04 15:00:40,788 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 15:00:40,789 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 15:00:40,789 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 15:00:40,789 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 15:00:40,800 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,800 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,809 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,809 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,811 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,814 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,815 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... [2018-02-04 15:00:40,816 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 15:00:40,816 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 15:00:40,816 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 15:00:40,816 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 15:00:40,817 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 15:00:40,855 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 15:00:40,855 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 15:00:40,856 INFO L136 BoogieDeclarations]: Found implementation of procedure cstrcat [2018-02-04 15:00:40,856 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 15:00:40,856 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 15:00:40,856 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 15:00:40,856 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 15:00:40,856 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 15:00:40,856 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 15:00:40,856 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 15:00:40,857 INFO L128 BoogieDeclarations]: Found specification of procedure cstrcat [2018-02-04 15:00:40,857 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 15:00:40,857 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 15:00:40,857 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 15:00:41,007 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 15:00:41,007 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 03:00:41 BoogieIcfgContainer [2018-02-04 15:00:41,008 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 15:00:41,008 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 15:00:41,008 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 15:00:41,010 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 15:00:41,010 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 03:00:40" (1/3) ... [2018-02-04 15:00:41,010 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@e7e6de4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 03:00:41, skipping insertion in model container [2018-02-04 15:00:41,010 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 03:00:40" (2/3) ... [2018-02-04 15:00:41,011 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@e7e6de4 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 03:00:41, skipping insertion in model container [2018-02-04 15:00:41,011 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 03:00:41" (3/3) ... [2018-02-04 15:00:41,012 INFO L107 eAbstractionObserver]: Analyzing ICFG openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i [2018-02-04 15:00:41,017 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:Craig_TreeInterpolation Determinization: PREDICATE_ABSTRACTION [2018-02-04 15:00:41,022 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 11 error locations. [2018-02-04 15:00:41,053 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 15:00:41,054 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 15:00:41,054 INFO L324 AbstractCegarLoop]: Compute interpolants for Craig_TreeInterpolation [2018-02-04 15:00:41,054 INFO L325 AbstractCegarLoop]: Backedges is CANONICAL [2018-02-04 15:00:41,054 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 15:00:41,054 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 15:00:41,054 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 15:00:41,055 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 15:00:41,056 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 15:00:41,069 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states. [2018-02-04 15:00:41,079 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-02-04 15:00:41,079 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:41,080 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:41,081 INFO L371 AbstractCegarLoop]: === Iteration 1 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:41,085 INFO L82 PathProgramCache]: Analyzing trace with hash 967400660, now seen corresponding path program 1 times [2018-02-04 15:00:41,137 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:41,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:41,188 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:41,240 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,243 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:41,243 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 15:00:41,244 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:41,244 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,245 INFO L182 omatonBuilderFactory]: Interpolants [53#true, 54#false, 55#(= |#valid| |old(#valid)|)] [2018-02-04 15:00:41,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,246 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 15:00:41,258 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 15:00:41,259 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 15:00:41,260 INFO L87 Difference]: Start difference. First operand 50 states. Second operand 3 states. [2018-02-04 15:00:41,347 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:41,351 INFO L93 Difference]: Finished difference Result 51 states and 56 transitions. [2018-02-04 15:00:41,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 15:00:41,429 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-02-04 15:00:41,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:41,435 INFO L225 Difference]: With dead ends: 51 [2018-02-04 15:00:41,436 INFO L226 Difference]: Without dead ends: 47 [2018-02-04 15:00:41,437 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 15:00:41,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-02-04 15:00:41,457 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-02-04 15:00:41,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-02-04 15:00:41,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 51 transitions. [2018-02-04 15:00:41,459 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 51 transitions. Word has length 11 [2018-02-04 15:00:41,460 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:41,460 INFO L432 AbstractCegarLoop]: Abstraction has 47 states and 51 transitions. [2018-02-04 15:00:41,460 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 15:00:41,460 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 51 transitions. [2018-02-04 15:00:41,460 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-04 15:00:41,460 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:41,460 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:41,460 INFO L371 AbstractCegarLoop]: === Iteration 2 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:41,461 INFO L82 PathProgramCache]: Analyzing trace with hash 1512837349, now seen corresponding path program 1 times [2018-02-04 15:00:41,461 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:41,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:41,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:41,532 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,532 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:41,532 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-04 15:00:41,532 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:41,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,533 INFO L182 omatonBuilderFactory]: Interpolants [154#true, 155#false, 156#(= 1 (select |#valid| |main_#t~malloc9.base|)), 157#(= 1 (select |#valid| main_~nondetString1~0.base))] [2018-02-04 15:00:41,533 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,535 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 15:00:41,535 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 15:00:41,535 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 15:00:41,535 INFO L87 Difference]: Start difference. First operand 47 states and 51 transitions. Second operand 4 states. [2018-02-04 15:00:41,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:41,594 INFO L93 Difference]: Finished difference Result 46 states and 50 transitions. [2018-02-04 15:00:41,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 15:00:41,594 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 15 [2018-02-04 15:00:41,594 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:41,595 INFO L225 Difference]: With dead ends: 46 [2018-02-04 15:00:41,595 INFO L226 Difference]: Without dead ends: 46 [2018-02-04 15:00:41,596 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:00:41,596 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-02-04 15:00:41,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2018-02-04 15:00:41,599 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-02-04 15:00:41,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-02-04 15:00:41,600 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 15 [2018-02-04 15:00:41,600 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:41,601 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-02-04 15:00:41,601 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 15:00:41,601 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-02-04 15:00:41,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-02-04 15:00:41,601 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:41,601 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:41,601 INFO L371 AbstractCegarLoop]: === Iteration 3 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:41,602 INFO L82 PathProgramCache]: Analyzing trace with hash 1512837350, now seen corresponding path program 1 times [2018-02-04 15:00:41,602 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:41,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:41,618 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:41,703 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,703 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:41,703 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:00:41,704 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:41,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,704 INFO L182 omatonBuilderFactory]: Interpolants [256#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 257#(and (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 252#true, 253#false, 254#(<= 1 main_~length1~0), 255#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1))] [2018-02-04 15:00:41,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,705 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:00:41,705 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:00:41,705 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:00:41,705 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 6 states. [2018-02-04 15:00:41,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:41,803 INFO L93 Difference]: Finished difference Result 45 states and 49 transitions. [2018-02-04 15:00:41,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 15:00:41,804 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 15 [2018-02-04 15:00:41,804 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:41,804 INFO L225 Difference]: With dead ends: 45 [2018-02-04 15:00:41,805 INFO L226 Difference]: Without dead ends: 45 [2018-02-04 15:00:41,805 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=23, Unknown=0, NotChecked=0, Total=42 [2018-02-04 15:00:41,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45 states. [2018-02-04 15:00:41,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45 to 45. [2018-02-04 15:00:41,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-02-04 15:00:41,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 49 transitions. [2018-02-04 15:00:41,809 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 49 transitions. Word has length 15 [2018-02-04 15:00:41,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:41,809 INFO L432 AbstractCegarLoop]: Abstraction has 45 states and 49 transitions. [2018-02-04 15:00:41,809 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:00:41,809 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 49 transitions. [2018-02-04 15:00:41,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-04 15:00:41,810 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:41,810 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:41,810 INFO L371 AbstractCegarLoop]: === Iteration 4 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:41,810 INFO L82 PathProgramCache]: Analyzing trace with hash -346682393, now seen corresponding path program 1 times [2018-02-04 15:00:41,811 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:41,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:41,822 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:41,843 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,843 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:41,843 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-02-04 15:00:41,844 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:41,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,844 INFO L182 omatonBuilderFactory]: Interpolants [352#(= 1 (select |#valid| |main_#t~malloc10.base|)), 353#(= 1 (select |#valid| main_~nondetString2~0.base)), 350#true, 351#false] [2018-02-04 15:00:41,844 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,844 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 15:00:41,845 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 15:00:41,845 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 15:00:41,845 INFO L87 Difference]: Start difference. First operand 45 states and 49 transitions. Second operand 4 states. [2018-02-04 15:00:41,876 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:41,876 INFO L93 Difference]: Finished difference Result 44 states and 48 transitions. [2018-02-04 15:00:41,877 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 15:00:41,877 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 16 [2018-02-04 15:00:41,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:41,878 INFO L225 Difference]: With dead ends: 44 [2018-02-04 15:00:41,878 INFO L226 Difference]: Without dead ends: 44 [2018-02-04 15:00:41,878 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:00:41,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-02-04 15:00:41,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-02-04 15:00:41,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-04 15:00:41,881 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-02-04 15:00:41,881 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 16 [2018-02-04 15:00:41,881 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:41,881 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-02-04 15:00:41,881 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 15:00:41,881 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-02-04 15:00:41,881 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-04 15:00:41,881 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:41,881 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:41,881 INFO L371 AbstractCegarLoop]: === Iteration 5 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:41,882 INFO L82 PathProgramCache]: Analyzing trace with hash -346682392, now seen corresponding path program 1 times [2018-02-04 15:00:41,882 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:41,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:41,893 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:41,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,945 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:41,945 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:00:41,945 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:41,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,945 INFO L182 omatonBuilderFactory]: Interpolants [448#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 449#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)), 444#true, 445#false, 446#(<= 2 main_~length2~0), 447#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0))] [2018-02-04 15:00:41,945 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:41,945 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:00:41,946 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:00:41,946 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:00:41,946 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 6 states. [2018-02-04 15:00:42,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:42,032 INFO L93 Difference]: Finished difference Result 59 states and 63 transitions. [2018-02-04 15:00:42,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 15:00:42,033 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-02-04 15:00:42,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:42,035 INFO L225 Difference]: With dead ends: 59 [2018-02-04 15:00:42,035 INFO L226 Difference]: Without dead ends: 59 [2018-02-04 15:00:42,036 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-02-04 15:00:42,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-02-04 15:00:42,042 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 51. [2018-02-04 15:00:42,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-02-04 15:00:42,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 55 transitions. [2018-02-04 15:00:42,045 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 55 transitions. Word has length 16 [2018-02-04 15:00:42,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:42,046 INFO L432 AbstractCegarLoop]: Abstraction has 51 states and 55 transitions. [2018-02-04 15:00:42,046 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:00:42,046 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 55 transitions. [2018-02-04 15:00:42,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-02-04 15:00:42,047 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:42,047 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:42,047 INFO L371 AbstractCegarLoop]: === Iteration 6 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:42,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1156029018, now seen corresponding path program 1 times [2018-02-04 15:00:42,048 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:42,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:42,057 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:42,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,129 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:42,129 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 15:00:42,129 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:42,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,130 INFO L182 omatonBuilderFactory]: Interpolants [566#true, 567#false, 568#(<= 1 main_~length1~0), 569#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 570#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 571#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0)), 572#(and (= main_~nondetString2~0.offset 0) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-02-04 15:00:42,130 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,130 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 15:00:42,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 15:00:42,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=30, Unknown=0, NotChecked=0, Total=42 [2018-02-04 15:00:42,131 INFO L87 Difference]: Start difference. First operand 51 states and 55 transitions. Second operand 7 states. [2018-02-04 15:00:42,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:42,227 INFO L93 Difference]: Finished difference Result 50 states and 54 transitions. [2018-02-04 15:00:42,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 15:00:42,227 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 16 [2018-02-04 15:00:42,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:42,228 INFO L225 Difference]: With dead ends: 50 [2018-02-04 15:00:42,228 INFO L226 Difference]: Without dead ends: 50 [2018-02-04 15:00:42,228 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-02-04 15:00:42,229 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-02-04 15:00:42,230 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 43. [2018-02-04 15:00:42,231 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-02-04 15:00:42,231 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-02-04 15:00:42,231 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 16 [2018-02-04 15:00:42,231 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:42,232 INFO L432 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-02-04 15:00:42,232 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 15:00:42,232 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-02-04 15:00:42,232 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-04 15:00:42,232 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:42,232 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:42,232 INFO L371 AbstractCegarLoop]: === Iteration 7 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:42,234 INFO L82 PathProgramCache]: Analyzing trace with hash -131455439, now seen corresponding path program 1 times [2018-02-04 15:00:42,235 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:42,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:42,244 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:42,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,277 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:42,278 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 15:00:42,278 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:42,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,278 INFO L182 omatonBuilderFactory]: Interpolants [674#true, 675#false, 676#(= 1 (select |#valid| main_~nondetString2~0.base)), 677#(= 1 (select |#valid| |cstrcat_#in~s.base|)), 678#(= 1 (select |#valid| cstrcat_~s.base))] [2018-02-04 15:00:42,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,278 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 15:00:42,279 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 15:00:42,279 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 15:00:42,279 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 5 states. [2018-02-04 15:00:42,321 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:42,322 INFO L93 Difference]: Finished difference Result 42 states and 46 transitions. [2018-02-04 15:00:42,322 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 15:00:42,322 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-02-04 15:00:42,322 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:42,322 INFO L225 Difference]: With dead ends: 42 [2018-02-04 15:00:42,323 INFO L226 Difference]: Without dead ends: 42 [2018-02-04 15:00:42,323 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:00:42,323 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-02-04 15:00:42,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2018-02-04 15:00:42,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-02-04 15:00:42,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 46 transitions. [2018-02-04 15:00:42,328 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 46 transitions. Word has length 20 [2018-02-04 15:00:42,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:42,328 INFO L432 AbstractCegarLoop]: Abstraction has 42 states and 46 transitions. [2018-02-04 15:00:42,328 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 15:00:42,329 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 46 transitions. [2018-02-04 15:00:42,329 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-02-04 15:00:42,329 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:42,329 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:42,329 INFO L371 AbstractCegarLoop]: === Iteration 8 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:42,329 INFO L82 PathProgramCache]: Analyzing trace with hash -131455438, now seen corresponding path program 1 times [2018-02-04 15:00:42,330 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:42,340 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:42,341 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:42,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,390 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:42,390 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 15:00:42,390 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:42,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,390 INFO L182 omatonBuilderFactory]: Interpolants [768#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 769#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 770#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|))), 771#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 765#true, 766#false, 767#(<= 2 main_~length2~0)] [2018-02-04 15:00:42,390 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,390 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 15:00:42,391 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 15:00:42,391 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 15:00:42,391 INFO L87 Difference]: Start difference. First operand 42 states and 46 transitions. Second operand 7 states. [2018-02-04 15:00:42,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:42,484 INFO L93 Difference]: Finished difference Result 48 states and 53 transitions. [2018-02-04 15:00:42,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 15:00:42,484 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 20 [2018-02-04 15:00:42,484 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:42,484 INFO L225 Difference]: With dead ends: 48 [2018-02-04 15:00:42,484 INFO L226 Difference]: Without dead ends: 48 [2018-02-04 15:00:42,484 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=80, Unknown=0, NotChecked=0, Total=110 [2018-02-04 15:00:42,485 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-02-04 15:00:42,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 44. [2018-02-04 15:00:42,486 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-02-04 15:00:42,486 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 48 transitions. [2018-02-04 15:00:42,486 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 48 transitions. Word has length 20 [2018-02-04 15:00:42,487 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:42,487 INFO L432 AbstractCegarLoop]: Abstraction has 44 states and 48 transitions. [2018-02-04 15:00:42,487 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 15:00:42,489 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 48 transitions. [2018-02-04 15:00:42,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 15:00:42,489 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:42,489 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:42,489 INFO L371 AbstractCegarLoop]: === Iteration 9 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:42,489 INFO L82 PathProgramCache]: Analyzing trace with hash -313436100, now seen corresponding path program 1 times [2018-02-04 15:00:42,490 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:42,498 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:42,498 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:42,546 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,546 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:42,546 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:00:42,546 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:42,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,547 INFO L182 omatonBuilderFactory]: Interpolants [872#true, 873#false, 874#(= 1 (select |#valid| main_~nondetString1~0.base)), 875#(= 1 (select |#valid| |cstrcat_#in~append.base|)), 876#(= 1 (select |#valid| cstrcat_~append.base)), 877#(= 1 (select |#valid| |cstrcat_#t~post3.base|))] [2018-02-04 15:00:42,547 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,550 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:00:42,551 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:00:42,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:00:42,551 INFO L87 Difference]: Start difference. First operand 44 states and 48 transitions. Second operand 6 states. [2018-02-04 15:00:42,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:42,627 INFO L93 Difference]: Finished difference Result 43 states and 47 transitions. [2018-02-04 15:00:42,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 15:00:42,627 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 24 [2018-02-04 15:00:42,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:42,628 INFO L225 Difference]: With dead ends: 43 [2018-02-04 15:00:42,628 INFO L226 Difference]: Without dead ends: 43 [2018-02-04 15:00:42,628 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:00:42,628 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-02-04 15:00:42,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 43. [2018-02-04 15:00:42,630 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 43 states. [2018-02-04 15:00:42,630 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43 states to 43 states and 47 transitions. [2018-02-04 15:00:42,630 INFO L78 Accepts]: Start accepts. Automaton has 43 states and 47 transitions. Word has length 24 [2018-02-04 15:00:42,631 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:42,631 INFO L432 AbstractCegarLoop]: Abstraction has 43 states and 47 transitions. [2018-02-04 15:00:42,631 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:00:42,631 INFO L276 IsEmpty]: Start isEmpty. Operand 43 states and 47 transitions. [2018-02-04 15:00:42,631 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 15:00:42,631 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:42,632 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:42,632 INFO L371 AbstractCegarLoop]: === Iteration 10 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:42,632 INFO L82 PathProgramCache]: Analyzing trace with hash -313436099, now seen corresponding path program 1 times [2018-02-04 15:00:42,632 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:42,640 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:42,641 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:42,756 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,757 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:42,757 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 15:00:42,757 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:42,757 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,757 INFO L182 omatonBuilderFactory]: Interpolants [976#(and (= |cstrcat_#t~post3.offset| 0) (<= 1 (select |#length| |cstrcat_#t~post3.base|))), 968#true, 969#false, 970#(<= 1 main_~length1~0), 971#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0)), 972#(and (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 973#(and (<= (+ main_~nondetString1~0.offset 1) (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 974#(and (= 0 |cstrcat_#in~append.offset|) (<= 1 (select |#length| |cstrcat_#in~append.base|))), 975#(and (= 0 cstrcat_~append.offset) (<= 1 (select |#length| cstrcat_~append.base)))] [2018-02-04 15:00:42,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,758 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 15:00:42,758 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 15:00:42,758 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-04 15:00:42,758 INFO L87 Difference]: Start difference. First operand 43 states and 47 transitions. Second operand 9 states. [2018-02-04 15:00:42,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:42,865 INFO L93 Difference]: Finished difference Result 50 states and 55 transitions. [2018-02-04 15:00:42,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 15:00:42,865 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-02-04 15:00:42,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:42,866 INFO L225 Difference]: With dead ends: 50 [2018-02-04 15:00:42,866 INFO L226 Difference]: Without dead ends: 50 [2018-02-04 15:00:42,866 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 21 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=43, Invalid=139, Unknown=0, NotChecked=0, Total=182 [2018-02-04 15:00:42,866 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 50 states. [2018-02-04 15:00:42,868 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 50 to 46. [2018-02-04 15:00:42,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-02-04 15:00:42,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 50 transitions. [2018-02-04 15:00:42,869 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 50 transitions. Word has length 24 [2018-02-04 15:00:42,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:42,869 INFO L432 AbstractCegarLoop]: Abstraction has 46 states and 50 transitions. [2018-02-04 15:00:42,869 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 15:00:42,870 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 50 transitions. [2018-02-04 15:00:42,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-02-04 15:00:42,870 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:42,870 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:42,870 INFO L371 AbstractCegarLoop]: === Iteration 11 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:42,870 INFO L82 PathProgramCache]: Analyzing trace with hash -313382859, now seen corresponding path program 1 times [2018-02-04 15:00:42,871 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:42,877 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:42,878 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:42,972 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,972 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:42,972 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-04 15:00:42,972 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:42,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,972 INFO L182 omatonBuilderFactory]: Interpolants [1088#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|))), 1089#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 1090#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 1083#true, 1084#false, 1085#(<= 2 main_~length2~0), 1086#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 1087#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base)))] [2018-02-04 15:00:42,972 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:42,973 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 15:00:42,973 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 15:00:42,973 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:00:42,973 INFO L87 Difference]: Start difference. First operand 46 states and 50 transitions. Second operand 8 states. [2018-02-04 15:00:43,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:43,064 INFO L93 Difference]: Finished difference Result 66 states and 73 transitions. [2018-02-04 15:00:43,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 15:00:43,064 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 24 [2018-02-04 15:00:43,065 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:43,066 INFO L225 Difference]: With dead ends: 66 [2018-02-04 15:00:43,066 INFO L226 Difference]: Without dead ends: 66 [2018-02-04 15:00:43,066 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-04 15:00:43,066 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-02-04 15:00:43,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 50. [2018-02-04 15:00:43,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-02-04 15:00:43,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 55 transitions. [2018-02-04 15:00:43,068 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 55 transitions. Word has length 24 [2018-02-04 15:00:43,068 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:43,068 INFO L432 AbstractCegarLoop]: Abstraction has 50 states and 55 transitions. [2018-02-04 15:00:43,068 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 15:00:43,068 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 55 transitions. [2018-02-04 15:00:43,069 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-04 15:00:43,069 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:43,069 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:43,069 INFO L371 AbstractCegarLoop]: === Iteration 12 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:43,069 INFO L82 PathProgramCache]: Analyzing trace with hash -1126584510, now seen corresponding path program 1 times [2018-02-04 15:00:43,069 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:43,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:43,076 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:43,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,108 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:43,108 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:00:43,108 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:43,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,108 INFO L182 omatonBuilderFactory]: Interpolants [1217#true, 1218#false, 1219#(= 1 (select |#valid| main_~nondetString2~0.base)), 1220#(= 1 (select |#valid| |cstrcat_#in~s.base|)), 1221#(= 1 (select |#valid| cstrcat_~s.base)), 1222#(= 1 (select |#valid| |cstrcat_#t~post2.base|))] [2018-02-04 15:00:43,109 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,109 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:00:43,109 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:00:43,109 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:00:43,109 INFO L87 Difference]: Start difference. First operand 50 states and 55 transitions. Second operand 6 states. [2018-02-04 15:00:43,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:43,165 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-02-04 15:00:43,165 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 15:00:43,165 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 25 [2018-02-04 15:00:43,166 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:43,166 INFO L225 Difference]: With dead ends: 49 [2018-02-04 15:00:43,166 INFO L226 Difference]: Without dead ends: 49 [2018-02-04 15:00:43,166 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:00:43,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-02-04 15:00:43,168 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-02-04 15:00:43,168 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-02-04 15:00:43,168 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 54 transitions. [2018-02-04 15:00:43,168 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 54 transitions. Word has length 25 [2018-02-04 15:00:43,168 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:43,168 INFO L432 AbstractCegarLoop]: Abstraction has 49 states and 54 transitions. [2018-02-04 15:00:43,168 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:00:43,168 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 54 transitions. [2018-02-04 15:00:43,169 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-02-04 15:00:43,169 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:43,169 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:43,169 INFO L371 AbstractCegarLoop]: === Iteration 13 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:43,169 INFO L82 PathProgramCache]: Analyzing trace with hash -1126584509, now seen corresponding path program 1 times [2018-02-04 15:00:43,170 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:43,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:43,175 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:43,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,229 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:43,230 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 15:00:43,230 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:43,230 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,230 INFO L182 omatonBuilderFactory]: Interpolants [1328#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 1329#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 1330#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|))), 1331#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 1332#(and (<= 0 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 2) (select |#length| |cstrcat_#t~post2.base|))), 1325#true, 1326#false, 1327#(<= 2 main_~length2~0)] [2018-02-04 15:00:43,231 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,231 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 15:00:43,231 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 15:00:43,231 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:00:43,231 INFO L87 Difference]: Start difference. First operand 49 states and 54 transitions. Second operand 8 states. [2018-02-04 15:00:43,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:43,340 INFO L93 Difference]: Finished difference Result 54 states and 60 transitions. [2018-02-04 15:00:43,340 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 15:00:43,340 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 25 [2018-02-04 15:00:43,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:43,341 INFO L225 Difference]: With dead ends: 54 [2018-02-04 15:00:43,341 INFO L226 Difference]: Without dead ends: 54 [2018-02-04 15:00:43,341 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-02-04 15:00:43,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-02-04 15:00:43,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 53. [2018-02-04 15:00:43,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 53 states. [2018-02-04 15:00:43,343 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 53 states to 53 states and 58 transitions. [2018-02-04 15:00:43,343 INFO L78 Accepts]: Start accepts. Automaton has 53 states and 58 transitions. Word has length 25 [2018-02-04 15:00:43,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:43,343 INFO L432 AbstractCegarLoop]: Abstraction has 53 states and 58 transitions. [2018-02-04 15:00:43,343 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 15:00:43,344 INFO L276 IsEmpty]: Start isEmpty. Operand 53 states and 58 transitions. [2018-02-04 15:00:43,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 15:00:43,344 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:43,344 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:43,344 INFO L371 AbstractCegarLoop]: === Iteration 14 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:43,344 INFO L82 PathProgramCache]: Analyzing trace with hash 718500024, now seen corresponding path program 2 times [2018-02-04 15:00:43,345 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:43,354 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:43,355 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:43,430 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:00:43,430 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:43,431 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 15:00:43,431 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:43,431 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,431 INFO L182 omatonBuilderFactory]: Interpolants [1456#(= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)), 1457#(= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)), 1458#(= |cstrcat_#t~mem1| 0), 1450#true, 1451#false, 1452#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1453#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1454#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1455#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)))] [2018-02-04 15:00:43,431 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:00:43,431 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 15:00:43,431 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 15:00:43,432 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=55, Unknown=0, NotChecked=0, Total=72 [2018-02-04 15:00:43,432 INFO L87 Difference]: Start difference. First operand 53 states and 58 transitions. Second operand 9 states. [2018-02-04 15:00:43,510 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:43,510 INFO L93 Difference]: Finished difference Result 76 states and 81 transitions. [2018-02-04 15:00:43,510 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 15:00:43,510 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 28 [2018-02-04 15:00:43,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:43,511 INFO L225 Difference]: With dead ends: 76 [2018-02-04 15:00:43,511 INFO L226 Difference]: Without dead ends: 76 [2018-02-04 15:00:43,511 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=117, Unknown=0, NotChecked=0, Total=156 [2018-02-04 15:00:43,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-02-04 15:00:43,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 65. [2018-02-04 15:00:43,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 65 states. [2018-02-04 15:00:43,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 65 states to 65 states and 71 transitions. [2018-02-04 15:00:43,517 INFO L78 Accepts]: Start accepts. Automaton has 65 states and 71 transitions. Word has length 28 [2018-02-04 15:00:43,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:43,517 INFO L432 AbstractCegarLoop]: Abstraction has 65 states and 71 transitions. [2018-02-04 15:00:43,517 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 15:00:43,517 INFO L276 IsEmpty]: Start isEmpty. Operand 65 states and 71 transitions. [2018-02-04 15:00:43,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 15:00:43,519 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:43,519 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:43,519 INFO L371 AbstractCegarLoop]: === Iteration 15 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:43,519 INFO L82 PathProgramCache]: Analyzing trace with hash -99148426, now seen corresponding path program 1 times [2018-02-04 15:00:43,520 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:43,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:43,531 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:43,659 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:00:43,659 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:43,660 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [12] imperfect sequences [] total 12 [2018-02-04 15:00:43,660 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:43,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:43,660 INFO L182 omatonBuilderFactory]: Interpolants [1616#(and (= main_~nondetString2~0.offset 0) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset))), 1617#(= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)), 1618#(= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)), 1619#(= |cstrcat_#t~mem1| 0), 1608#true, 1609#false, 1610#(<= 1 main_~length1~0), 1611#(<= main_~length2~0 (+ main_~length1~0 1)), 1612#(and (<= main_~length2~0 (+ main_~length1~0 1)) (<= 1 main_~length3~0)), 1613#(and (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1614#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= main_~length3~0 1)), 1615#(and (= main_~nondetString2~0.offset 0) (<= 1 main_~length3~0) (<= main_~length3~0 1))] [2018-02-04 15:00:43,661 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 15:00:43,661 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 15:00:43,661 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 15:00:43,661 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=108, Unknown=0, NotChecked=0, Total=132 [2018-02-04 15:00:43,662 INFO L87 Difference]: Start difference. First operand 65 states and 71 transitions. Second operand 12 states. [2018-02-04 15:00:43,878 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:43,878 INFO L93 Difference]: Finished difference Result 104 states and 111 transitions. [2018-02-04 15:00:43,878 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 15:00:43,878 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 28 [2018-02-04 15:00:43,878 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:43,879 INFO L225 Difference]: With dead ends: 104 [2018-02-04 15:00:43,879 INFO L226 Difference]: Without dead ends: 104 [2018-02-04 15:00:43,879 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 27 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=150, Invalid=500, Unknown=0, NotChecked=0, Total=650 [2018-02-04 15:00:43,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-02-04 15:00:43,881 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 66. [2018-02-04 15:00:43,881 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-02-04 15:00:43,882 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 73 transitions. [2018-02-04 15:00:43,882 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 73 transitions. Word has length 28 [2018-02-04 15:00:43,882 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:43,882 INFO L432 AbstractCegarLoop]: Abstraction has 66 states and 73 transitions. [2018-02-04 15:00:43,882 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 15:00:43,882 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 73 transitions. [2018-02-04 15:00:43,883 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-02-04 15:00:43,883 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:43,883 INFO L351 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:43,884 INFO L371 AbstractCegarLoop]: === Iteration 16 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:43,884 INFO L82 PathProgramCache]: Analyzing trace with hash 323553400, now seen corresponding path program 1 times [2018-02-04 15:00:43,884 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:43,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:43,892 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:44,023 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,023 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:44,023 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 15:00:44,023 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:44,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,023 INFO L182 omatonBuilderFactory]: Interpolants [1824#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))), 1825#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 1826#(and (= 0 |cstrcat_#in~s.offset|) (or (<= 3 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)))), 1827#(and (= cstrcat_~s.offset 0) (or (<= 3 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 1828#(and (= cstrcat_~s.offset 0) (or (<= 3 (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 1829#(and (<= 3 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 1830#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 1831#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 1818#true, 1819#false, 1820#(<= 1 main_~length1~0), 1821#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 1822#(and (<= (+ main_~length3~0 1) main_~length2~0) (<= 1 main_~length3~0)), 1823#(and (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length3~0 1) (select |#length| |main_#t~malloc10.base|)) (<= 1 main_~length3~0))] [2018-02-04 15:00:44,024 INFO L134 CoverageAnalysis]: Checked inductivity of 8 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,024 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 15:00:44,024 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 15:00:44,024 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=154, Unknown=0, NotChecked=0, Total=182 [2018-02-04 15:00:44,024 INFO L87 Difference]: Start difference. First operand 66 states and 73 transitions. Second operand 14 states. [2018-02-04 15:00:44,273 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:44,273 INFO L93 Difference]: Finished difference Result 87 states and 97 transitions. [2018-02-04 15:00:44,273 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 15:00:44,274 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 28 [2018-02-04 15:00:44,274 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:44,274 INFO L225 Difference]: With dead ends: 87 [2018-02-04 15:00:44,274 INFO L226 Difference]: Without dead ends: 87 [2018-02-04 15:00:44,275 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 61 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=95, Invalid=457, Unknown=0, NotChecked=0, Total=552 [2018-02-04 15:00:44,275 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-02-04 15:00:44,276 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 78. [2018-02-04 15:00:44,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-02-04 15:00:44,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 88 transitions. [2018-02-04 15:00:44,277 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 88 transitions. Word has length 28 [2018-02-04 15:00:44,277 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:44,278 INFO L432 AbstractCegarLoop]: Abstraction has 78 states and 88 transitions. [2018-02-04 15:00:44,278 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 15:00:44,278 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 88 transitions. [2018-02-04 15:00:44,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 15:00:44,279 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:44,279 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:44,279 INFO L371 AbstractCegarLoop]: === Iteration 17 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:44,279 INFO L82 PathProgramCache]: Analyzing trace with hash 1309566295, now seen corresponding path program 1 times [2018-02-04 15:00:44,280 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:44,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:44,287 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:44,460 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,460 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:44,460 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [] total 15 [2018-02-04 15:00:44,460 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:44,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,461 INFO L182 omatonBuilderFactory]: Interpolants [2017#true, 2018#false, 2019#(<= 1 main_~length1~0), 2020#(and (<= 1 main_~length1~0) (<= main_~length2~0 2)), 2021#(and (<= main_~length2~0 (+ main_~length3~0 1)) (<= 1 main_~length1~0)), 2022#(and (<= 1 main_~length1~0) (<= main_~length1~0 1)), 2023#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1) (<= main_~length1~0 1)), 2024#(and (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2025#(and (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (<= 1 main_~length1~0) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2026#(and (<= 1 main_~length1~0) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (<= main_~length1~0 1) (= main_~nondetString1~0.offset 0)), 2027#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 2028#(= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) |cstrcat_#in~append.offset|)), 2029#(= 0 (select (select |#memory_int| cstrcat_~append.base) cstrcat_~append.offset)), 2030#(= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 2031#(= |cstrcat_#t~mem5| 0)] [2018-02-04 15:00:44,461 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,461 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 15:00:44,461 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 15:00:44,461 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=172, Unknown=0, NotChecked=0, Total=210 [2018-02-04 15:00:44,461 INFO L87 Difference]: Start difference. First operand 78 states and 88 transitions. Second operand 15 states. [2018-02-04 15:00:44,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:44,818 INFO L93 Difference]: Finished difference Result 161 states and 178 transitions. [2018-02-04 15:00:44,818 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 15:00:44,819 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 29 [2018-02-04 15:00:44,819 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:44,819 INFO L225 Difference]: With dead ends: 161 [2018-02-04 15:00:44,819 INFO L226 Difference]: Without dead ends: 161 [2018-02-04 15:00:44,820 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 198 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=233, Invalid=889, Unknown=0, NotChecked=0, Total=1122 [2018-02-04 15:00:44,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-02-04 15:00:44,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 135. [2018-02-04 15:00:44,822 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-04 15:00:44,823 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 154 transitions. [2018-02-04 15:00:44,823 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 154 transitions. Word has length 29 [2018-02-04 15:00:44,823 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:44,823 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 154 transitions. [2018-02-04 15:00:44,823 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 15:00:44,823 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 154 transitions. [2018-02-04 15:00:44,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 15:00:44,824 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:44,824 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:44,824 INFO L371 AbstractCegarLoop]: === Iteration 18 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:44,824 INFO L82 PathProgramCache]: Analyzing trace with hash 1528421013, now seen corresponding path program 1 times [2018-02-04 15:00:44,824 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:44,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:44,830 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:44,987 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,987 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:44,987 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 15:00:44,987 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:44,987 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,988 INFO L182 omatonBuilderFactory]: Interpolants [2368#(<= 1 main_~length1~0), 2369#(and (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length1~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 2370#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (= (select |#valid| main_~nondetString1~0.base) 1)) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2371#(and (<= 1 main_~length1~0) (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base |main_#t~malloc10.base|))) (= main_~nondetString1~0.offset 0)), 2372#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 1)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 2373#(and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) main_~nondetString1~0.offset)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (<= 2 (select |#length| main_~nondetString1~0.base)))), 2374#(and (or (= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) |cstrcat_#in~append.offset|)) (<= 2 (select |#length| |cstrcat_#in~append.base|))) (= 0 |cstrcat_#in~append.offset|)), 2375#(and (or (= 0 (select (select |#memory_int| cstrcat_~append.base) cstrcat_~append.offset)) (<= 2 (select |#length| cstrcat_~append.base))) (= 0 cstrcat_~append.offset)), 2376#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (or (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (<= (+ cstrcat_~append.offset 1) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset)))), 2377#(or (and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)) (= |cstrcat_#t~mem5| 0)), 2378#(and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)), 2379#(and (<= 1 |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|))), 2366#true, 2367#false] [2018-02-04 15:00:44,988 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:44,988 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 15:00:44,988 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 15:00:44,988 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=152, Unknown=0, NotChecked=0, Total=182 [2018-02-04 15:00:44,988 INFO L87 Difference]: Start difference. First operand 135 states and 154 transitions. Second operand 14 states. [2018-02-04 15:00:45,221 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:45,222 INFO L93 Difference]: Finished difference Result 144 states and 165 transitions. [2018-02-04 15:00:45,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 15:00:45,227 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 29 [2018-02-04 15:00:45,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:45,228 INFO L225 Difference]: With dead ends: 144 [2018-02-04 15:00:45,228 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 15:00:45,228 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 23 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 86 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=88, Invalid=418, Unknown=0, NotChecked=0, Total=506 [2018-02-04 15:00:45,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 15:00:45,232 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 140. [2018-02-04 15:00:45,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-02-04 15:00:45,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 161 transitions. [2018-02-04 15:00:45,233 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 161 transitions. Word has length 29 [2018-02-04 15:00:45,233 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:45,233 INFO L432 AbstractCegarLoop]: Abstraction has 140 states and 161 transitions. [2018-02-04 15:00:45,233 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 15:00:45,233 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 161 transitions. [2018-02-04 15:00:45,233 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-02-04 15:00:45,233 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:45,234 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:45,234 INFO L371 AbstractCegarLoop]: === Iteration 19 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:45,234 INFO L82 PathProgramCache]: Analyzing trace with hash 1438570336, now seen corresponding path program 1 times [2018-02-04 15:00:45,234 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:45,238 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:45,238 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:45,301 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:45,301 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:45,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-04 15:00:45,301 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:45,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:45,301 INFO L182 omatonBuilderFactory]: Interpolants [2688#(and (<= 2 (select |#length| cstrcat_~s.base)) (= cstrcat_~s.offset 0)), 2689#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 2690#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 2682#true, 2683#false, 2684#(<= 2 main_~length2~0), 2685#(and (<= 2 (select |#length| |main_#t~malloc10.base|)) (= 0 |main_#t~malloc10.offset|)), 2686#(and (= 0 main_~nondetString2~0.offset) (<= 2 (select |#length| main_~nondetString2~0.base))), 2687#(and (= 0 |cstrcat_#in~s.offset|) (<= 2 (select |#length| |cstrcat_#in~s.base|)))] [2018-02-04 15:00:45,302 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:45,302 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 15:00:45,302 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 15:00:45,302 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-02-04 15:00:45,302 INFO L87 Difference]: Start difference. First operand 140 states and 161 transitions. Second operand 9 states. [2018-02-04 15:00:45,404 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:45,404 INFO L93 Difference]: Finished difference Result 153 states and 175 transitions. [2018-02-04 15:00:45,404 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 15:00:45,405 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-02-04 15:00:45,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:45,405 INFO L225 Difference]: With dead ends: 153 [2018-02-04 15:00:45,405 INFO L226 Difference]: Without dead ends: 153 [2018-02-04 15:00:45,406 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2018-02-04 15:00:45,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-02-04 15:00:45,409 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 145. [2018-02-04 15:00:45,409 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-02-04 15:00:45,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 165 transitions. [2018-02-04 15:00:45,410 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 165 transitions. Word has length 29 [2018-02-04 15:00:45,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:45,411 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 165 transitions. [2018-02-04 15:00:45,411 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 15:00:45,411 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 165 transitions. [2018-02-04 15:00:45,411 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-02-04 15:00:45,411 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:45,412 INFO L351 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:45,412 INFO L371 AbstractCegarLoop]: === Iteration 20 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:45,412 INFO L82 PathProgramCache]: Analyzing trace with hash -1106610309, now seen corresponding path program 2 times [2018-02-04 15:00:45,413 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:45,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:45,437 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:45,873 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:45,874 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:45,874 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20] total 20 [2018-02-04 15:00:45,874 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:45,875 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:45,875 INFO L182 omatonBuilderFactory]: Interpolants [3008#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 3009#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (or (not (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (= main_~nondetString1~0.offset 0)), 3010#(and (or (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (or (not (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= (+ main_~length3~0 1) (select |#length| main_~nondetString2~0.base)))) (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) (* 2 main_~nondetString1~0.offset)))) (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 3011#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (or (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 3 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))) (= main_~nondetString1~0.offset 0)), 3012#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 3 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1))) (<= 4 (select |#length| |cstrcat_#in~s.base|)))), 3013#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= 4 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 3 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 3014#(and (= cstrcat_~s.offset 0) (or (<= 4 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 3 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 3015#(and (or (<= 4 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 3 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 3016#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 3017#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 3018#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 3019#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 3020#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 3021#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 3001#true, 3002#false, 3003#(<= 1 main_~length1~0), 3004#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3005#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3006#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 3007#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0))] [2018-02-04 15:00:45,875 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 0 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:45,875 INFO L409 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-02-04 15:00:45,875 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-02-04 15:00:45,876 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=356, Unknown=0, NotChecked=0, Total=420 [2018-02-04 15:00:45,876 INFO L87 Difference]: Start difference. First operand 145 states and 165 transitions. Second operand 21 states. [2018-02-04 15:00:46,391 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:46,391 INFO L93 Difference]: Finished difference Result 181 states and 206 transitions. [2018-02-04 15:00:46,391 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 15:00:46,391 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 32 [2018-02-04 15:00:46,392 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:46,393 INFO L225 Difference]: With dead ends: 181 [2018-02-04 15:00:46,393 INFO L226 Difference]: Without dead ends: 181 [2018-02-04 15:00:46,393 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 35 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 268 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=195, Invalid=995, Unknown=0, NotChecked=0, Total=1190 [2018-02-04 15:00:46,394 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-02-04 15:00:46,398 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 157. [2018-02-04 15:00:46,398 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-02-04 15:00:46,399 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 180 transitions. [2018-02-04 15:00:46,399 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 180 transitions. Word has length 32 [2018-02-04 15:00:46,399 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:46,399 INFO L432 AbstractCegarLoop]: Abstraction has 157 states and 180 transitions. [2018-02-04 15:00:46,399 INFO L433 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-02-04 15:00:46,399 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 180 transitions. [2018-02-04 15:00:46,400 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-04 15:00:46,400 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:46,400 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:46,400 INFO L371 AbstractCegarLoop]: === Iteration 21 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:46,400 INFO L82 PathProgramCache]: Analyzing trace with hash 53168317, now seen corresponding path program 2 times [2018-02-04 15:00:46,400 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:46,407 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:46,408 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:46,476 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:46,476 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:46,476 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-04 15:00:46,476 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:46,476 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:46,476 INFO L182 omatonBuilderFactory]: Interpolants [3392#(= 0 |cstrcat_#in~s.offset|), 3393#(= cstrcat_~s.offset 0), 3394#(<= 1 cstrcat_~s.offset), 3395#(<= 2 cstrcat_~s.offset), 3396#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 3397#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 3388#true, 3389#false, 3390#(= 0 |main_#t~malloc10.offset|), 3391#(= 0 main_~nondetString2~0.offset)] [2018-02-04 15:00:46,476 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 3 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:46,477 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 15:00:46,477 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 15:00:46,477 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=70, Unknown=0, NotChecked=0, Total=90 [2018-02-04 15:00:46,477 INFO L87 Difference]: Start difference. First operand 157 states and 180 transitions. Second operand 10 states. [2018-02-04 15:00:46,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:46,582 INFO L93 Difference]: Finished difference Result 162 states and 184 transitions. [2018-02-04 15:00:46,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 15:00:46,582 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 33 [2018-02-04 15:00:46,583 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:46,583 INFO L225 Difference]: With dead ends: 162 [2018-02-04 15:00:46,584 INFO L226 Difference]: Without dead ends: 162 [2018-02-04 15:00:46,584 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=54, Invalid=186, Unknown=0, NotChecked=0, Total=240 [2018-02-04 15:00:46,584 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-04 15:00:46,587 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 149. [2018-02-04 15:00:46,587 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-02-04 15:00:46,588 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 169 transitions. [2018-02-04 15:00:46,588 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 169 transitions. Word has length 33 [2018-02-04 15:00:46,588 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:46,588 INFO L432 AbstractCegarLoop]: Abstraction has 149 states and 169 transitions. [2018-02-04 15:00:46,589 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 15:00:46,589 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 169 transitions. [2018-02-04 15:00:46,589 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 15:00:46,589 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:46,589 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:46,589 INFO L371 AbstractCegarLoop]: === Iteration 22 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:46,590 INFO L82 PathProgramCache]: Analyzing trace with hash -1452172801, now seen corresponding path program 2 times [2018-02-04 15:00:46,590 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:46,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:46,602 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:46,966 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:46,966 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:46,966 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 15:00:46,967 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:46,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:46,967 INFO L182 omatonBuilderFactory]: Interpolants [3721#true, 3722#false, 3723#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 3724#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 3725#(and (or (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (not (= (+ main_~nondetString1~0.offset main_~length1~0) 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 3726#(and (or (not (= (+ main_~nondetString1~0.offset main_~length1~0) 2)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 3727#(and (or (<= 3 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (and (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) 1)))) (= main_~nondetString1~0.offset 0)), 3728#(and (or (<= (select |#length| |cstrcat_#in~append.base|) 1) (and (= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) 1)) (not (= |cstrcat_#in~append.base| |cstrcat_#in~s.base|))) (<= 3 (select |#length| |cstrcat_#in~append.base|))) (= 0 |cstrcat_#in~append.offset|)), 3729#(and (or (and (not (= cstrcat_~append.base cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~append.base) 1))) (<= (select |#length| cstrcat_~append.base) 1) (<= 3 (select |#length| cstrcat_~append.base))) (= 0 cstrcat_~append.offset)), 3730#(and (or (<= (+ cstrcat_~append.offset 2) (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (= 0 (select (select |#memory_int| cstrcat_~append.base) 1)) (<= cstrcat_~append.offset (+ |cstrcat_#t~post3.offset| 1)) (not (= |cstrcat_#t~post2.base| cstrcat_~append.base))) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset)), 3731#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~append.offset 2) (select |#length| cstrcat_~append.base)) (and (= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~append.base) 1)) (<= cstrcat_~append.offset 1))) (<= 1 cstrcat_~append.offset)), 3732#(and (or (and (<= cstrcat_~append.offset 1) (= 0 (select (select |#memory_int| cstrcat_~append.base) 1))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~append.offset 2) (select |#length| cstrcat_~append.base))) (<= 1 cstrcat_~append.offset)), 3733#(and (<= 2 cstrcat_~append.offset) (or (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (and (= 1 |cstrcat_#t~post3.offset|) (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))), 3734#(and (<= 2 cstrcat_~append.offset) (or (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (= |cstrcat_#t~mem5| 0))), 3735#(and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 2 cstrcat_~append.offset)), 3736#(and (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)) (<= 2 |cstrcat_#t~post3.offset|))] [2018-02-04 15:00:46,967 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 0 proven. 11 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:46,967 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 15:00:46,968 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 15:00:46,968 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-04 15:00:46,968 INFO L87 Difference]: Start difference. First operand 149 states and 169 transitions. Second operand 16 states. [2018-02-04 15:00:47,366 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:47,366 INFO L93 Difference]: Finished difference Result 161 states and 184 transitions. [2018-02-04 15:00:47,366 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 15:00:47,366 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-02-04 15:00:47,367 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:47,367 INFO L225 Difference]: With dead ends: 161 [2018-02-04 15:00:47,367 INFO L226 Difference]: Without dead ends: 161 [2018-02-04 15:00:47,368 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=82, Invalid=470, Unknown=0, NotChecked=0, Total=552 [2018-02-04 15:00:47,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 161 states. [2018-02-04 15:00:47,370 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 161 to 154. [2018-02-04 15:00:47,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 154 states. [2018-02-04 15:00:47,370 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 154 states to 154 states and 176 transitions. [2018-02-04 15:00:47,370 INFO L78 Accepts]: Start accepts. Automaton has 154 states and 176 transitions. Word has length 34 [2018-02-04 15:00:47,370 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:47,370 INFO L432 AbstractCegarLoop]: Abstraction has 154 states and 176 transitions. [2018-02-04 15:00:47,371 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 15:00:47,371 INFO L276 IsEmpty]: Start isEmpty. Operand 154 states and 176 transitions. [2018-02-04 15:00:47,371 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 15:00:47,371 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:47,371 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:47,371 INFO L371 AbstractCegarLoop]: === Iteration 23 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:47,372 INFO L82 PathProgramCache]: Analyzing trace with hash 357476204, now seen corresponding path program 1 times [2018-02-04 15:00:47,372 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:47,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:47,380 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:47,565 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:47,566 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:47,566 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 15:00:47,566 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:47,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:47,566 INFO L182 omatonBuilderFactory]: Interpolants [4068#true, 4069#false, 4070#(<= 1 main_~length3~0), 4071#(<= (+ main_~length1~0 1) main_~length2~0), 4072#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4073#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 4074#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc10.base|))), 4075#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 4076#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 4077#(and (= 0 |cstrcat_#in~s.offset|) (<= (+ (select |#length| |cstrcat_#in~append.base|) 1) (select |#length| |cstrcat_#in~s.base|)) (= 0 |cstrcat_#in~append.offset|)), 4078#(and (<= (+ (select |#length| cstrcat_~append.base) 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 4079#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 4080#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 2 cstrcat_~s.offset)), 4081#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 2 cstrcat_~s.offset)), 4082#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 2 |cstrcat_#t~post2.offset|)), 4083#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:00:47,566 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:47,566 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 15:00:47,567 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 15:00:47,567 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-04 15:00:47,567 INFO L87 Difference]: Start difference. First operand 154 states and 176 transitions. Second operand 16 states. [2018-02-04 15:00:47,898 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:47,898 INFO L93 Difference]: Finished difference Result 187 states and 212 transitions. [2018-02-04 15:00:47,899 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 15:00:47,899 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 34 [2018-02-04 15:00:47,899 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:47,899 INFO L225 Difference]: With dead ends: 187 [2018-02-04 15:00:47,899 INFO L226 Difference]: Without dead ends: 187 [2018-02-04 15:00:47,900 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 104 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=124, Invalid=688, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:00:47,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-02-04 15:00:47,901 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 172. [2018-02-04 15:00:47,901 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 172 states. [2018-02-04 15:00:47,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 172 states to 172 states and 198 transitions. [2018-02-04 15:00:47,902 INFO L78 Accepts]: Start accepts. Automaton has 172 states and 198 transitions. Word has length 34 [2018-02-04 15:00:47,902 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:47,902 INFO L432 AbstractCegarLoop]: Abstraction has 172 states and 198 transitions. [2018-02-04 15:00:47,902 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 15:00:47,902 INFO L276 IsEmpty]: Start isEmpty. Operand 172 states and 198 transitions. [2018-02-04 15:00:47,902 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 15:00:47,902 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:47,903 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:47,903 INFO L371 AbstractCegarLoop]: === Iteration 24 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:47,903 INFO L82 PathProgramCache]: Analyzing trace with hash -679902947, now seen corresponding path program 1 times [2018-02-04 15:00:47,903 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:47,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:47,908 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:48,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:48,002 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 15:00:48,002 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 15:00:48,002 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:48,002 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:48,002 INFO L182 omatonBuilderFactory]: Interpolants [4469#true, 4470#false, 4471#(= |#valid| |old(#valid)|), 4472#(and (= (store |#valid| |main_#t~malloc9.base| 0) |old(#valid)|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4473#(and (= (store (store |#valid| |main_#t~malloc9.base| 0) |main_#t~malloc10.base| 0) |old(#valid)|) (not (= |main_#t~malloc9.base| |main_#t~malloc10.base|))), 4474#(= |old(#valid)| (store |#valid| |main_#t~malloc10.base| 0))] [2018-02-04 15:00:48,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:48,003 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 15:00:48,003 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 15:00:48,003 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 15:00:48,003 INFO L87 Difference]: Start difference. First operand 172 states and 198 transitions. Second operand 6 states. [2018-02-04 15:00:48,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:48,075 INFO L93 Difference]: Finished difference Result 171 states and 197 transitions. [2018-02-04 15:00:48,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 15:00:48,075 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-04 15:00:48,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:48,076 INFO L225 Difference]: With dead ends: 171 [2018-02-04 15:00:48,076 INFO L226 Difference]: Without dead ends: 130 [2018-02-04 15:00:48,076 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-04 15:00:48,076 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-02-04 15:00:48,078 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 125. [2018-02-04 15:00:48,078 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 125 states. [2018-02-04 15:00:48,079 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 125 states to 125 states and 134 transitions. [2018-02-04 15:00:48,079 INFO L78 Accepts]: Start accepts. Automaton has 125 states and 134 transitions. Word has length 35 [2018-02-04 15:00:48,079 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:48,079 INFO L432 AbstractCegarLoop]: Abstraction has 125 states and 134 transitions. [2018-02-04 15:00:48,079 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 15:00:48,079 INFO L276 IsEmpty]: Start isEmpty. Operand 125 states and 134 transitions. [2018-02-04 15:00:48,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 15:00:48,080 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:48,080 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:48,080 INFO L371 AbstractCegarLoop]: === Iteration 25 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:48,080 INFO L82 PathProgramCache]: Analyzing trace with hash -2067683903, now seen corresponding path program 1 times [2018-02-04 15:00:48,081 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:48,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:48,088 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:48,285 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:48,285 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:48,285 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16] total 16 [2018-02-04 15:00:48,285 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:48,286 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:48,286 INFO L182 omatonBuilderFactory]: Interpolants [4775#true, 4776#false, 4777#(<= 1 main_~length3~0), 4778#(<= (+ main_~length1~0 1) main_~length2~0), 4779#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length1~0 1) main_~length2~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 4780#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= (+ main_~length1~0 1) main_~length2~0)), 4781#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= (+ main_~length1~0 1) (select |#length| |main_#t~malloc10.base|))), 4782#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length1~0 1) (select |#length| main_~nondetString2~0.base))), 4783#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= (+ (select |#length| main_~nondetString1~0.base) 1) (select |#length| main_~nondetString2~0.base))), 4784#(and (= 0 |cstrcat_#in~s.offset|) (<= (+ (select |#length| |cstrcat_#in~append.base|) 1) (select |#length| |cstrcat_#in~s.base|)) (= 0 |cstrcat_#in~append.offset|)), 4785#(and (<= (+ (select |#length| cstrcat_~append.base) 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 4786#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset| 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 4787#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 4788#(and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 4789#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 2 cstrcat_~s.offset)), 4790#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset| 1) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 2 |cstrcat_#t~post2.offset|)), 4791#(and (<= (+ |cstrcat_#t~post2.offset| 2) (select |#length| |cstrcat_#t~post2.base|)) (<= 2 |cstrcat_#t~post2.offset|))] [2018-02-04 15:00:48,286 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 3 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:48,286 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 15:00:48,286 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 15:00:48,286 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=236, Unknown=0, NotChecked=0, Total=272 [2018-02-04 15:00:48,287 INFO L87 Difference]: Start difference. First operand 125 states and 134 transitions. Second operand 17 states. [2018-02-04 15:00:48,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:48,617 INFO L93 Difference]: Finished difference Result 135 states and 144 transitions. [2018-02-04 15:00:48,617 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 15:00:48,617 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 35 [2018-02-04 15:00:48,617 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:48,618 INFO L225 Difference]: With dead ends: 135 [2018-02-04 15:00:48,618 INFO L226 Difference]: Without dead ends: 135 [2018-02-04 15:00:48,618 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 28 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=128, Invalid=684, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:00:48,618 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-02-04 15:00:48,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 116. [2018-02-04 15:00:48,620 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 116 states. [2018-02-04 15:00:48,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 116 states to 116 states and 125 transitions. [2018-02-04 15:00:48,620 INFO L78 Accepts]: Start accepts. Automaton has 116 states and 125 transitions. Word has length 35 [2018-02-04 15:00:48,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:48,620 INFO L432 AbstractCegarLoop]: Abstraction has 116 states and 125 transitions. [2018-02-04 15:00:48,621 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 15:00:48,621 INFO L276 IsEmpty]: Start isEmpty. Operand 116 states and 125 transitions. [2018-02-04 15:00:48,621 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 15:00:48,621 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:48,621 INFO L351 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:48,621 INFO L371 AbstractCegarLoop]: === Iteration 26 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:48,621 INFO L82 PathProgramCache]: Analyzing trace with hash 1017556222, now seen corresponding path program 3 times [2018-02-04 15:00:48,622 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:48,632 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:48,633 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:49,175 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:49,175 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:49,175 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-02-04 15:00:49,175 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:49,175 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:49,175 INFO L182 omatonBuilderFactory]: Interpolants [5088#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset)), 5089#(and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 5067#true, 5068#false, 5069#(<= 1 main_~length1~0), 5070#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5071#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5072#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5073#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 5074#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 5075#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 5076#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 5077#(and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= 0 main_~nondetString2~0.offset) (= main_~nondetString1~0.offset 0)), 5078#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (<= 5 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1))))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 5079#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrcat_~s.base))))), 5080#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0) (and (or (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 5081#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= 4 (select |#length| cstrcat_~s.base))))), 5082#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 5083#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0))), 5084#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 5085#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= 2 cstrcat_~s.offset)), 5086#(and (<= 2 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 5087#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:00:49,176 INFO L134 CoverageAnalysis]: Checked inductivity of 32 backedges. 0 proven. 32 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:49,176 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 15:00:49,176 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 15:00:49,176 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=445, Unknown=0, NotChecked=0, Total=506 [2018-02-04 15:00:49,176 INFO L87 Difference]: Start difference. First operand 116 states and 125 transitions. Second operand 23 states. [2018-02-04 15:00:49,770 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:49,770 INFO L93 Difference]: Finished difference Result 141 states and 152 transitions. [2018-02-04 15:00:49,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-04 15:00:49,770 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 36 [2018-02-04 15:00:49,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:49,771 INFO L225 Difference]: With dead ends: 141 [2018-02-04 15:00:49,771 INFO L226 Difference]: Without dead ends: 141 [2018-02-04 15:00:49,771 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 289 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=165, Invalid=1241, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 15:00:49,771 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 141 states. [2018-02-04 15:00:49,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 141 to 124. [2018-02-04 15:00:49,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-04 15:00:49,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 134 transitions. [2018-02-04 15:00:49,774 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 134 transitions. Word has length 36 [2018-02-04 15:00:49,774 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:49,774 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 134 transitions. [2018-02-04 15:00:49,774 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 15:00:49,774 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 134 transitions. [2018-02-04 15:00:49,775 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 15:00:49,775 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:49,775 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:49,775 INFO L371 AbstractCegarLoop]: === Iteration 27 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:49,775 INFO L82 PathProgramCache]: Analyzing trace with hash 1572046895, now seen corresponding path program 2 times [2018-02-04 15:00:49,776 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:49,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:49,785 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:50,124 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:50,124 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:50,124 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-02-04 15:00:50,124 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:50,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:50,124 INFO L182 omatonBuilderFactory]: Interpolants [5385#true, 5386#false, 5387#(<= 1 main_~length3~0), 5388#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 5389#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 5390#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 5391#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 5392#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))), 5393#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)), 5394#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))), 5395#(and (= 0 |cstrcat_#in~s.offset|) (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= (+ (select |#length| |cstrcat_#in~append.base|) 2) (select |#length| |cstrcat_#in~s.base|)))), 5396#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (<= (+ (select |#length| cstrcat_~append.base) 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 5397#(and (or (<= (+ (select |#length| cstrcat_~append.base) 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 5398#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (<= (+ (select |#length| cstrcat_~append.base) 2) (select |#length| cstrcat_~s.base))), 5399#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 5400#(and (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 5401#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 3 cstrcat_~s.offset)), 5402#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 3 cstrcat_~s.offset)), 5403#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 3 |cstrcat_#t~post2.offset|)), 5404#(and (<= 3 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:00:50,124 INFO L134 CoverageAnalysis]: Checked inductivity of 14 backedges. 0 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:50,125 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 15:00:50,125 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 15:00:50,125 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=331, Unknown=0, NotChecked=0, Total=380 [2018-02-04 15:00:50,125 INFO L87 Difference]: Start difference. First operand 124 states and 134 transitions. Second operand 20 states. [2018-02-04 15:00:50,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:50,571 INFO L93 Difference]: Finished difference Result 145 states and 155 transitions. [2018-02-04 15:00:50,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 15:00:50,571 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 38 [2018-02-04 15:00:50,571 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:50,572 INFO L225 Difference]: With dead ends: 145 [2018-02-04 15:00:50,572 INFO L226 Difference]: Without dead ends: 145 [2018-02-04 15:00:50,572 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 205 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=128, Invalid=864, Unknown=0, NotChecked=0, Total=992 [2018-02-04 15:00:50,573 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-04 15:00:50,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 124. [2018-02-04 15:00:50,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-04 15:00:50,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 134 transitions. [2018-02-04 15:00:50,575 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 134 transitions. Word has length 38 [2018-02-04 15:00:50,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:50,575 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 134 transitions. [2018-02-04 15:00:50,575 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 15:00:50,575 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 134 transitions. [2018-02-04 15:00:50,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-02-04 15:00:50,576 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:50,576 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:50,576 INFO L371 AbstractCegarLoop]: === Iteration 28 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:50,576 INFO L82 PathProgramCache]: Analyzing trace with hash 1543171285, now seen corresponding path program 3 times [2018-02-04 15:00:50,576 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:50,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:50,585 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:50,776 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 15:00:50,776 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:50,776 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17] total 17 [2018-02-04 15:00:50,776 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:50,776 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:50,776 INFO L182 omatonBuilderFactory]: Interpolants [5698#true, 5699#false, 5700#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (= (select |#valid| |main_#t~malloc9.base|) 1)), 5701#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (= main_~nondetString1~0.offset 0)), 5702#(and (not (= main_~nondetString1~0.base |main_#t~malloc10.base|)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 5703#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5704#(and (= 0 (select (select (store |#memory_int| main_~nondetString2~0.base (store (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset main_~length3~0 (- 1)) 0)) main_~nondetString1~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (not (= main_~nondetString1~0.base main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 5705#(and (= 0 (select (select |#memory_int| |cstrcat_#in~append.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1)))) (not (= |cstrcat_#in~append.base| |cstrcat_#in~s.base|))), 5706#(and (not (= cstrcat_~append.base cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1))))), 5707#(and (not (= cstrcat_~append.base cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| |cstrcat_#t~post3.base|) (- 1)))) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (not (= |cstrcat_#t~post2.base| cstrcat_~append.base))), 5708#(and (= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (not (= cstrcat_~append.base cstrcat_~s.base))), 5709#(and (= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (not (= |cstrcat_#t~post2.base| cstrcat_~append.base))), 5710#(= 0 (select (select (store |#memory_int| |cstrcat_#t~post2.base| (store (select |#memory_int| |cstrcat_#t~post2.base|) |cstrcat_#t~post2.offset| |cstrcat_#t~mem5|)) cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))), 5711#(= 0 (select (select |#memory_int| cstrcat_~append.base) (+ (select |#length| cstrcat_~append.base) (- 1)))), 5712#(or (= 0 (select (select |#memory_int| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (and (or (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset))), 5713#(or (and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)) (= |cstrcat_#t~mem5| 0)), 5714#(and (<= (+ cstrcat_~append.offset 1) (select |#length| cstrcat_~append.base)) (<= 1 cstrcat_~append.offset)), 5715#(and (<= 1 |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post3.offset| 1) (select |#length| |cstrcat_#t~post3.base|)))] [2018-02-04 15:00:50,777 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 0 proven. 22 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-02-04 15:00:50,777 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 15:00:50,777 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 15:00:50,777 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=263, Unknown=0, NotChecked=0, Total=306 [2018-02-04 15:00:50,777 INFO L87 Difference]: Start difference. First operand 124 states and 134 transitions. Second operand 18 states. [2018-02-04 15:00:51,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:51,064 INFO L93 Difference]: Finished difference Result 123 states and 132 transitions. [2018-02-04 15:00:51,064 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 15:00:51,064 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 39 [2018-02-04 15:00:51,064 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:51,064 INFO L225 Difference]: With dead ends: 123 [2018-02-04 15:00:51,064 INFO L226 Difference]: Without dead ends: 93 [2018-02-04 15:00:51,065 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 82 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=140, Invalid=672, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:00:51,065 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-02-04 15:00:51,066 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 84. [2018-02-04 15:00:51,066 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-02-04 15:00:51,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 88 transitions. [2018-02-04 15:00:51,066 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 88 transitions. Word has length 39 [2018-02-04 15:00:51,067 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:51,067 INFO L432 AbstractCegarLoop]: Abstraction has 84 states and 88 transitions. [2018-02-04 15:00:51,067 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 15:00:51,067 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 88 transitions. [2018-02-04 15:00:51,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-02-04 15:00:51,067 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:51,067 INFO L351 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:51,067 INFO L371 AbstractCegarLoop]: === Iteration 29 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:51,067 INFO L82 PathProgramCache]: Analyzing trace with hash -11114239, now seen corresponding path program 4 times [2018-02-04 15:00:51,068 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:51,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:51,076 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:51,716 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:51,717 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:51,717 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-04 15:00:51,717 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:51,717 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:51,717 INFO L182 omatonBuilderFactory]: Interpolants [5952#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 5953#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 5954#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 5955#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (or (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 5956#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (<= 5 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 5957#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (<= 5 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= cstrcat_~s.offset 0)), 5958#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (<= 5 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0)) (= cstrcat_~s.offset 0)), 5959#(and (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (<= 5 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 5960#(and (= cstrcat_~s.offset 1) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 5961#(and (= cstrcat_~s.offset 1) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0))), 5962#(and (= cstrcat_~s.offset 1) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 5963#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 5964#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 5965#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 5966#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 5967#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 5968#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 5969#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 5970#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 5971#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 5945#true, 5946#false, 5947#(<= 1 main_~length1~0), 5948#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5949#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5950#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 5951#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0))] [2018-02-04 15:00:51,717 INFO L134 CoverageAnalysis]: Checked inductivity of 50 backedges. 0 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:51,717 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 15:00:51,718 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 15:00:51,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=610, Unknown=0, NotChecked=0, Total=702 [2018-02-04 15:00:51,718 INFO L87 Difference]: Start difference. First operand 84 states and 88 transitions. Second operand 27 states. [2018-02-04 15:00:52,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:52,503 INFO L93 Difference]: Finished difference Result 107 states and 113 transitions. [2018-02-04 15:00:52,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 15:00:52,503 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 40 [2018-02-04 15:00:52,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:52,503 INFO L225 Difference]: With dead ends: 107 [2018-02-04 15:00:52,503 INFO L226 Difference]: Without dead ends: 107 [2018-02-04 15:00:52,504 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 462 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=284, Invalid=1696, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 15:00:52,504 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-02-04 15:00:52,505 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 92. [2018-02-04 15:00:52,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-02-04 15:00:52,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 97 transitions. [2018-02-04 15:00:52,505 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 97 transitions. Word has length 40 [2018-02-04 15:00:52,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:52,505 INFO L432 AbstractCegarLoop]: Abstraction has 92 states and 97 transitions. [2018-02-04 15:00:52,505 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 15:00:52,506 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 97 transitions. [2018-02-04 15:00:52,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 15:00:52,506 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:52,506 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:52,506 INFO L371 AbstractCegarLoop]: === Iteration 30 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:52,506 INFO L82 PathProgramCache]: Analyzing trace with hash 862211954, now seen corresponding path program 3 times [2018-02-04 15:00:52,506 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:52,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:52,512 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:52,971 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:52,971 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:52,971 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-04 15:00:52,971 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:52,971 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:52,971 INFO L182 omatonBuilderFactory]: Interpolants [6208#false, 6209#(<= 1 main_~length3~0), 6210#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 6211#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 6212#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 6213#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 6214#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 6215#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 6216#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 6217#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 6218#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset))) (= cstrcat_~s.offset 0)), 6219#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (= |cstrcat_#t~mem1| 0) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 6220#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))), 6221#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 6222#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= |cstrcat_#t~mem1| 0))), 6223#(and (<= cstrcat_~s.offset 1) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (< 0 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 6224#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 6225#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 6226#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (and (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset))), 6227#(or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (and (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset))), 6228#(or (and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset)), 6229#(or (and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 6230#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 6207#true] [2018-02-04 15:00:52,971 INFO L134 CoverageAnalysis]: Checked inductivity of 25 backedges. 0 proven. 25 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:52,972 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 15:00:52,972 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 15:00:52,972 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=488, Unknown=0, NotChecked=0, Total=552 [2018-02-04 15:00:52,972 INFO L87 Difference]: Start difference. First operand 92 states and 97 transitions. Second operand 24 states. [2018-02-04 15:00:53,536 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:53,537 INFO L93 Difference]: Finished difference Result 102 states and 107 transitions. [2018-02-04 15:00:53,537 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-02-04 15:00:53,537 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 42 [2018-02-04 15:00:53,537 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:53,537 INFO L225 Difference]: With dead ends: 102 [2018-02-04 15:00:53,537 INFO L226 Difference]: Without dead ends: 102 [2018-02-04 15:00:53,538 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 319 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=165, Invalid=1241, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 15:00:53,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-02-04 15:00:53,539 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 97. [2018-02-04 15:00:53,539 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-02-04 15:00:53,540 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 102 transitions. [2018-02-04 15:00:53,540 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 102 transitions. Word has length 42 [2018-02-04 15:00:53,540 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:53,540 INFO L432 AbstractCegarLoop]: Abstraction has 97 states and 102 transitions. [2018-02-04 15:00:53,540 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 15:00:53,540 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 102 transitions. [2018-02-04 15:00:53,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-04 15:00:53,541 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:53,541 INFO L351 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:53,541 INFO L371 AbstractCegarLoop]: === Iteration 31 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:53,541 INFO L82 PathProgramCache]: Analyzing trace with hash 737307524, now seen corresponding path program 5 times [2018-02-04 15:00:53,541 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:53,553 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:53,554 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:54,471 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:54,472 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:54,493 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-04 15:00:54,493 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:54,493 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:54,494 INFO L182 omatonBuilderFactory]: Interpolants [6464#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 6465#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 6466#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 6467#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 6468#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ main_~nondetString1~0.offset (+ (select |#length| main_~nondetString2~0.base) (- 1))) (- 1)))))) (and (or (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 6469#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (<= 5 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 6470#(and (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= 6 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 6471#(and (= cstrcat_~s.offset 0) (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= 6 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 6472#(and (= cstrcat_~s.offset 0) (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= 6 (select |#length| cstrcat_~s.base))))), 6473#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 6474#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 6475#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 6476#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 6477#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 6478#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 6479#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 6480#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 6481#(and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 6482#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 6483#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= 0 cstrcat_~s.offset)), 6484#(and (<= 0 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 6485#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 6486#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 6458#true, 6459#false, 6460#(<= 1 main_~length1~0), 6461#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6462#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 6463#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0))] [2018-02-04 15:00:54,494 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:54,494 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 15:00:54,494 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 15:00:54,495 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=710, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:00:54,495 INFO L87 Difference]: Start difference. First operand 97 states and 102 transitions. Second operand 29 states. [2018-02-04 15:00:55,743 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:55,744 INFO L93 Difference]: Finished difference Result 124 states and 131 transitions. [2018-02-04 15:00:55,744 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 15:00:55,744 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 44 [2018-02-04 15:00:55,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:55,745 INFO L225 Difference]: With dead ends: 124 [2018-02-04 15:00:55,745 INFO L226 Difference]: Without dead ends: 124 [2018-02-04 15:00:55,745 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 592 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=335, Invalid=2115, Unknown=0, NotChecked=0, Total=2450 [2018-02-04 15:00:55,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-02-04 15:00:55,747 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 105. [2018-02-04 15:00:55,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-02-04 15:00:55,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 111 transitions. [2018-02-04 15:00:55,748 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 111 transitions. Word has length 44 [2018-02-04 15:00:55,748 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:55,748 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 111 transitions. [2018-02-04 15:00:55,748 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 15:00:55,748 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 111 transitions. [2018-02-04 15:00:55,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-02-04 15:00:55,749 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:55,749 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:55,749 INFO L371 AbstractCegarLoop]: === Iteration 32 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:55,749 INFO L82 PathProgramCache]: Analyzing trace with hash -1458979531, now seen corresponding path program 4 times [2018-02-04 15:00:55,750 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:55,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:55,760 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:56,885 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:56,885 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:56,886 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-04 15:00:56,886 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:56,886 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:56,886 INFO L182 omatonBuilderFactory]: Interpolants [6784#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 6758#true, 6759#false, 6760#(<= 1 main_~length3~0), 6761#(and (<= 1 main_~length3~0) (or (= main_~length2~0 (+ main_~length3~0 main_~length1~0)) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0) 1) (* 2 main_~length2~0)))), 6762#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length3~0) (or (= main_~length2~0 (+ main_~length3~0 main_~length1~0)) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0) 1) (* 2 main_~length2~0))) (= (select |#valid| |main_#t~malloc9.base|) 1)), 6763#(and (or (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= main_~length3~0 (div (+ main_~length2~0 (+ main_~nondetString1~0.offset (- 2))) 2))) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 6764#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (<= main_~length3~0 (div (+ (select |#length| |main_#t~malloc10.base|) (+ main_~nondetString1~0.offset (- 2))) 2))) (= main_~nondetString1~0.offset 0)), 6765#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (or (and (or (= (+ main_~length1~0 1) (+ main_~nondetString2~0.offset main_~length3~0)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString1~0.offset (* 2 main_~length1~0)) (select |#length| main_~nondetString2~0.base))) (<= main_~length3~0 (div (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 2))) 2)) (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~length3~0 1))) (<= 1 main_~length3~0) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (not (= (+ main_~nondetString1~0.offset main_~length1~0) (+ main_~length3~0 1))))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 6766#(and (= 0 main_~nondetString2~0.offset) (or (and (<= (select |#length| main_~nondetString1~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (= (+ main_~nondetString2~0.offset main_~length3~0) (+ (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2) 1)) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (<= (+ (* 2 main_~length3~0) 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 6767#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (select |#length| main_~nondetString1~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (div (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset)) 2))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (<= 6 (+ (* 2 main_~nondetString2~0.offset) (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1))) (= main_~nondetString1~0.offset 0)), 6768#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (and (or (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 2) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (div (select |#length| |cstrcat_#in~s.base|) 2)))) (<= (select |#length| |cstrcat_#in~append.base|) (div (select |#length| |cstrcat_#in~s.base|) 2))) (<= 2 (div (+ (select |#length| |cstrcat_#in~s.base|) (- 2)) 2))) (= 0 |cstrcat_#in~append.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 6769#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 cstrcat_~append.offset) (or (and (<= (select |#length| cstrcat_~append.base) (div (select |#length| cstrcat_~s.base) 2)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (select |#length| cstrcat_~s.base) 2))) (<= (+ (select |#length| cstrcat_~append.base) 1) (div (select |#length| cstrcat_~s.base) 2)))) (<= 6 (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 6770#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (and (<= (select |#length| cstrcat_~append.base) (div (select |#length| cstrcat_~s.base) 2)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (select |#length| cstrcat_~s.base) 2))) (<= (+ (select |#length| cstrcat_~append.base) 1) (div (select |#length| cstrcat_~s.base) 2)))) (<= 6 (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)) (= cstrcat_~s.offset 0)), 6771#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (and (<= (select |#length| cstrcat_~append.base) (div (select |#length| cstrcat_~s.base) 2)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (select |#length| cstrcat_~s.base) 2))) (<= (+ (select |#length| cstrcat_~append.base) 1) (div (select |#length| cstrcat_~s.base) 2)))) (<= 6 (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 6772#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)))))) (= 0 cstrcat_~append.offset)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 6773#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)))))) (= 0 cstrcat_~append.offset))), 6774#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2) 1)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1))) 2)))))) (= 0 cstrcat_~append.offset)), 6775#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 6776#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 6777#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 6778#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 6779#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 6780#(and (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset) (or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 6781#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 6782#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 6783#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))))] [2018-02-04 15:00:56,886 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:56,886 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 15:00:56,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 15:00:56,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=630, Unknown=0, NotChecked=0, Total=702 [2018-02-04 15:00:56,887 INFO L87 Difference]: Start difference. First operand 105 states and 111 transitions. Second operand 27 states. [2018-02-04 15:00:57,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:57,871 INFO L93 Difference]: Finished difference Result 119 states and 125 transitions. [2018-02-04 15:00:57,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 15:00:57,872 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 46 [2018-02-04 15:00:57,872 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:57,872 INFO L225 Difference]: With dead ends: 119 [2018-02-04 15:00:57,872 INFO L226 Difference]: Without dead ends: 119 [2018-02-04 15:00:57,873 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 44 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 436 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=196, Invalid=1696, Unknown=0, NotChecked=0, Total=1892 [2018-02-04 15:00:57,873 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-04 15:00:57,874 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 105. [2018-02-04 15:00:57,874 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-02-04 15:00:57,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 111 transitions. [2018-02-04 15:00:57,874 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 111 transitions. Word has length 46 [2018-02-04 15:00:57,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:57,874 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 111 transitions. [2018-02-04 15:00:57,874 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 15:00:57,874 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 111 transitions. [2018-02-04 15:00:57,875 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 15:00:57,875 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:57,875 INFO L351 BasicCegarLoop]: trace histogram [4, 4, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:57,875 INFO L371 AbstractCegarLoop]: === Iteration 33 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:57,875 INFO L82 PathProgramCache]: Analyzing trace with hash -620008806, now seen corresponding path program 5 times [2018-02-04 15:00:57,875 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:57,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:57,882 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:00:58,424 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:58,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:00:58,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23] total 23 [2018-02-04 15:00:58,424 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:00:58,425 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:58,425 INFO L182 omatonBuilderFactory]: Interpolants [7043#true, 7044#false, 7045#(<= 1 main_~length3~0), 7046#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7047#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7048#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 7049#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 7050#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 7051#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)))), 7052#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7053#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 7054#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset))) (= cstrcat_~s.offset 0)), 7055#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (= |cstrcat_#t~mem1| 0) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (= cstrcat_~s.offset 0)), 7056#(and (= cstrcat_~s.offset 0) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))), 7057#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 7058#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)) (= |cstrcat_#t~mem1| 0))), 7059#(and (<= cstrcat_~s.offset 1) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (< 0 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7060#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7061#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset)), 7062#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (<= 4 cstrcat_~s.offset) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 7063#(and (<= 4 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 7064#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 5 cstrcat_~s.offset)), 7065#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 5 |cstrcat_#t~post2.offset|)), 7066#(and (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)) (<= 5 |cstrcat_#t~post2.offset|))] [2018-02-04 15:00:58,425 INFO L134 CoverageAnalysis]: Checked inductivity of 34 backedges. 4 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:00:58,425 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 15:00:58,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 15:00:58,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=492, Unknown=0, NotChecked=0, Total=552 [2018-02-04 15:00:58,425 INFO L87 Difference]: Start difference. First operand 105 states and 111 transitions. Second operand 24 states. [2018-02-04 15:00:58,942 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:00:58,942 INFO L93 Difference]: Finished difference Result 124 states and 130 transitions. [2018-02-04 15:00:58,943 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-02-04 15:00:58,943 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 47 [2018-02-04 15:00:58,943 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:00:58,943 INFO L225 Difference]: With dead ends: 124 [2018-02-04 15:00:58,943 INFO L226 Difference]: Without dead ends: 109 [2018-02-04 15:00:58,944 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 38 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 329 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=159, Invalid=1323, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 15:00:58,944 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-02-04 15:00:58,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 105. [2018-02-04 15:00:58,945 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-02-04 15:00:58,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 110 transitions. [2018-02-04 15:00:58,946 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 110 transitions. Word has length 47 [2018-02-04 15:00:58,946 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:00:58,946 INFO L432 AbstractCegarLoop]: Abstraction has 105 states and 110 transitions. [2018-02-04 15:00:58,946 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 15:00:58,946 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 110 transitions. [2018-02-04 15:00:58,947 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 49 [2018-02-04 15:00:58,947 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:00:58,947 INFO L351 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:00:58,947 INFO L371 AbstractCegarLoop]: === Iteration 34 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:00:58,947 INFO L82 PathProgramCache]: Analyzing trace with hash -839682937, now seen corresponding path program 6 times [2018-02-04 15:00:58,948 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:00:58,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:00:58,961 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:00,328 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:00,329 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:00,329 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-04 15:01:00,329 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:00,329 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:00,329 INFO L182 omatonBuilderFactory]: Interpolants [7326#true, 7327#false, 7328#(<= 1 main_~length1~0), 7329#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7330#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7331#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 7332#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 7333#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7334#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 7335#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 7336#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 7337#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1))))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 7338#(and (or (and (<= 7 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))))) (= cstrcat_~s.offset 0)), 7339#(and (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0))), 7340#(and (or (and (<= 7 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))))) (= cstrcat_~s.offset 0)), 7341#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 7342#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 7343#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 7344#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 7345#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 7346#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 7347#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7348#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 7349#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7350#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 7351#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 7352#(and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7353#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 7354#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 7355#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 7356#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 7357#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 7358#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:01:00,329 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 0 proven. 98 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:00,330 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 15:01:00,330 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 15:01:00,330 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=145, Invalid=911, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 15:01:00,330 INFO L87 Difference]: Start difference. First operand 105 states and 110 transitions. Second operand 33 states. [2018-02-04 15:01:02,050 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:02,050 INFO L93 Difference]: Finished difference Result 132 states and 139 transitions. [2018-02-04 15:01:02,051 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 15:01:02,051 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 48 [2018-02-04 15:01:02,051 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:02,051 INFO L225 Difference]: With dead ends: 132 [2018-02-04 15:01:02,051 INFO L226 Difference]: Without dead ends: 132 [2018-02-04 15:01:02,052 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 808 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=481, Invalid=2711, Unknown=0, NotChecked=0, Total=3192 [2018-02-04 15:01:02,052 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-02-04 15:01:02,054 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 113. [2018-02-04 15:01:02,054 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-04 15:01:02,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 119 transitions. [2018-02-04 15:01:02,054 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 119 transitions. Word has length 48 [2018-02-04 15:01:02,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:02,055 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 119 transitions. [2018-02-04 15:01:02,055 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 15:01:02,055 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 119 transitions. [2018-02-04 15:01:02,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-04 15:01:02,055 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:02,055 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:02,056 INFO L371 AbstractCegarLoop]: === Iteration 35 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:02,056 INFO L82 PathProgramCache]: Analyzing trace with hash -823357064, now seen corresponding path program 6 times [2018-02-04 15:01:02,056 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:02,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:02,072 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:02,594 WARN L146 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 105 DAG size of output 32 [2018-02-04 15:01:02,843 WARN L146 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 117 DAG size of output 62 [2018-02-04 15:01:03,907 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 0 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:03,907 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:03,907 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-04 15:01:03,908 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:03,908 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:03,909 INFO L182 omatonBuilderFactory]: Interpolants [7680#(and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 7652#true, 7653#false, 7654#(<= 1 main_~length3~0), 7655#(and (<= 1 main_~length3~0) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0)) (* 2 main_~length2~0))), 7656#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= 1 main_~length3~0) (<= (+ (* 2 main_~length3~0) (* 2 main_~length1~0)) (* 2 main_~length2~0)) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7657#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 7658#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7659#(and (or (and (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= 0 main_~nondetString2~0.offset)), 7660#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 3) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ (* 2 main_~length3~0) 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)))), 7661#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) 1) (+ main_~nondetString1~0.offset (- 1)))))) (<= 7 (+ (* 2 main_~nondetString2~0.offset) (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) 2)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base))) (select |#length| main_~nondetString2~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (or (<= 3 (select |#length| main_~nondetString1~0.base)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base)))))) (= main_~nondetString1~0.offset 0)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7662#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (div (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 2) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~append.base|) 2) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 3) (select |#length| |cstrcat_#in~s.base|))))) (<= (select |#length| |cstrcat_#in~append.base|) (div (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) 2))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (select |#length| |cstrcat_#in~append.base|))) (<= 3 (select |#length| |cstrcat_#in~append.base|))) (<= (* 2 (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1))))) (<= 7 (select |#length| |cstrcat_#in~s.base|)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 7663#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (<= 7 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (<= 3 (select |#length| cstrcat_~append.base))) (<= (* 2 (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1))))))) (<= (select |#length| cstrcat_~append.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 7664#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (<= 7 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (<= 3 (select |#length| cstrcat_~append.base))) (<= (* 2 (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1))))))) (<= (select |#length| cstrcat_~append.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (= |cstrcat_#t~mem1| 0))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 7665#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (<= 7 (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (<= 3 (select |#length| cstrcat_~append.base))) (<= (* 2 (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1))))))) (<= (select |#length| cstrcat_~append.base) (div (+ (select |#length| cstrcat_~s.base) (- 1)) 2)))))) (= cstrcat_~s.offset 0)), 7666#(or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1)) (or (<= 3 (select |#length| cstrcat_~append.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2) 1))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 7667#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1)) (or (<= 3 (select |#length| cstrcat_~append.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2) 1))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset))), 7668#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1)) (or (<= 3 (select |#length| cstrcat_~append.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (div (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 2))) 2) 1))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7669#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))))), 7670#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)))), 7671#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 7672#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 7673#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= 3 cstrcat_~s.offset))), 7674#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 7675#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 7676#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset))), 7677#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (and (<= 6 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 7678#(or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (and (<= 6 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 7679#(or (and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|))] [2018-02-04 15:01:03,909 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 0 proven. 59 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:03,909 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 15:01:03,909 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 15:01:03,910 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=738, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:01:03,910 INFO L87 Difference]: Start difference. First operand 113 states and 119 transitions. Second operand 29 states. [2018-02-04 15:01:04,462 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 102 DAG size of output 101 [2018-02-04 15:01:04,795 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 111 DAG size of output 110 [2018-02-04 15:01:05,600 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:05,600 INFO L93 Difference]: Finished difference Result 127 states and 133 transitions. [2018-02-04 15:01:05,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 15:01:05,601 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 50 [2018-02-04 15:01:05,601 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:05,601 INFO L225 Difference]: With dead ends: 127 [2018-02-04 15:01:05,601 INFO L226 Difference]: Without dead ends: 127 [2018-02-04 15:01:05,602 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 520 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=197, Invalid=2059, Unknown=0, NotChecked=0, Total=2256 [2018-02-04 15:01:05,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-02-04 15:01:05,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 113. [2018-02-04 15:01:05,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-02-04 15:01:05,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 119 transitions. [2018-02-04 15:01:05,605 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 119 transitions. Word has length 50 [2018-02-04 15:01:05,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:05,605 INFO L432 AbstractCegarLoop]: Abstraction has 113 states and 119 transitions. [2018-02-04 15:01:05,605 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 15:01:05,605 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 119 transitions. [2018-02-04 15:01:05,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-04 15:01:05,606 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:05,606 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:05,606 INFO L371 AbstractCegarLoop]: === Iteration 36 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:05,606 INFO L82 PathProgramCache]: Analyzing trace with hash 1904418487, now seen corresponding path program 7 times [2018-02-04 15:01:05,607 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:05,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:05,619 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:06,627 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:06,627 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:06,627 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26] total 26 [2018-02-04 15:01:06,628 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:06,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:06,628 INFO L182 omatonBuilderFactory]: Interpolants [7959#true, 7960#false, 7961#(<= 1 main_~length3~0), 7962#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 7963#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 7964#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 7965#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 7966#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))), 7967#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)), 7968#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 7969#(and (= 0 |cstrcat_#in~s.offset|) (= 0 |cstrcat_#in~append.offset|) (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|)) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 7970#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 7971#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 7972#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 7973#(and (or (and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))) (= 0 cstrcat_~append.offset)), 7974#(and (= 0 cstrcat_~append.offset) (or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))))), 7975#(and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 7976#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 2))), 7977#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2) (= |cstrcat_#t~mem1| 0)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 7978#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 7979#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 7980#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))), 7981#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 1))) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset 1)) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= 5 cstrcat_~s.offset)), 7982#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) (* 2 cstrcat_~append.offset) 2))) (<= 5 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset 1))), 7983#(and (<= 6 cstrcat_~s.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) (* 2 cstrcat_~append.offset) 1)) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset 1))), 7984#(and (<= 6 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 7985#(and (<= 6 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:01:06,628 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 0 proven. 49 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:06,628 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 15:01:06,628 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 15:01:06,629 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=634, Unknown=0, NotChecked=0, Total=702 [2018-02-04 15:01:06,629 INFO L87 Difference]: Start difference. First operand 113 states and 119 transitions. Second operand 27 states. [2018-02-04 15:01:07,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:07,427 INFO L93 Difference]: Finished difference Result 132 states and 138 transitions. [2018-02-04 15:01:07,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-04 15:01:07,427 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 51 [2018-02-04 15:01:07,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:07,428 INFO L225 Difference]: With dead ends: 132 [2018-02-04 15:01:07,428 INFO L226 Difference]: Without dead ends: 132 [2018-02-04 15:01:07,428 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 42 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 400 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=173, Invalid=1633, Unknown=0, NotChecked=0, Total=1806 [2018-02-04 15:01:07,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-02-04 15:01:07,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 118. [2018-02-04 15:01:07,429 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-04 15:01:07,429 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 124 transitions. [2018-02-04 15:01:07,430 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 124 transitions. Word has length 51 [2018-02-04 15:01:07,430 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:07,430 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 124 transitions. [2018-02-04 15:01:07,430 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 15:01:07,430 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 124 transitions. [2018-02-04 15:01:07,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-02-04 15:01:07,430 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:07,430 INFO L351 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:07,430 INFO L371 AbstractCegarLoop]: === Iteration 37 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:07,430 INFO L82 PathProgramCache]: Analyzing trace with hash 108151818, now seen corresponding path program 7 times [2018-02-04 15:01:07,431 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:07,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:07,440 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:07,921 WARN L146 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 125 DAG size of output 62 [2018-02-04 15:01:09,436 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:09,436 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:09,436 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34] total 34 [2018-02-04 15:01:09,436 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:09,436 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:09,437 INFO L182 omatonBuilderFactory]: Interpolants [8268#true, 8269#false, 8270#(<= 1 main_~length1~0), 8271#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8272#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8273#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 8274#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 8275#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 8276#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8277#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 8278#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (- 1))))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 8279#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (<= 7 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (or (<= 9 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 8280#(and (= cstrcat_~s.offset 0) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 8 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1))))))), 8281#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 8 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 8282#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 8 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 8283#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 8284#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 8285#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 8286#(or (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8287#(or (and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 8288#(and (<= 2 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 8289#(or (and (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (<= 3 cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8290#(or (and (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (<= 3 cstrcat_~s.offset)) (= |cstrcat_#t~mem1| 0)), 8291#(and (or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (<= 3 cstrcat_~s.offset)), 8292#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 4 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))))), 8293#(or (and (<= 4 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 8294#(and (<= 4 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 8295#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8296#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset)) (= |cstrcat_#t~mem1| 0)), 8297#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset)), 8298#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 6 cstrcat_~s.offset)), 8299#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 6 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 8300#(and (<= 6 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 8301#(and (<= 7 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 8302#(and (<= 8 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:01:09,437 INFO L134 CoverageAnalysis]: Checked inductivity of 128 backedges. 0 proven. 128 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:09,437 INFO L409 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-02-04 15:01:09,437 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-02-04 15:01:09,437 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=1097, Unknown=0, NotChecked=0, Total=1190 [2018-02-04 15:01:09,437 INFO L87 Difference]: Start difference. First operand 118 states and 124 transitions. Second operand 35 states. [2018-02-04 15:01:11,300 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:11,300 INFO L93 Difference]: Finished difference Result 149 states and 157 transitions. [2018-02-04 15:01:11,300 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-04 15:01:11,300 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 52 [2018-02-04 15:01:11,300 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:11,301 INFO L225 Difference]: With dead ends: 149 [2018-02-04 15:01:11,301 INFO L226 Difference]: Without dead ends: 149 [2018-02-04 15:01:11,301 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 853 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=269, Invalid=3513, Unknown=0, NotChecked=0, Total=3782 [2018-02-04 15:01:11,302 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-02-04 15:01:11,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 126. [2018-02-04 15:01:11,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-04 15:01:11,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 133 transitions. [2018-02-04 15:01:11,303 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 133 transitions. Word has length 52 [2018-02-04 15:01:11,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:11,303 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 133 transitions. [2018-02-04 15:01:11,303 INFO L433 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-02-04 15:01:11,303 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 133 transitions. [2018-02-04 15:01:11,303 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-02-04 15:01:11,303 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:11,304 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:11,304 INFO L371 AbstractCegarLoop]: === Iteration 38 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:11,304 INFO L82 PathProgramCache]: Analyzing trace with hash -487224261, now seen corresponding path program 8 times [2018-02-04 15:01:11,304 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:11,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:11,320 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:12,605 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 0 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:12,605 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:12,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-04 15:01:12,605 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:12,606 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:12,606 INFO L182 omatonBuilderFactory]: Interpolants [8640#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))), 8641#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 4) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 3) (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 8642#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|)))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|)))) (= 0 |cstrcat_#in~append.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 8643#(and (= cstrcat_~s.offset 0) (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8644#(and (= cstrcat_~s.offset 0) (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 8645#(and (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1))) (= cstrcat_~s.offset 0)), 8646#(or (and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8647#(or (and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0))), 8648#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 8649#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8650#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))))) (= |cstrcat_#t~mem1| 0)), 8651#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 2 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))))), 8652#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8653#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)), 8654#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 3 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 8655#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 8656#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 8657#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 8658#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= 5 cstrcat_~s.offset))), 8659#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 6 cstrcat_~s.offset))), 8660#(or (and (<= 7 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset))), 8661#(or (and (<= 7 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset)), 8662#(or (and (<= 7 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 8663#(and (<= 7 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 8632#true, 8633#false, 8634#(<= 1 main_~length3~0), 8635#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8636#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 8637#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 8638#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 8639#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0))] [2018-02-04 15:01:12,606 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 0 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:12,606 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-04 15:01:12,606 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-04 15:01:12,606 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=82, Invalid=910, Unknown=0, NotChecked=0, Total=992 [2018-02-04 15:01:12,607 INFO L87 Difference]: Start difference. First operand 126 states and 133 transitions. Second operand 32 states. [2018-02-04 15:01:13,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:13,967 INFO L93 Difference]: Finished difference Result 144 states and 151 transitions. [2018-02-04 15:01:13,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 15:01:13,968 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 54 [2018-02-04 15:01:13,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:13,968 INFO L225 Difference]: With dead ends: 144 [2018-02-04 15:01:13,968 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 15:01:13,969 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 669 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=223, Invalid=2639, Unknown=0, NotChecked=0, Total=2862 [2018-02-04 15:01:13,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 15:01:13,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 126. [2018-02-04 15:01:13,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-04 15:01:13,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 133 transitions. [2018-02-04 15:01:13,970 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 133 transitions. Word has length 54 [2018-02-04 15:01:13,971 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:13,971 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 133 transitions. [2018-02-04 15:01:13,971 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-04 15:01:13,971 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 133 transitions. [2018-02-04 15:01:13,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-02-04 15:01:13,971 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:13,971 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:13,971 INFO L371 AbstractCegarLoop]: === Iteration 39 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:13,971 INFO L82 PathProgramCache]: Analyzing trace with hash -560366508, now seen corresponding path program 9 times [2018-02-04 15:01:13,972 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:13,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:13,981 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:15,237 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:15,237 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:15,237 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-02-04 15:01:15,237 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:15,237 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:15,238 INFO L182 omatonBuilderFactory]: Interpolants [8978#true, 8979#false, 8980#(<= 1 main_~length3~0), 8981#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 8982#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 8983#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 8984#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 8985#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 8986#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2))), 8987#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (not (= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (select |#length| main_~nondetString1~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ (select |#length| main_~nondetString1~0.base) 1))) (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 8988#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (select |#length| |cstrcat_#in~append.base|))) (not (= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (+ (select |#length| |cstrcat_#in~append.base|) 1))) (- 1)))))) (= 0 |cstrcat_#in~append.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 8989#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (+ (select |#length| cstrcat_~append.base) 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8990#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (+ (select |#length| cstrcat_~append.base) 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 8991#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (+ (select |#length| cstrcat_~append.base) 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 8992#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (or (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (- 1)))) (- 1)))))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 8993#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (or (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (- 1)))) (- 1)))))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0))), 8994#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (or (not (= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (- 1)))) (- 1)))))))), 8995#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))))) (not (= (select |#length| cstrcat_~append.base) 3)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 8996#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))))) (not (= (select |#length| cstrcat_~append.base) 3)))) (= |cstrcat_#t~mem1| 0)), 8997#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))))) (not (= (select |#length| cstrcat_~append.base) 3)))), 8998#(or (and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 2))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))), 8999#(or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (or (<= (select |#length| cstrcat_~append.base) 2) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset))), 9000#(or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 2))), 9001#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 9002#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 9003#(or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (and (<= (select |#length| |cstrcat_#t~post3.base|) 2) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset))), 9004#(or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))), 9005#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 9006#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 9007#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 9008#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:01:15,238 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 68 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:15,238 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 15:01:15,238 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 15:01:15,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=832, Unknown=0, NotChecked=0, Total=930 [2018-02-04 15:01:15,238 INFO L87 Difference]: Start difference. First operand 126 states and 133 transitions. Second operand 31 states. [2018-02-04 15:01:16,644 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:16,787 INFO L93 Difference]: Finished difference Result 154 states and 161 transitions. [2018-02-04 15:01:16,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 15:01:16,787 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 55 [2018-02-04 15:01:16,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:16,788 INFO L225 Difference]: With dead ends: 154 [2018-02-04 15:01:16,788 INFO L226 Difference]: Without dead ends: 154 [2018-02-04 15:01:16,788 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 639 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=289, Invalid=2261, Unknown=0, NotChecked=0, Total=2550 [2018-02-04 15:01:16,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-04 15:01:16,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 126. [2018-02-04 15:01:16,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-02-04 15:01:16,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 133 transitions. [2018-02-04 15:01:16,790 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 133 transitions. Word has length 55 [2018-02-04 15:01:16,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:16,790 INFO L432 AbstractCegarLoop]: Abstraction has 126 states and 133 transitions. [2018-02-04 15:01:16,790 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 15:01:16,790 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 133 transitions. [2018-02-04 15:01:16,790 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 15:01:16,790 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:16,790 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 4, 4, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:16,790 INFO L371 AbstractCegarLoop]: === Iteration 40 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:16,791 INFO L82 PathProgramCache]: Analyzing trace with hash 1888771701, now seen corresponding path program 10 times [2018-02-04 15:01:16,791 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:16,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:16,797 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:17,376 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:17,376 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:17,377 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-04 15:01:17,377 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:17,377 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:17,377 INFO L182 omatonBuilderFactory]: Interpolants [9344#(or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 9345#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 9346#(and (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 9347#(and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset)), 9348#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 9349#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 9350#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 9351#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 2)) (= |cstrcat_#t~post3.offset| 0)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 9352#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 2))), 9353#(or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))), 9354#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 9355#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 9356#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 9357#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 9329#true, 9330#false, 9331#(<= 1 main_~length3~0), 9332#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 9333#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 9334#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 9335#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 9336#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))))), 9337#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 1) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= 1 main_~length3~0)))), 9338#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 9339#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 9340#(and (or (and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1))) (= cstrcat_~s.offset 0)), 9341#(and (= cstrcat_~s.offset 0) (or (and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 9342#(and (or (and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1))) (= cstrcat_~s.offset 0)), 9343#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))))] [2018-02-04 15:01:17,377 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 0 proven. 63 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:17,377 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 15:01:17,377 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 15:01:17,377 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=88, Invalid=724, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:01:17,378 INFO L87 Difference]: Start difference. First operand 126 states and 133 transitions. Second operand 29 states. [2018-02-04 15:01:18,319 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:18,320 INFO L93 Difference]: Finished difference Result 154 states and 161 transitions. [2018-02-04 15:01:18,320 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 15:01:18,320 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 56 [2018-02-04 15:01:18,320 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:18,320 INFO L225 Difference]: With dead ends: 154 [2018-02-04 15:01:18,320 INFO L226 Difference]: Without dead ends: 154 [2018-02-04 15:01:18,321 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 653 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=281, Invalid=2371, Unknown=0, NotChecked=0, Total=2652 [2018-02-04 15:01:18,321 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-02-04 15:01:18,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 131. [2018-02-04 15:01:18,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 131 states. [2018-02-04 15:01:18,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 131 states to 131 states and 138 transitions. [2018-02-04 15:01:18,322 INFO L78 Accepts]: Start accepts. Automaton has 131 states and 138 transitions. Word has length 56 [2018-02-04 15:01:18,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:18,322 INFO L432 AbstractCegarLoop]: Abstraction has 131 states and 138 transitions. [2018-02-04 15:01:18,322 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 15:01:18,322 INFO L276 IsEmpty]: Start isEmpty. Operand 131 states and 138 transitions. [2018-02-04 15:01:18,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 15:01:18,323 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:18,323 INFO L351 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:18,323 INFO L371 AbstractCegarLoop]: === Iteration 41 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:18,323 INFO L82 PathProgramCache]: Analyzing trace with hash 1009228301, now seen corresponding path program 8 times [2018-02-04 15:01:18,323 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:18,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:18,334 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:19,060 WARN L146 SmtUtils]: Spent 226ms on a formula simplification. DAG size of input: 171 DAG size of output 69 [2018-02-04 15:01:19,215 WARN L146 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 133 DAG size of output 59 [2018-02-04 15:01:19,352 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 133 DAG size of output 59 [2018-02-04 15:01:19,496 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 135 DAG size of output 59 [2018-02-04 15:01:19,635 WARN L146 SmtUtils]: Spent 113ms on a formula simplification. DAG size of input: 133 DAG size of output 57 [2018-02-04 15:01:19,808 WARN L146 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 149 DAG size of output 67 [2018-02-04 15:01:19,992 WARN L146 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 151 DAG size of output 67 [2018-02-04 15:01:20,150 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 149 DAG size of output 65 [2018-02-04 15:01:21,184 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:21,184 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:21,184 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38] total 38 [2018-02-04 15:01:21,184 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:21,184 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:21,185 INFO L182 omatonBuilderFactory]: Interpolants [9689#true, 9690#false, 9691#(<= 1 main_~length1~0), 9692#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9693#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9694#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 9695#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 9696#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 9697#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 9698#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 9699#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1))))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 9700#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (or (<= 10 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1))))) (<= 9 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 9701#(and (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))))), 9702#(and (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0))), 9703#(and (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))))) (= cstrcat_~s.offset 0)), 9704#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 9705#(and (or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 9706#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 9707#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 9708#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 9709#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 9710#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 9711#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 9712#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 9713#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 9714#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 9715#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 9716#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 9717#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 9718#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 9719#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 9720#(or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 9721#(and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 9722#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 9723#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 9724#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 9725#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 9726#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 9727#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:01:21,185 INFO L134 CoverageAnalysis]: Checked inductivity of 162 backedges. 0 proven. 162 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:21,185 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-02-04 15:01:21,185 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-02-04 15:01:21,186 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=218, Invalid=1264, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 15:01:21,186 INFO L87 Difference]: Start difference. First operand 131 states and 138 transitions. Second operand 39 states. [2018-02-04 15:01:21,915 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 118 DAG size of output 117 [2018-02-04 15:01:23,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:23,831 INFO L93 Difference]: Finished difference Result 172 states and 181 transitions. [2018-02-04 15:01:23,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 15:01:23,831 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 56 [2018-02-04 15:01:23,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:23,832 INFO L225 Difference]: With dead ends: 172 [2018-02-04 15:01:23,832 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 15:01:23,832 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 68 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 67 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1247 ImplicationChecksByTransitivity, 4.7s TimeCoverageRelationStatistics Valid=746, Invalid=3946, Unknown=0, NotChecked=0, Total=4692 [2018-02-04 15:01:23,832 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 15:01:23,834 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 139. [2018-02-04 15:01:23,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-04 15:01:23,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-04 15:01:23,834 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 56 [2018-02-04 15:01:23,834 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:23,834 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-04 15:01:23,834 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-02-04 15:01:23,834 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-04 15:01:23,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-02-04 15:01:23,835 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:23,835 INFO L351 BasicCegarLoop]: trace histogram [8, 8, 7, 7, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:23,835 INFO L371 AbstractCegarLoop]: === Iteration 42 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:23,835 INFO L82 PathProgramCache]: Analyzing trace with hash -2136117890, now seen corresponding path program 11 times [2018-02-04 15:01:23,835 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:23,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:23,852 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:24,597 WARN L146 SmtUtils]: Spent 223ms on a formula simplification. DAG size of input: 154 DAG size of output 103 [2018-02-04 15:01:24,833 WARN L146 SmtUtils]: Spent 217ms on a formula simplification. DAG size of input: 127 DAG size of output 84 [2018-02-04 15:01:25,047 WARN L146 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 127 DAG size of output 84 [2018-02-04 15:01:25,261 WARN L146 SmtUtils]: Spent 189ms on a formula simplification. DAG size of input: 129 DAG size of output 84 [2018-02-04 15:01:25,477 WARN L146 SmtUtils]: Spent 188ms on a formula simplification. DAG size of input: 127 DAG size of output 82 [2018-02-04 15:01:25,694 WARN L146 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 150 DAG size of output 93 [2018-02-04 15:01:25,917 WARN L146 SmtUtils]: Spent 193ms on a formula simplification. DAG size of input: 152 DAG size of output 93 [2018-02-04 15:01:26,135 WARN L146 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 150 DAG size of output 90 [2018-02-04 15:01:27,147 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:27,148 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:27,148 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-04 15:01:27,148 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:27,148 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:27,148 INFO L182 omatonBuilderFactory]: Interpolants [10112#(and (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (and (<= 3 (div (select |#length| cstrcat_~s.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (select |#length| cstrcat_~s.base) 2) (- 1))))) (<= 9 (select |#length| cstrcat_~s.base)) (and (<= 3 (div (+ (select |#length| cstrcat_~s.base) (- 2)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 10113#(and (= cstrcat_~s.offset 1) (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset 2)) (- 1)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2) (- 1)))) (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2))))), 10114#(and (= cstrcat_~s.offset 1) (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset 2)) (- 1)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2) (- 1)))) (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2))) (= |cstrcat_#t~mem1| 0))), 10115#(and (= cstrcat_~s.offset 1) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset 2)) (- 1)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 3))) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2) (- 1)))) (<= (+ cstrcat_~s.offset 2) (div (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))) 2)))) (= 0 cstrcat_~append.offset)), 10116#(and (= 0 cstrcat_~append.offset) (or (and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (select |#length| cstrcat_~append.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (<= (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (<= cstrcat_~s.offset 2)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 10117#(and (= 0 cstrcat_~append.offset) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (or (not (= cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (<= (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (<= cstrcat_~s.offset 2)))), 10118#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (not (= cstrcat_~s.offset (select |#length| cstrcat_~append.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (select |#length| cstrcat_~append.base)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))))) (<= (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (<= cstrcat_~s.offset 2))) (= 0 cstrcat_~append.offset)), 10119#(or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 10120#(or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 10121#(and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 10122#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= 0 cstrcat_~append.offset)), 10123#(and (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (= |cstrcat_#t~mem1| 0))), 10124#(and (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))))), 10125#(and (or (and (or (<= (select |#length| cstrcat_~append.base) 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset)), 10126#(and (or (and (or (<= (select |#length| cstrcat_~append.base) 1) (= |cstrcat_#t~mem1| 0)) (<= (select |#length| cstrcat_~append.base) 2)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset)), 10127#(and (= 0 cstrcat_~append.offset) (or (<= (select |#length| cstrcat_~append.base) 1) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 10128#(and (or (<= (select |#length| cstrcat_~append.base) 1) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset)), 10129#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 cstrcat_~append.offset)), 10130#(and (or (< 1 (select |#length| |cstrcat_#t~post3.base|)) (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ |cstrcat_#t~post3.offset| 1) cstrcat_~append.offset))) (or (<= (select |#length| |cstrcat_#t~post3.base|) 1) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 10131#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 10132#(and (<= 1 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 10133#(and (<= 1 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 10134#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 10099#true, 10100#false, 10101#(<= 1 main_~length3~0), 10102#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10103#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 10104#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10105#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 10106#(and (= 0 main_~nondetString2~0.offset) (or (and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)))) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 10107#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 1 main_~length3~0) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (<= (+ main_~nondetString2~0.offset main_~length3~0) (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 10108#(and (= 0 main_~nondetString2~0.offset) (or (and (<= 3 (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (+ (- main_~nondetString1~0.offset) (- 2)))) 2) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString1~0.offset) 3) (+ main_~nondetString1~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 9 (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (<= 3 (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset))) 2) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (div (+ main_~nondetString2~0.offset (+ (select |#length| main_~nondetString2~0.base) (- main_~nondetString1~0.offset))) 2) (+ main_~nondetString1~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) 3)))) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (or (<= (+ (* 2 (select |#length| main_~nondetString1~0.base)) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (+ (select |#length| main_~nondetString2~0.base) (- 1))) (+ main_~nondetString2~0.offset (- 1)))))) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))))))) (= main_~nondetString1~0.offset 0)), 10109#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 3 (div (+ (select |#length| |cstrcat_#in~s.base|) (- 2)) 2))) (and (or (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 5) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (+ (select |#length| |cstrcat_#in~s.base|) (- 1))) (- 1))))) (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|)))))) (<= 9 (select |#length| |cstrcat_#in~s.base|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 3)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (div (select |#length| |cstrcat_#in~s.base|) 2) (- 1)))) (<= 3 (div (select |#length| |cstrcat_#in~s.base|) 2))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1))) (= 0 |cstrcat_#in~append.offset|)), 10110#(and (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (and (<= 3 (div (select |#length| cstrcat_~s.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (select |#length| cstrcat_~s.base) 2) (- 1))))) (<= 9 (select |#length| cstrcat_~s.base)) (and (<= 3 (div (+ (select |#length| cstrcat_~s.base) (- 2)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 10111#(and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))))) (and (<= 3 (div (select |#length| cstrcat_~s.base) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (div (select |#length| cstrcat_~s.base) 2) (- 1))))) (<= 9 (select |#length| cstrcat_~s.base)) (and (<= 3 (div (+ (select |#length| cstrcat_~s.base) (- 2)) 2)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))) (<= 7 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (= cstrcat_~s.offset 0))] [2018-02-04 15:01:27,148 INFO L134 CoverageAnalysis]: Checked inductivity of 109 backedges. 0 proven. 109 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:27,149 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 15:01:27,149 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 15:01:27,149 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=1122, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 15:01:27,149 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 36 states. [2018-02-04 15:01:27,496 WARN L146 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 133 DAG size of output 131 [2018-02-04 15:01:27,788 WARN L143 SmtUtils]: Spent 102ms on a formula simplification that was a NOOP. DAG size: 154 [2018-02-04 15:01:28,322 WARN L146 SmtUtils]: Spent 223ms on a formula simplification. DAG size of input: 172 DAG size of output 171 [2018-02-04 15:01:28,652 WARN L146 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 159 DAG size of output 157 [2018-02-04 15:01:28,912 WARN L146 SmtUtils]: Spent 217ms on a formula simplification. DAG size of input: 169 DAG size of output 164 [2018-02-04 15:01:29,136 WARN L146 SmtUtils]: Spent 192ms on a formula simplification. DAG size of input: 155 DAG size of output 154 [2018-02-04 15:01:29,307 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 130 DAG size of output 125 [2018-02-04 15:01:29,484 WARN L146 SmtUtils]: Spent 144ms on a formula simplification. DAG size of input: 137 DAG size of output 129 [2018-02-04 15:01:29,707 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 115 DAG size of output 113 [2018-02-04 15:01:29,880 WARN L146 SmtUtils]: Spent 141ms on a formula simplification. DAG size of input: 121 DAG size of output 116 [2018-02-04 15:01:30,280 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 109 DAG size of output 108 [2018-02-04 15:01:30,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:30,633 INFO L93 Difference]: Finished difference Result 172 states and 180 transitions. [2018-02-04 15:01:30,633 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-04 15:01:30,633 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 58 [2018-02-04 15:01:30,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:30,634 INFO L225 Difference]: With dead ends: 172 [2018-02-04 15:01:30,634 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 15:01:30,635 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 998 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=457, Invalid=3325, Unknown=0, NotChecked=0, Total=3782 [2018-02-04 15:01:30,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 15:01:30,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 139. [2018-02-04 15:01:30,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-04 15:01:30,636 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-04 15:01:30,637 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 58 [2018-02-04 15:01:30,637 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:30,637 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-04 15:01:30,637 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 15:01:30,637 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-04 15:01:30,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 15:01:30,637 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:30,637 INFO L351 BasicCegarLoop]: trace histogram [7, 7, 6, 6, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:30,637 INFO L371 AbstractCegarLoop]: === Iteration 43 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:30,638 INFO L82 PathProgramCache]: Analyzing trace with hash -136461455, now seen corresponding path program 12 times [2018-02-04 15:01:30,638 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:30,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:30,652 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:31,374 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 197 DAG size of output 87 [2018-02-04 15:01:31,521 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 130 DAG size of output 69 [2018-02-04 15:01:32,838 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:32,838 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:32,838 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32] total 32 [2018-02-04 15:01:32,838 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:32,838 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:32,839 INFO L182 omatonBuilderFactory]: Interpolants [10498#true, 10499#false, 10500#(<= 1 main_~length3~0), 10501#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10502#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 10503#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10504#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 10505#(and (= 0 main_~nondetString2~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10506#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (= main_~nondetString1~0.offset 0)), 10507#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) 1))) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset 1))) (+ main_~nondetString2~0.offset (+ (- main_~nondetString1~0.offset) (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (+ (- main_~nondetString2~0.offset) 3)) (+ (select |#length| main_~nondetString2~0.base) (- 1))) (+ main_~nondetString1~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 2) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString1~0.base) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset 2))) (- 1))))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- (+ (- (+ (- main_~nondetString2~0.offset) 3)) (select |#length| main_~nondetString2~0.base))) (select |#length| main_~nondetString2~0.base)) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= main_~nondetString1~0.offset 0)), 10508#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 3 1) (- 1)) (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~append.base|) 1) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (<= 9 (select |#length| |cstrcat_#in~s.base|)) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- 3) (+ (select |#length| |cstrcat_#in~s.base|) (- 1))) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (+ (- 3) (select |#length| |cstrcat_#in~s.base|))) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 2) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~append.base|) 2) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 3) (select |#length| |cstrcat_#in~s.base|))))) (= 0 |cstrcat_#in~append.offset|)), 10509#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s.base))) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1))))))), 10510#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s.base))) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1))))) (= |cstrcat_#t~mem1| 0))), 10511#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) (- 1)) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- 3) (select |#length| cstrcat_~s.base))) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (select |#length| cstrcat_~s.base)) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) 2) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- 3) (+ (select |#length| cstrcat_~s.base) (- 1))) (- 1))))))), 10512#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))))) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 1) (- 1))))))), 10513#(and (<= 1 cstrcat_~s.offset) (or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))))) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 1) (- 1)))))) (= 0 cstrcat_~append.offset)), 10514#(and (<= 1 cstrcat_~s.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 2)))) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 2) (- 1))))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (+ (- (+ cstrcat_~s.offset 2)) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1))))) (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1))))) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1))) 1) (- 1)))))) (= 0 cstrcat_~append.offset)), 10515#(and (or (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 2) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 10516#(and (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 2) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))) (= |cstrcat_#t~mem1| 0) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 10517#(and (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 2) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 2))) 1) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 1))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 4)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 10518#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 2) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset)), 10519#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (select |#length| cstrcat_~append.base) 2) (= |cstrcat_#t~mem1| 0) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset)), 10520#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (select |#length| cstrcat_~append.base) 2) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= 3 cstrcat_~s.offset)), 10521#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (select |#length| cstrcat_~append.base) 2))), 10522#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2) (and (<= (+ (* 2 (select |#length| cstrcat_~append.base)) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) 2)) (= |cstrcat_#t~mem1| 0))) (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 10523#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 10524#(and (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2)) (<= 5 cstrcat_~s.offset)), 10525#(and (<= 6 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 2))), 10526#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 1))) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= 7 cstrcat_~s.offset)), 10527#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))) (<= 7 cstrcat_~s.offset)), 10528#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= 8 cstrcat_~s.offset)), 10529#(and (<= 8 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 10530#(and (<= 8 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:01:32,839 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:32,839 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 15:01:32,839 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 15:01:32,839 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=972, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 15:01:32,839 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 33 states. [2018-02-04 15:01:33,570 WARN L146 SmtUtils]: Spent 125ms on a formula simplification. DAG size of input: 142 DAG size of output 141 [2018-02-04 15:01:34,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:34,656 INFO L93 Difference]: Finished difference Result 166 states and 174 transitions. [2018-02-04 15:01:34,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-02-04 15:01:34,656 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 59 [2018-02-04 15:01:34,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:34,657 INFO L225 Difference]: With dead ends: 166 [2018-02-04 15:01:34,657 INFO L226 Difference]: Without dead ends: 166 [2018-02-04 15:01:34,657 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 54 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 682 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=225, Invalid=2745, Unknown=0, NotChecked=0, Total=2970 [2018-02-04 15:01:34,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-02-04 15:01:34,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 139. [2018-02-04 15:01:34,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-04 15:01:34,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-04 15:01:34,658 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 59 [2018-02-04 15:01:34,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:34,659 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-04 15:01:34,659 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 15:01:34,659 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-04 15:01:34,659 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-02-04 15:01:34,659 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:34,659 INFO L351 BasicCegarLoop]: trace histogram [6, 6, 5, 5, 4, 4, 4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:34,659 INFO L371 AbstractCegarLoop]: === Iteration 44 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:34,659 INFO L82 PathProgramCache]: Analyzing trace with hash 2144926456, now seen corresponding path program 13 times [2018-02-04 15:01:34,659 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:34,666 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:34,666 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:35,535 WARN L146 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 108 DAG size of output 67 [2018-02-04 15:01:36,164 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 0 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:36,165 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:36,165 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31] total 31 [2018-02-04 15:01:36,165 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:36,165 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:36,165 INFO L182 omatonBuilderFactory]: Interpolants [10880#true, 10881#false, 10882#(<= 1 main_~length3~0), 10883#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 10884#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1) (= (select |#length| |main_#t~malloc9.base|) main_~length1~0)), 10885#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (= main_~nondetString1~0.offset 0)), 10886#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (= (select |#length| main_~nondetString1~0.base) main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 10887#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10888#(and (= 0 main_~nondetString2~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 10889#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString1~0.offset) 4) (+ (- main_~nondetString2~0.offset) (+ main_~nondetString1~0.offset (- 1)))) (+ main_~nondetString2~0.offset (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (<= (+ main_~nondetString1~0.offset (* 2 (select |#length| main_~nondetString1~0.base)) 1) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (select |#length| main_~nondetString1~0.base) (+ main_~nondetString1~0.offset (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (= main_~nondetString1~0.offset 0)), 10890#(and (= 0 |cstrcat_#in~s.offset|) (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 4 (- 1)) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (select |#length| |cstrcat_#in~append.base|) (- 1)))) (<= (+ (* 2 (select |#length| |cstrcat_#in~append.base|)) 1) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 10891#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (<= 9 (select |#length| cstrcat_~s.base))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 10892#(and (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (<= 9 (select |#length| cstrcat_~s.base))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 10893#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (select |#length| cstrcat_~append.base) (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 4 (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 1) (select |#length| cstrcat_~s.base)) (<= 9 (select |#length| cstrcat_~s.base))) (or (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 10894#(and (or (and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset)) (+ cstrcat_~s.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 1 cstrcat_~s.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1)))) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset)) (+ cstrcat_~s.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (+ (select |#length| cstrcat_~s.base) cstrcat_~s.offset)))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))) (= 0 cstrcat_~append.offset)), 10895#(and (= 0 cstrcat_~append.offset) (or (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset)) (+ cstrcat_~s.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 1 cstrcat_~s.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1)))) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)))))) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset)) (+ cstrcat_~s.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (+ (select |#length| cstrcat_~s.base) cstrcat_~s.offset)))))), 10896#(and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset)) (+ cstrcat_~s.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 1 cstrcat_~s.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1)))) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)))))) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset)) (+ cstrcat_~s.offset (- 1)))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 1))) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) (- 1)) (- 1)))) (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 2) (+ (select |#length| cstrcat_~s.base) cstrcat_~s.offset)))), 10897#(or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 2 cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (+ (select |#length| cstrcat_~s.base) cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 2))) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 10898#(or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 2 cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (+ (select |#length| cstrcat_~s.base) cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 2))) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 10899#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 2 cstrcat_~s.offset)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (or (<= (+ (* 2 (select |#length| cstrcat_~append.base)) 3) (+ (select |#length| cstrcat_~s.base) cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~append.base) (+ cstrcat_~s.offset (- 2))) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 10900#(and (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (select |#length| cstrcat_~append.base) 3) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 3 cstrcat_~s.offset)))), 10901#(and (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 3 cstrcat_~s.offset))) (or (<= (select |#length| cstrcat_~append.base) 3) (= |cstrcat_#t~mem1| 0) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 10902#(and (or (<= (select |#length| cstrcat_~append.base) 3) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 3 cstrcat_~s.offset)))), 10903#(and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 3)) (= 0 cstrcat_~append.offset)), 10904#(and (or (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) 3)) (= 0 cstrcat_~append.offset)), 10905#(and (or (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ cstrcat_~append.offset 2)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0)), 10906#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 2))), 10907#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 10908#(and (or (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= (select |#length| cstrcat_~append.base) (+ cstrcat_~append.offset 1))) (<= 1 cstrcat_~s.offset)), 10909#(and (<= 2 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 10910#(and (<= 2 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 10911#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:01:36,165 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 0 proven. 82 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:36,165 INFO L409 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-02-04 15:01:36,165 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-02-04 15:01:36,166 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=890, Unknown=0, NotChecked=0, Total=992 [2018-02-04 15:01:36,166 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 32 states. [2018-02-04 15:01:37,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:37,626 INFO L93 Difference]: Finished difference Result 181 states and 189 transitions. [2018-02-04 15:01:37,626 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-02-04 15:01:37,626 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 60 [2018-02-04 15:01:37,626 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:37,626 INFO L225 Difference]: With dead ends: 181 [2018-02-04 15:01:37,626 INFO L226 Difference]: Without dead ends: 181 [2018-02-04 15:01:37,627 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 861 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=319, Invalid=3103, Unknown=0, NotChecked=0, Total=3422 [2018-02-04 15:01:37,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-02-04 15:01:37,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 139. [2018-02-04 15:01:37,628 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-04 15:01:37,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-04 15:01:37,629 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 60 [2018-02-04 15:01:37,629 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:37,629 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-04 15:01:37,629 INFO L433 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-02-04 15:01:37,629 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-04 15:01:37,630 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-02-04 15:01:37,630 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:37,630 INFO L351 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:37,630 INFO L371 AbstractCegarLoop]: === Iteration 45 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:37,630 INFO L82 PathProgramCache]: Analyzing trace with hash 1265383056, now seen corresponding path program 9 times [2018-02-04 15:01:37,631 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:37,648 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:37,649 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:38,400 WARN L146 SmtUtils]: Spent 185ms on a formula simplification. DAG size of input: 244 DAG size of output 76 [2018-02-04 15:01:38,609 WARN L146 SmtUtils]: Spent 183ms on a formula simplification. DAG size of input: 219 DAG size of output 67 [2018-02-04 15:01:38,812 WARN L146 SmtUtils]: Spent 174ms on a formula simplification. DAG size of input: 219 DAG size of output 67 [2018-02-04 15:01:39,011 WARN L146 SmtUtils]: Spent 167ms on a formula simplification. DAG size of input: 221 DAG size of output 67 [2018-02-04 15:01:39,198 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 219 DAG size of output 65 [2018-02-04 15:01:39,430 WARN L146 SmtUtils]: Spent 190ms on a formula simplification. DAG size of input: 235 DAG size of output 75 [2018-02-04 15:01:39,660 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 237 DAG size of output 75 [2018-02-04 15:01:39,935 WARN L146 SmtUtils]: Spent 220ms on a formula simplification. DAG size of input: 235 DAG size of output 73 [2018-02-04 15:01:40,093 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 157 DAG size of output 64 [2018-02-04 15:01:40,251 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 159 DAG size of output 64 [2018-02-04 15:01:40,406 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 157 DAG size of output 62 [2018-02-04 15:01:41,316 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:41,316 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:41,342 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40] total 40 [2018-02-04 15:01:41,343 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:41,343 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:41,343 INFO L182 omatonBuilderFactory]: Interpolants [11286#true, 11287#false, 11288#(<= 1 main_~length1~0), 11289#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 11290#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 11291#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 11292#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 11293#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 11294#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 11295#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 11296#(and (= 0 main_~nondetString2~0.offset) (or (and (or (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) 1) (+ main_~nondetString2~0.offset (- 1)))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 11297#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (<= 10 (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s.base|)))) (and (<= 7 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 2) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 11298#(and (or (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 11 (select |#length| cstrcat_~s.base))) (<= 10 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 11299#(and (or (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 11 (select |#length| cstrcat_~s.base))) (<= 10 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 11300#(and (= cstrcat_~s.offset 0) (or (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 11 (select |#length| cstrcat_~s.base))) (<= 10 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1))))))), 11301#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 11302#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))))), 11303#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))))), 11304#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 11305#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 11306#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 11307#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))), 11308#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))), 11309#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))), 11310#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 11311#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 11312#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 11313#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 11314#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 11315#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 11316#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 11317#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 11318#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 11319#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 11320#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 11321#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 11322#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 11323#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= 0 cstrcat_~s.offset)), 11324#(and (<= 0 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 11325#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 11326#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:01:41,343 INFO L134 CoverageAnalysis]: Checked inductivity of 200 backedges. 0 proven. 200 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:41,344 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-02-04 15:01:41,344 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-02-04 15:01:41,344 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=224, Invalid=1416, Unknown=0, NotChecked=0, Total=1640 [2018-02-04 15:01:41,344 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 41 states. [2018-02-04 15:01:42,407 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 129 DAG size of output 123 [2018-02-04 15:01:42,785 WARN L146 SmtUtils]: Spent 117ms on a formula simplification. DAG size of input: 122 DAG size of output 116 [2018-02-04 15:01:42,917 WARN L146 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 115 DAG size of output 109 [2018-02-04 15:01:43,152 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 114 DAG size of output 108 [2018-02-04 15:01:44,673 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:44,673 INFO L93 Difference]: Finished difference Result 182 states and 192 transitions. [2018-02-04 15:01:44,674 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-02-04 15:01:44,674 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 60 [2018-02-04 15:01:44,674 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:44,674 INFO L225 Difference]: With dead ends: 182 [2018-02-04 15:01:44,674 INFO L226 Difference]: Without dead ends: 182 [2018-02-04 15:01:44,675 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1469 ImplicationChecksByTransitivity, 6.0s TimeCoverageRelationStatistics Valid=814, Invalid=4588, Unknown=0, NotChecked=0, Total=5402 [2018-02-04 15:01:44,675 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-02-04 15:01:44,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 147. [2018-02-04 15:01:44,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-02-04 15:01:44,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 156 transitions. [2018-02-04 15:01:44,677 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 156 transitions. Word has length 60 [2018-02-04 15:01:44,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:44,677 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 156 transitions. [2018-02-04 15:01:44,677 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-02-04 15:01:44,677 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 156 transitions. [2018-02-04 15:01:44,677 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-02-04 15:01:44,677 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:44,677 INFO L351 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:44,677 INFO L371 AbstractCegarLoop]: === Iteration 46 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:44,678 INFO L82 PathProgramCache]: Analyzing trace with hash -106216073, now seen corresponding path program 14 times [2018-02-04 15:01:44,678 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:44,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:44,684 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:45,228 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 27 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:45,228 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:45,228 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28] total 28 [2018-02-04 15:01:45,229 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:45,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:45,229 INFO L182 omatonBuilderFactory]: Interpolants [11722#true, 11723#false, 11724#(<= 1 main_~length3~0), 11725#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 11726#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 11727#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0) (= main_~nondetString1~0.offset 0)), 11728#(and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 11729#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= main_~nondetString1~0.offset 0)), 11730#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= main_~nondetString1~0.offset 0)), 11731#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1)))))))) (= main_~nondetString1~0.offset 0)), 11732#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1))) (= 0 |cstrcat_#in~append.offset|)), 11733#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 11734#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 11735#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 11736#(and (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))))), 11737#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0))) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 11738#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 1 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 11739#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 11740#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)) (= |cstrcat_#t~mem1| 0)), 11741#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 11742#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset)), 11743#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 11744#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 5 cstrcat_~s.offset)), 11745#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 5 cstrcat_~s.offset)), 11746#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 6 cstrcat_~s.offset)), 11747#(and (<= 7 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 11748#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 8 cstrcat_~s.offset)), 11749#(and (<= 8 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 11750#(and (<= 8 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:01:45,229 INFO L134 CoverageAnalysis]: Checked inductivity of 82 backedges. 27 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:45,229 INFO L409 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-02-04 15:01:45,229 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-02-04 15:01:45,229 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=734, Unknown=0, NotChecked=0, Total=812 [2018-02-04 15:01:45,229 INFO L87 Difference]: Start difference. First operand 147 states and 156 transitions. Second operand 29 states. [2018-02-04 15:01:45,990 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:45,990 INFO L93 Difference]: Finished difference Result 184 states and 193 transitions. [2018-02-04 15:01:45,990 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 15:01:45,990 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 61 [2018-02-04 15:01:45,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:45,991 INFO L225 Difference]: With dead ends: 184 [2018-02-04 15:01:45,991 INFO L226 Difference]: Without dead ends: 159 [2018-02-04 15:01:45,991 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 525 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=199, Invalid=1963, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 15:01:45,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-02-04 15:01:45,992 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 147. [2018-02-04 15:01:45,992 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-02-04 15:01:45,992 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 155 transitions. [2018-02-04 15:01:45,992 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 155 transitions. Word has length 61 [2018-02-04 15:01:45,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:45,992 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 155 transitions. [2018-02-04 15:01:45,993 INFO L433 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-02-04 15:01:45,993 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 155 transitions. [2018-02-04 15:01:45,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-02-04 15:01:45,993 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:45,993 INFO L351 BasicCegarLoop]: trace histogram [9, 9, 8, 8, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:45,993 INFO L371 AbstractCegarLoop]: === Iteration 47 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:45,993 INFO L82 PathProgramCache]: Analyzing trace with hash -784534207, now seen corresponding path program 15 times [2018-02-04 15:01:45,994 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:46,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:46,006 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:48,029 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 0 proven. 140 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:48,030 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:48,030 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38] total 38 [2018-02-04 15:01:48,030 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:48,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:48,030 INFO L182 omatonBuilderFactory]: Interpolants [12118#true, 12119#false, 12120#(<= 1 main_~length3~0), 12121#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 12122#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 12123#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 12124#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 12125#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (<= (+ main_~nondetString2~0.offset main_~length3~0) 3) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base))))), 12126#(and (= 0 main_~nondetString2~0.offset) (<= 1 main_~length3~0) (or (and (= 0 main_~nondetString1~0.offset) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))) (<= (+ main_~nondetString2~0.offset main_~length3~0) 3))), 12127#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ (- (select |#length| main_~nondetString1~0.base)) (- 1))) (+ main_~nondetString2~0.offset (- 1))))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 5) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))))), 12128#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (and (= 0 |cstrcat_#in~append.offset|) (or (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 7) (select |#length| |cstrcat_#in~s.base|)) (or (<= (+ (select |#length| |cstrcat_#in~append.base|) 8) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (+ (select |#length| |cstrcat_#in~s.base|) (- 1))) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 12129#(and (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= cstrcat_~s.offset 0)), 12130#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 12131#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 12132#(and (= cstrcat_~s.offset 1) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12133#(and (= cstrcat_~s.offset 1) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (= |cstrcat_#t~mem1| 0))), 12134#(and (= cstrcat_~s.offset 1) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12135#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))))) (= 0 cstrcat_~append.offset))), 12136#(or (= |cstrcat_#t~mem1| 0) (and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))))) (= 0 cstrcat_~append.offset))), 12137#(and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))))) (= 0 cstrcat_~append.offset)), 12138#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 12139#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 12140#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (select |#length| cstrcat_~append.base)) (- 1))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))), 12141#(or (and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 12142#(or (and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 12143#(and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 12144#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 12145#(or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)), 12146#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12147#(and (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 12148#(and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset)), 12149#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 12150#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 12151#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 12152#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ cstrcat_~s.offset (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 12153#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 12154#(and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 12155#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|))), 12156#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:01:48,030 INFO L134 CoverageAnalysis]: Checked inductivity of 140 backedges. 0 proven. 140 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:48,031 INFO L409 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-02-04 15:01:48,031 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-02-04 15:01:48,031 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=152, Invalid=1330, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 15:01:48,031 INFO L87 Difference]: Start difference. First operand 147 states and 155 transitions. Second operand 39 states. [2018-02-04 15:01:50,309 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:01:50,309 INFO L93 Difference]: Finished difference Result 171 states and 179 transitions. [2018-02-04 15:01:50,309 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-02-04 15:01:50,309 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 62 [2018-02-04 15:01:50,309 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:01:50,309 INFO L225 Difference]: With dead ends: 171 [2018-02-04 15:01:50,310 INFO L226 Difference]: Without dead ends: 132 [2018-02-04 15:01:50,310 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1281 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=505, Invalid=4325, Unknown=0, NotChecked=0, Total=4830 [2018-02-04 15:01:50,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-02-04 15:01:50,311 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 132. [2018-02-04 15:01:50,311 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-02-04 15:01:50,311 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 136 transitions. [2018-02-04 15:01:50,311 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 136 transitions. Word has length 62 [2018-02-04 15:01:50,311 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:01:50,311 INFO L432 AbstractCegarLoop]: Abstraction has 132 states and 136 transitions. [2018-02-04 15:01:50,311 INFO L433 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-02-04 15:01:50,311 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 136 transitions. [2018-02-04 15:01:50,312 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 15:01:50,312 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:01:50,312 INFO L351 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:01:50,312 INFO L371 AbstractCegarLoop]: === Iteration 48 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:01:50,312 INFO L82 PathProgramCache]: Analyzing trace with hash -1237788269, now seen corresponding path program 10 times [2018-02-04 15:01:50,312 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:01:50,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:01:50,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:01:51,398 WARN L146 SmtUtils]: Spent 343ms on a formula simplification. DAG size of input: 374 DAG size of output 85 [2018-02-04 15:01:51,708 WARN L146 SmtUtils]: Spent 275ms on a formula simplification. DAG size of input: 309 DAG size of output 74 [2018-02-04 15:01:52,072 WARN L146 SmtUtils]: Spent 321ms on a formula simplification. DAG size of input: 309 DAG size of output 74 [2018-02-04 15:01:52,435 WARN L146 SmtUtils]: Spent 317ms on a formula simplification. DAG size of input: 311 DAG size of output 74 [2018-02-04 15:01:52,804 WARN L146 SmtUtils]: Spent 315ms on a formula simplification. DAG size of input: 309 DAG size of output 72 [2018-02-04 15:01:53,216 WARN L146 SmtUtils]: Spent 354ms on a formula simplification. DAG size of input: 326 DAG size of output 83 [2018-02-04 15:01:53,605 WARN L146 SmtUtils]: Spent 327ms on a formula simplification. DAG size of input: 328 DAG size of output 83 [2018-02-04 15:01:53,981 WARN L146 SmtUtils]: Spent 311ms on a formula simplification. DAG size of input: 326 DAG size of output 81 [2018-02-04 15:01:54,257 WARN L146 SmtUtils]: Spent 225ms on a formula simplification. DAG size of input: 220 DAG size of output 72 [2018-02-04 15:01:54,545 WARN L146 SmtUtils]: Spent 234ms on a formula simplification. DAG size of input: 222 DAG size of output 72 [2018-02-04 15:01:54,819 WARN L146 SmtUtils]: Spent 216ms on a formula simplification. DAG size of input: 220 DAG size of output 70 [2018-02-04 15:01:54,996 WARN L146 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 145 DAG size of output 64 [2018-02-04 15:01:55,160 WARN L146 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 147 DAG size of output 64 [2018-02-04 15:01:55,330 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 145 DAG size of output 62 [2018-02-04 15:01:56,568 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:56,569 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:01:56,569 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44] total 44 [2018-02-04 15:01:56,569 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:01:56,569 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:56,570 INFO L182 omatonBuilderFactory]: Interpolants [12544#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 12545#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12546#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12547#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 12548#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12549#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12550#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 12551#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12552#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 12553#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 12554#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 12555#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12556#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 12557#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12558#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 12559#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 12560#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 12561#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 12562#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 12563#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 12564#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 12565#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 12566#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 12522#true, 12523#false, 12524#(<= 1 main_~length1~0), 12525#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 12526#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 12527#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 12528#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 12529#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 12530#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0))) (= main_~nondetString1~0.offset 0)), 12531#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= main_~nondetString1~0.offset 0)), 12532#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) 1) (- 1))))))) (and (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) (- 1))))))) (= main_~nondetString1~0.offset 0)), 12533#(and (= 0 |cstrcat_#in~s.offset|) (or (and (<= 9 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (<= 7 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1))))) (and (or (<= 12 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 1) 2) 1) (- 1))))) (<= 11 (select |#length| |cstrcat_#in~s.base|))) (and (<= 10 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 2) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 12534#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 10 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 12 (select |#length| cstrcat_~s.base))) (<= 11 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 12535#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 10 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 12 (select |#length| cstrcat_~s.base))) (<= 11 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 12536#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 10 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= 12 (select |#length| cstrcat_~s.base))) (<= 11 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 12537#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 12538#(and (or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 12539#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 12540#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12541#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 12542#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 12543#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))] [2018-02-04 15:01:56,570 INFO L134 CoverageAnalysis]: Checked inductivity of 242 backedges. 0 proven. 242 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:01:56,570 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-02-04 15:01:56,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-02-04 15:01:56,570 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=311, Invalid=1669, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 15:01:56,570 INFO L87 Difference]: Start difference. First operand 132 states and 136 transitions. Second operand 45 states. [2018-02-04 15:01:57,458 WARN L146 SmtUtils]: Spent 177ms on a formula simplification. DAG size of input: 146 DAG size of output 145 [2018-02-04 15:01:57,672 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 137 DAG size of output 131 [2018-02-04 15:01:57,851 WARN L146 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 140 DAG size of output 137 [2018-02-04 15:01:57,980 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 135 DAG size of output 131 [2018-02-04 15:01:58,261 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 133 DAG size of output 130 [2018-02-04 15:01:58,644 WARN L146 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 125 DAG size of output 122 [2018-02-04 15:01:59,358 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 112 DAG size of output 109 [2018-02-04 15:02:00,705 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:00,705 INFO L93 Difference]: Finished difference Result 155 states and 161 transitions. [2018-02-04 15:02:00,705 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-02-04 15:02:00,705 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 64 [2018-02-04 15:02:00,705 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:00,706 INFO L225 Difference]: With dead ends: 155 [2018-02-04 15:02:00,706 INFO L226 Difference]: Without dead ends: 155 [2018-02-04 15:02:00,706 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1809 ImplicationChecksByTransitivity, 9.3s TimeCoverageRelationStatistics Valid=1079, Invalid=5401, Unknown=0, NotChecked=0, Total=6480 [2018-02-04 15:02:00,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 155 states. [2018-02-04 15:02:00,707 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 155 to 140. [2018-02-04 15:02:00,707 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-02-04 15:02:00,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 145 transitions. [2018-02-04 15:02:00,708 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 145 transitions. Word has length 64 [2018-02-04 15:02:00,708 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:00,708 INFO L432 AbstractCegarLoop]: Abstraction has 140 states and 145 transitions. [2018-02-04 15:02:00,708 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-02-04 15:02:00,708 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 145 transitions. [2018-02-04 15:02:00,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-02-04 15:02:00,708 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:00,708 INFO L351 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:00,708 INFO L371 AbstractCegarLoop]: === Iteration 49 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:02:00,708 INFO L82 PathProgramCache]: Analyzing trace with hash -1150491772, now seen corresponding path program 16 times [2018-02-04 15:02:00,709 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:00,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:00,728 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:01,328 WARN L146 SmtUtils]: Spent 232ms on a formula simplification. DAG size of input: 35 DAG size of output 25 [2018-02-04 15:02:01,499 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 139 DAG size of output 79 [2018-02-04 15:02:01,648 WARN L146 SmtUtils]: Spent 133ms on a formula simplification. DAG size of input: 113 DAG size of output 71 [2018-02-04 15:02:01,811 WARN L146 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 113 DAG size of output 71 [2018-02-04 15:02:02,071 WARN L146 SmtUtils]: Spent 231ms on a formula simplification. DAG size of input: 115 DAG size of output 71 [2018-02-04 15:02:02,218 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 113 DAG size of output 69 [2018-02-04 15:02:02,430 WARN L146 SmtUtils]: Spent 164ms on a formula simplification. DAG size of input: 129 DAG size of output 77 [2018-02-04 15:02:02,612 WARN L146 SmtUtils]: Spent 139ms on a formula simplification. DAG size of input: 131 DAG size of output 77 [2018-02-04 15:02:02,750 WARN L146 SmtUtils]: Spent 106ms on a formula simplification. DAG size of input: 129 DAG size of output 72 [2018-02-04 15:02:03,975 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 0 proven. 175 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:03,975 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:03,975 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41] total 41 [2018-02-04 15:02:03,975 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:03,976 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:03,976 INFO L182 omatonBuilderFactory]: Interpolants [12934#true, 12935#false, 12936#(<= 1 main_~length3~0), 12937#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 12938#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 12939#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= (select |#valid| main_~nondetString1~0.base) 1) (<= 1 main_~length3~0)), 12940#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 12941#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 12942#(and (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (= (+ main_~nondetString2~0.offset main_~length3~0) 1) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)))) (= 0 main_~nondetString2~0.offset)), 12943#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 6) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (- main_~nondetString2~0.offset) 6) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 9) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 12944#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 |cstrcat_#in~append.offset|) (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 6 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 7) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 6 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (- (select |#length| |cstrcat_#in~append.base|)) (select |#length| |cstrcat_#in~s.base|)) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 9) (select |#length| |cstrcat_#in~s.base|))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 8) (select |#length| |cstrcat_#in~s.base|))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 12945#(and (or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 6 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 6 1) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= cstrcat_~s.offset 0)), 12946#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 6 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 6 1) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= |cstrcat_#t~mem1| 0))), 12947#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 6 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (- (select |#length| cstrcat_~append.base)) (select |#length| cstrcat_~s.base)) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 6 1) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 12948#(or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 5) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 5) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 12949#(or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 5) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 5) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0))), 12950#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 5) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 5) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ (select |#length| cstrcat_~s.base) (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset)), 12951#(or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))), 12952#(or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 12953#(or (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)))), 12954#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 12955#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 12956#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 12957#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 12958#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 12959#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 12960#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 12961#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 12962#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 12963#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 12964#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 12965#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 12966#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 12967#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 12968#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 12969#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 12970#(and (<= 0 cstrcat_~s.offset) (or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 12971#(and (or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))) (<= 1 cstrcat_~s.offset)), 12972#(and (<= 2 cstrcat_~s.offset) (or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 12973#(and (<= 2 cstrcat_~s.offset) (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))), 12974#(and (<= 2 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 12975#(and (<= 2 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:02:03,976 INFO L134 CoverageAnalysis]: Checked inductivity of 175 backedges. 0 proven. 175 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:03,976 INFO L409 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-02-04 15:02:03,976 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-02-04 15:02:03,977 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=221, Invalid=1501, Unknown=0, NotChecked=0, Total=1722 [2018-02-04 15:02:03,977 INFO L87 Difference]: Start difference. First operand 140 states and 145 transitions. Second operand 42 states. [2018-02-04 15:02:04,818 WARN L146 SmtUtils]: Spent 111ms on a formula simplification. DAG size of input: 141 DAG size of output 140 [2018-02-04 15:02:05,515 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 126 DAG size of output 123 [2018-02-04 15:02:05,907 WARN L146 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 119 DAG size of output 116 [2018-02-04 15:02:06,247 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 113 DAG size of output 110 [2018-02-04 15:02:06,587 WARN L146 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 107 DAG size of output 102 [2018-02-04 15:02:07,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:07,284 INFO L93 Difference]: Finished difference Result 150 states and 155 transitions. [2018-02-04 15:02:07,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-02-04 15:02:07,284 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 66 [2018-02-04 15:02:07,284 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:07,285 INFO L225 Difference]: With dead ends: 150 [2018-02-04 15:02:07,285 INFO L226 Difference]: Without dead ends: 150 [2018-02-04 15:02:07,285 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1509 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=687, Invalid=4569, Unknown=0, NotChecked=0, Total=5256 [2018-02-04 15:02:07,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-02-04 15:02:07,286 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 145. [2018-02-04 15:02:07,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-02-04 15:02:07,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 150 transitions. [2018-02-04 15:02:07,287 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 150 transitions. Word has length 66 [2018-02-04 15:02:07,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:07,287 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 150 transitions. [2018-02-04 15:02:07,287 INFO L433 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-02-04 15:02:07,287 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 150 transitions. [2018-02-04 15:02:07,287 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-02-04 15:02:07,287 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:07,288 INFO L351 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:07,288 INFO L371 AbstractCegarLoop]: === Iteration 50 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:02:07,288 INFO L82 PathProgramCache]: Analyzing trace with hash -735689962, now seen corresponding path program 11 times [2018-02-04 15:02:07,288 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:07,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:07,299 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:09,400 WARN L146 SmtUtils]: Spent 444ms on a formula simplification. DAG size of input: 423 DAG size of output 93 [2018-02-04 15:02:09,836 WARN L146 SmtUtils]: Spent 394ms on a formula simplification. DAG size of input: 322 DAG size of output 81 [2018-02-04 15:02:10,265 WARN L146 SmtUtils]: Spent 379ms on a formula simplification. DAG size of input: 322 DAG size of output 81 [2018-02-04 15:02:10,710 WARN L146 SmtUtils]: Spent 395ms on a formula simplification. DAG size of input: 324 DAG size of output 81 [2018-02-04 15:02:11,125 WARN L146 SmtUtils]: Spent 360ms on a formula simplification. DAG size of input: 322 DAG size of output 79 [2018-02-04 15:02:11,595 WARN L146 SmtUtils]: Spent 409ms on a formula simplification. DAG size of input: 340 DAG size of output 91 [2018-02-04 15:02:12,055 WARN L146 SmtUtils]: Spent 389ms on a formula simplification. DAG size of input: 342 DAG size of output 91 [2018-02-04 15:02:12,520 WARN L146 SmtUtils]: Spent 400ms on a formula simplification. DAG size of input: 340 DAG size of output 89 [2018-02-04 15:02:12,858 WARN L146 SmtUtils]: Spent 281ms on a formula simplification. DAG size of input: 234 DAG size of output 80 [2018-02-04 15:02:13,221 WARN L146 SmtUtils]: Spent 296ms on a formula simplification. DAG size of input: 236 DAG size of output 80 [2018-02-04 15:02:13,566 WARN L146 SmtUtils]: Spent 282ms on a formula simplification. DAG size of input: 234 DAG size of output 78 [2018-02-04 15:02:13,783 WARN L146 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 165 DAG size of output 71 [2018-02-04 15:02:14,012 WARN L146 SmtUtils]: Spent 176ms on a formula simplification. DAG size of input: 167 DAG size of output 71 [2018-02-04 15:02:14,234 WARN L146 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 165 DAG size of output 69 [2018-02-04 15:02:14,405 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 122 DAG size of output 64 [2018-02-04 15:02:14,571 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 124 DAG size of output 64 [2018-02-04 15:02:14,735 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 122 DAG size of output 62 [2018-02-04 15:02:15,965 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:15,965 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:15,965 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46] total 46 [2018-02-04 15:02:15,965 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:15,966 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:15,966 INFO L182 omatonBuilderFactory]: Interpolants [13376#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset) (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0))), 13377#(and (<= 2 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 13378#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 3 cstrcat_~s.offset)), 13379#(and (<= 4 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))), 13333#true, 13334#false, 13335#(<= 1 main_~length1~0), 13336#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 13337#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 13338#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 13339#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 13340#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 13341#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 13342#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 13343#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (- 1))))) (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 13 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) 1) (- 1))))))) (= main_~nondetString1~0.offset 0)), 13344#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (<= 7 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (<= 9 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 2) 1) (- 1))))) (and (<= 12 (select |#length| |cstrcat_#in~s.base|)) (or (<= 13 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 2) 1) 2) (- 1)))) (<= 11 (select |#length| |cstrcat_#in~s.base|))) (and (<= 10 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 2) 1) 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))))), 13345#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 11 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (and (<= 12 (select |#length| cstrcat_~s.base)) (or (<= 13 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 2) 1) (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 13346#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 11 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (and (<= 12 (select |#length| cstrcat_~s.base)) (or (<= 13 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 2) 1) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 13347#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (<= 11 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 2) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (and (<= 12 (select |#length| cstrcat_~s.base)) (or (<= 13 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= 9 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 2) 1) (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 13348#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 1) (- 1))))) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13349#(and (or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 1) (- 1))))) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset)), 13350#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 1) (- 1))))) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13351#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13352#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 13353#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13354#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 13355#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 13356#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 13357#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13358#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 13359#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13360#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13361#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 13362#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13363#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13364#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 13365#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 13366#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13367#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13368#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13369#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 13370#(or (and (<= 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))) (= |cstrcat_#t~mem1| 0)), 13371#(and (<= 0 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 13372#(and (<= 1 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 13373#(and (<= 1 cstrcat_~s.offset) (or (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0))), 13374#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 13375#(and (or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 2 cstrcat_~s.offset))] [2018-02-04 15:02:15,966 INFO L134 CoverageAnalysis]: Checked inductivity of 288 backedges. 0 proven. 288 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:15,967 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-02-04 15:02:15,967 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-02-04 15:02:15,967 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=252, Invalid=1910, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 15:02:15,967 INFO L87 Difference]: Start difference. First operand 145 states and 150 transitions. Second operand 47 states. [2018-02-04 15:02:16,328 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 113 DAG size of output 113 [2018-02-04 15:02:17,208 WARN L146 SmtUtils]: Spent 142ms on a formula simplification. DAG size of input: 153 DAG size of output 145 [2018-02-04 15:02:17,425 WARN L146 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 164 DAG size of output 151 [2018-02-04 15:02:17,582 WARN L146 SmtUtils]: Spent 128ms on a formula simplification. DAG size of input: 151 DAG size of output 143 [2018-02-04 15:02:17,757 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 146 DAG size of output 136 [2018-02-04 15:02:17,972 WARN L146 SmtUtils]: Spent 169ms on a formula simplification. DAG size of input: 157 DAG size of output 143 [2018-02-04 15:02:18,120 WARN L146 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 145 DAG size of output 137 [2018-02-04 15:02:18,281 WARN L146 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 143 DAG size of output 130 [2018-02-04 15:02:18,500 WARN L146 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 154 DAG size of output 137 [2018-02-04 15:02:18,652 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 142 DAG size of output 131 [2018-02-04 15:02:18,809 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 136 DAG size of output 123 [2018-02-04 15:02:18,994 WARN L146 SmtUtils]: Spent 149ms on a formula simplification. DAG size of input: 147 DAG size of output 130 [2018-02-04 15:02:19,421 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 139 DAG size of output 122 [2018-02-04 15:02:19,567 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 127 DAG size of output 116 [2018-02-04 15:02:19,705 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 122 DAG size of output 109 [2018-02-04 15:02:19,862 WARN L146 SmtUtils]: Spent 119ms on a formula simplification. DAG size of input: 133 DAG size of output 116 [2018-02-04 15:02:20,286 WARN L146 SmtUtils]: Spent 116ms on a formula simplification. DAG size of input: 124 DAG size of output 111 [2018-02-04 15:02:21,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:21,416 INFO L93 Difference]: Finished difference Result 172 states and 179 transitions. [2018-02-04 15:02:21,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-02-04 15:02:21,416 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 68 [2018-02-04 15:02:21,416 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:21,417 INFO L225 Difference]: With dead ends: 172 [2018-02-04 15:02:21,417 INFO L226 Difference]: Without dead ends: 172 [2018-02-04 15:02:21,417 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2054 ImplicationChecksByTransitivity, 11.9s TimeCoverageRelationStatistics Valid=979, Invalid=6331, Unknown=0, NotChecked=0, Total=7310 [2018-02-04 15:02:21,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-02-04 15:02:21,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 153. [2018-02-04 15:02:21,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-02-04 15:02:21,419 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 159 transitions. [2018-02-04 15:02:21,419 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 159 transitions. Word has length 68 [2018-02-04 15:02:21,419 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:21,419 INFO L432 AbstractCegarLoop]: Abstraction has 153 states and 159 transitions. [2018-02-04 15:02:21,419 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-02-04 15:02:21,419 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 159 transitions. [2018-02-04 15:02:21,420 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 71 [2018-02-04 15:02:21,420 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:21,420 INFO L351 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:21,420 INFO L371 AbstractCegarLoop]: === Iteration 51 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:02:21,420 INFO L82 PathProgramCache]: Analyzing trace with hash 329644103, now seen corresponding path program 17 times [2018-02-04 15:02:21,420 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:21,439 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:21,439 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:22,213 WARN L146 SmtUtils]: Spent 282ms on a formula simplification. DAG size of input: 168 DAG size of output 84 [2018-02-04 15:02:22,502 WARN L146 SmtUtils]: Spent 271ms on a formula simplification. DAG size of input: 150 DAG size of output 74 [2018-02-04 15:02:22,725 WARN L146 SmtUtils]: Spent 197ms on a formula simplification. DAG size of input: 150 DAG size of output 74 [2018-02-04 15:02:22,934 WARN L146 SmtUtils]: Spent 183ms on a formula simplification. DAG size of input: 152 DAG size of output 74 [2018-02-04 15:02:23,200 WARN L146 SmtUtils]: Spent 238ms on a formula simplification. DAG size of input: 150 DAG size of output 72 [2018-02-04 15:02:23,450 WARN L146 SmtUtils]: Spent 204ms on a formula simplification. DAG size of input: 168 DAG size of output 82 [2018-02-04 15:02:23,688 WARN L146 SmtUtils]: Spent 197ms on a formula simplification. DAG size of input: 170 DAG size of output 82 [2018-02-04 15:02:23,916 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 168 DAG size of output 78 [2018-02-04 15:02:24,087 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 127 DAG size of output 73 [2018-02-04 15:02:24,258 WARN L146 SmtUtils]: Spent 138ms on a formula simplification. DAG size of input: 129 DAG size of output 73 [2018-02-04 15:02:24,419 WARN L146 SmtUtils]: Spent 127ms on a formula simplification. DAG size of input: 127 DAG size of output 71 [2018-02-04 15:02:24,557 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 100 DAG size of output 66 [2018-02-04 15:02:24,713 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 102 DAG size of output 66 [2018-02-04 15:02:25,840 INFO L134 CoverageAnalysis]: Checked inductivity of 214 backedges. 0 proven. 214 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:25,840 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:25,840 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43] total 43 [2018-02-04 15:02:25,840 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:25,840 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:25,841 INFO L182 omatonBuilderFactory]: Interpolants [13824#(and (or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= 3 cstrcat_~s.offset)), 13825#(and (<= 3 |cstrcat_#t~post2.offset|) (or (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))), 13826#(and (<= 3 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 13783#true, 13784#false, 13785#(<= 1 main_~length3~0), 13786#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 13787#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= (select |#valid| |main_#t~malloc9.base|) 1)), 13788#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (or (< 1 (+ main_~nondetString1~0.offset main_~length1~0)) (and (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= (select |#valid| main_~nondetString1~0.base) 1))) (= main_~nondetString1~0.offset 0)), 13789#(and (or (< 1 (+ main_~nondetString1~0.offset main_~length1~0)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 13790#(and (= 0 main_~nondetString2~0.offset) (= main_~nondetString1~0.offset 0) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (or (< 1 (+ main_~nondetString1~0.offset main_~length1~0)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base))) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1))), 13791#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (or (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (<= (+ main_~length3~0 2) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 13792#(and (= 0 main_~nondetString2~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 6) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1))))) (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 11 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 3))) (+ main_~nondetString2~0.offset (- 1))))) (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 6) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (<= (+ main_~nondetString1~0.offset (select |#length| main_~nondetString1~0.base)) 1) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 2))) (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1))))))) (= main_~nondetString1~0.offset 0)), 13793#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 2)) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (or (<= 12 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 3)) (- 1))))) (<= 11 (select |#length| |cstrcat_#in~s.base|))) (and (<= 5 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1))))) (and (<= 10 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 6 1) (- 1))))) (and (<= (select |#length| |cstrcat_#in~append.base|) 1) (= 0 |cstrcat_#in~append.offset|)) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 6 (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 7 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 13794#(and (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 6 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 6 (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (or (<= 12 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= 11 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 13795#(and (= cstrcat_~s.offset 0) (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 6 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 6 (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (or (<= 12 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= 11 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 13796#(and (or (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1))))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 6 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 6 (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (or (<= 12 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= 11 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 0)), 13797#(or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 5) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 5) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 13798#(or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 5) 1) (- 1))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 5) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)))), 13799#(or (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 5) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 5) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)))), 13800#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 13801#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 13802#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 13803#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 13804#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 13805#(or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 13806#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))))), 13807#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1)))))) (= |cstrcat_#t~mem1| 0)), 13808#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))))), 13809#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 13810#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 13811#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 3)) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 13812#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13813#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0)), 13814#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 13815#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 13816#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)), 13817#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 13818#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 13819#(and (or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= 0 cstrcat_~s.offset)), 13820#(and (or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= 0 cstrcat_~s.offset)), 13821#(and (<= 1 cstrcat_~s.offset) (or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 13822#(and (or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))) (<= 2 cstrcat_~s.offset)), 13823#(and (<= 3 cstrcat_~s.offset) (or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))))] [2018-02-04 15:02:25,841 INFO L134 CoverageAnalysis]: Checked inductivity of 214 backedges. 0 proven. 214 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:25,841 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-02-04 15:02:25,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-02-04 15:02:25,841 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=233, Invalid=1659, Unknown=0, NotChecked=0, Total=1892 [2018-02-04 15:02:25,842 INFO L87 Difference]: Start difference. First operand 153 states and 159 transitions. Second operand 44 states. [2018-02-04 15:02:26,227 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 118 DAG size of output 117 [2018-02-04 15:02:26,842 WARN L146 SmtUtils]: Spent 156ms on a formula simplification. DAG size of input: 146 DAG size of output 144 [2018-02-04 15:02:26,982 WARN L146 SmtUtils]: Spent 112ms on a formula simplification. DAG size of input: 138 DAG size of output 137 [2018-02-04 15:02:27,138 WARN L146 SmtUtils]: Spent 122ms on a formula simplification. DAG size of input: 135 DAG size of output 132 [2018-02-04 15:02:27,343 WARN L146 SmtUtils]: Spent 166ms on a formula simplification. DAG size of input: 140 DAG size of output 138 [2018-02-04 15:02:27,479 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 135 DAG size of output 128 [2018-02-04 15:02:27,620 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 132 DAG size of output 126 [2018-02-04 15:02:27,792 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 137 DAG size of output 132 [2018-02-04 15:02:27,929 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 132 DAG size of output 122 [2018-02-04 15:02:28,075 WARN L146 SmtUtils]: Spent 104ms on a formula simplification. DAG size of input: 125 DAG size of output 119 [2018-02-04 15:02:28,232 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 130 DAG size of output 125 [2018-02-04 15:02:28,625 WARN L146 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 124 DAG size of output 119 [2018-02-04 15:02:29,004 WARN L146 SmtUtils]: Spent 103ms on a formula simplification. DAG size of input: 116 DAG size of output 111 [2018-02-04 15:02:29,360 WARN L146 SmtUtils]: Spent 107ms on a formula simplification. DAG size of input: 110 DAG size of output 105 [2018-02-04 15:02:30,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:30,140 INFO L93 Difference]: Finished difference Result 167 states and 173 transitions. [2018-02-04 15:02:30,140 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-02-04 15:02:30,140 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 70 [2018-02-04 15:02:30,140 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:30,141 INFO L225 Difference]: With dead ends: 167 [2018-02-04 15:02:30,141 INFO L226 Difference]: Without dead ends: 167 [2018-02-04 15:02:30,142 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1743 ImplicationChecksByTransitivity, 7.8s TimeCoverageRelationStatistics Valid=781, Invalid=5225, Unknown=0, NotChecked=0, Total=6006 [2018-02-04 15:02:30,142 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-02-04 15:02:30,143 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 153. [2018-02-04 15:02:30,143 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-02-04 15:02:30,144 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 159 transitions. [2018-02-04 15:02:30,144 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 159 transitions. Word has length 70 [2018-02-04 15:02:30,144 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:30,144 INFO L432 AbstractCegarLoop]: Abstraction has 153 states and 159 transitions. [2018-02-04 15:02:30,144 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-02-04 15:02:30,144 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 159 transitions. [2018-02-04 15:02:30,145 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-02-04 15:02:30,145 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:30,145 INFO L351 BasicCegarLoop]: trace histogram [10, 10, 9, 9, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:30,145 INFO L371 AbstractCegarLoop]: === Iteration 52 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:02:30,145 INFO L82 PathProgramCache]: Analyzing trace with hash -1007251000, now seen corresponding path program 18 times [2018-02-04 15:02:30,146 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:30,161 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:30,162 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:31,046 WARN L146 SmtUtils]: Spent 227ms on a formula simplification. DAG size of input: 126 DAG size of output 80 [2018-02-04 15:02:31,272 WARN L146 SmtUtils]: Spent 212ms on a formula simplification. DAG size of input: 105 DAG size of output 72 [2018-02-04 15:02:31,475 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 105 DAG size of output 72 [2018-02-04 15:02:31,684 WARN L146 SmtUtils]: Spent 191ms on a formula simplification. DAG size of input: 107 DAG size of output 72 [2018-02-04 15:02:31,890 WARN L146 SmtUtils]: Spent 185ms on a formula simplification. DAG size of input: 105 DAG size of output 70 [2018-02-04 15:02:32,119 WARN L146 SmtUtils]: Spent 203ms on a formula simplification. DAG size of input: 115 DAG size of output 72 [2018-02-04 15:02:32,364 WARN L146 SmtUtils]: Spent 219ms on a formula simplification. DAG size of input: 117 DAG size of output 72 [2018-02-04 15:02:32,582 WARN L146 SmtUtils]: Spent 185ms on a formula simplification. DAG size of input: 115 DAG size of output 68 [2018-02-04 15:02:32,752 WARN L146 SmtUtils]: Spent 147ms on a formula simplification. DAG size of input: 85 DAG size of output 63 [2018-02-04 15:02:32,929 WARN L146 SmtUtils]: Spent 151ms on a formula simplification. DAG size of input: 87 DAG size of output 63 [2018-02-04 15:02:33,089 WARN L146 SmtUtils]: Spent 130ms on a formula simplification. DAG size of input: 85 DAG size of output 60 [2018-02-04 15:02:33,219 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 67 DAG size of output 54 [2018-02-04 15:02:34,188 INFO L134 CoverageAnalysis]: Checked inductivity of 184 backedges. 4 proven. 180 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:34,188 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:34,188 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42] total 42 [2018-02-04 15:02:34,188 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:34,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:34,189 INFO L182 omatonBuilderFactory]: Interpolants [14215#true, 14216#false, 14217#(<= 1 main_~length3~0), 14218#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 14219#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 1 (select |#valid| |main_#t~malloc9.base|)) (<= 1 main_~length3~0)), 14220#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base))), 14221#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 14222#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= 1 main_~length3~0)), 14223#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base)) (<= (+ main_~nondetString2~0.offset main_~length3~0) 2)) (<= 1 main_~length3~0)), 14224#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (<= (+ (select |#length| main_~nondetString1~0.base) 9) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) 1) (- 1)))))) (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 14225#(and (= 0 |cstrcat_#in~s.offset|) (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 3 1) 1) (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 7) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 3 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 8) (select |#length| |cstrcat_#in~s.base|)) (or (<= (+ (select |#length| |cstrcat_#in~append.base|) 9) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))))))), 14226#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 3 1) (- 1))))))), 14227#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 3 1) (- 1))))) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 14228#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 3 1) (- 1))))))), 14229#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))))), 14230#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 cstrcat_~append.offset)), 14231#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 cstrcat_~append.offset)), 14232#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))))))), 14233#(or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 14234#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))), 14235#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))), 14236#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))))) (= 0 cstrcat_~append.offset)), 14237#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))), 14238#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 14239#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0))), 14240#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 14241#(and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))))) (= 0 cstrcat_~append.offset)), 14242#(and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (= |cstrcat_#t~mem1| 0))), 14243#(and (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))))), 14244#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= 0 cstrcat_~append.offset)), 14245#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (= |cstrcat_#t~mem1| 0))), 14246#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 14247#(and (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 14248#(and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset)), 14249#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 14250#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset)), 14251#(and (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 14252#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 14253#(<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)), 14254#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset)), 14255#(and (<= 1 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 14256#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|))), 14257#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|)))] [2018-02-04 15:02:34,189 INFO L134 CoverageAnalysis]: Checked inductivity of 184 backedges. 4 proven. 180 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:34,189 INFO L409 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-02-04 15:02:34,189 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-02-04 15:02:34,190 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=230, Invalid=1576, Unknown=0, NotChecked=0, Total=1806 [2018-02-04 15:02:34,190 INFO L87 Difference]: Start difference. First operand 153 states and 159 transitions. Second operand 43 states. [2018-02-04 15:02:35,003 WARN L146 SmtUtils]: Spent 129ms on a formula simplification. DAG size of input: 136 DAG size of output 135 [2018-02-04 15:02:35,216 WARN L146 SmtUtils]: Spent 109ms on a formula simplification. DAG size of input: 131 DAG size of output 123 [2018-02-04 15:02:35,388 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 135 DAG size of output 130 [2018-02-04 15:02:36,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:36,980 INFO L93 Difference]: Finished difference Result 171 states and 177 transitions. [2018-02-04 15:02:36,980 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-02-04 15:02:36,980 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 71 [2018-02-04 15:02:36,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:36,981 INFO L225 Difference]: With dead ends: 171 [2018-02-04 15:02:36,981 INFO L226 Difference]: Without dead ends: 157 [2018-02-04 15:02:36,981 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1657 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=779, Invalid=5073, Unknown=0, NotChecked=0, Total=5852 [2018-02-04 15:02:36,982 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-02-04 15:02:36,982 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 153. [2018-02-04 15:02:36,982 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-02-04 15:02:36,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 158 transitions. [2018-02-04 15:02:36,983 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 158 transitions. Word has length 71 [2018-02-04 15:02:36,983 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:36,983 INFO L432 AbstractCegarLoop]: Abstraction has 153 states and 158 transitions. [2018-02-04 15:02:36,983 INFO L433 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-02-04 15:02:36,983 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 158 transitions. [2018-02-04 15:02:36,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-02-04 15:02:36,983 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:36,983 INFO L351 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:36,983 INFO L371 AbstractCegarLoop]: === Iteration 53 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:02:36,983 INFO L82 PathProgramCache]: Analyzing trace with hash 40710937, now seen corresponding path program 12 times [2018-02-04 15:02:36,984 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:36,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:36,996 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:39,758 WARN L146 SmtUtils]: Spent 867ms on a formula simplification. DAG size of input: 552 DAG size of output 102 [2018-02-04 15:02:40,460 WARN L146 SmtUtils]: Spent 646ms on a formula simplification. DAG size of input: 445 DAG size of output 88 [2018-02-04 15:02:41,224 WARN L146 SmtUtils]: Spent 697ms on a formula simplification. DAG size of input: 445 DAG size of output 90 [2018-02-04 15:02:41,950 WARN L146 SmtUtils]: Spent 651ms on a formula simplification. DAG size of input: 447 DAG size of output 90 [2018-02-04 15:02:42,702 WARN L146 SmtUtils]: Spent 668ms on a formula simplification. DAG size of input: 445 DAG size of output 88 [2018-02-04 15:02:43,485 WARN L146 SmtUtils]: Spent 687ms on a formula simplification. DAG size of input: 463 DAG size of output 96 [2018-02-04 15:02:44,223 WARN L146 SmtUtils]: Spent 643ms on a formula simplification. DAG size of input: 465 DAG size of output 99 [2018-02-04 15:02:44,978 WARN L146 SmtUtils]: Spent 656ms on a formula simplification. DAG size of input: 463 DAG size of output 94 [2018-02-04 15:02:45,591 WARN L146 SmtUtils]: Spent 538ms on a formula simplification. DAG size of input: 323 DAG size of output 87 [2018-02-04 15:02:46,189 WARN L146 SmtUtils]: Spent 520ms on a formula simplification. DAG size of input: 325 DAG size of output 87 [2018-02-04 15:02:46,797 WARN L146 SmtUtils]: Spent 523ms on a formula simplification. DAG size of input: 323 DAG size of output 85 [2018-02-04 15:02:47,150 WARN L146 SmtUtils]: Spent 285ms on a formula simplification. DAG size of input: 231 DAG size of output 80 [2018-02-04 15:02:47,507 WARN L146 SmtUtils]: Spent 289ms on a formula simplification. DAG size of input: 233 DAG size of output 80 [2018-02-04 15:02:47,870 WARN L146 SmtUtils]: Spent 289ms on a formula simplification. DAG size of input: 231 DAG size of output 78 [2018-02-04 15:02:48,171 WARN L146 SmtUtils]: Spent 245ms on a formula simplification. DAG size of input: 171 DAG size of output 73 [2018-02-04 15:02:48,471 WARN L146 SmtUtils]: Spent 243ms on a formula simplification. DAG size of input: 173 DAG size of output 73 [2018-02-04 15:02:48,770 WARN L146 SmtUtils]: Spent 239ms on a formula simplification. DAG size of input: 171 DAG size of output 71 [2018-02-04 15:02:48,971 WARN L146 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 120 DAG size of output 65 [2018-02-04 15:02:49,158 WARN L146 SmtUtils]: Spent 136ms on a formula simplification. DAG size of input: 122 DAG size of output 65 [2018-02-04 15:02:49,336 WARN L146 SmtUtils]: Spent 123ms on a formula simplification. DAG size of input: 120 DAG size of output 63 [2018-02-04 15:02:49,604 WARN L146 SmtUtils]: Spent 101ms on a formula simplification. DAG size of input: 82 DAG size of output 55 [2018-02-04 15:02:50,788 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,788 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:02:50,788 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50] total 50 [2018-02-04 15:02:50,788 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:02:50,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,789 INFO L182 omatonBuilderFactory]: Interpolants [14650#true, 14651#false, 14652#(<= 1 main_~length1~0), 14653#(and (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 14654#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 14655#(and (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0)), 14656#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (= main_~nondetString1~0.offset 0)), 14657#(and (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= 1 main_~length1~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|)) (= main_~nondetString1~0.offset 0)), 14658#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0) (<= 1 main_~length1~0)) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 14659#(and (= 0 main_~nondetString2~0.offset) (or (= (+ main_~nondetString2~0.offset main_~length3~0) 2) (and (<= 1 main_~length3~0) (<= (+ main_~length3~0 1) (+ (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= (+ main_~nondetString2~0.offset main_~length3~0) 1)) (= main_~nondetString1~0.offset 0)), 14660#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (- 1))))) (<= 7 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 12 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 13 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 2))) (- 1))))) (<= 14 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= 4 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (+ main_~nondetString1~0.offset (- 1))) (+ main_~nondetString2~0.offset (- 1))))) (<= 8 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (and (<= 9 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 6 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) (- 1))))) (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= 5 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= 10 (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base) main_~nondetString1~0.offset)) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 2) 1) 1) (- 1))))))) (= main_~nondetString1~0.offset 0)), 14661#(and (= 0 |cstrcat_#in~s.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (<= 7 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1)))) (<= 6 (select |#length| |cstrcat_#in~s.base|))) (and (<= 9 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 2) 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= 4 (select |#length| |cstrcat_#in~s.base|))) (and (<= 13 (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 2)) (- 1)))) (<= 14 (select |#length| |cstrcat_#in~s.base|)))) (and (<= 12 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (<= 10 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 2) 1) 1) (- 1))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= 5 (select |#length| |cstrcat_#in~s.base|))) (and (<= 8 (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- 1)) (- 1))))))), 14662#(and (= cstrcat_~s.offset 0) (or (and (<= 12 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (<= 13 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= 14 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 2) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 11 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 1) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1))))))), 14663#(and (= cstrcat_~s.offset 0) (or (and (<= 12 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (<= 13 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= 14 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 2) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 11 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 1) (- 1))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1))))))), 14664#(and (or (and (<= 12 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 2) (- 1))))) (and (<= 13 (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= 14 (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 2) 1) (- 1)))) (<= 10 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= 4 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= 8 (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1)))) (<= 6 (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= 11 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 2) 1) 1) (- 1))))) (and (<= 5 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 2) (- 1)))) (<= 9 (select |#length| cstrcat_~s.base))) (and (<= 7 (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))))) (= cstrcat_~s.offset 0)), 14665#(and (or (and (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 13) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (= cstrcat_~s.offset 1)), 14666#(and (= cstrcat_~s.offset 1) (or (and (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 13) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0))), 14667#(and (= cstrcat_~s.offset 1) (or (and (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 13) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 2) 1) (- 1))))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))))), 14668#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14669#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 14670#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (<= (+ cstrcat_~s.offset 12) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14671#(or (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 14672#(or (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 14673#(or (and (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 14674#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))))), 14675#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))))), 14676#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))))), 14677#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14678#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 14679#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14680#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14681#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 14682#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14683#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14684#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 14685#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14686#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 14687#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 14688#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 1)) (- 1)))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 14689#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14690#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= |cstrcat_#t~mem1| 0)), 14691#(or (and (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 14692#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))), 14693#(or (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 14694#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))), 14695#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 14696#(or (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 14697#(<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)), 14698#(<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)), 14699#(and (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 0 cstrcat_~s.offset)), 14700#(and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:02:50,789 INFO L134 CoverageAnalysis]: Checked inductivity of 338 backedges. 0 proven. 338 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:02:50,789 INFO L409 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-02-04 15:02:50,789 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-02-04 15:02:50,790 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=424, Invalid=2126, Unknown=0, NotChecked=0, Total=2550 [2018-02-04 15:02:50,790 INFO L87 Difference]: Start difference. First operand 153 states and 158 transitions. Second operand 51 states. [2018-02-04 15:02:51,172 WARN L146 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 121 DAG size of output 121 [2018-02-04 15:02:51,955 WARN L146 SmtUtils]: Spent 206ms on a formula simplification. DAG size of input: 174 DAG size of output 173 [2018-02-04 15:02:52,245 WARN L146 SmtUtils]: Spent 150ms on a formula simplification. DAG size of input: 163 DAG size of output 157 [2018-02-04 15:02:52,489 WARN L146 SmtUtils]: Spent 194ms on a formula simplification. DAG size of input: 166 DAG size of output 163 [2018-02-04 15:02:52,654 WARN L146 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 161 DAG size of output 157 [2018-02-04 15:02:52,822 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 157 DAG size of output 151 [2018-02-04 15:02:53,050 WARN L146 SmtUtils]: Spent 185ms on a formula simplification. DAG size of input: 160 DAG size of output 157 [2018-02-04 15:02:53,209 WARN L146 SmtUtils]: Spent 131ms on a formula simplification. DAG size of input: 155 DAG size of output 151 [2018-02-04 15:02:53,398 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 150 DAG size of output 144 [2018-02-04 15:02:53,608 WARN L146 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 153 DAG size of output 150 [2018-02-04 15:02:53,760 WARN L146 SmtUtils]: Spent 120ms on a formula simplification. DAG size of input: 148 DAG size of output 144 [2018-02-04 15:02:53,916 WARN L146 SmtUtils]: Spent 118ms on a formula simplification. DAG size of input: 143 DAG size of output 137 [2018-02-04 15:02:54,114 WARN L146 SmtUtils]: Spent 157ms on a formula simplification. DAG size of input: 146 DAG size of output 143 [2018-02-04 15:02:54,303 WARN L146 SmtUtils]: Spent 143ms on a formula simplification. DAG size of input: 141 DAG size of output 137 [2018-02-04 15:02:54,461 WARN L146 SmtUtils]: Spent 114ms on a formula simplification. DAG size of input: 135 DAG size of output 129 [2018-02-04 15:02:54,642 WARN L146 SmtUtils]: Spent 135ms on a formula simplification. DAG size of input: 138 DAG size of output 135 [2018-02-04 15:02:54,783 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 133 DAG size of output 129 [2018-02-04 15:02:54,930 WARN L146 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 129 DAG size of output 123 [2018-02-04 15:02:55,095 WARN L146 SmtUtils]: Spent 121ms on a formula simplification. DAG size of input: 132 DAG size of output 129 [2018-02-04 15:02:55,385 WARN L146 SmtUtils]: Spent 105ms on a formula simplification. DAG size of input: 123 DAG size of output 117 [2018-02-04 15:02:55,544 WARN L146 SmtUtils]: Spent 110ms on a formula simplification. DAG size of input: 126 DAG size of output 123 [2018-02-04 15:02:56,008 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 118 DAG size of output 115 [2018-02-04 15:02:57,275 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:02:57,276 INFO L93 Difference]: Finished difference Result 180 states and 187 transitions. [2018-02-04 15:02:57,276 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-02-04 15:02:57,276 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 72 [2018-02-04 15:02:57,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:02:57,276 INFO L225 Difference]: With dead ends: 180 [2018-02-04 15:02:57,276 INFO L226 Difference]: Without dead ends: 180 [2018-02-04 15:02:57,277 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 91 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2455 ImplicationChecksByTransitivity, 17.8s TimeCoverageRelationStatistics Valid=1480, Invalid=7076, Unknown=0, NotChecked=0, Total=8556 [2018-02-04 15:02:57,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-02-04 15:02:57,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 161. [2018-02-04 15:02:57,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-02-04 15:02:57,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 167 transitions. [2018-02-04 15:02:57,278 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 167 transitions. Word has length 72 [2018-02-04 15:02:57,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:02:57,278 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 167 transitions. [2018-02-04 15:02:57,278 INFO L433 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-02-04 15:02:57,278 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 167 transitions. [2018-02-04 15:02:57,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-04 15:02:57,279 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:02:57,279 INFO L351 BasicCegarLoop]: trace histogram [12, 12, 11, 11, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:02:57,279 INFO L371 AbstractCegarLoop]: === Iteration 54 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:02:57,279 INFO L82 PathProgramCache]: Analyzing trace with hash -873401462, now seen corresponding path program 19 times [2018-02-04 15:02:57,279 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:02:57,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:02:57,298 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:02:59,151 WARN L146 SmtUtils]: Spent 365ms on a formula simplification. DAG size of input: 180 DAG size of output 97 [2018-02-04 15:02:59,496 WARN L146 SmtUtils]: Spent 327ms on a formula simplification. DAG size of input: 149 DAG size of output 88 [2018-02-04 15:02:59,892 WARN L146 SmtUtils]: Spent 372ms on a formula simplification. DAG size of input: 149 DAG size of output 88 [2018-02-04 15:03:00,278 WARN L146 SmtUtils]: Spent 360ms on a formula simplification. DAG size of input: 151 DAG size of output 88 [2018-02-04 15:03:00,644 WARN L146 SmtUtils]: Spent 338ms on a formula simplification. DAG size of input: 149 DAG size of output 86 [2018-02-04 15:03:01,099 WARN L146 SmtUtils]: Spent 423ms on a formula simplification. DAG size of input: 163 DAG size of output 92 [2018-02-04 15:03:01,549 WARN L146 SmtUtils]: Spent 413ms on a formula simplification. DAG size of input: 165 DAG size of output 92 [2018-02-04 15:03:02,112 WARN L146 SmtUtils]: Spent 511ms on a formula simplification. DAG size of input: 163 DAG size of output 88 [2018-02-04 15:03:02,438 WARN L146 SmtUtils]: Spent 293ms on a formula simplification. DAG size of input: 126 DAG size of output 80 [2018-02-04 15:03:02,786 WARN L146 SmtUtils]: Spent 308ms on a formula simplification. DAG size of input: 128 DAG size of output 80 [2018-02-04 15:03:03,107 WARN L146 SmtUtils]: Spent 269ms on a formula simplification. DAG size of input: 126 DAG size of output 78 [2018-02-04 15:03:03,328 WARN L146 SmtUtils]: Spent 186ms on a formula simplification. DAG size of input: 105 DAG size of output 72 [2018-02-04 15:03:03,549 WARN L146 SmtUtils]: Spent 187ms on a formula simplification. DAG size of input: 107 DAG size of output 72 [2018-02-04 15:03:03,763 WARN L146 SmtUtils]: Spent 177ms on a formula simplification. DAG size of input: 105 DAG size of output 70 [2018-02-04 15:03:03,926 WARN L146 SmtUtils]: Spent 132ms on a formula simplification. DAG size of input: 86 DAG size of output 64 [2018-02-04 15:03:04,082 WARN L146 SmtUtils]: Spent 124ms on a formula simplification. DAG size of input: 88 DAG size of output 64 [2018-02-04 15:03:04,233 WARN L146 SmtUtils]: Spent 115ms on a formula simplification. DAG size of input: 86 DAG size of output 62 [2018-02-04 15:03:05,357 INFO L134 CoverageAnalysis]: Checked inductivity of 257 backedges. 0 proven. 257 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:05,357 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:05,357 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47] total 47 [2018-02-04 15:03:05,357 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:05,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:05,358 INFO L182 omatonBuilderFactory]: Interpolants [15168#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base))), 15169#(or (and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|) cstrcat_~append.offset)) (and (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset))), 15170#(or (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset) (and (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= (+ |cstrcat_#t~post2.offset| 1) cstrcat_~s.offset))), 15171#(or (and (<= 1 cstrcat_~s.offset) (<= (+ cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base))) (<= (select |#length| cstrcat_~append.base) cstrcat_~append.offset)), 15172#(or (and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))) (<= (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post3.offset|)), 15173#(and (<= 1 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 15126#true, 15127#false, 15128#(<= 1 main_~length3~0), 15129#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 15130#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 1 (select |#valid| |main_#t~malloc9.base|)) (<= 1 main_~length3~0)), 15131#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base))), 15132#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 15133#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)), 15134#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))), 15135#(and (= 0 main_~nondetString2~0.offset) (= 0 main_~nondetString1~0.offset) (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (or (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) 1) 1) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 11) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (<= (+ (select |#length| main_~nondetString1~0.base) 10) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) 1) 1) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (select |#length| main_~nondetString2~0.base) (- (select |#length| main_~nondetString1~0.base))) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 9) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 3) 1) 1) 1) (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))))), 15136#(and (= 0 |cstrcat_#in~s.offset|) (or (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 7) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (select |#length| |cstrcat_#in~s.base|) (- (select |#length| |cstrcat_#in~append.base|))) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 9) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 10) (select |#length| |cstrcat_#in~s.base|)) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 11) (select |#length| |cstrcat_#in~s.base|)))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 3 1) 1) (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 8) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 3 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1))) (= 0 |cstrcat_#in~append.offset|)), 15137#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 11) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 3 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 15138#(and (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 11) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 3 1) (- 1))))) (= |cstrcat_#t~mem1| 0) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0)), 15139#(and (= 0 cstrcat_~append.offset) (= cstrcat_~s.offset 0) (or (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 11) (select |#length| cstrcat_~s.base))) (<= (+ (select |#length| cstrcat_~append.base) 10) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 3 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ 3 1) 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- (select |#length| cstrcat_~append.base))) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 3 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 3 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ 3 1) 1) 1) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base))))), 15140#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) 1) (- 1)))))) (and (= cstrcat_~s.offset 1) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))) (= 0 cstrcat_~append.offset)), 15141#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= cstrcat_~s.offset 1) (= |cstrcat_#t~mem1| 0)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) 1) (- 1))))))) (= 0 cstrcat_~append.offset)), 15142#(and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (+ (- (+ cstrcat_~s.offset (+ (select |#length| cstrcat_~append.base) (- 1)))) (+ cstrcat_~s.offset (- 1)))) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) 1) (- 1)))))))), 15143#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 15144#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 15145#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 11) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 15146#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 15147#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 15148#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 10) (select |#length| cstrcat_~s.base)))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))), 15149#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 15150#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 15151#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) 1) (- 1))))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)))), 15152#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 15153#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 15154#(or (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 2) 1) 1) (- 1)))) (<= (+ cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 15155#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 15156#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1))))) (= |cstrcat_#t~mem1| 0)), 15157#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (<= (+ cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 2) 1) (- 1))))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))))), 15158#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 15159#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)), 15160#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))) (<= (+ cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base))) (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (select |#length| cstrcat_~s.base) (- 2)) (- 1)))) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)))), 15161#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 15162#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))) (= |cstrcat_#t~mem1| 0)), 15163#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (and (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (or (<= (+ cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 15164#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 15165#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)), 15166#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))), 15167#(or (and (= 0 cstrcat_~append.offset) (<= (select |#length| cstrcat_~append.base) 1)) (<= (+ cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))] [2018-02-04 15:03:05,358 INFO L134 CoverageAnalysis]: Checked inductivity of 257 backedges. 0 proven. 257 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:05,358 INFO L409 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-02-04 15:03:05,358 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-02-04 15:03:05,358 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=323, Invalid=1933, Unknown=0, NotChecked=0, Total=2256 [2018-02-04 15:03:05,359 INFO L87 Difference]: Start difference. First operand 161 states and 167 transitions. Second operand 48 states. [2018-02-04 15:03:06,465 WARN L146 SmtUtils]: Spent 179ms on a formula simplification. DAG size of input: 170 DAG size of output 169 [2018-02-04 15:03:06,735 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 158 DAG size of output 155 [2018-02-04 15:03:07,131 WARN L146 SmtUtils]: Spent 126ms on a formula simplification. DAG size of input: 151 DAG size of output 148 [2018-02-04 15:03:07,485 WARN L146 SmtUtils]: Spent 108ms on a formula simplification. DAG size of input: 144 DAG size of output 141 [2018-02-04 15:03:09,472 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:09,472 INFO L93 Difference]: Finished difference Result 175 states and 181 transitions. [2018-02-04 15:03:09,473 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-02-04 15:03:09,473 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 74 [2018-02-04 15:03:09,473 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:09,473 INFO L225 Difference]: With dead ends: 175 [2018-02-04 15:03:09,473 INFO L226 Difference]: Without dead ends: 175 [2018-02-04 15:03:09,473 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2170 ImplicationChecksByTransitivity, 10.1s TimeCoverageRelationStatistics Valid=1069, Invalid=6241, Unknown=0, NotChecked=0, Total=7310 [2018-02-04 15:03:09,474 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-02-04 15:03:09,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 161. [2018-02-04 15:03:09,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-02-04 15:03:09,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 167 transitions. [2018-02-04 15:03:09,475 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 167 transitions. Word has length 74 [2018-02-04 15:03:09,475 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:09,475 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 167 transitions. [2018-02-04 15:03:09,475 INFO L433 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-02-04 15:03:09,476 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 167 transitions. [2018-02-04 15:03:09,476 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 76 [2018-02-04 15:03:09,476 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:09,476 INFO L351 BasicCegarLoop]: trace histogram [11, 11, 10, 10, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:09,476 INFO L371 AbstractCegarLoop]: === Iteration 55 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:03:09,476 INFO L82 PathProgramCache]: Analyzing trace with hash 353042149, now seen corresponding path program 20 times [2018-02-04 15:03:09,477 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:09,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:09,491 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:10,473 WARN L146 SmtUtils]: Spent 217ms on a formula simplification. DAG size of input: 310 DAG size of output 87 [2018-02-04 15:03:10,702 WARN L146 SmtUtils]: Spent 205ms on a formula simplification. DAG size of input: 232 DAG size of output 80 [2018-02-04 15:03:10,968 WARN L146 SmtUtils]: Spent 241ms on a formula simplification. DAG size of input: 232 DAG size of output 80 [2018-02-04 15:03:11,234 WARN L146 SmtUtils]: Spent 236ms on a formula simplification. DAG size of input: 234 DAG size of output 80 [2018-02-04 15:03:11,477 WARN L146 SmtUtils]: Spent 209ms on a formula simplification. DAG size of input: 232 DAG size of output 78 [2018-02-04 15:03:11,718 WARN L146 SmtUtils]: Spent 203ms on a formula simplification. DAG size of input: 242 DAG size of output 82 [2018-02-04 15:03:11,959 WARN L146 SmtUtils]: Spent 200ms on a formula simplification. DAG size of input: 244 DAG size of output 82 [2018-02-04 15:03:12,232 WARN L146 SmtUtils]: Spent 228ms on a formula simplification. DAG size of input: 242 DAG size of output 79 [2018-02-04 15:03:12,442 WARN L146 SmtUtils]: Spent 172ms on a formula simplification. DAG size of input: 164 DAG size of output 71 [2018-02-04 15:03:12,631 WARN L146 SmtUtils]: Spent 148ms on a formula simplification. DAG size of input: 166 DAG size of output 71 [2018-02-04 15:03:12,812 WARN L146 SmtUtils]: Spent 137ms on a formula simplification. DAG size of input: 164 DAG size of output 68 [2018-02-04 15:03:14,277 INFO L134 CoverageAnalysis]: Checked inductivity of 223 backedges. 4 proven. 219 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:14,278 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 15:03:14,278 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44] total 44 [2018-02-04 15:03:14,278 INFO L142 lantAutomatonBuilder]: Constructing canonical interpolant automaton, with selfloop in false state [2018-02-04 15:03:14,278 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:14,278 INFO L182 omatonBuilderFactory]: Interpolants [15616#(or (and (<= 6 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= |cstrcat_#t~mem1| 0)), 15617#(and (<= 6 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 15618#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 7 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 15619#(or (= |cstrcat_#t~mem1| 0) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 7 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))), 15620#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (<= 7 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1)))))), 15621#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (<= 8 cstrcat_~s.offset) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 15622#(and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= |cstrcat_#t~mem1| 0)) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (<= 8 cstrcat_~s.offset)), 15623#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 cstrcat_~append.offset) (<= 8 cstrcat_~s.offset)), 15624#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 1) (select |#length| cstrcat_~s.base)) (<= 9 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 15625#(and (<= 10 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (select |#length| cstrcat_~s.base))), 15626#(and (= |cstrcat_#t~post3.base| cstrcat_~append.base) (= |cstrcat_#t~post3.offset| 0) (<= (+ (select |#length| |cstrcat_#t~post3.base|) cstrcat_~s.offset |cstrcat_#t~post3.offset|) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 11 cstrcat_~s.offset)), 15627#(and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset)) (<= 11 cstrcat_~s.offset)), 15628#(and (<= 12 cstrcat_~s.offset) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset) (+ (select |#length| cstrcat_~s.base) cstrcat_~append.offset))), 15629#(and (<= (+ (select |#length| |cstrcat_#t~post3.base|) |cstrcat_#t~post2.offset|) (+ (select |#length| |cstrcat_#t~post2.base|) |cstrcat_#t~post3.offset|)) (<= 12 |cstrcat_#t~post2.offset|)), 15630#(and (<= 12 |cstrcat_#t~post2.offset|) (<= (+ |cstrcat_#t~post2.offset| 1) (select |#length| |cstrcat_#t~post2.base|))), 15586#true, 15587#false, 15588#(<= 1 main_~length3~0), 15589#(and (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0)), 15590#(and (= main_~length1~0 (select |#length| |main_#t~malloc9.base|)) (= 0 |main_#t~malloc9.offset|) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (= 1 (select |#valid| |main_#t~malloc9.base|)) (<= 1 main_~length3~0)), 15591#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) main_~length2~0) (<= 1 main_~length3~0) (= 1 (select |#valid| main_~nondetString1~0.base))), 15592#(and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (= 0 |main_#t~malloc10.offset|) (<= 1 main_~length3~0) (<= (+ main_~length3~0 main_~length1~0) (select |#length| |main_#t~malloc10.base|))), 15593#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (= main_~length1~0 (select |#length| main_~nondetString1~0.base)) (<= (+ main_~length3~0 main_~length1~0) (select |#length| main_~nondetString2~0.base)) (<= 1 main_~length3~0)))), 15594#(and (= 0 main_~nondetString2~0.offset) (or (= 2 (+ main_~nondetString2~0.offset main_~length3~0)) (and (= 0 main_~nondetString1~0.offset) (<= 1 main_~length3~0) (<= (+ main_~length3~0 (select |#length| main_~nondetString1~0.base)) (select |#length| main_~nondetString2~0.base))))), 15595#(and (= 0 main_~nondetString2~0.offset) (or (and (= 0 main_~nondetString1~0.offset) (or (and (<= (+ (select |#length| main_~nondetString1~0.base) 5) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 5) (+ main_~nondetString2~0.offset (- 1)))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) main_~nondetString2~0.offset)) (and (<= (+ (select |#length| main_~nondetString1~0.base) 4) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 4) (+ main_~nondetString2~0.offset (- 1)))))) (and (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) (+ main_~nondetString2~0.offset (- 1))))) (<= (+ (select |#length| main_~nondetString1~0.base) 6) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base)))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 7) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 1) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 3) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (- main_~nondetString2~0.offset) 3) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 8) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) (+ main_~nondetString2~0.offset (- 1)))))) (and (<= (+ (select |#length| main_~nondetString1~0.base) 9) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (or (<= (+ (select |#length| main_~nondetString1~0.base) 10) (+ main_~nondetString2~0.offset (select |#length| main_~nondetString2~0.base))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) (+ main_~nondetString2~0.offset (+ (+ (+ (+ (+ (- main_~nondetString2~0.offset) 5) 1) 2) 1) (- 1))))))))) (= 0 (select (select |#memory_int| main_~nondetString2~0.base) 1)))), 15596#(and (= 0 |cstrcat_#in~s.offset|) (or (and (= 0 |cstrcat_#in~append.offset|) (or (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) |cstrcat_#in~s.offset|)) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 3 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 3) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 5) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 5 (- 1))))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 9) (select |#length| |cstrcat_#in~s.base|)) (or (<= (+ (select |#length| |cstrcat_#in~append.base|) 10) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 2) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 8) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ 4 (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 4) (select |#length| |cstrcat_#in~s.base|))) (and (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ 5 1) (- 1)))) (<= (+ (select |#length| |cstrcat_#in~append.base|) 6) (select |#length| |cstrcat_#in~s.base|))) (and (<= (+ (select |#length| |cstrcat_#in~append.base|) 7) (select |#length| |cstrcat_#in~s.base|)) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) (+ (+ (+ 5 1) 1) (- 1))))))) (= 0 (select (select |#memory_int| |cstrcat_#in~s.base|) 1)))), 15597#(and (= cstrcat_~s.offset 0) (or (and (or (and (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 10) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))) (= 0 cstrcat_~append.offset)) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 15598#(and (= cstrcat_~s.offset 0) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 10) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1))))) (= |cstrcat_#t~mem1| 0))) (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)))), 15599#(and (or (= 0 (select (select |#memory_int| cstrcat_~s.base) 1)) (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) 9) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ 5 1) 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 10) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 4 (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 5 (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ 3 (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ 5 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) 6) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) 8) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ 5 1) 2) (- 1)))))))) (= cstrcat_~s.offset 0)), 15600#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))), 15601#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (or (and (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))) (= |cstrcat_#t~mem1| 0))), 15602#(and (<= cstrcat_~s.offset 1) (< 0 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 1) (- 1))))) (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 9) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 4) 1) 2) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 15603#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset))), 15604#(or (= |cstrcat_#t~mem1| 0) (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset))), 15605#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (or (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) 1) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 8) (select |#length| cstrcat_~s.base)))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 1) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (<= 2 cstrcat_~s.offset) (= 0 cstrcat_~append.offset)), 15606#(or (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1))))))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset))), 15607#(or (= |cstrcat_#t~mem1| 0) (and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1))))))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset))), 15608#(and (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 2) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 7) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ (+ cstrcat_~s.offset 3) 2) 1) (- 1))))))) (= 0 cstrcat_~append.offset) (<= 3 cstrcat_~s.offset)), 15609#(or (and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset))), 15610#(or (and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))) (= |cstrcat_#t~mem1| 0)), 15611#(and (<= 4 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 6) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 4) 1) (- 1)))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 4) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))))), 15612#(and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base)))) (= 0 cstrcat_~append.offset) (<= 5 cstrcat_~s.offset)), 15613#(and (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (= |cstrcat_#t~mem1| 0)) (= 0 cstrcat_~append.offset) (<= 5 cstrcat_~s.offset)), 15614#(and (= 0 cstrcat_~append.offset) (<= 5 cstrcat_~s.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 5) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ (+ cstrcat_~s.offset 3) 1) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))) (and (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1)))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))))), 15615#(or (and (<= 6 cstrcat_~s.offset) (= 0 cstrcat_~append.offset) (or (and (or (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 4) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 3) (- 1))))) (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 3) (select |#length| cstrcat_~s.base))) (and (<= (+ (select |#length| cstrcat_~append.base) cstrcat_~s.offset 2) (select |#length| cstrcat_~s.base)) (= 0 (select (select |#memory_int| cstrcat_~s.base) (+ (+ cstrcat_~s.offset 2) (- 1))))))) (= 0 (select (select |#memory_int| cstrcat_~s.base) cstrcat_~s.offset)))] [2018-02-04 15:03:14,279 INFO L134 CoverageAnalysis]: Checked inductivity of 223 backedges. 4 proven. 219 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 15:03:14,279 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-02-04 15:03:14,279 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-02-04 15:03:14,279 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=116, Invalid=1864, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 15:03:14,279 INFO L87 Difference]: Start difference. First operand 161 states and 167 transitions. Second operand 45 states. [2018-02-04 15:03:14,942 WARN L146 SmtUtils]: Spent 153ms on a formula simplification. DAG size of input: 139 DAG size of output 138 [2018-02-04 15:03:17,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 15:03:17,811 INFO L93 Difference]: Finished difference Result 180 states and 186 transitions. [2018-02-04 15:03:17,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-02-04 15:03:17,811 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 75 [2018-02-04 15:03:17,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 15:03:17,812 INFO L225 Difference]: With dead ends: 180 [2018-02-04 15:03:17,812 INFO L226 Difference]: Without dead ends: 165 [2018-02-04 15:03:17,812 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 80 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 79 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1561 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=341, Invalid=6139, Unknown=0, NotChecked=0, Total=6480 [2018-02-04 15:03:17,812 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-02-04 15:03:17,813 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 161. [2018-02-04 15:03:17,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-02-04 15:03:17,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 166 transitions. [2018-02-04 15:03:17,813 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 166 transitions. Word has length 75 [2018-02-04 15:03:17,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 15:03:17,813 INFO L432 AbstractCegarLoop]: Abstraction has 161 states and 166 transitions. [2018-02-04 15:03:17,813 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-02-04 15:03:17,813 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 166 transitions. [2018-02-04 15:03:17,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-04 15:03:17,814 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 15:03:17,814 INFO L351 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 15:03:17,814 INFO L371 AbstractCegarLoop]: === Iteration 56 === [cstrcatErr0RequiresViolation, cstrcatErr2RequiresViolation, cstrcatErr1RequiresViolation, cstrcatErr5RequiresViolation, cstrcatErr3RequiresViolation, cstrcatErr4RequiresViolation, mainErr3RequiresViolation, mainErr1RequiresViolation, mainErr2RequiresViolation, mainErr0RequiresViolation, mainErr4EnsuresViolation]=== [2018-02-04 15:03:17,814 INFO L82 PathProgramCache]: Analyzing trace with hash -739874404, now seen corresponding path program 13 times [2018-02-04 15:03:17,814 INFO L67 tionRefinementEngine]: Using refinement strategy FixedTraceAbstractionRefinementStrategy [2018-02-04 15:03:17,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 15:03:17,831 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 15:03:23,866 WARN L146 SmtUtils]: Spent 1574ms on a formula simplification. DAG size of input: 1170 DAG size of output 104 [2018-02-04 15:03:25,315 WARN L146 SmtUtils]: Spent 1338ms on a formula simplification. DAG size of input: 938 DAG size of output 95 [2018-02-04 15:03:26,806 WARN L146 SmtUtils]: Spent 1370ms on a formula simplification. DAG size of input: 938 DAG size of output 95 [2018-02-04 15:03:28,139 WARN L146 SmtUtils]: Spent 1216ms on a formula simplification. DAG size of input: 940 DAG size of output 95 [2018-02-04 15:03:29,465 WARN L146 SmtUtils]: Spent 1201ms on a formula simplification. DAG size of input: 938 DAG size of output 93 [2018-02-04 15:03:31,017 WARN L146 SmtUtils]: Spent 1415ms on a formula simplification. DAG size of input: 958 DAG size of output 107 [2018-02-04 15:03:32,608 WARN L146 SmtUtils]: Spent 1444ms on a formula simplification. DAG size of input: 960 DAG size of output 107 [2018-02-04 15:03:34,082 WARN L146 SmtUtils]: Spent 1317ms on a formula simplification. DAG size of input: 958 DAG size of output 105 [2018-02-04 15:03:35,123 WARN L146 SmtUtils]: Spent 915ms on a formula simplification. DAG size of input: 643 DAG size of output 96 [2018-02-04 15:03:36,096 WARN L146 SmtUtils]: Spent 852ms on a formula simplification. DAG size of input: 645 DAG size of output 96 [2018-02-04 15:03:37,065 WARN L146 SmtUtils]: Spent 822ms on a formula simplification. DAG size of input: 643 DAG size of output 94 [2018-02-04 15:03:37,647 WARN L146 SmtUtils]: Spent 491ms on a formula simplification. DAG size of input: 463 DAG size of output 87 [2018-02-04 15:03:38,242 WARN L146 SmtUtils]: Spent 501ms on a formula simplification. DAG size of input: 465 DAG size of output 87 [2018-02-04 15:03:38,840 WARN L146 SmtUtils]: Spent 494ms on a formula simplification. DAG size of input: 463 DAG size of output 85 [2018-02-04 15:03:39,250 WARN L146 SmtUtils]: Spent 330ms on a formula simplification. DAG size of input: 319 DAG size of output 80 [2018-02-04 15:03:39,703 WARN L146 SmtUtils]: Spent 374ms on a formula simplification. DAG size of input: 321 DAG size of output 80 [2018-02-04 15:03:40,105 WARN L146 SmtUtils]: Spent 319ms on a formula simplification. DAG size of input: 319 DAG size of output 78 [2018-02-04 15:03:40,342 WARN L146 SmtUtils]: Spent 175ms on a formula simplification. DAG size of input: 212 DAG size of output 72 [2018-02-04 15:03:40,570 WARN L146 SmtUtils]: Spent 164ms on a formula simplification. DAG size of input: 214 DAG size of output 72 Received shutdown request... [2018-02-04 15:03:40,580 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 15:03:40,583 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 15:03:40,583 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 03:03:40 BoogieIcfgContainer [2018-02-04 15:03:40,583 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 15:03:40,584 INFO L168 Benchmark]: Toolchain (without parser) took 179955.11 ms. Allocated memory was 389.0 MB in the beginning and 2.1 GB in the end (delta: 1.7 GB). Free memory was 343.1 MB in the beginning and 1.6 GB in the end (delta: -1.2 GB). Peak memory consumption was 460.0 MB. Max. memory is 5.3 GB. [2018-02-04 15:03:40,585 INFO L168 Benchmark]: CDTParser took 0.17 ms. Allocated memory is still 389.0 MB. Free memory is still 348.3 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 15:03:40,585 INFO L168 Benchmark]: CACSL2BoogieTranslator took 158.33 ms. Allocated memory is still 389.0 MB. Free memory was 343.1 MB in the beginning and 332.5 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-02-04 15:03:40,585 INFO L168 Benchmark]: Boogie Preprocessor took 27.17 ms. Allocated memory is still 389.0 MB. Free memory was 332.5 MB in the beginning and 329.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-02-04 15:03:40,585 INFO L168 Benchmark]: RCFGBuilder took 191.49 ms. Allocated memory is still 389.0 MB. Free memory was 329.8 MB in the beginning and 310.0 MB in the end (delta: 19.8 MB). Peak memory consumption was 19.8 MB. Max. memory is 5.3 GB. [2018-02-04 15:03:40,586 INFO L168 Benchmark]: TraceAbstraction took 179575.19 ms. Allocated memory was 389.0 MB in the beginning and 2.1 GB in the end (delta: 1.7 GB). Free memory was 310.0 MB in the beginning and 1.6 GB in the end (delta: -1.2 GB). Peak memory consumption was 427.0 MB. Max. memory is 5.3 GB. [2018-02-04 15:03:40,587 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.17 ms. Allocated memory is still 389.0 MB. Free memory is still 348.3 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 158.33 ms. Allocated memory is still 389.0 MB. Free memory was 343.1 MB in the beginning and 332.5 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 27.17 ms. Allocated memory is still 389.0 MB. Free memory was 332.5 MB in the beginning and 329.8 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 191.49 ms. Allocated memory is still 389.0 MB. Free memory was 329.8 MB in the beginning and 310.0 MB in the end (delta: 19.8 MB). Peak memory consumption was 19.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 179575.19 ms. Allocated memory was 389.0 MB in the beginning and 2.1 GB in the end (delta: 1.7 GB). Free memory was 310.0 MB in the beginning and 1.6 GB in the end (delta: -1.2 GB). Peak memory consumption was 427.0 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 544). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 544). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 545). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 564). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 565). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 564). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - TimeoutResultAtElement [Line: 548]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 548). Cancelled while BasicCegarLoop was analyzing trace of length 77 with TraceHistMax 15, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 29 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 50 locations, 11 error locations. TIMEOUT Result, 179.5s OverallTime, 56 OverallIterations, 15 TraceHistogramMax, 69.4s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1578 SDtfs, 3907 SDslu, 15019 SDs, 0 SdLazy, 20948 SolverSat, 1838 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 10.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 2123 GetRequests, 65 SyntacticMatches, 6 SemanticMatches, 2052 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 30341 ImplicationChecksByTransitivity, 129.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=172occurred in iteration=23, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 66/3719 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 55 MinimizatonAttempts, 738 StatesRemovedByMinimization, 47 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.5s SatisfiabilityAnalysisTime, 85.6s InterpolantComputationTime, 2299 NumberOfCodeBlocks, 2299 NumberOfCodeBlocksAsserted, 55 NumberOfCheckSat, 2244 ConstructedInterpolants, 0 QuantifiedInterpolants, 5124197 SizeOfPredicates, 0 NumberOfNonLiveVariables, 0 ConjunctsInSsa, 0 ConjunctsInUnsatCore, 55 InterpolantComputations, 16 PerfectInterpolantSequences, 66/3719 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_15-03-40-593.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/openbsd_cstrcat-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_Array.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_15-03-40-593.csv Completed graceful shutdown