java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 19:03:52,267 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 19:03:52,269 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 19:03:52,280 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 19:03:52,280 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 19:03:52,281 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 19:03:52,281 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 19:03:52,282 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 19:03:52,284 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 19:03:52,284 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 19:03:52,285 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 19:03:52,285 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 19:03:52,286 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 19:03:52,287 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 19:03:52,288 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 19:03:52,290 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 19:03:52,291 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 19:03:52,293 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 19:03:52,294 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 19:03:52,295 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 19:03:52,296 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 19:03:52,297 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 19:03:52,297 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 19:03:52,298 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 19:03:52,298 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 19:03:52,299 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 19:03:52,300 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 19:03:52,300 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 19:03:52,300 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 19:03:52,300 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 19:03:52,301 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 19:03:52,301 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-02-04 19:03:52,311 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 19:03:52,311 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 19:03:52,312 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 19:03:52,312 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 19:03:52,312 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 19:03:52,312 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 19:03:52,313 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 19:03:52,314 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 19:03:52,314 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 19:03:52,314 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 19:03:52,314 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 19:03:52,314 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 19:03:52,314 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 19:03:52,315 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 19:03:52,315 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 19:03:52,315 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 19:03:52,315 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 19:03:52,315 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL [2018-02-04 19:03:52,344 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 19:03:52,353 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 19:03:52,357 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 19:03:52,358 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 19:03:52,358 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 19:03:52,359 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test15_false-valid-memtrack.i [2018-02-04 19:03:52,572 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 19:03:52,573 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 19:03:52,574 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 19:03:52,574 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 19:03:52,580 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 19:03:52,581 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,583 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@f13972f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52, skipping insertion in model container [2018-02-04 19:03:52,583 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,593 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 19:03:52,629 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 19:03:52,715 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 19:03:52,732 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 19:03:52,740 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52 WrapperNode [2018-02-04 19:03:52,741 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 19:03:52,741 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 19:03:52,742 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 19:03:52,742 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 19:03:52,750 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,751 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,758 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,758 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,764 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,766 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,768 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... [2018-02-04 19:03:52,771 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 19:03:52,771 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 19:03:52,771 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 19:03:52,772 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 19:03:52,772 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 19:03:52,807 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 19:03:52,807 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 19:03:52,807 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_nonpositive [2018-02-04 19:03:52,807 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_zalloc [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_get_drvdata [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_dev_set_drvdata [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_get_drvdata [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_hid_set_drvdata [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_arvo_device_struct [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_init_specials_unsafe [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure lvd_arvo_remove_specials [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_probe_unsafe [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_arvo_remove [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 19:03:52,808 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 19:03:52,808 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 19:03:52,808 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.meminit [2018-02-04 19:03:52,809 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.meminit [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_nonpositive [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_zalloc [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_get_drvdata [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_dev_set_drvdata [2018-02-04 19:03:52,809 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_get_drvdata [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_hid_set_drvdata [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_arvo_device_struct [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_init_specials_unsafe [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure lvd_arvo_remove_specials [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_probe_unsafe [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_arvo_remove [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 19:03:52,810 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 19:03:53,155 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 19:03:53,156 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 07:03:53 BoogieIcfgContainer [2018-02-04 19:03:53,156 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 19:03:53,156 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 19:03:53,156 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 19:03:53,159 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 19:03:53,159 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 07:03:52" (1/3) ... [2018-02-04 19:03:53,159 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@64fa4bb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 07:03:53, skipping insertion in model container [2018-02-04 19:03:53,160 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 07:03:52" (2/3) ... [2018-02-04 19:03:53,160 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@64fa4bb3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 07:03:53, skipping insertion in model container [2018-02-04 19:03:53,160 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 07:03:53" (3/3) ... [2018-02-04 19:03:53,161 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test15_false-valid-memtrack.i [2018-02-04 19:03:53,168 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 19:03:53,176 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 45 error locations. [2018-02-04 19:03:53,200 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 19:03:53,200 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 19:03:53,200 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 19:03:53,201 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 19:03:53,201 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 19:03:53,201 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 19:03:53,201 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 19:03:53,201 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 19:03:53,201 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 19:03:53,213 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states. [2018-02-04 19:03:53,221 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-02-04 19:03:53,221 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:53,221 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:53,222 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:53,224 INFO L82 PathProgramCache]: Analyzing trace with hash 462743197, now seen corresponding path program 1 times [2018-02-04 19:03:53,225 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:53,226 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:53,269 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:53,269 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:53,269 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:53,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:53,325 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:53,497 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 19:03:53,499 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:03:53,499 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:03:53,501 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 19:03:53,510 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 19:03:53,511 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 19:03:53,512 INFO L87 Difference]: Start difference. First operand 165 states. Second operand 6 states. [2018-02-04 19:03:53,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:53,582 INFO L93 Difference]: Finished difference Result 165 states and 177 transitions. [2018-02-04 19:03:53,582 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 19:03:53,583 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 22 [2018-02-04 19:03:53,584 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:53,593 INFO L225 Difference]: With dead ends: 165 [2018-02-04 19:03:53,593 INFO L226 Difference]: Without dead ends: 162 [2018-02-04 19:03:53,594 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:03:53,606 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-04 19:03:53,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-04 19:03:53,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-04 19:03:53,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 174 transitions. [2018-02-04 19:03:53,633 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 174 transitions. Word has length 22 [2018-02-04 19:03:53,635 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:53,635 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 174 transitions. [2018-02-04 19:03:53,635 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 19:03:53,635 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 174 transitions. [2018-02-04 19:03:53,637 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-02-04 19:03:53,637 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:53,637 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:53,637 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:53,637 INFO L82 PathProgramCache]: Analyzing trace with hash -844495449, now seen corresponding path program 1 times [2018-02-04 19:03:53,637 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:53,637 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:53,639 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:53,639 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:53,639 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:53,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:53,662 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:53,715 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 19:03:53,715 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:03:53,715 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:03:53,716 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 19:03:53,716 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 19:03:53,717 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 19:03:53,717 INFO L87 Difference]: Start difference. First operand 162 states and 174 transitions. Second operand 6 states. [2018-02-04 19:03:53,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:53,764 INFO L93 Difference]: Finished difference Result 162 states and 173 transitions. [2018-02-04 19:03:53,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 19:03:53,764 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 33 [2018-02-04 19:03:53,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:53,765 INFO L225 Difference]: With dead ends: 162 [2018-02-04 19:03:53,766 INFO L226 Difference]: Without dead ends: 162 [2018-02-04 19:03:53,766 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:03:53,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-02-04 19:03:53,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-02-04 19:03:53,771 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-02-04 19:03:53,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 173 transitions. [2018-02-04 19:03:53,772 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 173 transitions. Word has length 33 [2018-02-04 19:03:53,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:53,773 INFO L432 AbstractCegarLoop]: Abstraction has 162 states and 173 transitions. [2018-02-04 19:03:53,773 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 19:03:53,773 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 173 transitions. [2018-02-04 19:03:53,773 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-02-04 19:03:53,773 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:53,773 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:53,773 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:53,774 INFO L82 PathProgramCache]: Analyzing trace with hash 902320110, now seen corresponding path program 1 times [2018-02-04 19:03:53,774 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:53,774 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:53,775 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:53,775 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:53,775 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:53,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:53,800 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:53,809 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:03:53,810 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:53,810 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:53,811 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:53,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:53,855 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:53,904 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 20 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 19:03:53,904 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:03:53,904 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:03:53,905 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 19:03:53,905 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 19:03:53,905 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 19:03:53,905 INFO L87 Difference]: Start difference. First operand 162 states and 173 transitions. Second operand 6 states. [2018-02-04 19:03:53,995 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:53,995 INFO L93 Difference]: Finished difference Result 168 states and 179 transitions. [2018-02-04 19:03:53,995 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 19:03:53,995 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 44 [2018-02-04 19:03:53,996 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:53,997 INFO L225 Difference]: With dead ends: 168 [2018-02-04 19:03:53,997 INFO L226 Difference]: Without dead ends: 163 [2018-02-04 19:03:53,997 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 45 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=39, Unknown=0, NotChecked=0, Total=56 [2018-02-04 19:03:53,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-02-04 19:03:54,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 163. [2018-02-04 19:03:54,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 163 states. [2018-02-04 19:03:54,006 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 163 states to 163 states and 174 transitions. [2018-02-04 19:03:54,006 INFO L78 Accepts]: Start accepts. Automaton has 163 states and 174 transitions. Word has length 44 [2018-02-04 19:03:54,006 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:54,006 INFO L432 AbstractCegarLoop]: Abstraction has 163 states and 174 transitions. [2018-02-04 19:03:54,006 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 19:03:54,006 INFO L276 IsEmpty]: Start isEmpty. Operand 163 states and 174 transitions. [2018-02-04 19:03:54,007 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-02-04 19:03:54,007 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:54,008 INFO L351 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:54,008 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:54,008 INFO L82 PathProgramCache]: Analyzing trace with hash -506792822, now seen corresponding path program 1 times [2018-02-04 19:03:54,008 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:54,008 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:54,009 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:54,009 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:54,010 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:54,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:54,031 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:54,036 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:03:54,036 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:54,036 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:54,037 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:54,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:54,073 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:54,120 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 26 proven. 1 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 19:03:54,121 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:03:54,121 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-02-04 19:03:54,121 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 19:03:54,121 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 19:03:54,122 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:03:54,122 INFO L87 Difference]: Start difference. First operand 163 states and 174 transitions. Second operand 7 states. [2018-02-04 19:03:54,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:54,201 INFO L93 Difference]: Finished difference Result 169 states and 180 transitions. [2018-02-04 19:03:54,202 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 19:03:54,202 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 47 [2018-02-04 19:03:54,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:54,203 INFO L225 Difference]: With dead ends: 169 [2018-02-04 19:03:54,203 INFO L226 Difference]: Without dead ends: 164 [2018-02-04 19:03:54,204 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 41 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-04 19:03:54,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 164 states. [2018-02-04 19:03:54,210 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 164 to 164. [2018-02-04 19:03:54,211 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 164 states. [2018-02-04 19:03:54,212 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164 states to 164 states and 175 transitions. [2018-02-04 19:03:54,212 INFO L78 Accepts]: Start accepts. Automaton has 164 states and 175 transitions. Word has length 47 [2018-02-04 19:03:54,212 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:54,212 INFO L432 AbstractCegarLoop]: Abstraction has 164 states and 175 transitions. [2018-02-04 19:03:54,213 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 19:03:54,213 INFO L276 IsEmpty]: Start isEmpty. Operand 164 states and 175 transitions. [2018-02-04 19:03:54,213 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-02-04 19:03:54,214 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:54,214 INFO L351 BasicCegarLoop]: trace histogram [6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:54,214 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:54,214 INFO L82 PathProgramCache]: Analyzing trace with hash -1284083602, now seen corresponding path program 2 times [2018-02-04 19:03:54,214 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:54,214 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:54,215 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:54,215 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:54,215 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:54,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:54,235 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:54,239 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:03:54,240 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:54,240 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:54,241 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:03:54,278 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:03:54,278 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:03:54,283 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:54,387 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 32 proven. 3 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 19:03:54,387 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:03:54,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8] total 8 [2018-02-04 19:03:54,387 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 19:03:54,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 19:03:54,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 19:03:54,388 INFO L87 Difference]: Start difference. First operand 164 states and 175 transitions. Second operand 8 states. [2018-02-04 19:03:54,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:54,509 INFO L93 Difference]: Finished difference Result 170 states and 181 transitions. [2018-02-04 19:03:54,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 19:03:54,510 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 50 [2018-02-04 19:03:54,510 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:54,511 INFO L225 Difference]: With dead ends: 170 [2018-02-04 19:03:54,511 INFO L226 Difference]: Without dead ends: 165 [2018-02-04 19:03:54,511 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 51 GetRequests, 43 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:03:54,511 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-02-04 19:03:54,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-02-04 19:03:54,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-02-04 19:03:54,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 176 transitions. [2018-02-04 19:03:54,517 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 176 transitions. Word has length 50 [2018-02-04 19:03:54,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:54,517 INFO L432 AbstractCegarLoop]: Abstraction has 165 states and 176 transitions. [2018-02-04 19:03:54,517 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 19:03:54,518 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 176 transitions. [2018-02-04 19:03:54,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-04 19:03:54,518 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:54,519 INFO L351 BasicCegarLoop]: trace histogram [9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:54,519 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:54,519 INFO L82 PathProgramCache]: Analyzing trace with hash -202175990, now seen corresponding path program 3 times [2018-02-04 19:03:54,519 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:54,519 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:54,520 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:54,520 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:03:54,520 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:54,538 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:54,539 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:54,543 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:03:54,544 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:54,544 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:54,545 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 19:03:54,572 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-02-04 19:03:54,572 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:03:54,576 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:54,592 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:03:54,593 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:54,595 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:03:54,595 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 19:03:54,677 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:54,680 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-02-04 19:03:54,680 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:54,684 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:03:54,684 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-02-04 19:03:54,708 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:54,715 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:54,716 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 19:03:54,717 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:54,721 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:03:54,722 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-02-04 19:03:54,737 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 50 proven. 4 refuted. 0 times theorem prover too weak. 39 trivial. 0 not checked. [2018-02-04 19:03:54,738 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:03:54,738 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-02-04 19:03:54,738 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 19:03:54,738 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 19:03:54,739 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=24, Invalid=66, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:03:54,739 INFO L87 Difference]: Start difference. First operand 165 states and 176 transitions. Second operand 10 states. [2018-02-04 19:03:55,196 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:55,196 INFO L93 Difference]: Finished difference Result 208 states and 226 transitions. [2018-02-04 19:03:55,196 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 19:03:55,196 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 53 [2018-02-04 19:03:55,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:55,198 INFO L225 Difference]: With dead ends: 208 [2018-02-04 19:03:55,198 INFO L226 Difference]: Without dead ends: 208 [2018-02-04 19:03:55,199 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 42 SyntacticMatches, 3 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:03:55,199 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-02-04 19:03:55,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 178. [2018-02-04 19:03:55,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 178 states. [2018-02-04 19:03:55,206 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 178 states to 178 states and 195 transitions. [2018-02-04 19:03:55,206 INFO L78 Accepts]: Start accepts. Automaton has 178 states and 195 transitions. Word has length 53 [2018-02-04 19:03:55,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:55,207 INFO L432 AbstractCegarLoop]: Abstraction has 178 states and 195 transitions. [2018-02-04 19:03:55,207 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 19:03:55,207 INFO L276 IsEmpty]: Start isEmpty. Operand 178 states and 195 transitions. [2018-02-04 19:03:55,208 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-02-04 19:03:55,208 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:55,208 INFO L351 BasicCegarLoop]: trace histogram [9, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:55,208 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:55,209 INFO L82 PathProgramCache]: Analyzing trace with hash -202175989, now seen corresponding path program 1 times [2018-02-04 19:03:55,209 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:55,209 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:55,210 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:55,210 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:03:55,211 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:55,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:55,228 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:55,386 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 0 proven. 52 refuted. 0 times theorem prover too weak. 41 trivial. 0 not checked. [2018-02-04 19:03:55,386 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:55,386 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:55,387 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:55,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:55,421 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:55,549 INFO L134 CoverageAnalysis]: Checked inductivity of 93 backedges. 50 proven. 6 refuted. 0 times theorem prover too weak. 37 trivial. 0 not checked. [2018-02-04 19:03:55,549 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:03:55,549 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9] total 17 [2018-02-04 19:03:55,550 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 19:03:55,550 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 19:03:55,551 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=237, Unknown=0, NotChecked=0, Total=272 [2018-02-04 19:03:55,551 INFO L87 Difference]: Start difference. First operand 178 states and 195 transitions. Second operand 17 states. [2018-02-04 19:03:55,767 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:55,767 INFO L93 Difference]: Finished difference Result 184 states and 201 transitions. [2018-02-04 19:03:55,767 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 19:03:55,767 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 53 [2018-02-04 19:03:55,767 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:55,768 INFO L225 Difference]: With dead ends: 184 [2018-02-04 19:03:55,768 INFO L226 Difference]: Without dead ends: 179 [2018-02-04 19:03:55,768 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 67 GetRequests, 47 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=61, Invalid=401, Unknown=0, NotChecked=0, Total=462 [2018-02-04 19:03:55,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-02-04 19:03:55,771 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2018-02-04 19:03:55,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-02-04 19:03:55,772 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 196 transitions. [2018-02-04 19:03:55,773 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 196 transitions. Word has length 53 [2018-02-04 19:03:55,773 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:55,773 INFO L432 AbstractCegarLoop]: Abstraction has 179 states and 196 transitions. [2018-02-04 19:03:55,773 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 19:03:55,773 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 196 transitions. [2018-02-04 19:03:55,774 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 19:03:55,774 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:55,774 INFO L351 BasicCegarLoop]: trace histogram [12, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:55,774 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:55,774 INFO L82 PathProgramCache]: Analyzing trace with hash -734121745, now seen corresponding path program 2 times [2018-02-04 19:03:55,774 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:55,774 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:55,775 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:55,776 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:03:55,776 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:55,793 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:55,794 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:55,930 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-04 19:03:55,930 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:55,930 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:55,931 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:03:55,951 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:03:55,951 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:03:55,954 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:56,126 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 64 proven. 10 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-02-04 19:03:56,126 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:03:56,126 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10] total 18 [2018-02-04 19:03:56,126 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 19:03:56,127 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 19:03:56,127 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=269, Unknown=0, NotChecked=0, Total=306 [2018-02-04 19:03:56,127 INFO L87 Difference]: Start difference. First operand 179 states and 196 transitions. Second operand 18 states. [2018-02-04 19:03:56,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:03:56,411 INFO L93 Difference]: Finished difference Result 185 states and 202 transitions. [2018-02-04 19:03:56,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 19:03:56,412 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-02-04 19:03:56,412 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:03:56,412 INFO L225 Difference]: With dead ends: 185 [2018-02-04 19:03:56,412 INFO L226 Difference]: Without dead ends: 180 [2018-02-04 19:03:56,413 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 49 SyntacticMatches, 1 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=67, Invalid=485, Unknown=0, NotChecked=0, Total=552 [2018-02-04 19:03:56,413 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-02-04 19:03:56,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-02-04 19:03:56,416 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-02-04 19:03:56,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 197 transitions. [2018-02-04 19:03:56,416 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 197 transitions. Word has length 56 [2018-02-04 19:03:56,417 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:03:56,417 INFO L432 AbstractCegarLoop]: Abstraction has 180 states and 197 transitions. [2018-02-04 19:03:56,417 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 19:03:56,417 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 197 transitions. [2018-02-04 19:03:56,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-02-04 19:03:56,418 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:03:56,418 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:03:56,418 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:03:56,418 INFO L82 PathProgramCache]: Analyzing trace with hash 1514307467, now seen corresponding path program 3 times [2018-02-04 19:03:56,418 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:03:56,418 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:03:56,419 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:56,419 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:03:56,419 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:03:56,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:03:56,436 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:03:56,455 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:03:56,455 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:03:56,455 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:03:56,456 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 19:03:56,481 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-02-04 19:03:56,481 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:03:56,487 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:03:56,495 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 28 [2018-02-04 19:03:56,496 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,497 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 19:03:56,498 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,516 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 19:03:56,516 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,550 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 27 [2018-02-04 19:03:56,551 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,566 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:03:56,566 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:56, output treesize:52 [2018-02-04 19:03:56,829 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 18 [2018-02-04 19:03:56,830 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,844 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 13 [2018-02-04 19:03:56,844 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2018-02-04 19:03:56,858 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,870 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 15 [2018-02-04 19:03:56,871 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:56,881 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:03:56,881 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:41, output treesize:29 [2018-02-04 19:03:58,900 WARN L1033 $PredicateComparison]: unable to prove that (or (exists ((v_prenex_12 Int) (v_prenex_11 Int)) (let ((.cse0 (mod v_prenex_11 4294967296))) (and (= .cse0 (+ (select |c_#length| v_prenex_12) 4294967296)) (< 2147483647 .cse0)))) (exists ((ldv_zalloc_~size Int) (|ldv_zalloc_#t~malloc1.base| Int)) (let ((.cse1 (mod ldv_zalloc_~size 4294967296))) (and (<= .cse1 2147483647) (= (select |c_#length| |ldv_zalloc_#t~malloc1.base|) .cse1))))) is different from true [2018-02-04 19:03:58,984 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:58,985 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:58,986 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 28 [2018-02-04 19:03:58,986 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:59,009 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:59,010 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:59,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 26 [2018-02-04 19:03:59,011 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:59,025 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 19:03:59,026 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:59,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:03:59,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 37 [2018-02-04 19:03:59,058 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:03:59,084 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:03:59,084 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:67, output treesize:49 [2018-02-04 19:03:59,135 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 90 proven. 10 refuted. 0 times theorem prover too weak. 41 trivial. 39 not checked. [2018-02-04 19:03:59,136 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:03:59,136 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-02-04 19:03:59,136 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 19:03:59,136 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 19:03:59,136 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=149, Unknown=2, NotChecked=24, Total=210 [2018-02-04 19:03:59,136 INFO L87 Difference]: Start difference. First operand 180 states and 197 transitions. Second operand 15 states. [2018-02-04 19:04:00,584 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:00,584 INFO L93 Difference]: Finished difference Result 223 states and 243 transitions. [2018-02-04 19:04:00,585 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 19:04:00,585 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 59 [2018-02-04 19:04:00,585 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:00,586 INFO L225 Difference]: With dead ends: 223 [2018-02-04 19:04:00,586 INFO L226 Difference]: Without dead ends: 223 [2018-02-04 19:04:00,586 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 1 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=112, Invalid=539, Unknown=3, NotChecked=48, Total=702 [2018-02-04 19:04:00,587 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 223 states. [2018-02-04 19:04:00,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 223 to 187. [2018-02-04 19:04:00,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-02-04 19:04:00,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 209 transitions. [2018-02-04 19:04:00,592 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 209 transitions. Word has length 59 [2018-02-04 19:04:00,593 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:00,593 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 209 transitions. [2018-02-04 19:04:00,593 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 19:04:00,593 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 209 transitions. [2018-02-04 19:04:00,594 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-02-04 19:04:00,594 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:00,594 INFO L351 BasicCegarLoop]: trace histogram [15, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:00,594 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:00,594 INFO L82 PathProgramCache]: Analyzing trace with hash 1708156291, now seen corresponding path program 1 times [2018-02-04 19:04:00,594 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:00,594 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:00,595 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:00,595 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:04:00,596 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:00,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:00,611 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:00,668 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 172 trivial. 0 not checked. [2018-02-04 19:04:00,668 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:00,668 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:00,669 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:00,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:00,695 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:00,796 INFO L134 CoverageAnalysis]: Checked inductivity of 180 backedges. 90 proven. 15 refuted. 0 times theorem prover too weak. 75 trivial. 0 not checked. [2018-02-04 19:04:00,796 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:04:00,796 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 11] total 15 [2018-02-04 19:04:00,796 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 19:04:00,797 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 19:04:00,797 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=183, Unknown=0, NotChecked=0, Total=210 [2018-02-04 19:04:00,797 INFO L87 Difference]: Start difference. First operand 187 states and 209 transitions. Second operand 15 states. [2018-02-04 19:04:00,967 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:00,967 INFO L93 Difference]: Finished difference Result 192 states and 214 transitions. [2018-02-04 19:04:00,968 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 19:04:00,968 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 64 [2018-02-04 19:04:00,968 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:00,969 INFO L225 Difference]: With dead ends: 192 [2018-02-04 19:04:00,969 INFO L226 Difference]: Without dead ends: 187 [2018-02-04 19:04:00,969 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=56, Invalid=324, Unknown=0, NotChecked=0, Total=380 [2018-02-04 19:04:00,969 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-02-04 19:04:00,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2018-02-04 19:04:00,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-02-04 19:04:00,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 209 transitions. [2018-02-04 19:04:00,973 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 209 transitions. Word has length 64 [2018-02-04 19:04:00,973 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:00,973 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 209 transitions. [2018-02-04 19:04:00,973 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 19:04:00,973 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 209 transitions. [2018-02-04 19:04:00,974 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-02-04 19:04:00,974 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:00,974 INFO L351 BasicCegarLoop]: trace histogram [18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:00,974 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:00,975 INFO L82 PathProgramCache]: Analyzing trace with hash 426697248, now seen corresponding path program 1 times [2018-02-04 19:04:00,975 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:00,975 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:00,976 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:00,976 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:00,976 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:00,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:00,990 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:01,041 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 229 trivial. 0 not checked. [2018-02-04 19:04:01,041 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:04:01,042 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 19:04:01,042 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 19:04:01,042 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 19:04:01,042 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:04:01,043 INFO L87 Difference]: Start difference. First operand 187 states and 209 transitions. Second operand 7 states. [2018-02-04 19:04:01,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:01,113 INFO L93 Difference]: Finished difference Result 186 states and 207 transitions. [2018-02-04 19:04:01,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 19:04:01,115 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 67 [2018-02-04 19:04:01,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:01,116 INFO L225 Difference]: With dead ends: 186 [2018-02-04 19:04:01,116 INFO L226 Difference]: Without dead ends: 186 [2018-02-04 19:04:01,116 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:04:01,116 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-02-04 19:04:01,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2018-02-04 19:04:01,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-02-04 19:04:01,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 207 transitions. [2018-02-04 19:04:01,121 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 207 transitions. Word has length 67 [2018-02-04 19:04:01,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:01,121 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 207 transitions. [2018-02-04 19:04:01,121 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 19:04:01,121 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 207 transitions. [2018-02-04 19:04:01,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-02-04 19:04:01,122 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:01,122 INFO L351 BasicCegarLoop]: trace histogram [18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:01,122 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:01,123 INFO L82 PathProgramCache]: Analyzing trace with hash 342744625, now seen corresponding path program 1 times [2018-02-04 19:04:01,123 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:01,123 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:01,124 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:01,124 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:01,124 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:01,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:01,138 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:01,293 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 229 trivial. 0 not checked. [2018-02-04 19:04:01,293 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:04:01,293 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:04:01,293 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 19:04:01,294 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 19:04:01,294 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:04:01,294 INFO L87 Difference]: Start difference. First operand 186 states and 207 transitions. Second operand 7 states. [2018-02-04 19:04:01,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:01,425 INFO L93 Difference]: Finished difference Result 185 states and 206 transitions. [2018-02-04 19:04:01,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 19:04:01,425 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 68 [2018-02-04 19:04:01,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:01,426 INFO L225 Difference]: With dead ends: 185 [2018-02-04 19:04:01,426 INFO L226 Difference]: Without dead ends: 185 [2018-02-04 19:04:01,426 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=23, Invalid=67, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:04:01,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 185 states. [2018-02-04 19:04:01,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 185 to 185. [2018-02-04 19:04:01,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 185 states. [2018-02-04 19:04:01,430 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 185 states to 185 states and 206 transitions. [2018-02-04 19:04:01,431 INFO L78 Accepts]: Start accepts. Automaton has 185 states and 206 transitions. Word has length 68 [2018-02-04 19:04:01,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:01,431 INFO L432 AbstractCegarLoop]: Abstraction has 185 states and 206 transitions. [2018-02-04 19:04:01,431 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 19:04:01,431 INFO L276 IsEmpty]: Start isEmpty. Operand 185 states and 206 transitions. [2018-02-04 19:04:01,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-02-04 19:04:01,432 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:01,432 INFO L351 BasicCegarLoop]: trace histogram [18, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:01,432 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:01,432 INFO L82 PathProgramCache]: Analyzing trace with hash 342744626, now seen corresponding path program 1 times [2018-02-04 19:04:01,432 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:01,433 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:01,433 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:01,434 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:01,434 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:01,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:01,460 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:01,621 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 0 proven. 133 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-02-04 19:04:01,621 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:01,621 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:01,622 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:01,644 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:01,649 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:01,912 INFO L134 CoverageAnalysis]: Checked inductivity of 237 backedges. 112 proven. 21 refuted. 0 times theorem prover too weak. 104 trivial. 0 not checked. [2018-02-04 19:04:01,913 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:04:01,913 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12] total 23 [2018-02-04 19:04:01,913 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 19:04:01,913 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 19:04:01,914 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=47, Invalid=459, Unknown=0, NotChecked=0, Total=506 [2018-02-04 19:04:01,914 INFO L87 Difference]: Start difference. First operand 185 states and 206 transitions. Second operand 23 states. [2018-02-04 19:04:02,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:02,294 INFO L93 Difference]: Finished difference Result 191 states and 212 transitions. [2018-02-04 19:04:02,295 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 19:04:02,295 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 68 [2018-02-04 19:04:02,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:02,295 INFO L225 Difference]: With dead ends: 191 [2018-02-04 19:04:02,296 INFO L226 Difference]: Without dead ends: 186 [2018-02-04 19:04:02,296 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 88 GetRequests, 59 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=85, Invalid=845, Unknown=0, NotChecked=0, Total=930 [2018-02-04 19:04:02,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-02-04 19:04:02,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2018-02-04 19:04:02,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-02-04 19:04:02,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 207 transitions. [2018-02-04 19:04:02,305 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 207 transitions. Word has length 68 [2018-02-04 19:04:02,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:02,305 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 207 transitions. [2018-02-04 19:04:02,305 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 19:04:02,305 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 207 transitions. [2018-02-04 19:04:02,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-02-04 19:04:02,307 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:02,308 INFO L351 BasicCegarLoop]: trace histogram [21, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:02,308 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:02,308 INFO L82 PathProgramCache]: Analyzing trace with hash 1946516686, now seen corresponding path program 2 times [2018-02-04 19:04:02,308 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:02,308 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:02,309 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:02,309 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:02,309 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:02,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:02,379 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:02,598 INFO L134 CoverageAnalysis]: Checked inductivity of 303 backedges. 0 proven. 170 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-02-04 19:04:02,599 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:02,599 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:02,599 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:04:02,623 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:04:02,623 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:04:02,627 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:02,838 INFO L134 CoverageAnalysis]: Checked inductivity of 303 backedges. 142 proven. 28 refuted. 0 times theorem prover too weak. 133 trivial. 0 not checked. [2018-02-04 19:04:02,839 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:04:02,839 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 24 [2018-02-04 19:04:02,839 INFO L409 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-02-04 19:04:02,839 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-02-04 19:04:02,840 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=49, Invalid=503, Unknown=0, NotChecked=0, Total=552 [2018-02-04 19:04:02,840 INFO L87 Difference]: Start difference. First operand 186 states and 207 transitions. Second operand 24 states. [2018-02-04 19:04:03,124 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:03,124 INFO L93 Difference]: Finished difference Result 192 states and 213 transitions. [2018-02-04 19:04:03,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 19:04:03,125 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 71 [2018-02-04 19:04:03,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:03,126 INFO L225 Difference]: With dead ends: 192 [2018-02-04 19:04:03,126 INFO L226 Difference]: Without dead ends: 187 [2018-02-04 19:04:03,126 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 61 SyntacticMatches, 1 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 83 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=91, Invalid=965, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 19:04:03,126 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-02-04 19:04:03,129 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2018-02-04 19:04:03,130 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-02-04 19:04:03,131 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 208 transitions. [2018-02-04 19:04:03,131 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 208 transitions. Word has length 71 [2018-02-04 19:04:03,131 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:03,131 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 208 transitions. [2018-02-04 19:04:03,131 INFO L433 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-02-04 19:04:03,131 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 208 transitions. [2018-02-04 19:04:03,132 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-02-04 19:04:03,132 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:03,132 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:03,132 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:03,132 INFO L82 PathProgramCache]: Analyzing trace with hash 395214514, now seen corresponding path program 3 times [2018-02-04 19:04:03,132 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:03,132 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:03,133 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:03,133 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:04:03,133 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:03,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:03,152 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:03,374 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 174 proven. 36 refuted. 0 times theorem prover too weak. 168 trivial. 0 not checked. [2018-02-04 19:04:03,374 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:03,374 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:03,375 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 19:04:03,389 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-02-04 19:04:03,389 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:04:03,392 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:03,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 19:04:03,419 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:03,438 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 19:04:03,438 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:03,449 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:04:03,449 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:44, output treesize:42 [2018-02-04 19:04:09,786 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:04:09,787 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:04:09,787 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,788 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,793 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:04:09,794 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:04:09,794 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,795 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,797 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,798 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:32, output treesize:21 [2018-02-04 19:04:09,822 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-02-04 19:04:09,827 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-02-04 19:04:09,827 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,829 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,833 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-02-04 19:04:09,834 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 3 [2018-02-04 19:04:09,834 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,835 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,837 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:09,837 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:39, output treesize:9 [2018-02-04 19:04:09,873 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 178 proven. 8 refuted. 0 times theorem prover too weak. 192 trivial. 0 not checked. [2018-02-04 19:04:09,873 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:04:09,873 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 11] total 27 [2018-02-04 19:04:09,874 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 19:04:09,874 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 19:04:09,874 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=686, Unknown=3, NotChecked=0, Total=756 [2018-02-04 19:04:09,874 INFO L87 Difference]: Start difference. First operand 187 states and 208 transitions. Second operand 28 states. [2018-02-04 19:04:11,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:11,263 INFO L93 Difference]: Finished difference Result 194 states and 219 transitions. [2018-02-04 19:04:11,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-04 19:04:11,264 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 74 [2018-02-04 19:04:11,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:11,264 INFO L225 Difference]: With dead ends: 194 [2018-02-04 19:04:11,265 INFO L226 Difference]: Without dead ends: 194 [2018-02-04 19:04:11,265 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 237 ImplicationChecksByTransitivity, 7.0s TimeCoverageRelationStatistics Valid=187, Invalid=1880, Unknown=3, NotChecked=0, Total=2070 [2018-02-04 19:04:11,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 194 states. [2018-02-04 19:04:11,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 194 to 186. [2018-02-04 19:04:11,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-02-04 19:04:11,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 207 transitions. [2018-02-04 19:04:11,269 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 207 transitions. Word has length 74 [2018-02-04 19:04:11,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:11,269 INFO L432 AbstractCegarLoop]: Abstraction has 186 states and 207 transitions. [2018-02-04 19:04:11,269 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 19:04:11,269 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 207 transitions. [2018-02-04 19:04:11,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-04 19:04:11,270 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:11,270 INFO L351 BasicCegarLoop]: trace histogram [24, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:11,270 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:11,270 INFO L82 PathProgramCache]: Analyzing trace with hash 1844027634, now seen corresponding path program 1 times [2018-02-04 19:04:11,271 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:11,271 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:11,271 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:11,271 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:04:11,271 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:11,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:11,301 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:11,308 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:04:11,308 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:11,308 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:11,309 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:11,333 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:11,339 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:11,445 INFO L134 CoverageAnalysis]: Checked inductivity of 378 backedges. 180 proven. 36 refuted. 0 times theorem prover too weak. 162 trivial. 0 not checked. [2018-02-04 19:04:11,445 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:04:11,445 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-02-04 19:04:11,445 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 19:04:11,446 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 19:04:11,446 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=157, Unknown=0, NotChecked=0, Total=182 [2018-02-04 19:04:11,446 INFO L87 Difference]: Start difference. First operand 186 states and 207 transitions. Second operand 14 states. [2018-02-04 19:04:11,587 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:11,587 INFO L93 Difference]: Finished difference Result 192 states and 213 transitions. [2018-02-04 19:04:11,587 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 19:04:11,587 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 76 [2018-02-04 19:04:11,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:11,588 INFO L225 Difference]: With dead ends: 192 [2018-02-04 19:04:11,588 INFO L226 Difference]: Without dead ends: 187 [2018-02-04 19:04:11,588 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 63 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=33, Invalid=207, Unknown=0, NotChecked=0, Total=240 [2018-02-04 19:04:11,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-02-04 19:04:11,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2018-02-04 19:04:11,591 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-02-04 19:04:11,591 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 208 transitions. [2018-02-04 19:04:11,591 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 208 transitions. Word has length 76 [2018-02-04 19:04:11,591 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:11,591 INFO L432 AbstractCegarLoop]: Abstraction has 187 states and 208 transitions. [2018-02-04 19:04:11,591 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 19:04:11,592 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 208 transitions. [2018-02-04 19:04:11,592 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-02-04 19:04:11,592 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:11,592 INFO L351 BasicCegarLoop]: trace histogram [27, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:11,592 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:11,592 INFO L82 PathProgramCache]: Analyzing trace with hash 10632590, now seen corresponding path program 2 times [2018-02-04 19:04:11,593 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:11,593 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:11,593 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:11,593 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:11,593 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:11,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:11,609 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:11,613 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:04:11,613 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:11,613 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:11,614 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:04:11,637 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:04:11,637 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:04:11,641 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:11,804 INFO L134 CoverageAnalysis]: Checked inductivity of 462 backedges. 325 proven. 45 refuted. 0 times theorem prover too weak. 92 trivial. 0 not checked. [2018-02-04 19:04:11,805 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:04:11,805 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15] total 15 [2018-02-04 19:04:11,805 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 19:04:11,805 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 19:04:11,805 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=183, Unknown=0, NotChecked=0, Total=210 [2018-02-04 19:04:11,805 INFO L87 Difference]: Start difference. First operand 187 states and 208 transitions. Second operand 15 states. [2018-02-04 19:04:12,155 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:12,155 INFO L93 Difference]: Finished difference Result 210 states and 234 transitions. [2018-02-04 19:04:12,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-02-04 19:04:12,156 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 79 [2018-02-04 19:04:12,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:12,156 INFO L225 Difference]: With dead ends: 210 [2018-02-04 19:04:12,156 INFO L226 Difference]: Without dead ends: 210 [2018-02-04 19:04:12,157 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 89 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=143, Invalid=507, Unknown=0, NotChecked=0, Total=650 [2018-02-04 19:04:12,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 210 states. [2018-02-04 19:04:12,159 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 210 to 210. [2018-02-04 19:04:12,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-02-04 19:04:12,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 234 transitions. [2018-02-04 19:04:12,161 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 234 transitions. Word has length 79 [2018-02-04 19:04:12,161 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:12,161 INFO L432 AbstractCegarLoop]: Abstraction has 210 states and 234 transitions. [2018-02-04 19:04:12,161 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 19:04:12,161 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 234 transitions. [2018-02-04 19:04:12,162 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-04 19:04:12,162 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:12,162 INFO L351 BasicCegarLoop]: trace histogram [29, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:12,162 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:12,162 INFO L82 PathProgramCache]: Analyzing trace with hash 826541594, now seen corresponding path program 3 times [2018-02-04 19:04:12,162 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:12,162 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:12,163 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:12,163 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:04:12,163 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:12,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:12,179 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:12,183 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:04:12,183 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:12,183 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:12,184 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 19:04:12,208 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-02-04 19:04:12,208 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:04:12,211 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:12,213 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:04:12,213 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,214 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,214 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 19:04:12,241 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:04:12,242 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,243 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:04:12,243 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:6, output treesize:5 [2018-02-04 19:04:12,274 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 19:04:12,274 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,278 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,278 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-02-04 19:04:12,298 WARN L1033 $PredicateComparison]: unable to prove that (exists ((|ldv_zalloc_#t~malloc1.base| Int)) (= |c_#valid| (store |c_old(#valid)| |ldv_zalloc_#t~malloc1.base| 1))) is different from true [2018-02-04 19:04:12,299 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:04:12,299 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,300 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:04:12,300 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:6, output treesize:5 [2018-02-04 19:04:12,311 WARN L1033 $PredicateComparison]: unable to prove that (and (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_4| Int)) (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_4|))) (exists ((|ldv_zalloc_#t~malloc1.base| Int)) (= |c_#valid| (store |c_old(#valid)| |ldv_zalloc_#t~malloc1.base| 1)))) is different from true [2018-02-04 19:04:12,321 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:04:12,322 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:12,328 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 19:04:12,328 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 3 variables, input treesize:22, output treesize:21 [2018-02-04 19:04:12,354 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 8 proven. 0 refuted. 0 times theorem prover too weak. 507 trivial. 8 not checked. [2018-02-04 19:04:12,355 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:04:12,355 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13] total 13 [2018-02-04 19:04:12,355 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 19:04:12,355 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 19:04:12,356 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=101, Unknown=2, NotChecked=42, Total=182 [2018-02-04 19:04:12,356 INFO L87 Difference]: Start difference. First operand 210 states and 234 transitions. Second operand 14 states. [2018-02-04 19:04:12,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:12,669 INFO L93 Difference]: Finished difference Result 229 states and 255 transitions. [2018-02-04 19:04:12,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 19:04:12,669 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 81 [2018-02-04 19:04:12,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:12,670 INFO L225 Difference]: With dead ends: 229 [2018-02-04 19:04:12,670 INFO L226 Difference]: Without dead ends: 229 [2018-02-04 19:04:12,670 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 85 GetRequests, 62 SyntacticMatches, 9 SemanticMatches, 14 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 62 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=48, Invalid=140, Unknown=2, NotChecked=50, Total=240 [2018-02-04 19:04:12,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-02-04 19:04:12,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 209. [2018-02-04 19:04:12,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2018-02-04 19:04:12,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 233 transitions. [2018-02-04 19:04:12,675 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 233 transitions. Word has length 81 [2018-02-04 19:04:12,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:12,676 INFO L432 AbstractCegarLoop]: Abstraction has 209 states and 233 transitions. [2018-02-04 19:04:12,676 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 19:04:12,676 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 233 transitions. [2018-02-04 19:04:12,676 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 82 [2018-02-04 19:04:12,676 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:12,676 INFO L351 BasicCegarLoop]: trace histogram [29, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:12,677 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:12,677 INFO L82 PathProgramCache]: Analyzing trace with hash 826541595, now seen corresponding path program 1 times [2018-02-04 19:04:12,677 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:12,677 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:12,677 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:12,678 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:04:12,678 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:12,704 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:12,705 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:13,007 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 0 proven. 300 refuted. 0 times theorem prover too weak. 223 trivial. 0 not checked. [2018-02-04 19:04:13,007 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:13,007 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:13,007 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:13,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:13,029 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:13,387 INFO L134 CoverageAnalysis]: Checked inductivity of 523 backedges. 249 proven. 55 refuted. 0 times theorem prover too weak. 219 trivial. 0 not checked. [2018-02-04 19:04:13,387 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:04:13,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16] total 31 [2018-02-04 19:04:13,388 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 19:04:13,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 19:04:13,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=866, Unknown=0, NotChecked=0, Total=930 [2018-02-04 19:04:13,388 INFO L87 Difference]: Start difference. First operand 209 states and 233 transitions. Second operand 31 states. [2018-02-04 19:04:14,356 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:14,356 INFO L93 Difference]: Finished difference Result 223 states and 246 transitions. [2018-02-04 19:04:14,357 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 19:04:14,357 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 81 [2018-02-04 19:04:14,357 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:14,357 INFO L225 Difference]: With dead ends: 223 [2018-02-04 19:04:14,357 INFO L226 Difference]: Without dead ends: 213 [2018-02-04 19:04:14,358 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 68 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 340 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=228, Invalid=2634, Unknown=0, NotChecked=0, Total=2862 [2018-02-04 19:04:14,358 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-02-04 19:04:14,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 207. [2018-02-04 19:04:14,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-02-04 19:04:14,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 228 transitions. [2018-02-04 19:04:14,361 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 228 transitions. Word has length 81 [2018-02-04 19:04:14,361 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:14,361 INFO L432 AbstractCegarLoop]: Abstraction has 207 states and 228 transitions. [2018-02-04 19:04:14,361 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 19:04:14,361 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 228 transitions. [2018-02-04 19:04:14,361 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-04 19:04:14,361 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:14,361 INFO L351 BasicCegarLoop]: trace histogram [31, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:14,361 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:14,362 INFO L82 PathProgramCache]: Analyzing trace with hash 132830479, now seen corresponding path program 2 times [2018-02-04 19:04:14,362 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:14,362 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:14,362 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:14,362 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:04:14,362 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:14,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:14,379 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:14,586 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 0 proven. 344 refuted. 0 times theorem prover too weak. 244 trivial. 0 not checked. [2018-02-04 19:04:14,586 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:14,586 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:14,587 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:04:14,619 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:04:14,619 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:04:14,625 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:14,943 INFO L134 CoverageAnalysis]: Checked inductivity of 588 backedges. 409 proven. 66 refuted. 0 times theorem prover too weak. 113 trivial. 0 not checked. [2018-02-04 19:04:14,943 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:04:14,943 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17] total 33 [2018-02-04 19:04:14,944 INFO L409 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-02-04 19:04:14,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-02-04 19:04:14,944 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=989, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 19:04:14,944 INFO L87 Difference]: Start difference. First operand 207 states and 228 transitions. Second operand 33 states. [2018-02-04 19:04:16,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:04:16,033 INFO L93 Difference]: Finished difference Result 222 states and 246 transitions. [2018-02-04 19:04:16,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-04 19:04:16,033 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 83 [2018-02-04 19:04:16,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:04:16,034 INFO L225 Difference]: With dead ends: 222 [2018-02-04 19:04:16,034 INFO L226 Difference]: Without dead ends: 217 [2018-02-04 19:04:16,035 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 69 SyntacticMatches, 0 SemanticMatches, 57 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 396 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=255, Invalid=3167, Unknown=0, NotChecked=0, Total=3422 [2018-02-04 19:04:16,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-02-04 19:04:16,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 208. [2018-02-04 19:04:16,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 208 states. [2018-02-04 19:04:16,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 208 states to 208 states and 229 transitions. [2018-02-04 19:04:16,038 INFO L78 Accepts]: Start accepts. Automaton has 208 states and 229 transitions. Word has length 83 [2018-02-04 19:04:16,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:04:16,039 INFO L432 AbstractCegarLoop]: Abstraction has 208 states and 229 transitions. [2018-02-04 19:04:16,039 INFO L433 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-02-04 19:04:16,039 INFO L276 IsEmpty]: Start isEmpty. Operand 208 states and 229 transitions. [2018-02-04 19:04:16,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 86 [2018-02-04 19:04:16,039 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:04:16,039 INFO L351 BasicCegarLoop]: trace histogram [33, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:04:16,040 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:04:16,040 INFO L82 PathProgramCache]: Analyzing trace with hash 1935927963, now seen corresponding path program 3 times [2018-02-04 19:04:16,040 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:04:16,040 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:04:16,041 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:16,041 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:04:16,041 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:04:16,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:04:16,068 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:04:16,075 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:04:16,076 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:04:16,076 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:04:16,076 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 19:04:16,112 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-02-04 19:04:16,112 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:04:16,116 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:04:16,122 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 25 [2018-02-04 19:04:16,122 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,124 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 22 [2018-02-04 19:04:16,124 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,141 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 19:04:16,141 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,158 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 19:04:16,158 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,173 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:04:16,173 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:50, output treesize:46 [2018-02-04 19:04:16,299 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 26 [2018-02-04 19:04:16,300 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,312 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,313 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 20 [2018-02-04 19:04:16,313 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,324 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 19:04:16,325 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,336 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,336 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 18 [2018-02-04 19:04:16,337 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,353 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:04:16,353 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:53, output treesize:39 [2018-02-04 19:04:16,424 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,425 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 41 [2018-02-04 19:04:16,426 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,452 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,453 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,453 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 53 [2018-02-04 19:04:16,454 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,478 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,478 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,479 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 43 [2018-02-04 19:04:16,479 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,497 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,498 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,498 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 41 [2018-02-04 19:04:16,498 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,514 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:04:16,514 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:79, output treesize:69 [2018-02-04 19:04:16,572 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 20 [2018-02-04 19:04:16,593 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,604 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 14 [2018-02-04 19:04:16,604 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,611 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 15 [2018-02-04 19:04:16,611 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,617 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 14 treesize of output 13 [2018-02-04 19:04:16,617 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,623 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 4 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:04:16,623 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 8 variables, input treesize:41, output treesize:29 [2018-02-04 19:04:16,700 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,700 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,701 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,702 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 46 [2018-02-04 19:04:16,702 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,760 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 45 [2018-02-04 19:04:16,760 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,845 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,846 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,847 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,848 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,849 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,850 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 78 [2018-02-04 19:04:16,850 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,918 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,919 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,919 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,920 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,920 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 50 [2018-02-04 19:04:16,920 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:16,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,975 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:16,975 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 48 [2018-02-04 19:04:16,976 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:17,027 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,028 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 67 [2018-02-04 19:04:17,028 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:17,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,083 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 5 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 46 treesize of output 67 [2018-02-04 19:04:17,083 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:17,130 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,131 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,131 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:04:17,132 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 50 treesize of output 47 [2018-02-04 19:04:17,132 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-02-04 19:04:17,172 INFO L267 ElimStorePlain]: Start of recursive call 1: 16 dim-0 vars, 8 dim-1 vars, End of recursive call: 16 dim-0 vars, and 4 xjuncts. [2018-02-04 19:04:17,172 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 24 variables, input treesize:213, output treesize:165 [2018-02-04 19:04:39,216 WARN L146 SmtUtils]: Spent 21997ms on a formula simplification. DAG size of input: 91 DAG size of output 71 [2018-02-04 19:04:39,267 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 2 proven. 280 refuted. 0 times theorem prover too weak. 375 trivial. 0 not checked. [2018-02-04 19:04:39,267 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:04:39,267 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14] total 14 [2018-02-04 19:04:39,267 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 19:04:39,267 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 19:04:39,267 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=163, Unknown=3, NotChecked=0, Total=210 [2018-02-04 19:04:39,267 INFO L87 Difference]: Start difference. First operand 208 states and 229 transitions. Second operand 15 states. [2018-02-04 19:04:41,564 WARN L146 SmtUtils]: Spent 100ms on a formula simplification. DAG size of input: 86 DAG size of output 64 [2018-02-04 19:05:10,512 WARN L146 SmtUtils]: Spent 20730ms on a formula simplification. DAG size of input: 94 DAG size of output 94 [2018-02-04 19:05:23,495 WARN L143 SmtUtils]: Spent 10682ms on a formula simplification that was a NOOP. DAG size: 96 [2018-02-04 19:05:24,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:24,863 INFO L93 Difference]: Finished difference Result 257 states and 273 transitions. [2018-02-04 19:05:24,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 19:05:24,864 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 85 [2018-02-04 19:05:24,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:24,865 INFO L225 Difference]: With dead ends: 257 [2018-02-04 19:05:24,865 INFO L226 Difference]: Without dead ends: 257 [2018-02-04 19:05:24,865 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 67 SyntacticMatches, 4 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 112 ImplicationChecksByTransitivity, 58.0s TimeCoverageRelationStatistics Valid=111, Invalid=482, Unknown=7, NotChecked=0, Total=600 [2018-02-04 19:05:24,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states. [2018-02-04 19:05:24,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 207. [2018-02-04 19:05:24,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-02-04 19:05:24,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 228 transitions. [2018-02-04 19:05:24,869 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 228 transitions. Word has length 85 [2018-02-04 19:05:24,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:24,869 INFO L432 AbstractCegarLoop]: Abstraction has 207 states and 228 transitions. [2018-02-04 19:05:24,869 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 19:05:24,869 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 228 transitions. [2018-02-04 19:05:24,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-04 19:05:24,869 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:24,869 INFO L351 BasicCegarLoop]: trace histogram [33, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:24,870 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:24,870 INFO L82 PathProgramCache]: Analyzing trace with hash -1850576373, now seen corresponding path program 1 times [2018-02-04 19:05:24,870 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:24,870 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:24,870 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:24,870 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:05:24,870 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:24,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:24,888 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:24,928 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 657 trivial. 0 not checked. [2018-02-04 19:05:24,928 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:05:24,928 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:05:24,929 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 19:05:24,929 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 19:05:24,929 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:05:24,929 INFO L87 Difference]: Start difference. First operand 207 states and 228 transitions. Second operand 7 states. [2018-02-04 19:05:25,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:25,103 INFO L93 Difference]: Finished difference Result 213 states and 235 transitions. [2018-02-04 19:05:25,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 19:05:25,103 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 90 [2018-02-04 19:05:25,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:25,104 INFO L225 Difference]: With dead ends: 213 [2018-02-04 19:05:25,105 INFO L226 Difference]: Without dead ends: 213 [2018-02-04 19:05:25,105 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=53, Unknown=0, NotChecked=0, Total=72 [2018-02-04 19:05:25,105 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 213 states. [2018-02-04 19:05:25,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 213 to 206. [2018-02-04 19:05:25,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 206 states. [2018-02-04 19:05:25,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206 states to 206 states and 227 transitions. [2018-02-04 19:05:25,109 INFO L78 Accepts]: Start accepts. Automaton has 206 states and 227 transitions. Word has length 90 [2018-02-04 19:05:25,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:25,110 INFO L432 AbstractCegarLoop]: Abstraction has 206 states and 227 transitions. [2018-02-04 19:05:25,110 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 19:05:25,110 INFO L276 IsEmpty]: Start isEmpty. Operand 206 states and 227 transitions. [2018-02-04 19:05:25,110 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-04 19:05:25,110 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:25,110 INFO L351 BasicCegarLoop]: trace histogram [33, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:25,110 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:25,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1850576372, now seen corresponding path program 1 times [2018-02-04 19:05:25,111 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:25,111 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:25,111 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:25,112 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:25,112 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:25,130 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:25,131 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:25,257 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 649 trivial. 0 not checked. [2018-02-04 19:05:25,257 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:25,257 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:25,258 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:25,286 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:25,294 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:25,644 INFO L134 CoverageAnalysis]: Checked inductivity of 657 backedges. 454 proven. 78 refuted. 0 times theorem prover too weak. 125 trivial. 0 not checked. [2018-02-04 19:05:25,644 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:05:25,644 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 18] total 27 [2018-02-04 19:05:25,645 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 19:05:25,645 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 19:05:25,645 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=650, Unknown=0, NotChecked=0, Total=702 [2018-02-04 19:05:25,645 INFO L87 Difference]: Start difference. First operand 206 states and 227 transitions. Second operand 27 states. [2018-02-04 19:05:26,435 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:26,435 INFO L93 Difference]: Finished difference Result 250 states and 279 transitions. [2018-02-04 19:05:26,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-02-04 19:05:26,435 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 90 [2018-02-04 19:05:26,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:26,436 INFO L225 Difference]: With dead ends: 250 [2018-02-04 19:05:26,436 INFO L226 Difference]: Without dead ends: 250 [2018-02-04 19:05:26,436 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 120 GetRequests, 74 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 227 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=275, Invalid=1887, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 19:05:26,437 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-02-04 19:05:26,439 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 231. [2018-02-04 19:05:26,440 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2018-02-04 19:05:26,440 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 255 transitions. [2018-02-04 19:05:26,440 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 255 transitions. Word has length 90 [2018-02-04 19:05:26,440 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:26,440 INFO L432 AbstractCegarLoop]: Abstraction has 231 states and 255 transitions. [2018-02-04 19:05:26,440 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 19:05:26,440 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 255 transitions. [2018-02-04 19:05:26,441 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-04 19:05:26,441 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:26,441 INFO L351 BasicCegarLoop]: trace histogram [34, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:26,441 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:26,441 INFO L82 PathProgramCache]: Analyzing trace with hash 669580800, now seen corresponding path program 1 times [2018-02-04 19:05:26,442 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:26,442 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:26,442 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:26,442 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:26,443 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:26,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:26,480 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:26,734 INFO L134 CoverageAnalysis]: Checked inductivity of 693 backedges. 189 proven. 238 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:26,734 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:26,734 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:26,735 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:26,752 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:26,756 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:27,095 INFO L134 CoverageAnalysis]: Checked inductivity of 693 backedges. 477 proven. 91 refuted. 0 times theorem prover too weak. 125 trivial. 0 not checked. [2018-02-04 19:05:27,096 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:05:27,096 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19] total 36 [2018-02-04 19:05:27,096 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 19:05:27,096 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 19:05:27,096 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=74, Invalid=1186, Unknown=0, NotChecked=0, Total=1260 [2018-02-04 19:05:27,096 INFO L87 Difference]: Start difference. First operand 231 states and 255 transitions. Second operand 36 states. [2018-02-04 19:05:28,318 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:28,318 INFO L93 Difference]: Finished difference Result 255 states and 285 transitions. [2018-02-04 19:05:28,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-02-04 19:05:28,318 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 93 [2018-02-04 19:05:28,319 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:28,319 INFO L225 Difference]: With dead ends: 255 [2018-02-04 19:05:28,319 INFO L226 Difference]: Without dead ends: 250 [2018-02-04 19:05:28,320 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 140 GetRequests, 77 SyntacticMatches, 1 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 523 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=310, Invalid=3722, Unknown=0, NotChecked=0, Total=4032 [2018-02-04 19:05:28,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250 states. [2018-02-04 19:05:28,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250 to 232. [2018-02-04 19:05:28,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-02-04 19:05:28,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 256 transitions. [2018-02-04 19:05:28,323 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 256 transitions. Word has length 93 [2018-02-04 19:05:28,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:28,323 INFO L432 AbstractCegarLoop]: Abstraction has 232 states and 256 transitions. [2018-02-04 19:05:28,323 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 19:05:28,323 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 256 transitions. [2018-02-04 19:05:28,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-02-04 19:05:28,323 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:28,323 INFO L351 BasicCegarLoop]: trace histogram [35, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:28,323 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:28,324 INFO L82 PathProgramCache]: Analyzing trace with hash 272267660, now seen corresponding path program 2 times [2018-02-04 19:05:28,324 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:28,324 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:28,324 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:28,324 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:28,324 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:28,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:28,360 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:28,689 INFO L134 CoverageAnalysis]: Checked inductivity of 730 backedges. 202 proven. 262 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:28,690 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:28,690 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:28,690 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:05:28,709 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:05:28,709 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:05:28,712 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:28,748 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:05:28,749 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:28,750 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:28,751 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:28,753 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:28,754 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:11 [2018-02-04 19:05:28,852 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-02-04 19:05:28,853 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-02-04 19:05:28,853 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:28,854 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:28,857 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:28,857 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:26, output treesize:11 [2018-02-04 19:05:28,896 INFO L134 CoverageAnalysis]: Checked inductivity of 730 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 730 trivial. 0 not checked. [2018-02-04 19:05:28,896 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:05:28,897 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [20] total 28 [2018-02-04 19:05:28,897 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 19:05:28,897 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 19:05:28,897 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=703, Unknown=0, NotChecked=0, Total=756 [2018-02-04 19:05:28,897 INFO L87 Difference]: Start difference. First operand 232 states and 256 transitions. Second operand 28 states. [2018-02-04 19:05:29,657 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:29,657 INFO L93 Difference]: Finished difference Result 266 states and 297 transitions. [2018-02-04 19:05:29,657 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-02-04 19:05:29,657 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 94 [2018-02-04 19:05:29,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:29,658 INFO L225 Difference]: With dead ends: 266 [2018-02-04 19:05:29,658 INFO L226 Difference]: Without dead ends: 258 [2018-02-04 19:05:29,658 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 87 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=85, Invalid=1105, Unknown=0, NotChecked=0, Total=1190 [2018-02-04 19:05:29,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 258 states. [2018-02-04 19:05:29,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 258 to 229. [2018-02-04 19:05:29,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2018-02-04 19:05:29,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 251 transitions. [2018-02-04 19:05:29,662 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 251 transitions. Word has length 94 [2018-02-04 19:05:29,662 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:29,662 INFO L432 AbstractCegarLoop]: Abstraction has 229 states and 251 transitions. [2018-02-04 19:05:29,662 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 19:05:29,662 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 251 transitions. [2018-02-04 19:05:29,663 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-02-04 19:05:29,663 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:29,663 INFO L351 BasicCegarLoop]: trace histogram [36, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:29,663 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:29,663 INFO L82 PathProgramCache]: Analyzing trace with hash 840462209, now seen corresponding path program 1 times [2018-02-04 19:05:29,663 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:29,663 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:29,663 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:29,664 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:05:29,664 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:29,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:29,690 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:30,007 INFO L134 CoverageAnalysis]: Checked inductivity of 768 backedges. 215 proven. 287 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:30,008 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:30,008 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:30,008 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:30,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:30,044 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:30,413 INFO L134 CoverageAnalysis]: Checked inductivity of 768 backedges. 523 proven. 120 refuted. 0 times theorem prover too weak. 125 trivial. 0 not checked. [2018-02-04 19:05:30,413 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:05:30,413 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21] total 41 [2018-02-04 19:05:30,413 INFO L409 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-02-04 19:05:30,413 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-02-04 19:05:30,414 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=340, Invalid=1300, Unknown=0, NotChecked=0, Total=1640 [2018-02-04 19:05:30,414 INFO L87 Difference]: Start difference. First operand 229 states and 251 transitions. Second operand 41 states. [2018-02-04 19:05:30,933 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:30,933 INFO L93 Difference]: Finished difference Result 270 states and 302 transitions. [2018-02-04 19:05:30,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-02-04 19:05:30,933 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 95 [2018-02-04 19:05:30,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:30,934 INFO L225 Difference]: With dead ends: 270 [2018-02-04 19:05:30,934 INFO L226 Difference]: Without dead ends: 263 [2018-02-04 19:05:30,935 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=814, Invalid=2726, Unknown=0, NotChecked=0, Total=3540 [2018-02-04 19:05:30,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 263 states. [2018-02-04 19:05:30,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 263 to 230. [2018-02-04 19:05:30,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-02-04 19:05:30,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 251 transitions. [2018-02-04 19:05:30,938 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 251 transitions. Word has length 95 [2018-02-04 19:05:30,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:30,938 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 251 transitions. [2018-02-04 19:05:30,938 INFO L433 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-02-04 19:05:30,938 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 251 transitions. [2018-02-04 19:05:30,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-02-04 19:05:30,939 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:30,939 INFO L351 BasicCegarLoop]: trace histogram [37, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:30,939 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:30,939 INFO L82 PathProgramCache]: Analyzing trace with hash 1274624013, now seen corresponding path program 2 times [2018-02-04 19:05:30,939 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:30,939 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:30,940 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:30,940 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:30,940 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:30,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:30,967 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:31,299 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 228 proven. 313 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:31,299 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:31,299 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:31,300 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:05:31,313 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 19:05:31,314 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:05:31,317 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:31,364 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:05:31,365 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:31,365 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,366 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,374 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 19:05:31,375 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 19:05:31,375 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,377 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,382 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,382 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:41, output treesize:27 [2018-02-04 19:05:31,553 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 23 [2018-02-04 19:05:31,554 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 11 [2018-02-04 19:05:31,554 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,555 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,559 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 24 [2018-02-04 19:05:31,561 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 24 treesize of output 9 [2018-02-04 19:05:31,561 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,563 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,565 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:31,565 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:45, output treesize:9 [2018-02-04 19:05:31,610 INFO L134 CoverageAnalysis]: Checked inductivity of 807 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 807 trivial. 0 not checked. [2018-02-04 19:05:31,610 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:05:31,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [23] total 31 [2018-02-04 19:05:31,611 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 19:05:31,611 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 19:05:31,611 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=869, Unknown=0, NotChecked=0, Total=930 [2018-02-04 19:05:31,611 INFO L87 Difference]: Start difference. First operand 230 states and 251 transitions. Second operand 31 states. [2018-02-04 19:05:32,527 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:32,527 INFO L93 Difference]: Finished difference Result 276 states and 310 transitions. [2018-02-04 19:05:32,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-02-04 19:05:32,527 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 96 [2018-02-04 19:05:32,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:32,528 INFO L225 Difference]: With dead ends: 276 [2018-02-04 19:05:32,528 INFO L226 Difference]: Without dead ends: 271 [2018-02-04 19:05:32,528 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=94, Invalid=1312, Unknown=0, NotChecked=0, Total=1406 [2018-02-04 19:05:32,529 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 271 states. [2018-02-04 19:05:32,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 271 to 230. [2018-02-04 19:05:32,531 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-02-04 19:05:32,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 251 transitions. [2018-02-04 19:05:32,532 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 251 transitions. Word has length 96 [2018-02-04 19:05:32,532 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:32,532 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 251 transitions. [2018-02-04 19:05:32,532 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 19:05:32,532 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 251 transitions. [2018-02-04 19:05:32,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-02-04 19:05:32,532 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:32,532 INFO L351 BasicCegarLoop]: trace histogram [38, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:32,532 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:32,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1476304642, now seen corresponding path program 1 times [2018-02-04 19:05:32,532 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:32,532 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:32,533 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:32,533 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:05:32,533 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:32,555 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:32,556 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:32,988 INFO L134 CoverageAnalysis]: Checked inductivity of 847 backedges. 241 proven. 340 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:32,988 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:32,988 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:32,989 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:33,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:33,018 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:33,515 INFO L134 CoverageAnalysis]: Checked inductivity of 847 backedges. 569 proven. 153 refuted. 0 times theorem prover too weak. 125 trivial. 0 not checked. [2018-02-04 19:05:33,515 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:05:33,515 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23] total 44 [2018-02-04 19:05:33,515 INFO L409 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-02-04 19:05:33,515 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-02-04 19:05:33,516 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=1802, Unknown=0, NotChecked=0, Total=1892 [2018-02-04 19:05:33,516 INFO L87 Difference]: Start difference. First operand 230 states and 251 transitions. Second operand 44 states. [2018-02-04 19:05:35,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:35,400 INFO L93 Difference]: Finished difference Result 281 states and 317 transitions. [2018-02-04 19:05:35,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-02-04 19:05:35,400 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 98 [2018-02-04 19:05:35,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:35,401 INFO L225 Difference]: With dead ends: 281 [2018-02-04 19:05:35,401 INFO L226 Difference]: Without dead ends: 276 [2018-02-04 19:05:35,402 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 78 SyntacticMatches, 1 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 815 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=428, Invalid=5892, Unknown=0, NotChecked=0, Total=6320 [2018-02-04 19:05:35,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 276 states. [2018-02-04 19:05:35,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 276 to 231. [2018-02-04 19:05:35,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2018-02-04 19:05:35,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 252 transitions. [2018-02-04 19:05:35,406 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 252 transitions. Word has length 98 [2018-02-04 19:05:35,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:35,406 INFO L432 AbstractCegarLoop]: Abstraction has 231 states and 252 transitions. [2018-02-04 19:05:35,406 INFO L433 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-02-04 19:05:35,406 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 252 transitions. [2018-02-04 19:05:35,406 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 100 [2018-02-04 19:05:35,406 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:35,407 INFO L351 BasicCegarLoop]: trace histogram [39, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:35,407 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:35,407 INFO L82 PathProgramCache]: Analyzing trace with hash -850887946, now seen corresponding path program 2 times [2018-02-04 19:05:35,407 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:35,407 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:35,407 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:35,408 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:35,408 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:35,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:35,441 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:35,860 INFO L134 CoverageAnalysis]: Checked inductivity of 888 backedges. 254 proven. 368 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:35,860 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:35,860 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:35,860 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 19:05:35,922 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 19:05:35,922 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:05:35,934 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:36,546 INFO L134 CoverageAnalysis]: Checked inductivity of 888 backedges. 592 proven. 171 refuted. 0 times theorem prover too weak. 125 trivial. 0 not checked. [2018-02-04 19:05:36,547 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:05:36,547 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24] total 47 [2018-02-04 19:05:36,547 INFO L409 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-02-04 19:05:36,547 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-02-04 19:05:36,547 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=95, Invalid=2067, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 19:05:36,548 INFO L87 Difference]: Start difference. First operand 231 states and 252 transitions. Second operand 47 states. [2018-02-04 19:05:38,858 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:38,858 INFO L93 Difference]: Finished difference Result 288 states and 326 transitions. [2018-02-04 19:05:38,858 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-02-04 19:05:38,859 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 99 [2018-02-04 19:05:38,859 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:38,859 INFO L225 Difference]: With dead ends: 288 [2018-02-04 19:05:38,859 INFO L226 Difference]: Without dead ends: 283 [2018-02-04 19:05:38,861 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 164 GetRequests, 79 SyntacticMatches, 0 SemanticMatches, 85 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 903 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=452, Invalid=7030, Unknown=0, NotChecked=0, Total=7482 [2018-02-04 19:05:38,861 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283 states. [2018-02-04 19:05:38,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283 to 232. [2018-02-04 19:05:38,865 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-02-04 19:05:38,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 253 transitions. [2018-02-04 19:05:38,866 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 253 transitions. Word has length 99 [2018-02-04 19:05:38,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:38,866 INFO L432 AbstractCegarLoop]: Abstraction has 232 states and 253 transitions. [2018-02-04 19:05:38,866 INFO L433 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-02-04 19:05:38,866 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 253 transitions. [2018-02-04 19:05:38,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 101 [2018-02-04 19:05:38,867 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:38,867 INFO L351 BasicCegarLoop]: trace histogram [40, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:38,867 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:38,867 INFO L82 PathProgramCache]: Analyzing trace with hash 20585858, now seen corresponding path program 3 times [2018-02-04 19:05:38,867 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:38,867 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:38,868 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:38,868 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:05:38,868 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:38,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:38,918 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:39,494 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 267 proven. 397 refuted. 0 times theorem prover too weak. 266 trivial. 0 not checked. [2018-02-04 19:05:39,494 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:39,494 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:39,495 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 19:05:39,533 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-02-04 19:05:39,534 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 19:05:39,539 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:39,541 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:05:39,541 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,543 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,543 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-02-04 19:05:39,719 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:39,720 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 13 [2018-02-04 19:05:39,720 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,721 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:39,721 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-02-04 19:05:39,791 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:39,792 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:39,792 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 24 [2018-02-04 19:05:39,792 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,795 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,795 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:15 [2018-02-04 19:05:39,819 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:05:39,820 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:39,820 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,821 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,825 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,825 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:28, output treesize:27 [2018-02-04 19:05:39,881 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 53 [2018-02-04 19:05:39,883 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 19:05:39,883 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,885 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,888 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,888 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:64, output treesize:27 [2018-02-04 19:05:39,891 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 19:05:39,892 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 19:05:39,892 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,893 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,909 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 3 case distinctions, treesize of input 35 treesize of output 45 [2018-02-04 19:05:39,911 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 35 [2018-02-04 19:05:39,911 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:39,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 31 treesize of output 39 [2018-02-04 19:05:39,928 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-02-04 19:05:39,939 INFO L267 ElimStorePlain]: Start of recursive call 4: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-02-04 19:05:39,951 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 2 xjuncts. [2018-02-04 19:05:39,951 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 4 variables, input treesize:60, output treesize:121 [2018-02-04 19:05:40,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 55 [2018-02-04 19:05:40,245 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-02-04 19:05:40,246 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,251 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,264 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 80 [2018-02-04 19:05:40,265 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 40 [2018-02-04 19:05:40,266 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,270 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,282 INFO L267 ElimStorePlain]: Start of recursive call 1: 5 dim-0 vars, 2 dim-2 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:05:40,282 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 7 variables, input treesize:146, output treesize:105 [2018-02-04 19:05:40,404 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 1 case distinctions, treesize of input 71 treesize of output 58 [2018-02-04 19:05:40,406 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 51 treesize of output 36 [2018-02-04 19:05:40,406 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 28 [2018-02-04 19:05:40,420 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:40,434 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 24 [2018-02-04 19:05:40,435 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:40,445 INFO L267 ElimStorePlain]: Start of recursive call 2: 3 dim-1 vars, End of recursive call: 2 dim-0 vars, and 2 xjuncts. [2018-02-04 19:05:40,462 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 33 [2018-02-04 19:05:40,463 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 8 [2018-02-04 19:05:40,463 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,466 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:40,480 INFO L267 ElimStorePlain]: Start of recursive call 1: 6 dim-0 vars, 2 dim-2 vars, End of recursive call: 5 dim-0 vars, and 3 xjuncts. [2018-02-04 19:05:40,481 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 8 variables, input treesize:117, output treesize:60 [2018-02-04 19:05:40,554 INFO L134 CoverageAnalysis]: Checked inductivity of 930 backedges. 412 proven. 0 refuted. 0 times theorem prover too weak. 518 trivial. 0 not checked. [2018-02-04 19:05:40,554 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:05:40,554 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [20] imperfect sequences [26] total 45 [2018-02-04 19:05:40,554 INFO L409 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-02-04 19:05:40,554 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-02-04 19:05:40,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=1869, Unknown=0, NotChecked=0, Total=1980 [2018-02-04 19:05:40,555 INFO L87 Difference]: Start difference. First operand 232 states and 253 transitions. Second operand 45 states. [2018-02-04 19:05:44,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:44,793 INFO L93 Difference]: Finished difference Result 311 states and 353 transitions. [2018-02-04 19:05:44,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-02-04 19:05:44,793 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 100 [2018-02-04 19:05:44,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:44,794 INFO L225 Difference]: With dead ends: 311 [2018-02-04 19:05:44,794 INFO L226 Difference]: Without dead ends: 306 [2018-02-04 19:05:44,795 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 166 GetRequests, 80 SyntacticMatches, 3 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1063 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=390, Invalid=6750, Unknown=0, NotChecked=0, Total=7140 [2018-02-04 19:05:44,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 306 states. [2018-02-04 19:05:44,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 306 to 232. [2018-02-04 19:05:44,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 232 states. [2018-02-04 19:05:44,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232 states to 232 states and 253 transitions. [2018-02-04 19:05:44,798 INFO L78 Accepts]: Start accepts. Automaton has 232 states and 253 transitions. Word has length 100 [2018-02-04 19:05:44,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:44,799 INFO L432 AbstractCegarLoop]: Abstraction has 232 states and 253 transitions. [2018-02-04 19:05:44,799 INFO L433 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-02-04 19:05:44,799 INFO L276 IsEmpty]: Start isEmpty. Operand 232 states and 253 transitions. [2018-02-04 19:05:44,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-02-04 19:05:44,799 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:44,799 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:44,799 INFO L371 AbstractCegarLoop]: === Iteration 31 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:44,799 INFO L82 PathProgramCache]: Analyzing trace with hash 1266470007, now seen corresponding path program 1 times [2018-02-04 19:05:44,799 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:44,799 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:44,800 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:44,800 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 19:05:44,800 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:44,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:44,855 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:44,877 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:05:44,877 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:44,877 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:44,878 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:44,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:45,009 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:45,012 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:05:45,012 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,014 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,015 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-02-04 19:05:45,204 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:45,205 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 5 [2018-02-04 19:05:45,205 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,206 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:45,206 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:12, output treesize:5 [2018-02-04 19:05:45,255 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:45,255 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:45,256 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-02-04 19:05:45,256 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,260 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,260 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:23, output treesize:21 [2018-02-04 19:05:45,306 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 24 [2018-02-04 19:05:45,306 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,317 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 21 [2018-02-04 19:05:45,317 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,327 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:05:45,327 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:48, output treesize:46 [2018-02-04 19:05:45,351 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 15 [2018-02-04 19:05:45,351 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,360 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 18 treesize of output 13 [2018-02-04 19:05:45,360 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:45,367 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:05:45,367 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:39, output treesize:29 [2018-02-04 19:05:49,537 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:49,538 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:49,538 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:05:49,539 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-02-04 19:05:49,539 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,549 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,549 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:34, output treesize:27 [2018-02-04 19:05:49,578 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-02-04 19:05:49,578 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,589 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:05:49,590 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:49,590 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,592 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,601 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:05:49,603 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:49,603 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,604 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,611 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,611 INFO L202 ElimStorePlain]: Needed 6 recursive calls to eliminate 4 variables, input treesize:55, output treesize:51 [2018-02-04 19:05:49,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 106 treesize of output 100 [2018-02-04 19:05:49,687 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 19:05:49,687 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,691 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,702 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 48 [2018-02-04 19:05:49,703 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 1 [2018-02-04 19:05:49,703 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,705 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,710 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,711 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:125, output treesize:51 [2018-02-04 19:05:49,716 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 39 treesize of output 40 [2018-02-04 19:05:49,718 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:49,718 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,724 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,738 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 28 [2018-02-04 19:05:49,741 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:05:49,742 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,746 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,754 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:49,754 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:66, output treesize:85 [2018-02-04 19:05:49,982 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 1 [2018-02-04 19:05:49,982 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:50,000 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 3 new quantified variables, introduced 0 case distinctions, treesize of input 95 treesize of output 68 [2018-02-04 19:05:50,001 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 19:05:50,002 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 25 [2018-02-04 19:05:50,002 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:50,008 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 29 [2018-02-04 19:05:50,009 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:50,015 INFO L267 ElimStorePlain]: Start of recursive call 3: 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:05:50,022 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 28 treesize of output 24 [2018-02-04 19:05:50,024 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 5 [2018-02-04 19:05:50,024 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:50,028 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 3 [2018-02-04 19:05:50,028 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:50,029 INFO L267 ElimStorePlain]: Start of recursive call 6: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:50,032 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, 2 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:05:50,033 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 4 variables, input treesize:111, output treesize:9 [2018-02-04 19:05:50,083 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 45 proven. 750 refuted. 0 times theorem prover too weak. 178 trivial. 0 not checked. [2018-02-04 19:05:50,084 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:05:50,084 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35] total 35 [2018-02-04 19:05:50,084 INFO L409 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-02-04 19:05:50,084 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-02-04 19:05:50,084 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=105, Invalid=1153, Unknown=2, NotChecked=0, Total=1260 [2018-02-04 19:05:50,085 INFO L87 Difference]: Start difference. First operand 232 states and 253 transitions. Second operand 36 states. [2018-02-04 19:05:55,382 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:55,382 INFO L93 Difference]: Finished difference Result 254 states and 277 transitions. [2018-02-04 19:05:55,382 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-02-04 19:05:55,382 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 101 [2018-02-04 19:05:55,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:55,383 INFO L225 Difference]: With dead ends: 254 [2018-02-04 19:05:55,383 INFO L226 Difference]: Without dead ends: 254 [2018-02-04 19:05:55,384 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 62 SyntacticMatches, 4 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 981 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=396, Invalid=4024, Unknown=2, NotChecked=0, Total=4422 [2018-02-04 19:05:55,384 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 254 states. [2018-02-04 19:05:55,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 254 to 231. [2018-02-04 19:05:55,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 231 states. [2018-02-04 19:05:55,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 231 states to 231 states and 252 transitions. [2018-02-04 19:05:55,386 INFO L78 Accepts]: Start accepts. Automaton has 231 states and 252 transitions. Word has length 101 [2018-02-04 19:05:55,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:55,386 INFO L432 AbstractCegarLoop]: Abstraction has 231 states and 252 transitions. [2018-02-04 19:05:55,386 INFO L433 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-02-04 19:05:55,386 INFO L276 IsEmpty]: Start isEmpty. Operand 231 states and 252 transitions. [2018-02-04 19:05:55,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-02-04 19:05:55,387 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:55,387 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:55,387 INFO L371 AbstractCegarLoop]: === Iteration 32 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:55,387 INFO L82 PathProgramCache]: Analyzing trace with hash -1391181879, now seen corresponding path program 1 times [2018-02-04 19:05:55,387 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:55,387 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:55,387 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:55,388 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:55,388 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:55,399 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:55,400 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:55,459 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 973 trivial. 0 not checked. [2018-02-04 19:05:55,459 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:05:55,459 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 19:05:55,459 INFO L409 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-02-04 19:05:55,459 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-02-04 19:05:55,459 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=91, Unknown=0, NotChecked=0, Total=110 [2018-02-04 19:05:55,460 INFO L87 Difference]: Start difference. First operand 231 states and 252 transitions. Second operand 11 states. [2018-02-04 19:05:55,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:55,614 INFO L93 Difference]: Finished difference Result 237 states and 259 transitions. [2018-02-04 19:05:55,615 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-02-04 19:05:55,615 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 107 [2018-02-04 19:05:55,615 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:55,615 INFO L225 Difference]: With dead ends: 237 [2018-02-04 19:05:55,615 INFO L226 Difference]: Without dead ends: 237 [2018-02-04 19:05:55,615 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=35, Invalid=175, Unknown=0, NotChecked=0, Total=210 [2018-02-04 19:05:55,616 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-02-04 19:05:55,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 230. [2018-02-04 19:05:55,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 230 states. [2018-02-04 19:05:55,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 230 states to 230 states and 251 transitions. [2018-02-04 19:05:55,618 INFO L78 Accepts]: Start accepts. Automaton has 230 states and 251 transitions. Word has length 107 [2018-02-04 19:05:55,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:55,618 INFO L432 AbstractCegarLoop]: Abstraction has 230 states and 251 transitions. [2018-02-04 19:05:55,618 INFO L433 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-02-04 19:05:55,618 INFO L276 IsEmpty]: Start isEmpty. Operand 230 states and 251 transitions. [2018-02-04 19:05:55,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-02-04 19:05:55,618 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:55,619 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:55,619 INFO L371 AbstractCegarLoop]: === Iteration 33 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:55,619 INFO L82 PathProgramCache]: Analyzing trace with hash -1391181878, now seen corresponding path program 1 times [2018-02-04 19:05:55,619 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:55,619 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:55,620 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:55,620 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:55,620 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:55,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:55,635 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:55,814 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 965 trivial. 0 not checked. [2018-02-04 19:05:55,814 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:55,814 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:55,815 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:55,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:55,883 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:56,117 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 965 trivial. 0 not checked. [2018-02-04 19:05:56,118 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:05:56,118 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 27 [2018-02-04 19:05:56,118 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 19:05:56,118 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 19:05:56,118 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=64, Invalid=692, Unknown=0, NotChecked=0, Total=756 [2018-02-04 19:05:56,119 INFO L87 Difference]: Start difference. First operand 230 states and 251 transitions. Second operand 28 states. [2018-02-04 19:05:56,500 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:56,500 INFO L93 Difference]: Finished difference Result 236 states and 258 transitions. [2018-02-04 19:05:56,500 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 19:05:56,500 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 107 [2018-02-04 19:05:56,500 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:56,501 INFO L225 Difference]: With dead ends: 236 [2018-02-04 19:05:56,501 INFO L226 Difference]: Without dead ends: 236 [2018-02-04 19:05:56,501 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 131 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=127, Invalid=1355, Unknown=0, NotChecked=0, Total=1482 [2018-02-04 19:05:56,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236 states. [2018-02-04 19:05:56,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236 to 229. [2018-02-04 19:05:56,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2018-02-04 19:05:56,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 250 transitions. [2018-02-04 19:05:56,504 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 250 transitions. Word has length 107 [2018-02-04 19:05:56,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:56,505 INFO L432 AbstractCegarLoop]: Abstraction has 229 states and 250 transitions. [2018-02-04 19:05:56,505 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 19:05:56,505 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 250 transitions. [2018-02-04 19:05:56,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-02-04 19:05:56,505 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:56,506 INFO L351 BasicCegarLoop]: trace histogram [53, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:56,506 INFO L371 AbstractCegarLoop]: === Iteration 34 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:56,506 INFO L82 PathProgramCache]: Analyzing trace with hash 1525240570, now seen corresponding path program 1 times [2018-02-04 19:05:56,506 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:56,506 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:56,507 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:56,507 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:56,507 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:56,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:56,530 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:56,607 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 1638 trivial. 0 not checked. [2018-02-04 19:05:56,607 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:05:56,607 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 19:05:56,607 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 19:05:56,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 19:05:56,608 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 19:05:56,608 INFO L87 Difference]: Start difference. First operand 229 states and 250 transitions. Second operand 8 states. [2018-02-04 19:05:56,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:05:56,796 INFO L93 Difference]: Finished difference Result 227 states and 248 transitions. [2018-02-04 19:05:56,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 19:05:56,797 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 130 [2018-02-04 19:05:56,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:05:56,798 INFO L225 Difference]: With dead ends: 227 [2018-02-04 19:05:56,798 INFO L226 Difference]: Without dead ends: 227 [2018-02-04 19:05:56,798 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-04 19:05:56,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-02-04 19:05:56,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 225. [2018-02-04 19:05:56,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-02-04 19:05:56,801 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 246 transitions. [2018-02-04 19:05:56,802 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 246 transitions. Word has length 130 [2018-02-04 19:05:56,802 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:05:56,802 INFO L432 AbstractCegarLoop]: Abstraction has 225 states and 246 transitions. [2018-02-04 19:05:56,802 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 19:05:56,802 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 246 transitions. [2018-02-04 19:05:56,803 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-02-04 19:05:56,803 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:05:56,803 INFO L351 BasicCegarLoop]: trace histogram [53, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:05:56,803 INFO L371 AbstractCegarLoop]: === Iteration 35 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:05:56,803 INFO L82 PathProgramCache]: Analyzing trace with hash 1525240571, now seen corresponding path program 1 times [2018-02-04 19:05:56,803 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:05:56,803 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:05:56,804 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:56,804 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:56,804 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:05:56,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:56,835 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:05:57,102 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 590 proven. 78 refuted. 0 times theorem prover too weak. 982 trivial. 0 not checked. [2018-02-04 19:05:57,102 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:05:57,102 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:05:57,103 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:05:57,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:05:57,147 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:05:57,173 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 19:05:57,173 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:57,184 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 19:05:57,184 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:05:57,193 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:05:57,193 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 19:06:03,819 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 595 proven. 2 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-02-04 19:06:03,819 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 19:06:03,819 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 9] total 30 [2018-02-04 19:06:03,819 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 19:06:03,820 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 19:06:03,820 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=70, Invalid=857, Unknown=3, NotChecked=0, Total=930 [2018-02-04 19:06:03,820 INFO L87 Difference]: Start difference. First operand 225 states and 246 transitions. Second operand 31 states. [2018-02-04 19:06:06,006 WARN L143 SmtUtils]: Spent 2031ms on a formula simplification that was a NOOP. DAG size: 27 [2018-02-04 19:06:08,767 WARN L143 SmtUtils]: Spent 2018ms on a formula simplification that was a NOOP. DAG size: 25 [2018-02-04 19:06:09,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:09,334 INFO L93 Difference]: Finished difference Result 246 states and 272 transitions. [2018-02-04 19:06:09,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-02-04 19:06:09,335 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 130 [2018-02-04 19:06:09,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:09,335 INFO L225 Difference]: With dead ends: 246 [2018-02-04 19:06:09,335 INFO L226 Difference]: Without dead ends: 241 [2018-02-04 19:06:09,336 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 121 SyntacticMatches, 1 SemanticMatches, 49 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 279 ImplicationChecksByTransitivity, 11.4s TimeCoverageRelationStatistics Valid=177, Invalid=2370, Unknown=3, NotChecked=0, Total=2550 [2018-02-04 19:06:09,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 241 states. [2018-02-04 19:06:09,338 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 241 to 225. [2018-02-04 19:06:09,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-02-04 19:06:09,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 249 transitions. [2018-02-04 19:06:09,339 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 249 transitions. Word has length 130 [2018-02-04 19:06:09,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:09,340 INFO L432 AbstractCegarLoop]: Abstraction has 225 states and 249 transitions. [2018-02-04 19:06:09,340 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 19:06:09,340 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 249 transitions. [2018-02-04 19:06:09,340 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-02-04 19:06:09,341 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:09,341 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:09,341 INFO L371 AbstractCegarLoop]: === Iteration 36 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:09,341 INFO L82 PathProgramCache]: Analyzing trace with hash 2055227473, now seen corresponding path program 1 times [2018-02-04 19:06:09,341 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:09,341 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:09,342 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,342 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:09,342 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:09,358 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:09,383 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 973 trivial. 0 not checked. [2018-02-04 19:06:09,383 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:06:09,383 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 19:06:09,383 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 19:06:09,383 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 19:06:09,383 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 19:06:09,383 INFO L87 Difference]: Start difference. First operand 225 states and 249 transitions. Second operand 4 states. [2018-02-04 19:06:09,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:09,388 INFO L93 Difference]: Finished difference Result 233 states and 257 transitions. [2018-02-04 19:06:09,388 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 19:06:09,388 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 122 [2018-02-04 19:06:09,388 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:09,388 INFO L225 Difference]: With dead ends: 233 [2018-02-04 19:06:09,388 INFO L226 Difference]: Without dead ends: 233 [2018-02-04 19:06:09,388 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 19:06:09,389 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-02-04 19:06:09,391 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 233. [2018-02-04 19:06:09,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 233 states. [2018-02-04 19:06:09,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 233 states to 233 states and 257 transitions. [2018-02-04 19:06:09,392 INFO L78 Accepts]: Start accepts. Automaton has 233 states and 257 transitions. Word has length 122 [2018-02-04 19:06:09,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:09,392 INFO L432 AbstractCegarLoop]: Abstraction has 233 states and 257 transitions. [2018-02-04 19:06:09,392 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 19:06:09,392 INFO L276 IsEmpty]: Start isEmpty. Operand 233 states and 257 transitions. [2018-02-04 19:06:09,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-02-04 19:06:09,393 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:09,393 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:09,393 INFO L371 AbstractCegarLoop]: === Iteration 37 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:09,393 INFO L82 PathProgramCache]: Analyzing trace with hash -1331978799, now seen corresponding path program 1 times [2018-02-04 19:06:09,393 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:09,394 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:09,394 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,394 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:09,394 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:09,414 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:09,463 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 973 trivial. 0 not checked. [2018-02-04 19:06:09,463 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:06:09,464 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 19:06:09,464 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 19:06:09,464 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 19:06:09,464 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 19:06:09,464 INFO L87 Difference]: Start difference. First operand 233 states and 257 transitions. Second operand 5 states. [2018-02-04 19:06:09,478 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:09,478 INFO L93 Difference]: Finished difference Result 237 states and 261 transitions. [2018-02-04 19:06:09,479 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 19:06:09,479 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 123 [2018-02-04 19:06:09,479 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:09,480 INFO L225 Difference]: With dead ends: 237 [2018-02-04 19:06:09,480 INFO L226 Difference]: Without dead ends: 237 [2018-02-04 19:06:09,480 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 19:06:09,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-02-04 19:06:09,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 237. [2018-02-04 19:06:09,483 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-02-04 19:06:09,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 261 transitions. [2018-02-04 19:06:09,484 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 261 transitions. Word has length 123 [2018-02-04 19:06:09,484 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:09,484 INFO L432 AbstractCegarLoop]: Abstraction has 237 states and 261 transitions. [2018-02-04 19:06:09,486 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 19:06:09,486 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 261 transitions. [2018-02-04 19:06:09,488 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-02-04 19:06:09,489 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:09,489 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:09,489 INFO L371 AbstractCegarLoop]: === Iteration 38 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:09,489 INFO L82 PathProgramCache]: Analyzing trace with hash -1775220838, now seen corresponding path program 1 times [2018-02-04 19:06:09,489 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:09,489 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:09,490 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,490 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:09,490 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:09,510 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:09,586 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 973 trivial. 0 not checked. [2018-02-04 19:06:09,586 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:06:09,586 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-02-04 19:06:09,586 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 19:06:09,586 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 19:06:09,586 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 19:06:09,586 INFO L87 Difference]: Start difference. First operand 237 states and 261 transitions. Second operand 8 states. [2018-02-04 19:06:09,803 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:09,803 INFO L93 Difference]: Finished difference Result 272 states and 300 transitions. [2018-02-04 19:06:09,803 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 19:06:09,803 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 125 [2018-02-04 19:06:09,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:09,804 INFO L225 Difference]: With dead ends: 272 [2018-02-04 19:06:09,804 INFO L226 Difference]: Without dead ends: 272 [2018-02-04 19:06:09,804 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 4 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-02-04 19:06:09,804 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 272 states. [2018-02-04 19:06:09,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 272 to 258. [2018-02-04 19:06:09,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 258 states. [2018-02-04 19:06:09,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 258 states to 258 states and 290 transitions. [2018-02-04 19:06:09,812 INFO L78 Accepts]: Start accepts. Automaton has 258 states and 290 transitions. Word has length 125 [2018-02-04 19:06:09,812 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:09,812 INFO L432 AbstractCegarLoop]: Abstraction has 258 states and 290 transitions. [2018-02-04 19:06:09,812 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 19:06:09,812 INFO L276 IsEmpty]: Start isEmpty. Operand 258 states and 290 transitions. [2018-02-04 19:06:09,813 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-02-04 19:06:09,813 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:09,813 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:09,813 INFO L371 AbstractCegarLoop]: === Iteration 39 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:09,813 INFO L82 PathProgramCache]: Analyzing trace with hash -1775220837, now seen corresponding path program 1 times [2018-02-04 19:06:09,813 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:09,813 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:09,814 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,814 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:09,814 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:09,838 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:09,839 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:10,060 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 8 refuted. 0 times theorem prover too weak. 965 trivial. 0 not checked. [2018-02-04 19:06:10,060 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:06:10,060 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:06:10,061 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:10,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:10,115 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:06:10,207 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 973 trivial. 0 not checked. [2018-02-04 19:06:10,207 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:06:10,207 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [15] total 22 [2018-02-04 19:06:10,207 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 19:06:10,207 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 19:06:10,208 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=52, Invalid=454, Unknown=0, NotChecked=0, Total=506 [2018-02-04 19:06:10,208 INFO L87 Difference]: Start difference. First operand 258 states and 290 transitions. Second operand 23 states. [2018-02-04 19:06:10,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:10,753 INFO L93 Difference]: Finished difference Result 284 states and 310 transitions. [2018-02-04 19:06:10,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 19:06:10,753 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 125 [2018-02-04 19:06:10,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:10,754 INFO L225 Difference]: With dead ends: 284 [2018-02-04 19:06:10,754 INFO L226 Difference]: Without dead ends: 284 [2018-02-04 19:06:10,754 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 118 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 115 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=109, Invalid=947, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 19:06:10,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 284 states. [2018-02-04 19:06:10,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 284 to 265. [2018-02-04 19:06:10,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 265 states. [2018-02-04 19:06:10,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 265 states to 265 states and 297 transitions. [2018-02-04 19:06:10,757 INFO L78 Accepts]: Start accepts. Automaton has 265 states and 297 transitions. Word has length 125 [2018-02-04 19:06:10,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:10,757 INFO L432 AbstractCegarLoop]: Abstraction has 265 states and 297 transitions. [2018-02-04 19:06:10,757 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 19:06:10,757 INFO L276 IsEmpty]: Start isEmpty. Operand 265 states and 297 transitions. [2018-02-04 19:06:10,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 139 [2018-02-04 19:06:10,758 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:10,758 INFO L351 BasicCegarLoop]: trace histogram [53, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:10,758 INFO L371 AbstractCegarLoop]: === Iteration 40 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:10,758 INFO L82 PathProgramCache]: Analyzing trace with hash 2097940321, now seen corresponding path program 1 times [2018-02-04 19:06:10,758 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:10,758 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:10,759 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:10,759 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:10,759 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:10,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:10,771 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:10,814 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 1638 trivial. 0 not checked. [2018-02-04 19:06:10,814 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 19:06:10,814 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 19:06:10,815 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 19:06:10,815 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 19:06:10,815 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 19:06:10,815 INFO L87 Difference]: Start difference. First operand 265 states and 297 transitions. Second operand 6 states. [2018-02-04 19:06:10,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:10,826 INFO L93 Difference]: Finished difference Result 256 states and 285 transitions. [2018-02-04 19:06:10,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 19:06:10,826 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 138 [2018-02-04 19:06:10,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:10,827 INFO L225 Difference]: With dead ends: 256 [2018-02-04 19:06:10,827 INFO L226 Difference]: Without dead ends: 256 [2018-02-04 19:06:10,827 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 19:06:10,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-02-04 19:06:10,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 256. [2018-02-04 19:06:10,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256 states. [2018-02-04 19:06:10,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 285 transitions. [2018-02-04 19:06:10,831 INFO L78 Accepts]: Start accepts. Automaton has 256 states and 285 transitions. Word has length 138 [2018-02-04 19:06:10,831 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:10,831 INFO L432 AbstractCegarLoop]: Abstraction has 256 states and 285 transitions. [2018-02-04 19:06:10,831 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 19:06:10,831 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 285 transitions. [2018-02-04 19:06:10,832 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-02-04 19:06:10,832 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:10,832 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:10,832 INFO L371 AbstractCegarLoop]: === Iteration 41 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:10,832 INFO L82 PathProgramCache]: Analyzing trace with hash -885209541, now seen corresponding path program 1 times [2018-02-04 19:06:10,832 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:10,833 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:10,833 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:10,833 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:10,833 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:10,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:10,900 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:10,909 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:06:10,909 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:06:10,909 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:06:10,910 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:11,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:11,138 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:06:11,186 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 19:06:11,187 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 19:06:11,187 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,188 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,190 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,191 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:19, output treesize:11 [2018-02-04 19:06:11,276 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int)) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_dev_set_drvdata_#in~dev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.base))) (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_dev_set_drvdata_#in~dev.offset|))) is different from true [2018-02-04 19:06:11,280 WARN L1033 $PredicateComparison]: unable to prove that (exists ((ldv_dev_set_drvdata_~data.base Int) (ldv_dev_set_drvdata_~dev.offset Int)) (and (<= ldv_dev_set_drvdata_~dev.offset |c_ldv_hid_set_drvdata_#in~hdev.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base| (store (select |c_old(#memory_$Pointer$.base)| |c_ldv_hid_set_drvdata_#in~hdev.base|) (+ ldv_dev_set_drvdata_~dev.offset 4) ldv_dev_set_drvdata_~data.base))))) is different from true [2018-02-04 19:06:11,330 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-02-04 19:06:11,332 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:06:11,333 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 29 [2018-02-04 19:06:11,333 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,337 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,341 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,341 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:28, output treesize:11 [2018-02-04 19:06:11,403 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 21 treesize of output 17 [2018-02-04 19:06:11,404 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 5 [2018-02-04 19:06:11,404 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,404 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,405 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:11,405 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:21, output treesize:5 [2018-02-04 19:06:11,448 INFO L134 CoverageAnalysis]: Checked inductivity of 973 backedges. 0 proven. 316 refuted. 0 times theorem prover too weak. 657 trivial. 0 not checked. [2018-02-04 19:06:11,448 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-02-04 19:06:11,448 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27] total 27 [2018-02-04 19:06:11,448 INFO L409 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-02-04 19:06:11,449 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-02-04 19:06:11,449 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=588, Unknown=10, NotChecked=98, Total=756 [2018-02-04 19:06:11,449 INFO L87 Difference]: Start difference. First operand 256 states and 285 transitions. Second operand 28 states. [2018-02-04 19:06:12,467 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 19:06:12,468 INFO L93 Difference]: Finished difference Result 265 states and 288 transitions. [2018-02-04 19:06:12,468 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-02-04 19:06:12,468 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 127 [2018-02-04 19:06:12,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 19:06:12,469 INFO L225 Difference]: With dead ends: 265 [2018-02-04 19:06:12,469 INFO L226 Difference]: Without dead ends: 265 [2018-02-04 19:06:12,469 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 137 GetRequests, 100 SyntacticMatches, 0 SemanticMatches, 37 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 101 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=127, Invalid=1183, Unknown=30, NotChecked=142, Total=1482 [2018-02-04 19:06:12,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-02-04 19:06:12,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 256. [2018-02-04 19:06:12,471 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 256 states. [2018-02-04 19:06:12,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 256 states to 256 states and 284 transitions. [2018-02-04 19:06:12,472 INFO L78 Accepts]: Start accepts. Automaton has 256 states and 284 transitions. Word has length 127 [2018-02-04 19:06:12,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 19:06:12,472 INFO L432 AbstractCegarLoop]: Abstraction has 256 states and 284 transitions. [2018-02-04 19:06:12,472 INFO L433 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-02-04 19:06:12,472 INFO L276 IsEmpty]: Start isEmpty. Operand 256 states and 284 transitions. [2018-02-04 19:06:12,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 128 [2018-02-04 19:06:12,472 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 19:06:12,473 INFO L351 BasicCegarLoop]: trace histogram [41, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 19:06:12,473 INFO L371 AbstractCegarLoop]: === Iteration 42 === [ldv_dev_set_drvdataErr0RequiresViolation, ldv_dev_set_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr1RequiresViolation, ldv_dev_get_drvdataErr0RequiresViolation, mainErr0EnsuresViolation, entry_pointErr5RequiresViolation, entry_pointErr14RequiresViolation, entry_pointErr0RequiresViolation, entry_pointErr1RequiresViolation, entry_pointErr13RequiresViolation, entry_pointErr6RequiresViolation, entry_pointErr8RequiresViolation, entry_pointErr11RequiresViolation, entry_pointErr3RequiresViolation, entry_pointErr16RequiresViolation, entry_pointErr7RequiresViolation, entry_pointErr12RequiresViolation, entry_pointErr15RequiresViolation, entry_pointErr17RequiresViolation, entry_pointErr4RequiresViolation, entry_pointErr2RequiresViolation, entry_pointErr9RequiresViolation, entry_pointErr10RequiresViolation, ldv_arvo_init_arvo_device_structErr0RequiresViolation, ldv_arvo_init_arvo_device_structErr2RequiresViolation, ldv_arvo_init_arvo_device_structErr4RequiresViolation, ldv_arvo_init_arvo_device_structErr5RequiresViolation, ldv_arvo_init_arvo_device_structErr1RequiresViolation, ldv_arvo_init_arvo_device_structErr3RequiresViolation, lvd_arvo_remove_specialsErr4RequiresViolation, lvd_arvo_remove_specialsErr1RequiresViolation, lvd_arvo_remove_specialsErr0RequiresViolation, lvd_arvo_remove_specialsErr6RequiresViolation, lvd_arvo_remove_specialsErr7RequiresViolation, lvd_arvo_remove_specialsErr5RequiresViolation, lvd_arvo_remove_specialsErr2RequiresViolation, lvd_arvo_remove_specialsErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr3RequiresViolation, ldv_arvo_init_specials_unsafeErr1RequiresViolation, ldv_arvo_init_specials_unsafeErr5RequiresViolation, ldv_arvo_init_specials_unsafeErr4RequiresViolation, ldv_arvo_init_specials_unsafeErr2RequiresViolation, ldv_arvo_init_specials_unsafeErr0RequiresViolation, ldv_arvo_init_specials_unsafeErr6RequiresViolation, ldv_arvo_init_specials_unsafeErr7RequiresViolation]=== [2018-02-04 19:06:12,473 INFO L82 PathProgramCache]: Analyzing trace with hash -885209540, now seen corresponding path program 1 times [2018-02-04 19:06:12,473 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 19:06:12,473 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 19:06:12,474 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:12,474 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:12,474 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 19:06:12,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:12,533 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 19:06:12,609 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 19:06:12,609 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 19:06:12,609 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 19:06:12,610 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 19:06:12,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 19:06:12,832 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 19:06:12,845 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-02-04 19:06:12,846 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,849 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,849 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-02-04 19:06:12,899 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 19:06:12,901 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 19:06:12,901 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,903 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,913 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-02-04 19:06:12,915 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-02-04 19:06:12,915 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,916 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,923 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:12,923 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:41, output treesize:33 [2018-02-04 19:06:12,944 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 22 [2018-02-04 19:06:12,947 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 23 [2018-02-04 19:06:12,948 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,952 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,965 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 22 [2018-02-04 19:06:12,969 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 23 [2018-02-04 19:06:12,969 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,973 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:12,983 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:12,983 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:63, output treesize:55 [2018-02-04 19:06:13,010 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 31 [2018-02-04 19:06:13,016 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 34 [2018-02-04 19:06:13,016 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,023 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,041 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 31 [2018-02-04 19:06:13,047 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 34 [2018-02-04 19:06:13,047 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,053 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,066 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:13,067 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:85, output treesize:77 [2018-02-04 19:06:13,099 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 40 [2018-02-04 19:06:13,106 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 45 [2018-02-04 19:06:13,106 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,113 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,131 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 40 [2018-02-04 19:06:13,149 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 45 [2018-02-04 19:06:13,150 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,155 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,168 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:13,168 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:107, output treesize:99 [2018-02-04 19:06:13,199 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 49 [2018-02-04 19:06:13,209 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 56 [2018-02-04 19:06:13,209 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,217 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,239 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 60 treesize of output 49 [2018-02-04 19:06:13,249 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 56 [2018-02-04 19:06:13,249 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,256 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,271 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:13,271 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 3 variables, input treesize:129, output treesize:121 [2018-02-04 19:06:13,309 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-02-04 19:06:13,329 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 65 [2018-02-04 19:06:13,329 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,346 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,372 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 56 [2018-02-04 19:06:13,383 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 56 treesize of output 65 [2018-02-04 19:06:13,383 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,389 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,406 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:13,406 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 4 variables, input treesize:152, output treesize:144 [2018-02-04 19:06:13,452 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 63 [2018-02-04 19:06:13,484 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 74 [2018-02-04 19:06:13,485 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,497 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,533 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 63 [2018-02-04 19:06:13,558 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 74 [2018-02-04 19:06:13,559 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,567 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:13,591 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:13,591 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 5 variables, input treesize:175, output treesize:167 [2018-02-04 19:06:13,989 WARN L143 SmtUtils]: Spent 362ms on a formula simplification that was a NOOP. DAG size: 72 [2018-02-04 19:06:13,995 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 70 [2018-02-04 19:06:14,041 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 0 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 70 treesize of output 83 [2018-02-04 19:06:14,042 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:14,057 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:14,105 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 87 treesize of output 70 [2018-02-04 19:06:14,128 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 0 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 70 treesize of output 83 [2018-02-04 19:06:14,129 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:14,138 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 19:06:14,163 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-2 vars, End of recursive call: 4 dim-0 vars, and 1 xjuncts. [2018-02-04 19:06:14,163 INFO L202 ElimStorePlain]: Needed 5 recursive calls to eliminate 6 variables, input treesize:193, output treesize:185 [2018-02-04 19:06:17,407 WARN L143 SmtUtils]: Spent 789ms on a formula simplification that was a NOOP. DAG size: 77 [2018-02-04 19:06:17,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 36 [2018-02-04 19:06:17,686 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:17,704 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 33 [2018-02-04 19:06:17,704 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:17,720 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 19:06:17,721 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:72, output treesize:70 [2018-02-04 19:06:17,773 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:06:17,774 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 30 treesize of output 31 [2018-02-04 19:06:17,774 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:17,788 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 19:06:17,789 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 32 treesize of output 33 [2018-02-04 19:06:17,789 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 19:06:17,800 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 2 dim-1 vars, End of recursive call: 4 dim-0 vars, and 2 xjuncts. [2018-02-04 19:06:17,801 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 6 variables, input treesize:63, output treesize:51 [2018-02-04 19:06:17,855 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int)) (let ((.cse0 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0)))))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse1 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse1) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse1))))) (and (exists ((v_prenex_98 Int)) (let ((.cse2 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse2 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse2 0)) |c_#memory_$Pointer$.offset|)))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse3 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse3 2147483647) (= .cse3 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:17,874 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_98 Int)) (let ((.cse0 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse2 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse2 2147483647) (= .cse2 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (v_prenex_99 Int)) (let ((.cse3 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse4 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse3 0) .cse4 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse3 0) .cse4 0)))))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse5 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse5) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse5)))))) is different from true [2018-02-04 19:06:18,360 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (v_prenex_107 Int)) (let ((.cse0 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse1 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0)) |c_#memory_$Pointer$.offset|)))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse5 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse5) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse5))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_102 Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_108 Int)) (let ((.cse6 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse7 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse8 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse10 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse11 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse11 2147483647) (= .cse11 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:18,387 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse0 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse0) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse0)))) (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int)) (let ((.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse5 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse6 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0)) |c_#memory_$Pointer$.offset|))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_112 Int) (v_prenex_102 Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_108 Int)) (let ((.cse7 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse10 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse11 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse12 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0)) |c_#memory_$Pointer$.offset|)))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse13 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse13 2147483647) (= .cse13 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:19,235 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse0 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse0) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse0)))) (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int)) (let ((.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse5 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse6 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse7 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0))))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_102 Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_118 Int) (v_prenex_108 Int)) (let ((.cse9 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse10 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse11 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse12 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse13 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse14 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse15 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse16 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0)) |c_#memory_$Pointer$.offset|)))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse17 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse17 2147483647) (= .cse17 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:19,283 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse0 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse0) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse0)))) (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (v_prenex_121 Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int)) (let ((.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse5 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse6 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse7 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0))) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0))))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_118 Int) (v_prenex_108 Int)) (let ((.cse10 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse11 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse12 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse13 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse14 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse15 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse16 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse17 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse18 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0)) |c_#memory_$Pointer$.offset|)))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse19 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse19 2147483647) (= .cse19 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:19,328 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_123 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_118 Int) (v_prenex_108 Int)) (let ((.cse0 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse5 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse6 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse7 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ v_prenex_123 |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0)) |c_#memory_$Pointer$.offset|)))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse10 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse10 2147483647) (= .cse10 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (v_prenex_121 Int) (|v_#Ultimate.meminit_#t~loopctr33_195| Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int)) (let ((.cse11 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse12 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse13 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse14 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse15 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse16 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse17 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse18 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse19 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|)) (.cse20 (+ |v_#Ultimate.meminit_#t~loopctr33_195| |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0)))))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse21 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse21) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse21)))))) is different from true [2018-02-04 19:06:19,416 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_196| Int) (|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_123 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_118 Int) (v_prenex_108 Int)) (let ((.cse0 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse5 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse6 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse7 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ v_prenex_123 |c_#Ultimate.meminit_#ptr.offset|)) (.cse10 (+ |v_#Ultimate.meminit_#t~loopctr33_196| |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse11 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse11 2147483647) (= .cse11 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (v_prenex_126 Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (v_prenex_121 Int) (|v_#Ultimate.meminit_#t~loopctr33_195| Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int)) (let ((.cse12 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse13 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse14 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse15 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse16 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse17 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse18 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse19 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse20 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|)) (.cse21 (+ |v_#Ultimate.meminit_#t~loopctr33_195| |c_#Ultimate.meminit_#ptr.offset|)) (.cse22 (+ v_prenex_126 |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0)))))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse23 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse23) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse23)))))) is different from true [2018-02-04 19:06:19,496 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_196| Int) (|v_#Ultimate.meminit_#t~loopctr33_197| Int) (|v_#Ultimate.meminit_#t~loopctr33_187| Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_123 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (v_prenex_118 Int) (v_prenex_108 Int)) (let ((.cse0 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse5 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse6 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse7 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ v_prenex_123 |c_#Ultimate.meminit_#ptr.offset|)) (.cse10 (+ |v_#Ultimate.meminit_#t~loopctr33_196| |c_#Ultimate.meminit_#ptr.offset|)) (.cse11 (+ |v_#Ultimate.meminit_#t~loopctr33_197| |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0))) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse12 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse12 2147483647) (= .cse12 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (v_prenex_126 Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (v_prenex_121 Int) (|v_#Ultimate.meminit_#t~loopctr33_195| Int) (v_prenex_130 Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int)) (let ((.cse13 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse14 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse15 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse16 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse17 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse18 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse19 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse20 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse21 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|)) (.cse22 (+ |v_#Ultimate.meminit_#t~loopctr33_195| |c_#Ultimate.meminit_#ptr.offset|)) (.cse23 (+ v_prenex_126 |c_#Ultimate.meminit_#ptr.offset|)) (.cse24 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_130))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0))) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse13 0) .cse14 0) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0)) |c_#memory_$Pointer$.offset|)))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse25 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse25) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse25)))))) is different from true [2018-02-04 19:06:24,080 WARN L143 SmtUtils]: Spent 295ms on a formula simplification that was a NOOP. DAG size: 154 [2018-02-04 19:06:24,181 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (|v_#Ultimate.meminit_#t~loopctr33_195| Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int) (v_prenex_126 Int) (v_prenex_135 Int) (v_prenex_121 Int) (v_prenex_132 Int) (v_prenex_130 Int)) (let ((.cse0 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse1 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse5 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse6 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse7 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse8 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ |v_#Ultimate.meminit_#t~loopctr33_195| |c_#Ultimate.meminit_#ptr.offset|)) (.cse10 (+ v_prenex_126 |c_#Ultimate.meminit_#ptr.offset|)) (.cse11 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_130)) (.cse12 (+ v_prenex_132 |c_#Ultimate.meminit_#ptr.offset|)) (.cse13 (+ v_prenex_135 |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0))) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0)))))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse14 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse14) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse14))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_196| Int) (|v_#Ultimate.meminit_#t~loopctr33_197| Int) (|v_#Ultimate.meminit_#t~loopctr33_187| Int) (|v_#Ultimate.meminit_#t~loopctr33_198| Int) (|v_#Ultimate.meminit_#t~loopctr33_199| Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (v_prenex_118 Int) (v_prenex_108 Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_123 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int)) (let ((.cse15 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse16 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse17 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse18 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse19 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse20 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse21 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse22 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse23 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|)) (.cse24 (+ v_prenex_123 |c_#Ultimate.meminit_#ptr.offset|)) (.cse25 (+ |v_#Ultimate.meminit_#t~loopctr33_196| |c_#Ultimate.meminit_#ptr.offset|)) (.cse26 (+ |v_#Ultimate.meminit_#t~loopctr33_197| |c_#Ultimate.meminit_#ptr.offset|)) (.cse27 (+ |v_#Ultimate.meminit_#t~loopctr33_198| |c_#Ultimate.meminit_#ptr.offset|)) (.cse28 (+ |v_#Ultimate.meminit_#t~loopctr33_199| |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0) .cse25 0) .cse26 0) .cse27 0) .cse28 0))) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse15 0) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0) .cse25 0) .cse26 0) .cse27 0) .cse28 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse29 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse29 2147483647) (= .cse29 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:24,363 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_196| Int) (|v_#Ultimate.meminit_#t~loopctr33_197| Int) (|v_#Ultimate.meminit_#t~loopctr33_187| Int) (|v_#Ultimate.meminit_#t~loopctr33_198| Int) (|v_#Ultimate.meminit_#t~loopctr33_199| Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (v_prenex_118 Int) (v_prenex_108 Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_123 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (|v_#Ultimate.meminit_#t~loopctr33_200| Int)) (let ((.cse0 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse1 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse5 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse6 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse7 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse8 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ v_prenex_123 |c_#Ultimate.meminit_#ptr.offset|)) (.cse10 (+ |v_#Ultimate.meminit_#t~loopctr33_196| |c_#Ultimate.meminit_#ptr.offset|)) (.cse11 (+ |v_#Ultimate.meminit_#t~loopctr33_197| |c_#Ultimate.meminit_#ptr.offset|)) (.cse12 (+ |v_#Ultimate.meminit_#t~loopctr33_198| |c_#Ultimate.meminit_#ptr.offset|)) (.cse13 (+ |v_#Ultimate.meminit_#t~loopctr33_199| |c_#Ultimate.meminit_#ptr.offset|)) (.cse14 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_200|))) (and (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0)) |c_#memory_$Pointer$.offset|) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse15 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse15 2147483647) (= .cse15 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (|v_#Ultimate.meminit_#t~loopctr33_195| Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int) (v_prenex_139 Int) (v_prenex_126 Int) (v_prenex_135 Int) (v_prenex_121 Int) (v_prenex_132 Int) (v_prenex_130 Int)) (let ((.cse16 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse17 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse18 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse19 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse20 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse21 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse22 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse23 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse24 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|)) (.cse25 (+ |v_#Ultimate.meminit_#t~loopctr33_195| |c_#Ultimate.meminit_#ptr.offset|)) (.cse26 (+ v_prenex_126 |c_#Ultimate.meminit_#ptr.offset|)) (.cse27 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_130)) (.cse28 (+ v_prenex_132 |c_#Ultimate.meminit_#ptr.offset|)) (.cse29 (+ v_prenex_135 |c_#Ultimate.meminit_#ptr.offset|)) (.cse30 (+ v_prenex_139 |c_#Ultimate.meminit_#ptr.offset|))) (and (= (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0) .cse25 0) .cse26 0) .cse27 0) .cse28 0) .cse29 0) .cse30 0)) |c_#memory_$Pointer$.base|) (= (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse16 0) .cse17 0) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0) .cse25 0) .cse26 0) .cse27 0) .cse28 0) .cse29 0) .cse30 0)) |c_#memory_$Pointer$.offset|)))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse31 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse31) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse31)))))) is different from true [2018-02-04 19:06:32,836 WARN L143 SmtUtils]: Spent 629ms on a formula simplification that was a NOOP. DAG size: 178 [2018-02-04 19:06:33,284 WARN L1033 $PredicateComparison]: unable to prove that (or (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_186| Int) (|v_#Ultimate.meminit_#t~loopctr33_188| Int) (|v_#Ultimate.meminit_#t~loopctr33_192| Int) (v_prenex_99 Int) (|v_#Ultimate.meminit_#t~loopctr33_193| Int) (|v_#Ultimate.meminit_#t~loopctr33_195| Int) (|v_#Ultimate.meminit_#t~loopctr33_190| Int) (|v_#Ultimate.meminit_#t~loopctr33_191| Int) (v_prenex_107 Int) (v_prenex_139 Int) (v_prenex_126 Int) (v_prenex_135 Int) (v_prenex_121 Int) (v_prenex_132 Int) (v_prenex_130 Int) (v_prenex_142 Int) (|v_#Ultimate.meminit_#t~loopctr33_202| Int)) (let ((.cse0 (+ |v_#Ultimate.meminit_#t~loopctr33_186| |c_#Ultimate.meminit_#ptr.offset|)) (.cse1 (+ v_prenex_99 |c_#Ultimate.meminit_#ptr.offset|)) (.cse2 (+ |v_#Ultimate.meminit_#t~loopctr33_188| |c_#Ultimate.meminit_#ptr.offset|)) (.cse3 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_107)) (.cse4 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_190|)) (.cse5 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_191|)) (.cse6 (+ |v_#Ultimate.meminit_#t~loopctr33_192| |c_#Ultimate.meminit_#ptr.offset|)) (.cse7 (+ |v_#Ultimate.meminit_#t~loopctr33_193| |c_#Ultimate.meminit_#ptr.offset|)) (.cse8 (+ v_prenex_121 |c_#Ultimate.meminit_#ptr.offset|)) (.cse9 (+ |v_#Ultimate.meminit_#t~loopctr33_195| |c_#Ultimate.meminit_#ptr.offset|)) (.cse10 (+ v_prenex_126 |c_#Ultimate.meminit_#ptr.offset|)) (.cse11 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_130)) (.cse12 (+ v_prenex_132 |c_#Ultimate.meminit_#ptr.offset|)) (.cse13 (+ v_prenex_135 |c_#Ultimate.meminit_#ptr.offset|)) (.cse14 (+ v_prenex_139 |c_#Ultimate.meminit_#ptr.offset|)) (.cse15 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_142)) (.cse16 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_202|))) (and (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0))) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse0 0) .cse1 0) .cse2 0) .cse3 0) .cse4 0) .cse5 0) .cse6 0) .cse7 0) .cse8 0) .cse9 0) .cse10 0) .cse11 0) .cse12 0) .cse13 0) .cse14 0) .cse15 0) .cse16 0)))))) (exists ((v_prenex_96 Int) (v_prenex_95 Int)) (let ((.cse17 (mod v_prenex_96 4294967296))) (and (< 2147483647 .cse17) (= 1 (select |c_#valid| v_prenex_95)) (= (+ (select |c_#length| v_prenex_95) 4294967296) .cse17))))) (and (exists ((|v_#Ultimate.meminit_#t~loopctr33_196| Int) (|v_#Ultimate.meminit_#t~loopctr33_197| Int) (|v_#Ultimate.meminit_#t~loopctr33_187| Int) (|v_#Ultimate.meminit_#t~loopctr33_198| Int) (|v_#Ultimate.meminit_#t~loopctr33_199| Int) (|v_#Ultimate.meminit_#t~loopctr33_194| Int) (v_prenex_98 Int) (v_prenex_118 Int) (v_prenex_108 Int) (v_prenex_114 Int) (v_prenex_112 Int) (v_prenex_123 Int) (v_prenex_145 Int) (v_prenex_102 Int) (|v_#Ultimate.meminit_#t~loopctr33_189| Int) (|v_#Ultimate.meminit_#t~loopctr33_200| Int) (|v_#Ultimate.meminit_#t~loopctr33_201| Int)) (let ((.cse18 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_98)) (.cse19 (+ |v_#Ultimate.meminit_#t~loopctr33_187| |c_#Ultimate.meminit_#ptr.offset|)) (.cse20 (+ v_prenex_102 |c_#Ultimate.meminit_#ptr.offset|)) (.cse21 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_189|)) (.cse22 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_108)) (.cse23 (+ v_prenex_112 |c_#Ultimate.meminit_#ptr.offset|)) (.cse24 (+ v_prenex_114 |c_#Ultimate.meminit_#ptr.offset|)) (.cse25 (+ |c_#Ultimate.meminit_#ptr.offset| v_prenex_118)) (.cse26 (+ |v_#Ultimate.meminit_#t~loopctr33_194| |c_#Ultimate.meminit_#ptr.offset|)) (.cse27 (+ v_prenex_123 |c_#Ultimate.meminit_#ptr.offset|)) (.cse28 (+ |v_#Ultimate.meminit_#t~loopctr33_196| |c_#Ultimate.meminit_#ptr.offset|)) (.cse29 (+ |v_#Ultimate.meminit_#t~loopctr33_197| |c_#Ultimate.meminit_#ptr.offset|)) (.cse30 (+ |v_#Ultimate.meminit_#t~loopctr33_198| |c_#Ultimate.meminit_#ptr.offset|)) (.cse31 (+ |v_#Ultimate.meminit_#t~loopctr33_199| |c_#Ultimate.meminit_#ptr.offset|)) (.cse32 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_200|)) (.cse33 (+ |c_#Ultimate.meminit_#ptr.offset| |v_#Ultimate.meminit_#t~loopctr33_201|)) (.cse34 (+ v_prenex_145 |c_#Ultimate.meminit_#ptr.offset|))) (and (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_#Ultimate.meminit_#ptr.base|) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0) .cse25 0) .cse26 0) .cse27 0) .cse28 0) .cse29 0) .cse30 0) .cse31 0) .cse32 0) .cse33 0) .cse34 0))) (= |c_#memory_$Pointer$.base| (store |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base| (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (store (select |c_old(#memory_$Pointer$.base)| |c_#Ultimate.meminit_#ptr.base|) .cse18 0) .cse19 0) .cse20 0) .cse21 0) .cse22 0) .cse23 0) .cse24 0) .cse25 0) .cse26 0) .cse27 0) .cse28 0) .cse29 0) .cse30 0) .cse31 0) .cse32 0) .cse33 0) .cse34 0)))))) (exists ((|v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14| Int) (|v_ldv_zalloc_#in~size_BEFORE_CALL_23| Int)) (let ((.cse35 (mod |v_ldv_zalloc_#in~size_BEFORE_CALL_23| 4294967296))) (and (= 1 (select |c_#valid| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|)) (<= .cse35 2147483647) (= .cse35 (select |c_#length| |v_ldv_zalloc_#t~malloc1.base_BEFORE_CALL_14|))))))) is different from true [2018-02-04 19:06:50,035 WARN L143 SmtUtils]: Spent 724ms on a formula simplification that was a NOOP. DAG size: 194 Received shutdown request... [2018-02-04 19:07:10,409 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-02-04 19:07:10,409 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 19:07:10,413 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 19:07:10,413 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 07:07:10 BoogieIcfgContainer [2018-02-04 19:07:10,413 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 19:07:10,414 INFO L168 Benchmark]: Toolchain (without parser) took 197841.27 ms. Allocated memory was 403.2 MB in the beginning and 1.2 GB in the end (delta: 842.0 MB). Free memory was 360.1 MB in the beginning and 1.0 GB in the end (delta: -676.8 MB). Peak memory consumption was 165.2 MB. Max. memory is 5.3 GB. [2018-02-04 19:07:10,415 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 403.2 MB. Free memory is still 366.7 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 19:07:10,415 INFO L168 Benchmark]: CACSL2BoogieTranslator took 166.96 ms. Allocated memory is still 403.2 MB. Free memory was 360.1 MB in the beginning and 345.2 MB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 5.3 GB. [2018-02-04 19:07:10,415 INFO L168 Benchmark]: Boogie Preprocessor took 29.49 ms. Allocated memory is still 403.2 MB. Free memory was 345.2 MB in the beginning and 343.9 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-02-04 19:07:10,415 INFO L168 Benchmark]: RCFGBuilder took 384.58 ms. Allocated memory is still 403.2 MB. Free memory was 342.6 MB in the beginning and 301.8 MB in the end (delta: 40.8 MB). Peak memory consumption was 40.8 MB. Max. memory is 5.3 GB. [2018-02-04 19:07:10,415 INFO L168 Benchmark]: TraceAbstraction took 197256.99 ms. Allocated memory was 403.2 MB in the beginning and 1.2 GB in the end (delta: 842.0 MB). Free memory was 301.8 MB in the beginning and 1.0 GB in the end (delta: -735.0 MB). Peak memory consumption was 107.0 MB. Max. memory is 5.3 GB. [2018-02-04 19:07:10,416 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 403.2 MB. Free memory is still 366.7 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 166.96 ms. Allocated memory is still 403.2 MB. Free memory was 360.1 MB in the beginning and 345.2 MB in the end (delta: 14.8 MB). Peak memory consumption was 14.8 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 29.49 ms. Allocated memory is still 403.2 MB. Free memory was 345.2 MB in the beginning and 343.9 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 384.58 ms. Allocated memory is still 403.2 MB. Free memory was 342.6 MB in the beginning and 301.8 MB in the end (delta: 40.8 MB). Peak memory consumption was 40.8 MB. Max. memory is 5.3 GB. * TraceAbstraction took 197256.99 ms. Allocated memory was 403.2 MB in the beginning and 1.2 GB in the end (delta: 842.0 MB). Free memory was 301.8 MB in the beginning and 1.0 GB in the end (delta: -735.0 MB). Peak memory consumption was 107.0 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1198). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1193). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1533]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1533). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1513). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1526). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1528). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1516). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1514). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1517). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1524). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1456). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1454). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1455). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1484). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1490). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1486). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1464). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1463). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1479). Cancelled while BasicCegarLoop was analyzing trace of length 128 with TraceHistMax 41, while TraceCheckSpWp was constructing forward predicates, while PredicateUnifier was unifying predicates, while SimplifyDDAWithTimeout was simplifying term of DAG size 202. - StatisticsResult: Ultimate Automizer benchmark data CFG has 16 procedures, 165 locations, 45 error locations. TIMEOUT Result, 197.2s OverallTime, 42 OverallIterations, 53 TraceHistogramMax, 79.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 5714 SDtfs, 3851 SDslu, 78397 SDs, 0 SdLazy, 35030 SolverSat, 1316 SolverUnsat, 224 SolverUnknown, 0 SolverNotchecked, 26.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 3307 GetRequests, 2097 SyntacticMatches, 31 SemanticMatches, 1179 ConstructedPredicates, 5 IntricatePredicates, 0 DeprecatedPredicates, 7858 ImplicationChecksByTransitivity, 102.6s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=265occurred in iteration=39, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 41 MinimizatonAttempts, 573 StatesRemovedByMinimization, 24 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 1.9s SatisfiabilityAnalysisTime, 56.5s InterpolantComputationTime, 5983 NumberOfCodeBlocks, 5694 NumberOfCodeBlocksAsserted, 86 NumberOfCheckSat, 5121 ConstructedInterpolants, 329 QuantifiedInterpolants, 2040412 SizeOfPredicates, 244 NumberOfNonLiveVariables, 11423 ConjunctsInSsa, 991 ConjunctsInUnsatCore, 60 InterpolantComputations, 16 PerfectInterpolantSequences, 31723/37407 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_false-valid-memtrack.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_19-07-10-422.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test15_false-valid-memtrack.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_19-07-10-422.csv Completed graceful shutdown