java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_5_false-valid-deref.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-c17473d-m [2018-02-04 18:55:03,074 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-02-04 18:55:03,075 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-02-04 18:55:03,086 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-02-04 18:55:03,086 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-02-04 18:55:03,087 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-02-04 18:55:03,087 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-02-04 18:55:03,088 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-02-04 18:55:03,090 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-02-04 18:55:03,091 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-02-04 18:55:03,091 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-02-04 18:55:03,092 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-02-04 18:55:03,092 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-02-04 18:55:03,093 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-02-04 18:55:03,094 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-02-04 18:55:03,096 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-02-04 18:55:03,097 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-02-04 18:55:03,099 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-02-04 18:55:03,100 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-02-04 18:55:03,101 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-02-04 18:55:03,102 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-02-04 18:55:03,103 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-02-04 18:55:03,103 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-02-04 18:55:03,104 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-02-04 18:55:03,104 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-02-04 18:55:03,105 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-02-04 18:55:03,106 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-02-04 18:55:03,106 INFO L177 SettingsManager]: PEA to Boogie provides no preferences, ignoring... [2018-02-04 18:55:03,106 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-02-04 18:55:03,106 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-02-04 18:55:03,107 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-02-04 18:55:03,107 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-02-04 18:55:03,116 INFO L110 SettingsManager]: Loading preferences was successful [2018-02-04 18:55:03,117 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-02-04 18:55:03,118 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-02-04 18:55:03,118 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-02-04 18:55:03,118 INFO L133 SettingsManager]: * Use SBE=true [2018-02-04 18:55:03,118 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-02-04 18:55:03,119 INFO L133 SettingsManager]: * sizeof long=4 [2018-02-04 18:55:03,119 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-02-04 18:55:03,119 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-02-04 18:55:03,119 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-02-04 18:55:03,119 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-02-04 18:55:03,119 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-02-04 18:55:03,120 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-02-04 18:55:03,120 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-02-04 18:55:03,120 INFO L133 SettingsManager]: * sizeof long double=12 [2018-02-04 18:55:03,120 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-02-04 18:55:03,120 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-02-04 18:55:03,120 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-02-04 18:55:03,121 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-02-04 18:55:03,121 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 18:55:03,121 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-02-04 18:55:03,121 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-02-04 18:55:03,121 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-02-04 18:55:03,121 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL [2018-02-04 18:55:03,150 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-02-04 18:55:03,161 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully initialized [2018-02-04 18:55:03,164 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-02-04 18:55:03,165 INFO L271 PluginConnector]: Initializing CDTParser... [2018-02-04 18:55:03,165 INFO L276 PluginConnector]: CDTParser initialized [2018-02-04 18:55:03,166 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/memleaks_test22_5_false-valid-deref.i [2018-02-04 18:55:03,323 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-02-04 18:55:03,324 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-02-04 18:55:03,325 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-02-04 18:55:03,325 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-02-04 18:55:03,330 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-02-04 18:55:03,331 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,334 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@ef0a5f5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03, skipping insertion in model container [2018-02-04 18:55:03,334 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,347 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 18:55:03,383 INFO L153 Dispatcher]: Using SV-COMP mode [2018-02-04 18:55:03,469 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 18:55:03,485 INFO L450 PostProcessor]: Settings: Checked method=main [2018-02-04 18:55:03,492 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03 WrapperNode [2018-02-04 18:55:03,493 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-02-04 18:55:03,493 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-02-04 18:55:03,493 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-02-04 18:55:03,493 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-02-04 18:55:03,505 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,506 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,515 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,515 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,521 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,524 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,525 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... [2018-02-04 18:55:03,527 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-02-04 18:55:03,528 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-02-04 18:55:03,528 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-02-04 18:55:03,528 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-02-04 18:55:03,529 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-02-04 18:55:03,561 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ##fun~$Pointer$~TO~VOID [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_malloc [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure LDV_INIT_LIST_HEAD [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_atomic_sub_return [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_sub [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_init [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kref_put [2018-02-04 18:55:03,562 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_cleanup [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_release [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_put [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init_internal [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_init [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure ldv_kobject_create [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure f_22_put [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure entry_point [2018-02-04 18:55:03,563 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-02-04 18:55:03,563 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-02-04 18:55:03,563 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-02-04 18:55:03,563 INFO L128 BoogieDeclarations]: Found specification of procedure write~$Pointer$ [2018-02-04 18:55:03,563 INFO L128 BoogieDeclarations]: Found specification of procedure read~$Pointer$ [2018-02-04 18:55:03,563 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.free [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.C_memset [2018-02-04 18:55:03,564 INFO L136 BoogieDeclarations]: Found implementation of procedure #Ultimate.C_memset [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure memset [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_malloc [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure LDV_INIT_LIST_HEAD [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_atomic_sub_return [2018-02-04 18:55:03,564 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_sub [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ##fun~$Pointer$~TO~VOID [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_init [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kref_put [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_cleanup [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_release [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_put [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init_internal [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_init [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ldv_kobject_create [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure f_22_put [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure entry_point [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-02-04 18:55:03,565 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-02-04 18:55:03,727 WARN L455 $ProcedureCfgBuilder]: Label in the middle of a codeblock. [2018-02-04 18:55:03,855 INFO L257 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-02-04 18:55:03,855 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 06:55:03 BoogieIcfgContainer [2018-02-04 18:55:03,855 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-02-04 18:55:03,856 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-02-04 18:55:03,856 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-02-04 18:55:03,858 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-02-04 18:55:03,858 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 04.02 06:55:03" (1/3) ... [2018-02-04 18:55:03,859 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3b6ea4d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 06:55:03, skipping insertion in model container [2018-02-04 18:55:03,859 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 04.02 06:55:03" (2/3) ... [2018-02-04 18:55:03,859 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3b6ea4d7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 04.02 06:55:03, skipping insertion in model container [2018-02-04 18:55:03,859 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 04.02 06:55:03" (3/3) ... [2018-02-04 18:55:03,860 INFO L107 eAbstractionObserver]: Analyzing ICFG memleaks_test22_5_false-valid-deref.i [2018-02-04 18:55:03,866 INFO L128 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-02-04 18:55:03,871 INFO L140 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-02-04 18:55:03,893 INFO L322 AbstractCegarLoop]: Interprodecural is true [2018-02-04 18:55:03,894 INFO L323 AbstractCegarLoop]: Hoare is false [2018-02-04 18:55:03,894 INFO L324 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-02-04 18:55:03,894 INFO L325 AbstractCegarLoop]: Backedges is TWOTRACK [2018-02-04 18:55:03,894 INFO L326 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-02-04 18:55:03,894 INFO L327 AbstractCegarLoop]: Difference is false [2018-02-04 18:55:03,894 INFO L328 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-02-04 18:55:03,894 INFO L333 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-02-04 18:55:03,895 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-02-04 18:55:03,904 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states. [2018-02-04 18:55:03,912 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-02-04 18:55:03,912 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:03,913 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:03,913 INFO L371 AbstractCegarLoop]: === Iteration 1 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:03,916 INFO L82 PathProgramCache]: Analyzing trace with hash 1211515492, now seen corresponding path program 1 times [2018-02-04 18:55:03,918 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:03,918 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:03,952 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:03,952 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:03,952 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:03,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:03,991 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:04,124 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:04,126 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:04,126 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 18:55:04,127 INFO L409 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-02-04 18:55:04,135 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-02-04 18:55:04,135 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 18:55:04,137 INFO L87 Difference]: Start difference. First operand 123 states. Second operand 5 states. [2018-02-04 18:55:04,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:04,188 INFO L93 Difference]: Finished difference Result 129 states and 137 transitions. [2018-02-04 18:55:04,188 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 18:55:04,189 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-02-04 18:55:04,190 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:04,199 INFO L225 Difference]: With dead ends: 129 [2018-02-04 18:55:04,199 INFO L226 Difference]: Without dead ends: 126 [2018-02-04 18:55:04,200 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-02-04 18:55:04,212 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-02-04 18:55:04,231 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 124. [2018-02-04 18:55:04,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-02-04 18:55:04,235 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 132 transitions. [2018-02-04 18:55:04,236 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 132 transitions. Word has length 17 [2018-02-04 18:55:04,236 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:04,236 INFO L432 AbstractCegarLoop]: Abstraction has 124 states and 132 transitions. [2018-02-04 18:55:04,236 INFO L433 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-02-04 18:55:04,237 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 132 transitions. [2018-02-04 18:55:04,237 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-04 18:55:04,237 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:04,237 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:04,237 INFO L371 AbstractCegarLoop]: === Iteration 2 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:04,238 INFO L82 PathProgramCache]: Analyzing trace with hash 774524518, now seen corresponding path program 1 times [2018-02-04 18:55:04,238 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:04,238 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:04,239 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,239 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:04,240 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:04,257 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:04,301 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:04,301 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:04,301 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-02-04 18:55:04,302 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 18:55:04,303 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 18:55:04,303 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 18:55:04,303 INFO L87 Difference]: Start difference. First operand 124 states and 132 transitions. Second operand 6 states. [2018-02-04 18:55:04,440 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:04,440 INFO L93 Difference]: Finished difference Result 125 states and 133 transitions. [2018-02-04 18:55:04,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 18:55:04,441 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 19 [2018-02-04 18:55:04,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:04,442 INFO L225 Difference]: With dead ends: 125 [2018-02-04 18:55:04,442 INFO L226 Difference]: Without dead ends: 125 [2018-02-04 18:55:04,443 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 18:55:04,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 125 states. [2018-02-04 18:55:04,450 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 125 to 123. [2018-02-04 18:55:04,450 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-02-04 18:55:04,452 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 131 transitions. [2018-02-04 18:55:04,452 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 131 transitions. Word has length 19 [2018-02-04 18:55:04,452 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:04,452 INFO L432 AbstractCegarLoop]: Abstraction has 123 states and 131 transitions. [2018-02-04 18:55:04,452 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 18:55:04,453 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 131 transitions. [2018-02-04 18:55:04,453 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-02-04 18:55:04,453 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:04,453 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:04,453 INFO L371 AbstractCegarLoop]: === Iteration 3 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:04,454 INFO L82 PathProgramCache]: Analyzing trace with hash 774524519, now seen corresponding path program 1 times [2018-02-04 18:55:04,454 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:04,454 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:04,455 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,455 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:04,456 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,472 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:04,473 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:04,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:04,637 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:04,637 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 18:55:04,637 INFO L409 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-02-04 18:55:04,637 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-02-04 18:55:04,637 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-02-04 18:55:04,637 INFO L87 Difference]: Start difference. First operand 123 states and 131 transitions. Second operand 7 states. [2018-02-04 18:55:04,771 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:04,771 INFO L93 Difference]: Finished difference Result 124 states and 132 transitions. [2018-02-04 18:55:04,771 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 18:55:04,771 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-02-04 18:55:04,771 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:04,772 INFO L225 Difference]: With dead ends: 124 [2018-02-04 18:55:04,772 INFO L226 Difference]: Without dead ends: 124 [2018-02-04 18:55:04,772 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-02-04 18:55:04,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-02-04 18:55:04,776 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 122. [2018-02-04 18:55:04,776 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-02-04 18:55:04,777 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 130 transitions. [2018-02-04 18:55:04,777 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 130 transitions. Word has length 19 [2018-02-04 18:55:04,777 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:04,777 INFO L432 AbstractCegarLoop]: Abstraction has 122 states and 130 transitions. [2018-02-04 18:55:04,777 INFO L433 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-02-04 18:55:04,777 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 130 transitions. [2018-02-04 18:55:04,778 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-02-04 18:55:04,778 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:04,778 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:04,778 INFO L371 AbstractCegarLoop]: === Iteration 4 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:04,778 INFO L82 PathProgramCache]: Analyzing trace with hash 1886266821, now seen corresponding path program 1 times [2018-02-04 18:55:04,778 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:04,778 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:04,779 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,779 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:04,779 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:04,796 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:04,877 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:04,878 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:04,878 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 18:55:04,878 INFO L409 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-02-04 18:55:04,878 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-02-04 18:55:04,879 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=57, Unknown=0, NotChecked=0, Total=72 [2018-02-04 18:55:04,879 INFO L87 Difference]: Start difference. First operand 122 states and 130 transitions. Second operand 9 states. [2018-02-04 18:55:04,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:04,965 INFO L93 Difference]: Finished difference Result 139 states and 149 transitions. [2018-02-04 18:55:04,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 18:55:04,965 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 31 [2018-02-04 18:55:04,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:04,967 INFO L225 Difference]: With dead ends: 139 [2018-02-04 18:55:04,967 INFO L226 Difference]: Without dead ends: 139 [2018-02-04 18:55:04,967 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 11 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-02-04 18:55:04,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-02-04 18:55:04,974 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 135. [2018-02-04 18:55:04,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-04 18:55:04,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 144 transitions. [2018-02-04 18:55:04,976 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 144 transitions. Word has length 31 [2018-02-04 18:55:04,976 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:04,976 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 144 transitions. [2018-02-04 18:55:04,976 INFO L433 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-02-04 18:55:04,976 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 144 transitions. [2018-02-04 18:55:04,977 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 18:55:04,977 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:04,977 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:04,977 INFO L371 AbstractCegarLoop]: === Iteration 5 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:04,978 INFO L82 PathProgramCache]: Analyzing trace with hash 107698799, now seen corresponding path program 1 times [2018-02-04 18:55:04,978 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:04,978 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:04,979 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,979 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:04,979 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:04,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:04,991 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:05,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:05,073 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:05,073 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 18:55:05,073 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 18:55:05,074 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 18:55:05,074 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 18:55:05,074 INFO L87 Difference]: Start difference. First operand 135 states and 144 transitions. Second operand 10 states. [2018-02-04 18:55:05,247 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:05,247 INFO L93 Difference]: Finished difference Result 134 states and 143 transitions. [2018-02-04 18:55:05,247 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 18:55:05,247 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 34 [2018-02-04 18:55:05,248 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:05,248 INFO L225 Difference]: With dead ends: 134 [2018-02-04 18:55:05,248 INFO L226 Difference]: Without dead ends: 134 [2018-02-04 18:55:05,249 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 18:55:05,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 134 states. [2018-02-04 18:55:05,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 134 to 134. [2018-02-04 18:55:05,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-02-04 18:55:05,256 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 143 transitions. [2018-02-04 18:55:05,256 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 143 transitions. Word has length 34 [2018-02-04 18:55:05,257 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:05,257 INFO L432 AbstractCegarLoop]: Abstraction has 134 states and 143 transitions. [2018-02-04 18:55:05,257 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 18:55:05,257 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 143 transitions. [2018-02-04 18:55:05,258 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-02-04 18:55:05,258 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:05,258 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:05,258 INFO L371 AbstractCegarLoop]: === Iteration 6 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:05,258 INFO L82 PathProgramCache]: Analyzing trace with hash 107698800, now seen corresponding path program 1 times [2018-02-04 18:55:05,258 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:05,259 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:05,260 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:05,260 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:05,260 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:05,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:05,271 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:05,294 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:05,295 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:05,295 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-02-04 18:55:05,295 INFO L409 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-02-04 18:55:05,295 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-02-04 18:55:05,296 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-02-04 18:55:05,296 INFO L87 Difference]: Start difference. First operand 134 states and 143 transitions. Second operand 4 states. [2018-02-04 18:55:05,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:05,307 INFO L93 Difference]: Finished difference Result 137 states and 146 transitions. [2018-02-04 18:55:05,307 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-02-04 18:55:05,307 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 34 [2018-02-04 18:55:05,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:05,308 INFO L225 Difference]: With dead ends: 137 [2018-02-04 18:55:05,309 INFO L226 Difference]: Without dead ends: 135 [2018-02-04 18:55:05,309 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-02-04 18:55:05,309 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 135 states. [2018-02-04 18:55:05,313 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 135 to 135. [2018-02-04 18:55:05,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-02-04 18:55:05,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 144 transitions. [2018-02-04 18:55:05,313 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 144 transitions. Word has length 34 [2018-02-04 18:55:05,314 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:05,314 INFO L432 AbstractCegarLoop]: Abstraction has 135 states and 144 transitions. [2018-02-04 18:55:05,314 INFO L433 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-02-04 18:55:05,314 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 144 transitions. [2018-02-04 18:55:05,314 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-02-04 18:55:05,314 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:05,315 INFO L351 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:05,315 INFO L371 AbstractCegarLoop]: === Iteration 7 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:05,315 INFO L82 PathProgramCache]: Analyzing trace with hash -1590593736, now seen corresponding path program 1 times [2018-02-04 18:55:05,315 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:05,315 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:05,316 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:05,316 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:05,316 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:05,323 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:05,324 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:05,340 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:05,340 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:05,340 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:05,341 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:05,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:05,361 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:05,381 INFO L134 CoverageAnalysis]: Checked inductivity of 1 backedges. 0 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:05,381 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:05,382 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5] total 6 [2018-02-04 18:55:05,382 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 18:55:05,382 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 18:55:05,382 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=12, Invalid=18, Unknown=0, NotChecked=0, Total=30 [2018-02-04 18:55:05,383 INFO L87 Difference]: Start difference. First operand 135 states and 144 transitions. Second operand 6 states. [2018-02-04 18:55:05,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:05,400 INFO L93 Difference]: Finished difference Result 138 states and 147 transitions. [2018-02-04 18:55:05,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-02-04 18:55:05,401 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-02-04 18:55:05,401 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:05,401 INFO L225 Difference]: With dead ends: 138 [2018-02-04 18:55:05,401 INFO L226 Difference]: Without dead ends: 136 [2018-02-04 18:55:05,401 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 35 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=16, Invalid=26, Unknown=0, NotChecked=0, Total=42 [2018-02-04 18:55:05,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-02-04 18:55:05,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 136. [2018-02-04 18:55:05,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-02-04 18:55:05,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 145 transitions. [2018-02-04 18:55:05,406 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 145 transitions. Word has length 35 [2018-02-04 18:55:05,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:05,407 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 145 transitions. [2018-02-04 18:55:05,407 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 18:55:05,407 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 145 transitions. [2018-02-04 18:55:05,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 18:55:05,408 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:05,408 INFO L351 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:05,408 INFO L371 AbstractCegarLoop]: === Iteration 8 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:05,408 INFO L82 PathProgramCache]: Analyzing trace with hash 1596912496, now seen corresponding path program 2 times [2018-02-04 18:55:05,408 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:05,408 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:05,409 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:05,409 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:05,409 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:05,421 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:05,422 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:05,445 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:05,445 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:05,445 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:05,446 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 18:55:05,469 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 18:55:05,469 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:05,473 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:05,497 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 18:55:05,499 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:05,510 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 18:55:05,511 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:05,536 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 18:55:05,537 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 18:55:05,796 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-02-04 18:55:05,796 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 18:55:05,796 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [6] total 20 [2018-02-04 18:55:05,797 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 18:55:05,797 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 18:55:05,797 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=329, Unknown=0, NotChecked=0, Total=380 [2018-02-04 18:55:05,797 INFO L87 Difference]: Start difference. First operand 136 states and 145 transitions. Second operand 20 states. [2018-02-04 18:55:06,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:06,315 INFO L93 Difference]: Finished difference Result 155 states and 164 transitions. [2018-02-04 18:55:06,315 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-02-04 18:55:06,315 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 36 [2018-02-04 18:55:06,316 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:06,316 INFO L225 Difference]: With dead ends: 155 [2018-02-04 18:55:06,316 INFO L226 Difference]: Without dead ends: 153 [2018-02-04 18:55:06,316 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 50 GetRequests, 23 SyntacticMatches, 0 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=104, Invalid=708, Unknown=0, NotChecked=0, Total=812 [2018-02-04 18:55:06,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-02-04 18:55:06,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 136. [2018-02-04 18:55:06,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 136 states. [2018-02-04 18:55:06,319 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 136 states to 136 states and 145 transitions. [2018-02-04 18:55:06,319 INFO L78 Accepts]: Start accepts. Automaton has 136 states and 145 transitions. Word has length 36 [2018-02-04 18:55:06,319 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:06,320 INFO L432 AbstractCegarLoop]: Abstraction has 136 states and 145 transitions. [2018-02-04 18:55:06,320 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 18:55:06,320 INFO L276 IsEmpty]: Start isEmpty. Operand 136 states and 145 transitions. [2018-02-04 18:55:06,320 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-02-04 18:55:06,320 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:06,321 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:06,321 INFO L371 AbstractCegarLoop]: === Iteration 9 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:06,321 INFO L82 PathProgramCache]: Analyzing trace with hash 2040634480, now seen corresponding path program 1 times [2018-02-04 18:55:06,321 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:06,321 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:06,323 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,323 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:06,323 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:06,329 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:06,362 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 18:55:06,362 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:06,362 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-02-04 18:55:06,362 INFO L409 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-02-04 18:55:06,363 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-02-04 18:55:06,363 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 18:55:06,363 INFO L87 Difference]: Start difference. First operand 136 states and 145 transitions. Second operand 3 states. [2018-02-04 18:55:06,444 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:06,445 INFO L93 Difference]: Finished difference Result 154 states and 165 transitions. [2018-02-04 18:55:06,445 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-02-04 18:55:06,445 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 36 [2018-02-04 18:55:06,445 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:06,446 INFO L225 Difference]: With dead ends: 154 [2018-02-04 18:55:06,446 INFO L226 Difference]: Without dead ends: 142 [2018-02-04 18:55:06,447 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 14 GetRequests, 13 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-02-04 18:55:06,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-02-04 18:55:06,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 132. [2018-02-04 18:55:06,454 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-02-04 18:55:06,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 140 transitions. [2018-02-04 18:55:06,455 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 140 transitions. Word has length 36 [2018-02-04 18:55:06,455 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:06,455 INFO L432 AbstractCegarLoop]: Abstraction has 132 states and 140 transitions. [2018-02-04 18:55:06,455 INFO L433 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-02-04 18:55:06,455 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 140 transitions. [2018-02-04 18:55:06,456 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-02-04 18:55:06,456 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:06,456 INFO L351 BasicCegarLoop]: trace histogram [2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:06,457 INFO L371 AbstractCegarLoop]: === Iteration 10 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:06,457 INFO L82 PathProgramCache]: Analyzing trace with hash 746437934, now seen corresponding path program 1 times [2018-02-04 18:55:06,457 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:06,457 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:06,458 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,458 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:06,458 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:06,470 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:06,500 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-02-04 18:55:06,500 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:06,500 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-02-04 18:55:06,501 INFO L409 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-02-04 18:55:06,501 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-02-04 18:55:06,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-02-04 18:55:06,501 INFO L87 Difference]: Start difference. First operand 132 states and 140 transitions. Second operand 6 states. [2018-02-04 18:55:06,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:06,522 INFO L93 Difference]: Finished difference Result 119 states and 125 transitions. [2018-02-04 18:55:06,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-02-04 18:55:06,522 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 38 [2018-02-04 18:55:06,522 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:06,523 INFO L225 Difference]: With dead ends: 119 [2018-02-04 18:55:06,523 INFO L226 Difference]: Without dead ends: 119 [2018-02-04 18:55:06,523 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-02-04 18:55:06,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-02-04 18:55:06,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119. [2018-02-04 18:55:06,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-02-04 18:55:06,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 125 transitions. [2018-02-04 18:55:06,527 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 125 transitions. Word has length 38 [2018-02-04 18:55:06,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:06,527 INFO L432 AbstractCegarLoop]: Abstraction has 119 states and 125 transitions. [2018-02-04 18:55:06,527 INFO L433 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-02-04 18:55:06,527 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 125 transitions. [2018-02-04 18:55:06,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 18:55:06,528 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:06,528 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:06,528 INFO L371 AbstractCegarLoop]: === Iteration 11 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:06,529 INFO L82 PathProgramCache]: Analyzing trace with hash -98646161, now seen corresponding path program 1 times [2018-02-04 18:55:06,529 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:06,529 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:06,530 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,530 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:06,530 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:06,542 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:06,606 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-02-04 18:55:06,607 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:06,607 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-02-04 18:55:06,607 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 18:55:06,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 18:55:06,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 18:55:06,608 INFO L87 Difference]: Start difference. First operand 119 states and 125 transitions. Second operand 10 states. [2018-02-04 18:55:06,751 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:06,751 INFO L93 Difference]: Finished difference Result 117 states and 123 transitions. [2018-02-04 18:55:06,751 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 18:55:06,751 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 42 [2018-02-04 18:55:06,751 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:06,752 INFO L225 Difference]: With dead ends: 117 [2018-02-04 18:55:06,752 INFO L226 Difference]: Without dead ends: 117 [2018-02-04 18:55:06,752 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 12 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 18:55:06,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-02-04 18:55:06,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-02-04 18:55:06,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-02-04 18:55:06,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 123 transitions. [2018-02-04 18:55:06,756 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 123 transitions. Word has length 42 [2018-02-04 18:55:06,756 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:06,756 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 123 transitions. [2018-02-04 18:55:06,756 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 18:55:06,756 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 123 transitions. [2018-02-04 18:55:06,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-02-04 18:55:06,757 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:06,757 INFO L351 BasicCegarLoop]: trace histogram [3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:06,757 INFO L371 AbstractCegarLoop]: === Iteration 12 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:06,757 INFO L82 PathProgramCache]: Analyzing trace with hash -98646160, now seen corresponding path program 1 times [2018-02-04 18:55:06,757 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:06,757 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:06,758 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,758 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:06,758 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:06,770 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:06,810 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:06,811 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:06,811 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:06,812 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:06,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:06,830 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:06,841 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:06,841 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:06,842 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7] total 8 [2018-02-04 18:55:06,842 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 18:55:06,842 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 18:55:06,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=33, Unknown=0, NotChecked=0, Total=56 [2018-02-04 18:55:06,842 INFO L87 Difference]: Start difference. First operand 117 states and 123 transitions. Second operand 8 states. [2018-02-04 18:55:06,863 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:06,863 INFO L93 Difference]: Finished difference Result 120 states and 126 transitions. [2018-02-04 18:55:06,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-02-04 18:55:06,864 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 42 [2018-02-04 18:55:06,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:06,865 INFO L225 Difference]: With dead ends: 120 [2018-02-04 18:55:06,865 INFO L226 Difference]: Without dead ends: 118 [2018-02-04 18:55:06,865 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 49 GetRequests, 42 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-02-04 18:55:06,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-02-04 18:55:06,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 118. [2018-02-04 18:55:06,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 118 states. [2018-02-04 18:55:06,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 118 states to 118 states and 124 transitions. [2018-02-04 18:55:06,868 INFO L78 Accepts]: Start accepts. Automaton has 118 states and 124 transitions. Word has length 42 [2018-02-04 18:55:06,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:06,868 INFO L432 AbstractCegarLoop]: Abstraction has 118 states and 124 transitions. [2018-02-04 18:55:06,868 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 18:55:06,869 INFO L276 IsEmpty]: Start isEmpty. Operand 118 states and 124 transitions. [2018-02-04 18:55:06,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-02-04 18:55:06,869 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:06,869 INFO L351 BasicCegarLoop]: trace histogram [4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:06,869 INFO L371 AbstractCegarLoop]: === Iteration 13 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:06,870 INFO L82 PathProgramCache]: Analyzing trace with hash -1065378760, now seen corresponding path program 2 times [2018-02-04 18:55:06,870 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:06,870 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:06,870 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,871 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:06,871 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:06,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:06,881 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:06,915 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 10 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:06,915 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:06,916 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:06,916 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 18:55:06,932 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 18:55:06,932 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:06,936 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:06,951 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 18:55:06,952 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:06,965 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 18:55:06,966 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:06,978 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 18:55:06,978 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 18:55:07,237 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-02-04 18:55:07,237 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 18:55:07,238 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [15] imperfect sequences [8] total 22 [2018-02-04 18:55:07,238 INFO L409 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-02-04 18:55:07,238 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-02-04 18:55:07,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=62, Invalid=400, Unknown=0, NotChecked=0, Total=462 [2018-02-04 18:55:07,238 INFO L87 Difference]: Start difference. First operand 118 states and 124 transitions. Second operand 22 states. [2018-02-04 18:55:07,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:07,720 INFO L93 Difference]: Finished difference Result 119 states and 125 transitions. [2018-02-04 18:55:07,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-02-04 18:55:07,720 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 43 [2018-02-04 18:55:07,720 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:07,721 INFO L225 Difference]: With dead ends: 119 [2018-02-04 18:55:07,721 INFO L226 Difference]: Without dead ends: 117 [2018-02-04 18:55:07,722 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 61 GetRequests, 28 SyntacticMatches, 2 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 170 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=139, Invalid=917, Unknown=0, NotChecked=0, Total=1056 [2018-02-04 18:55:07,722 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-02-04 18:55:07,724 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-02-04 18:55:07,724 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-02-04 18:55:07,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 123 transitions. [2018-02-04 18:55:07,725 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 123 transitions. Word has length 43 [2018-02-04 18:55:07,725 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:07,725 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 123 transitions. [2018-02-04 18:55:07,725 INFO L433 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-02-04 18:55:07,725 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 123 transitions. [2018-02-04 18:55:07,725 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-02-04 18:55:07,726 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:07,726 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:07,726 INFO L371 AbstractCegarLoop]: === Iteration 14 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:07,726 INFO L82 PathProgramCache]: Analyzing trace with hash -403711437, now seen corresponding path program 1 times [2018-02-04 18:55:07,726 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:07,726 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:07,728 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:07,728 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:07,728 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:07,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:07,739 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:07,778 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 18:55:07,778 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:07,778 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-02-04 18:55:07,778 INFO L409 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-02-04 18:55:07,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-02-04 18:55:07,779 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=43, Unknown=0, NotChecked=0, Total=56 [2018-02-04 18:55:07,779 INFO L87 Difference]: Start difference. First operand 117 states and 123 transitions. Second operand 8 states. [2018-02-04 18:55:07,814 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:07,814 INFO L93 Difference]: Finished difference Result 119 states and 124 transitions. [2018-02-04 18:55:07,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-02-04 18:55:07,814 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 51 [2018-02-04 18:55:07,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:07,815 INFO L225 Difference]: With dead ends: 119 [2018-02-04 18:55:07,815 INFO L226 Difference]: Without dead ends: 117 [2018-02-04 18:55:07,815 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=21, Invalid=69, Unknown=0, NotChecked=0, Total=90 [2018-02-04 18:55:07,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-02-04 18:55:07,817 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-02-04 18:55:07,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-02-04 18:55:07,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 122 transitions. [2018-02-04 18:55:07,817 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 122 transitions. Word has length 51 [2018-02-04 18:55:07,817 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:07,817 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 122 transitions. [2018-02-04 18:55:07,817 INFO L433 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-02-04 18:55:07,817 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 122 transitions. [2018-02-04 18:55:07,818 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-02-04 18:55:07,818 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:07,818 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:07,818 INFO L371 AbstractCegarLoop]: === Iteration 15 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:07,818 INFO L82 PathProgramCache]: Analyzing trace with hash 90191936, now seen corresponding path program 1 times [2018-02-04 18:55:07,818 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:07,818 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:07,819 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:07,819 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:07,819 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:07,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:07,825 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:07,868 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 18:55:07,868 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:07,868 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-02-04 18:55:07,868 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 18:55:07,869 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 18:55:07,869 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=73, Unknown=0, NotChecked=0, Total=90 [2018-02-04 18:55:07,869 INFO L87 Difference]: Start difference. First operand 117 states and 122 transitions. Second operand 10 states. [2018-02-04 18:55:07,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:07,917 INFO L93 Difference]: Finished difference Result 121 states and 125 transitions. [2018-02-04 18:55:07,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-02-04 18:55:07,917 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 56 [2018-02-04 18:55:07,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:07,918 INFO L225 Difference]: With dead ends: 121 [2018-02-04 18:55:07,918 INFO L226 Difference]: Without dead ends: 117 [2018-02-04 18:55:07,919 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=127, Unknown=0, NotChecked=0, Total=156 [2018-02-04 18:55:07,919 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-02-04 18:55:07,921 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-02-04 18:55:07,921 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-02-04 18:55:07,922 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 121 transitions. [2018-02-04 18:55:07,922 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 121 transitions. Word has length 56 [2018-02-04 18:55:07,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:07,922 INFO L432 AbstractCegarLoop]: Abstraction has 117 states and 121 transitions. [2018-02-04 18:55:07,922 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 18:55:07,923 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 121 transitions. [2018-02-04 18:55:07,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-02-04 18:55:07,923 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:07,923 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:07,923 INFO L371 AbstractCegarLoop]: === Iteration 16 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:07,924 INFO L82 PathProgramCache]: Analyzing trace with hash 222221704, now seen corresponding path program 1 times [2018-02-04 18:55:07,924 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:07,924 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:07,925 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:07,925 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:07,925 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:07,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:07,939 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:08,155 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-02-04 18:55:08,155 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:08,155 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [] total 22 [2018-02-04 18:55:08,155 INFO L409 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-02-04 18:55:08,155 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-02-04 18:55:08,156 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=461, Unknown=0, NotChecked=0, Total=506 [2018-02-04 18:55:08,156 INFO L87 Difference]: Start difference. First operand 117 states and 121 transitions. Second operand 23 states. [2018-02-04 18:55:08,517 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:08,517 INFO L93 Difference]: Finished difference Result 144 states and 153 transitions. [2018-02-04 18:55:08,517 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-02-04 18:55:08,517 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 67 [2018-02-04 18:55:08,518 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:08,518 INFO L225 Difference]: With dead ends: 144 [2018-02-04 18:55:08,518 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 18:55:08,518 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 30 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=77, Invalid=853, Unknown=0, NotChecked=0, Total=930 [2018-02-04 18:55:08,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 18:55:08,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 139. [2018-02-04 18:55:08,520 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-04 18:55:08,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 149 transitions. [2018-02-04 18:55:08,521 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 149 transitions. Word has length 67 [2018-02-04 18:55:08,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:08,521 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 149 transitions. [2018-02-04 18:55:08,521 INFO L433 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-02-04 18:55:08,521 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 149 transitions. [2018-02-04 18:55:08,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-02-04 18:55:08,522 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:08,522 INFO L351 BasicCegarLoop]: trace histogram [5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:08,522 INFO L371 AbstractCegarLoop]: === Iteration 17 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:08,522 INFO L82 PathProgramCache]: Analyzing trace with hash 222221705, now seen corresponding path program 1 times [2018-02-04 18:55:08,522 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:08,522 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:08,523 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:08,523 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:08,523 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:08,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:08,532 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:08,580 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:08,581 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:08,581 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:08,581 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:08,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:08,605 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:08,626 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:08,626 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:08,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 10 [2018-02-04 18:55:08,626 INFO L409 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-02-04 18:55:08,627 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-02-04 18:55:08,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=38, Invalid=52, Unknown=0, NotChecked=0, Total=90 [2018-02-04 18:55:08,627 INFO L87 Difference]: Start difference. First operand 139 states and 149 transitions. Second operand 10 states. [2018-02-04 18:55:08,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:08,651 INFO L93 Difference]: Finished difference Result 142 states and 152 transitions. [2018-02-04 18:55:08,651 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-02-04 18:55:08,652 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 67 [2018-02-04 18:55:08,652 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:08,652 INFO L225 Difference]: With dead ends: 142 [2018-02-04 18:55:08,652 INFO L226 Difference]: Without dead ends: 140 [2018-02-04 18:55:08,653 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 76 GetRequests, 67 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=42, Invalid=68, Unknown=0, NotChecked=0, Total=110 [2018-02-04 18:55:08,653 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 140 states. [2018-02-04 18:55:08,655 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 140 to 140. [2018-02-04 18:55:08,655 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-02-04 18:55:08,656 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 150 transitions. [2018-02-04 18:55:08,656 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 150 transitions. Word has length 67 [2018-02-04 18:55:08,656 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:08,656 INFO L432 AbstractCegarLoop]: Abstraction has 140 states and 150 transitions. [2018-02-04 18:55:08,656 INFO L433 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-02-04 18:55:08,657 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 150 transitions. [2018-02-04 18:55:08,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-02-04 18:55:08,657 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:08,657 INFO L351 BasicCegarLoop]: trace histogram [6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:08,657 INFO L371 AbstractCegarLoop]: === Iteration 18 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:08,657 INFO L82 PathProgramCache]: Analyzing trace with hash -1652723263, now seen corresponding path program 2 times [2018-02-04 18:55:08,658 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:08,658 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:08,658 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:08,658 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:08,659 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:08,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:08,671 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:08,724 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 21 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:08,724 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:08,724 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:08,725 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 18:55:08,747 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 18:55:08,748 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:08,753 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:08,789 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 18:55:08,790 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:08,803 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 18:55:08,803 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:08,814 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 18:55:08,815 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 18:55:09,212 INFO L134 CoverageAnalysis]: Checked inductivity of 21 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-02-04 18:55:09,212 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 18:55:09,213 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [22] imperfect sequences [10] total 31 [2018-02-04 18:55:09,213 INFO L409 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-02-04 18:55:09,213 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-02-04 18:55:09,213 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=98, Invalid=832, Unknown=0, NotChecked=0, Total=930 [2018-02-04 18:55:09,213 INFO L87 Difference]: Start difference. First operand 140 states and 150 transitions. Second operand 31 states. [2018-02-04 18:55:09,917 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:09,917 INFO L93 Difference]: Finished difference Result 141 states and 149 transitions. [2018-02-04 18:55:09,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-02-04 18:55:09,917 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 68 [2018-02-04 18:55:09,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:09,917 INFO L225 Difference]: With dead ends: 141 [2018-02-04 18:55:09,918 INFO L226 Difference]: Without dead ends: 139 [2018-02-04 18:55:09,918 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 47 SyntacticMatches, 1 SemanticMatches, 45 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 331 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=223, Invalid=1939, Unknown=0, NotChecked=0, Total=2162 [2018-02-04 18:55:09,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-02-04 18:55:09,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-02-04 18:55:09,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-02-04 18:55:09,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 147 transitions. [2018-02-04 18:55:09,921 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 147 transitions. Word has length 68 [2018-02-04 18:55:09,921 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:09,921 INFO L432 AbstractCegarLoop]: Abstraction has 139 states and 147 transitions. [2018-02-04 18:55:09,921 INFO L433 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-02-04 18:55:09,921 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 147 transitions. [2018-02-04 18:55:09,922 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-02-04 18:55:09,922 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:09,922 INFO L351 BasicCegarLoop]: trace histogram [7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:09,922 INFO L371 AbstractCegarLoop]: === Iteration 19 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:09,922 INFO L82 PathProgramCache]: Analyzing trace with hash 973434245, now seen corresponding path program 1 times [2018-02-04 18:55:09,922 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:09,922 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:09,923 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:09,923 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:09,923 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:09,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:09,932 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:10,011 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 18:55:10,011 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:10,011 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [13] imperfect sequences [] total 13 [2018-02-04 18:55:10,011 INFO L409 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-02-04 18:55:10,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-02-04 18:55:10,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=133, Unknown=0, NotChecked=0, Total=156 [2018-02-04 18:55:10,012 INFO L87 Difference]: Start difference. First operand 139 states and 147 transitions. Second operand 13 states. [2018-02-04 18:55:10,072 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:10,072 INFO L93 Difference]: Finished difference Result 143 states and 149 transitions. [2018-02-04 18:55:10,072 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 18:55:10,072 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 76 [2018-02-04 18:55:10,073 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:10,073 INFO L225 Difference]: With dead ends: 143 [2018-02-04 18:55:10,073 INFO L226 Difference]: Without dead ends: 137 [2018-02-04 18:55:10,073 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 17 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=39, Invalid=233, Unknown=0, NotChecked=0, Total=272 [2018-02-04 18:55:10,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-02-04 18:55:10,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-02-04 18:55:10,076 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-02-04 18:55:10,077 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 143 transitions. [2018-02-04 18:55:10,077 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 143 transitions. Word has length 76 [2018-02-04 18:55:10,077 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:10,077 INFO L432 AbstractCegarLoop]: Abstraction has 137 states and 143 transitions. [2018-02-04 18:55:10,078 INFO L433 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-02-04 18:55:10,078 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 143 transitions. [2018-02-04 18:55:10,078 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-04 18:55:10,078 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:10,078 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:10,079 INFO L371 AbstractCegarLoop]: === Iteration 20 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:10,079 INFO L82 PathProgramCache]: Analyzing trace with hash -323701284, now seen corresponding path program 1 times [2018-02-04 18:55:10,079 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:10,079 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:10,080 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:10,080 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:10,080 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:10,093 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:10,094 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:10,349 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-02-04 18:55:10,349 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-02-04 18:55:10,349 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [] total 26 [2018-02-04 18:55:10,349 INFO L409 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-02-04 18:55:10,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-02-04 18:55:10,350 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=53, Invalid=649, Unknown=0, NotChecked=0, Total=702 [2018-02-04 18:55:10,350 INFO L87 Difference]: Start difference. First operand 137 states and 143 transitions. Second operand 27 states. [2018-02-04 18:55:10,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:10,842 INFO L93 Difference]: Finished difference Result 147 states and 156 transitions. [2018-02-04 18:55:10,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-02-04 18:55:10,843 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 83 [2018-02-04 18:55:10,843 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:10,843 INFO L225 Difference]: With dead ends: 147 [2018-02-04 18:55:10,844 INFO L226 Difference]: Without dead ends: 147 [2018-02-04 18:55:10,844 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 96 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=93, Invalid=1239, Unknown=0, NotChecked=0, Total=1332 [2018-02-04 18:55:10,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-02-04 18:55:10,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 143. [2018-02-04 18:55:10,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-02-04 18:55:10,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 153 transitions. [2018-02-04 18:55:10,848 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 153 transitions. Word has length 83 [2018-02-04 18:55:10,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:10,848 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 153 transitions. [2018-02-04 18:55:10,848 INFO L433 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-02-04 18:55:10,848 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 153 transitions. [2018-02-04 18:55:10,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-02-04 18:55:10,849 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:10,849 INFO L351 BasicCegarLoop]: trace histogram [7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:10,849 INFO L371 AbstractCegarLoop]: === Iteration 21 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:10,850 INFO L82 PathProgramCache]: Analyzing trace with hash -323701283, now seen corresponding path program 1 times [2018-02-04 18:55:10,850 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:10,850 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:10,851 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:10,851 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:10,851 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:10,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:10,865 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:10,935 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:10,935 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:10,935 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:10,936 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:10,955 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:10,959 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:10,972 INFO L134 CoverageAnalysis]: Checked inductivity of 28 backedges. 0 proven. 28 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:10,972 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:10,972 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11] total 12 [2018-02-04 18:55:10,973 INFO L409 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-02-04 18:55:10,973 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-02-04 18:55:10,973 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=75, Unknown=0, NotChecked=0, Total=132 [2018-02-04 18:55:10,973 INFO L87 Difference]: Start difference. First operand 143 states and 153 transitions. Second operand 12 states. [2018-02-04 18:55:10,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:10,999 INFO L93 Difference]: Finished difference Result 146 states and 156 transitions. [2018-02-04 18:55:10,999 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-02-04 18:55:11,000 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 83 [2018-02-04 18:55:11,000 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:11,000 INFO L225 Difference]: With dead ends: 146 [2018-02-04 18:55:11,000 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 18:55:11,001 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 83 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=61, Invalid=95, Unknown=0, NotChecked=0, Total=156 [2018-02-04 18:55:11,001 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 18:55:11,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 144. [2018-02-04 18:55:11,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-02-04 18:55:11,005 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 154 transitions. [2018-02-04 18:55:11,005 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 154 transitions. Word has length 83 [2018-02-04 18:55:11,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:11,005 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 154 transitions. [2018-02-04 18:55:11,005 INFO L433 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-02-04 18:55:11,005 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 154 transitions. [2018-02-04 18:55:11,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-02-04 18:55:11,006 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:11,006 INFO L351 BasicCegarLoop]: trace histogram [8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:11,006 INFO L371 AbstractCegarLoop]: === Iteration 22 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:11,006 INFO L82 PathProgramCache]: Analyzing trace with hash 1768153621, now seen corresponding path program 2 times [2018-02-04 18:55:11,007 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:11,007 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:11,007 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:11,008 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:11,008 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:11,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:11,022 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:11,089 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 36 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:11,089 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:11,089 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:11,090 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 18:55:11,112 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-02-04 18:55:11,113 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:11,118 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:11,134 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 16 [2018-02-04 18:55:11,135 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:11,148 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 19 [2018-02-04 18:55:11,149 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:11,160 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 18:55:11,160 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:38, output treesize:36 [2018-02-04 18:55:11,605 INFO L134 CoverageAnalysis]: Checked inductivity of 36 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-02-04 18:55:11,605 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-02-04 18:55:11,605 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [26] imperfect sequences [12] total 37 [2018-02-04 18:55:11,606 INFO L409 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-02-04 18:55:11,606 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-02-04 18:55:11,606 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=129, Invalid=1203, Unknown=0, NotChecked=0, Total=1332 [2018-02-04 18:55:11,606 INFO L87 Difference]: Start difference. First operand 144 states and 154 transitions. Second operand 37 states. [2018-02-04 18:55:12,602 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:12,602 INFO L93 Difference]: Finished difference Result 145 states and 154 transitions. [2018-02-04 18:55:12,603 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-02-04 18:55:12,603 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 84 [2018-02-04 18:55:12,603 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:12,604 INFO L225 Difference]: With dead ends: 145 [2018-02-04 18:55:12,604 INFO L226 Difference]: Without dead ends: 143 [2018-02-04 18:55:12,605 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 57 SyntacticMatches, 3 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 531 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=304, Invalid=2888, Unknown=0, NotChecked=0, Total=3192 [2018-02-04 18:55:12,605 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 143 states. [2018-02-04 18:55:12,608 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 143 to 143. [2018-02-04 18:55:12,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-02-04 18:55:12,609 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 152 transitions. [2018-02-04 18:55:12,609 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 152 transitions. Word has length 84 [2018-02-04 18:55:12,609 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:12,609 INFO L432 AbstractCegarLoop]: Abstraction has 143 states and 152 transitions. [2018-02-04 18:55:12,609 INFO L433 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-02-04 18:55:12,610 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 152 transitions. [2018-02-04 18:55:12,610 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-02-04 18:55:12,610 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:12,611 INFO L351 BasicCegarLoop]: trace histogram [9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:12,611 INFO L371 AbstractCegarLoop]: === Iteration 23 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:12,611 INFO L82 PathProgramCache]: Analyzing trace with hash -11138274, now seen corresponding path program 1 times [2018-02-04 18:55:12,611 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:12,611 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:12,612 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:12,612 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:12,612 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:12,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:12,629 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:12,714 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:12,715 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:12,715 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:12,716 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:12,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:12,741 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:12,755 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 0 proven. 45 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:12,756 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:12,756 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13] total 14 [2018-02-04 18:55:12,756 INFO L409 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-02-04 18:55:12,757 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-02-04 18:55:12,757 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=80, Invalid=102, Unknown=0, NotChecked=0, Total=182 [2018-02-04 18:55:12,757 INFO L87 Difference]: Start difference. First operand 143 states and 152 transitions. Second operand 14 states. [2018-02-04 18:55:12,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:12,785 INFO L93 Difference]: Finished difference Result 146 states and 155 transitions. [2018-02-04 18:55:12,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-02-04 18:55:12,785 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 89 [2018-02-04 18:55:12,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:12,786 INFO L225 Difference]: With dead ends: 146 [2018-02-04 18:55:12,786 INFO L226 Difference]: Without dead ends: 144 [2018-02-04 18:55:12,786 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 102 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 26 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=84, Invalid=126, Unknown=0, NotChecked=0, Total=210 [2018-02-04 18:55:12,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-02-04 18:55:12,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 144. [2018-02-04 18:55:12,789 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-02-04 18:55:12,790 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 153 transitions. [2018-02-04 18:55:12,790 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 153 transitions. Word has length 89 [2018-02-04 18:55:12,790 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:12,790 INFO L432 AbstractCegarLoop]: Abstraction has 144 states and 153 transitions. [2018-02-04 18:55:12,790 INFO L433 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-02-04 18:55:12,791 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 153 transitions. [2018-02-04 18:55:12,791 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-02-04 18:55:12,791 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:12,791 INFO L351 BasicCegarLoop]: trace histogram [10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:12,791 INFO L371 AbstractCegarLoop]: === Iteration 24 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:12,792 INFO L82 PathProgramCache]: Analyzing trace with hash 558968150, now seen corresponding path program 2 times [2018-02-04 18:55:12,792 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:12,792 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:12,793 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:12,793 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:12,793 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:12,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:12,808 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:12,914 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:12,914 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:12,914 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:12,915 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 18:55:12,950 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 18:55:12,950 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:12,955 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:12,988 INFO L134 CoverageAnalysis]: Checked inductivity of 55 backedges. 0 proven. 55 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:12,988 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:12,988 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 15 [2018-02-04 18:55:12,989 INFO L409 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-02-04 18:55:12,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-02-04 18:55:12,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=93, Invalid=117, Unknown=0, NotChecked=0, Total=210 [2018-02-04 18:55:12,989 INFO L87 Difference]: Start difference. First operand 144 states and 153 transitions. Second operand 15 states. [2018-02-04 18:55:13,020 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:13,020 INFO L93 Difference]: Finished difference Result 147 states and 156 transitions. [2018-02-04 18:55:13,020 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-02-04 18:55:13,020 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 90 [2018-02-04 18:55:13,021 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:13,021 INFO L225 Difference]: With dead ends: 147 [2018-02-04 18:55:13,021 INFO L226 Difference]: Without dead ends: 145 [2018-02-04 18:55:13,022 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 90 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=97, Invalid=143, Unknown=0, NotChecked=0, Total=240 [2018-02-04 18:55:13,022 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-02-04 18:55:13,024 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 145. [2018-02-04 18:55:13,024 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-02-04 18:55:13,025 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 154 transitions. [2018-02-04 18:55:13,025 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 154 transitions. Word has length 90 [2018-02-04 18:55:13,025 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:13,025 INFO L432 AbstractCegarLoop]: Abstraction has 145 states and 154 transitions. [2018-02-04 18:55:13,026 INFO L433 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-02-04 18:55:13,026 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 154 transitions. [2018-02-04 18:55:13,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 92 [2018-02-04 18:55:13,026 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:13,026 INFO L351 BasicCegarLoop]: trace histogram [11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:13,026 INFO L371 AbstractCegarLoop]: === Iteration 25 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:13,027 INFO L82 PathProgramCache]: Analyzing trace with hash 1052398110, now seen corresponding path program 3 times [2018-02-04 18:55:13,027 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:13,027 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:13,027 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,028 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:13,028 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:13,043 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:13,144 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,144 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:13,144 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:13,145 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-02-04 18:55:13,183 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 7 check-sat command(s) [2018-02-04 18:55:13,183 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:13,188 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:13,201 INFO L134 CoverageAnalysis]: Checked inductivity of 66 backedges. 0 proven. 66 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,201 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:13,202 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 16 [2018-02-04 18:55:13,202 INFO L409 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-02-04 18:55:13,202 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-02-04 18:55:13,202 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=107, Invalid=133, Unknown=0, NotChecked=0, Total=240 [2018-02-04 18:55:13,203 INFO L87 Difference]: Start difference. First operand 145 states and 154 transitions. Second operand 16 states. [2018-02-04 18:55:13,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:13,234 INFO L93 Difference]: Finished difference Result 148 states and 157 transitions. [2018-02-04 18:55:13,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-02-04 18:55:13,235 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 91 [2018-02-04 18:55:13,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:13,236 INFO L225 Difference]: With dead ends: 148 [2018-02-04 18:55:13,236 INFO L226 Difference]: Without dead ends: 146 [2018-02-04 18:55:13,236 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 91 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=111, Invalid=161, Unknown=0, NotChecked=0, Total=272 [2018-02-04 18:55:13,236 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-02-04 18:55:13,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 146. [2018-02-04 18:55:13,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-02-04 18:55:13,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 155 transitions. [2018-02-04 18:55:13,239 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 155 transitions. Word has length 91 [2018-02-04 18:55:13,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:13,240 INFO L432 AbstractCegarLoop]: Abstraction has 146 states and 155 transitions. [2018-02-04 18:55:13,240 INFO L433 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-02-04 18:55:13,240 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 155 transitions. [2018-02-04 18:55:13,240 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-02-04 18:55:13,240 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:13,241 INFO L351 BasicCegarLoop]: trace histogram [12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:13,241 INFO L371 AbstractCegarLoop]: === Iteration 26 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:13,241 INFO L82 PathProgramCache]: Analyzing trace with hash -831142314, now seen corresponding path program 4 times [2018-02-04 18:55:13,241 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:13,241 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:13,242 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,242 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:13,242 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,256 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:13,257 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:13,371 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,371 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:13,371 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:13,372 INFO L109 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-02-04 18:55:13,393 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-02-04 18:55:13,394 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:13,396 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:13,423 INFO L134 CoverageAnalysis]: Checked inductivity of 78 backedges. 0 proven. 78 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,423 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:13,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 17 [2018-02-04 18:55:13,424 INFO L409 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-02-04 18:55:13,424 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-02-04 18:55:13,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=122, Invalid=150, Unknown=0, NotChecked=0, Total=272 [2018-02-04 18:55:13,424 INFO L87 Difference]: Start difference. First operand 146 states and 155 transitions. Second operand 17 states. [2018-02-04 18:55:13,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:13,450 INFO L93 Difference]: Finished difference Result 149 states and 158 transitions. [2018-02-04 18:55:13,450 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-02-04 18:55:13,450 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 92 [2018-02-04 18:55:13,450 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:13,451 INFO L225 Difference]: With dead ends: 149 [2018-02-04 18:55:13,451 INFO L226 Difference]: Without dead ends: 147 [2018-02-04 18:55:13,451 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 108 GetRequests, 92 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=126, Invalid=180, Unknown=0, NotChecked=0, Total=306 [2018-02-04 18:55:13,451 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-02-04 18:55:13,453 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-02-04 18:55:13,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-02-04 18:55:13,454 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 156 transitions. [2018-02-04 18:55:13,454 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 156 transitions. Word has length 92 [2018-02-04 18:55:13,454 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:13,454 INFO L432 AbstractCegarLoop]: Abstraction has 147 states and 156 transitions. [2018-02-04 18:55:13,455 INFO L433 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-02-04 18:55:13,455 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 156 transitions. [2018-02-04 18:55:13,455 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-02-04 18:55:13,455 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:13,455 INFO L351 BasicCegarLoop]: trace histogram [13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:13,455 INFO L371 AbstractCegarLoop]: === Iteration 27 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:13,456 INFO L82 PathProgramCache]: Analyzing trace with hash 908646686, now seen corresponding path program 5 times [2018-02-04 18:55:13,456 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:13,456 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:13,457 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,457 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:13,457 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,476 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:13,477 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:13,633 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,633 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:13,633 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:13,634 INFO L109 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-02-04 18:55:13,666 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-02-04 18:55:13,666 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:13,671 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:13,693 INFO L134 CoverageAnalysis]: Checked inductivity of 91 backedges. 0 proven. 91 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,693 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:13,693 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17] total 18 [2018-02-04 18:55:13,694 INFO L409 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-02-04 18:55:13,694 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-02-04 18:55:13,694 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=138, Invalid=168, Unknown=0, NotChecked=0, Total=306 [2018-02-04 18:55:13,694 INFO L87 Difference]: Start difference. First operand 147 states and 156 transitions. Second operand 18 states. [2018-02-04 18:55:13,728 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:13,728 INFO L93 Difference]: Finished difference Result 150 states and 159 transitions. [2018-02-04 18:55:13,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-02-04 18:55:13,728 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 93 [2018-02-04 18:55:13,729 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:13,729 INFO L225 Difference]: With dead ends: 150 [2018-02-04 18:55:13,729 INFO L226 Difference]: Without dead ends: 148 [2018-02-04 18:55:13,729 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 93 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=142, Invalid=200, Unknown=0, NotChecked=0, Total=342 [2018-02-04 18:55:13,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-02-04 18:55:13,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 148. [2018-02-04 18:55:13,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 148 states. [2018-02-04 18:55:13,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 148 states to 148 states and 157 transitions. [2018-02-04 18:55:13,733 INFO L78 Accepts]: Start accepts. Automaton has 148 states and 157 transitions. Word has length 93 [2018-02-04 18:55:13,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:13,733 INFO L432 AbstractCegarLoop]: Abstraction has 148 states and 157 transitions. [2018-02-04 18:55:13,733 INFO L433 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-02-04 18:55:13,733 INFO L276 IsEmpty]: Start isEmpty. Operand 148 states and 157 transitions. [2018-02-04 18:55:13,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-02-04 18:55:13,734 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:13,734 INFO L351 BasicCegarLoop]: trace histogram [14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:13,734 INFO L371 AbstractCegarLoop]: === Iteration 28 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:13,734 INFO L82 PathProgramCache]: Analyzing trace with hash -992469162, now seen corresponding path program 6 times [2018-02-04 18:55:13,735 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:13,735 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:13,735 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,735 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:13,735 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:13,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:13,752 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:13,926 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,926 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:13,927 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:13,927 INFO L109 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-02-04 18:55:13,965 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-02-04 18:55:13,965 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:13,970 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:13,984 INFO L134 CoverageAnalysis]: Checked inductivity of 105 backedges. 0 proven. 105 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:13,984 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:13,984 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 19 [2018-02-04 18:55:13,985 INFO L409 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-02-04 18:55:13,985 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-02-04 18:55:13,985 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=155, Invalid=187, Unknown=0, NotChecked=0, Total=342 [2018-02-04 18:55:13,985 INFO L87 Difference]: Start difference. First operand 148 states and 157 transitions. Second operand 19 states. [2018-02-04 18:55:14,024 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:14,024 INFO L93 Difference]: Finished difference Result 151 states and 160 transitions. [2018-02-04 18:55:14,024 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-02-04 18:55:14,024 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 94 [2018-02-04 18:55:14,024 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:14,025 INFO L225 Difference]: With dead ends: 151 [2018-02-04 18:55:14,025 INFO L226 Difference]: Without dead ends: 149 [2018-02-04 18:55:14,025 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 94 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 41 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=159, Invalid=221, Unknown=0, NotChecked=0, Total=380 [2018-02-04 18:55:14,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-02-04 18:55:14,028 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-02-04 18:55:14,028 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-02-04 18:55:14,028 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 158 transitions. [2018-02-04 18:55:14,028 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 158 transitions. Word has length 94 [2018-02-04 18:55:14,029 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:14,029 INFO L432 AbstractCegarLoop]: Abstraction has 149 states and 158 transitions. [2018-02-04 18:55:14,029 INFO L433 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-02-04 18:55:14,029 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 158 transitions. [2018-02-04 18:55:14,029 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-02-04 18:55:14,029 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:14,029 INFO L351 BasicCegarLoop]: trace histogram [15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:14,030 INFO L371 AbstractCegarLoop]: === Iteration 29 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:14,030 INFO L82 PathProgramCache]: Analyzing trace with hash 202481694, now seen corresponding path program 7 times [2018-02-04 18:55:14,030 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:14,030 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:14,031 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:14,031 INFO L107 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-02-04 18:55:14,031 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:14,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:14,045 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:14,189 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:14,190 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:14,190 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:14,190 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:14,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:14,212 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:14,225 INFO L134 CoverageAnalysis]: Checked inductivity of 120 backedges. 0 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-02-04 18:55:14,225 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-02-04 18:55:14,225 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19] total 20 [2018-02-04 18:55:14,226 INFO L409 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-02-04 18:55:14,226 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-02-04 18:55:14,226 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=173, Invalid=207, Unknown=0, NotChecked=0, Total=380 [2018-02-04 18:55:14,226 INFO L87 Difference]: Start difference. First operand 149 states and 158 transitions. Second operand 20 states. [2018-02-04 18:55:14,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-02-04 18:55:14,264 INFO L93 Difference]: Finished difference Result 152 states and 161 transitions. [2018-02-04 18:55:14,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-02-04 18:55:14,264 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 95 [2018-02-04 18:55:14,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-02-04 18:55:14,265 INFO L225 Difference]: With dead ends: 152 [2018-02-04 18:55:14,265 INFO L226 Difference]: Without dead ends: 150 [2018-02-04 18:55:14,266 INFO L554 BasicCegarLoop]: 0 DeclaredPredicates, 114 GetRequests, 95 SyntacticMatches, 0 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=177, Invalid=243, Unknown=0, NotChecked=0, Total=420 [2018-02-04 18:55:14,266 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-02-04 18:55:14,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 150. [2018-02-04 18:55:14,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-02-04 18:55:14,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 159 transitions. [2018-02-04 18:55:14,269 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 159 transitions. Word has length 95 [2018-02-04 18:55:14,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-02-04 18:55:14,269 INFO L432 AbstractCegarLoop]: Abstraction has 150 states and 159 transitions. [2018-02-04 18:55:14,269 INFO L433 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-02-04 18:55:14,269 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 159 transitions. [2018-02-04 18:55:14,270 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-02-04 18:55:14,270 INFO L343 BasicCegarLoop]: Found error trace [2018-02-04 18:55:14,270 INFO L351 BasicCegarLoop]: trace histogram [16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-02-04 18:55:14,270 INFO L371 AbstractCegarLoop]: === Iteration 30 === [ldv_kref_initErr0RequiresViolation, ldv_kref_initErr1RequiresViolation, ldv_kobject_createErr0RequiresViolation, ldv_kobject_createErr1RequiresViolation, ldv_atomic_sub_returnErr1RequiresViolation, ldv_atomic_sub_returnErr0RequiresViolation, ldv_atomic_sub_returnErr3RequiresViolation, ldv_atomic_sub_returnErr2RequiresViolation, ldv_kobject_cleanupErr4RequiresViolation, ldv_kobject_cleanupErr2RequiresViolation, ldv_kobject_cleanupErr5RequiresViolation, ldv_kobject_cleanupErr3RequiresViolation, ldv_kobject_cleanupErr0RequiresViolation, ldv_kobject_cleanupErr1RequiresViolation, mainErr0EnsuresViolation, LDV_INIT_LIST_HEADErr1RequiresViolation, LDV_INIT_LIST_HEADErr3RequiresViolation, LDV_INIT_LIST_HEADErr2RequiresViolation, LDV_INIT_LIST_HEADErr0RequiresViolation]=== [2018-02-04 18:55:14,270 INFO L82 PathProgramCache]: Analyzing trace with hash -1408747434, now seen corresponding path program 8 times [2018-02-04 18:55:14,270 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-02-04 18:55:14,270 INFO L67 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-02-04 18:55:14,271 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:14,271 INFO L109 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-02-04 18:55:14,271 INFO L125 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-02-04 18:55:14,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-02-04 18:55:14,320 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-02-04 18:55:14,333 INFO L430 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-02-04 18:55:14,333 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-02-04 18:55:14,333 INFO L213 onRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-02-04 18:55:14,334 INFO L109 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-02-04 18:55:14,389 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-02-04 18:55:14,389 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-02-04 18:55:14,397 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-02-04 18:55:14,418 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-02-04 18:55:14,419 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-02-04 18:55:14,420 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,421 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,425 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,425 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:17, output treesize:13 [2018-02-04 18:55:14,439 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 20 [2018-02-04 18:55:14,442 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,444 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-02-04 18:55:14,444 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,450 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,455 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,455 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:28, output treesize:24 [2018-02-04 18:55:14,474 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 29 [2018-02-04 18:55:14,477 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,480 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 38 [2018-02-04 18:55:14,480 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,487 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,495 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:14,496 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:44, output treesize:40 [2018-02-04 18:55:14,522 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 38 [2018-02-04 18:55:14,530 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,533 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 1 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 49 [2018-02-04 18:55:14,560 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,569 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,582 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:14,582 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:60, output treesize:56 [2018-02-04 18:55:14,636 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 48 [2018-02-04 18:55:14,646 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,651 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 1 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 48 treesize of output 61 [2018-02-04 18:55:14,651 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,659 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,669 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:14,670 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:72, output treesize:68 [2018-02-04 18:55:14,737 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 71 treesize of output 58 [2018-02-04 18:55:14,753 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,760 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 2 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 83 [2018-02-04 18:55:14,760 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,771 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,783 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:14,783 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:84, output treesize:80 [2018-02-04 18:55:14,822 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 68 [2018-02-04 18:55:14,828 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,832 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,841 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,845 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,848 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 4 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 68 treesize of output 115 [2018-02-04 18:55:14,849 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,863 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:14,877 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:14,877 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:96, output treesize:92 [2018-02-04 18:55:14,972 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 95 treesize of output 78 [2018-02-04 18:55:14,980 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,987 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:14,988 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:15,005 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:15,006 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:15,008 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:15,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:15,019 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 7 select indices, 7 select index equivalence classes, 7 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 78 treesize of output 157 [2018-02-04 18:55:15,020 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:15,038 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:15,054 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:15,054 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:108, output treesize:104 [2018-02-04 18:55:16,403 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 107 treesize of output 88 [2018-02-04 18:55:16,408 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,422 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,423 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,424 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,430 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,431 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,432 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,446 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,455 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,456 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,457 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,457 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 8 select indices, 8 select index equivalence classes, 11 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 88 treesize of output 209 [2018-02-04 18:55:16,458 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:16,490 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:16,506 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:16,506 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:120, output treesize:116 [2018-02-04 18:55:16,571 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 119 treesize of output 98 [2018-02-04 18:55:16,582 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,585 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,586 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,586 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,587 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,590 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,590 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,591 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,591 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,596 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,607 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 9 select indices, 9 select index equivalence classes, 16 disjoint index pairs (out of 36 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 98 treesize of output 271 [2018-02-04 18:55:16,607 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:16,637 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:16,660 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:16,660 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:132, output treesize:128 [2018-02-04 18:55:16,727 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 131 treesize of output 108 [2018-02-04 18:55:16,741 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,745 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,746 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,747 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,748 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,748 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,753 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,754 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,754 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,755 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,772 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,773 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,773 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,776 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,776 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,777 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,777 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,778 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,779 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 10 select indices, 10 select index equivalence classes, 22 disjoint index pairs (out of 45 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 108 treesize of output 343 [2018-02-04 18:55:16,779 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:16,848 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:16,867 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:16,867 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:144, output treesize:140 [2018-02-04 18:55:16,955 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 143 treesize of output 118 [2018-02-04 18:55:16,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,965 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,971 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,973 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,975 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,976 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,979 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,984 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,985 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:16,987 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,009 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,011 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,012 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,013 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,014 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,026 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,042 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,043 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,046 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,048 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,049 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,050 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,052 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 11 select indices, 11 select index equivalence classes, 29 disjoint index pairs (out of 55 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 118 treesize of output 425 [2018-02-04 18:55:17,053 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:17,106 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:17,129 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:17,130 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:156, output treesize:152 [2018-02-04 18:55:17,290 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 155 treesize of output 128 [2018-02-04 18:55:17,316 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,317 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,324 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,325 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,326 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,327 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,328 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,329 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,330 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,336 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,337 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,338 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,339 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,339 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,341 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,347 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,347 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,349 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,349 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,350 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,351 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,354 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,383 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,384 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,386 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,387 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,388 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,389 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,390 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,391 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,392 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,393 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,394 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,396 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,397 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,397 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,398 INFO L303 Elim1Store]: Index analysis took 106 ms [2018-02-04 18:55:17,399 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 12 select indices, 12 select index equivalence classes, 37 disjoint index pairs (out of 66 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 128 treesize of output 517 [2018-02-04 18:55:17,399 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:17,470 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:17,498 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:17,499 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:168, output treesize:164 [2018-02-04 18:55:17,597 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 167 treesize of output 138 [2018-02-04 18:55:17,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,608 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,618 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,619 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,626 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,635 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,636 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,638 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,639 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,639 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,640 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,640 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,642 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,644 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,645 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,645 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,646 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,646 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,655 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,656 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,656 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,657 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,657 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,658 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,667 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,668 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,669 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,670 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,671 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,672 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,672 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,673 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:17,674 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 13 select indices, 13 select index equivalence classes, 46 disjoint index pairs (out of 78 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 138 treesize of output 619 [2018-02-04 18:55:17,675 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:17,759 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:17,784 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:17,784 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:180, output treesize:176 [2018-02-04 18:55:19,926 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 179 treesize of output 148 [2018-02-04 18:55:19,932 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,935 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,936 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,938 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,938 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,943 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,944 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,945 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,946 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,947 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,950 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,951 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,953 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,954 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,962 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,964 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,965 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,989 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,990 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,992 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:19,999 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,000 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,002 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,003 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,004 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,005 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,006 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,013 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,014 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,018 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,024 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,026 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,027 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,028 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,029 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,035 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,036 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,037 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,038 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,039 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,071 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,072 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,075 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,080 INFO L303 Elim1Store]: Index analysis took 152 ms [2018-02-04 18:55:20,081 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 14 select indices, 14 select index equivalence classes, 56 disjoint index pairs (out of 91 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 148 treesize of output 731 [2018-02-04 18:55:20,082 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:20,225 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:20,253 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:20,253 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:192, output treesize:188 [2018-02-04 18:55:20,459 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 190 treesize of output 157 [2018-02-04 18:55:20,495 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,496 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,497 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,500 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,501 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,502 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,504 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,507 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,510 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,512 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,513 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,513 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,514 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,517 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,518 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,519 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,520 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,522 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,525 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,526 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,527 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,529 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,533 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,534 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,535 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,536 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,539 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,542 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,543 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,544 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,546 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,547 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,548 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,549 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,552 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,554 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,555 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,556 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,575 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,576 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,577 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,579 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,582 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,583 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,584 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,585 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,586 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,589 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,594 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,624 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,625 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,631 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,633 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:20,634 INFO L303 Elim1Store]: Index analysis took 173 ms [2018-02-04 18:55:20,636 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 67 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 157 treesize of output 841 [2018-02-04 18:55:20,637 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:20,817 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:20,860 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:20,861 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:211, output treesize:207 [2018-02-04 18:55:24,067 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:24,069 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:24,070 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:24,070 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:42, output treesize:27 [2018-02-04 18:55:24,072 WARN L1033 $PredicateComparison]: unable to prove that (exists ((v_DerPreprocessor_2 Int)) (= |c_#memory_$Pointer$.offset| (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base| (let ((.cse0 (+ |c_ldv_kobject_init_internal_#in~kobj.offset| 4))) (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_internal_#in~kobj.base|) (+ |c_ldv_kobject_init_internal_#in~kobj.offset| 12) v_DerPreprocessor_2) .cse0 .cse0) (+ |c_ldv_kobject_init_internal_#in~kobj.offset| 8) .cse0))))) is different from true [2018-02-04 18:55:24,074 WARN L1033 $PredicateComparison]: unable to prove that (exists ((v_DerPreprocessor_2 Int)) (= (store |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base| (let ((.cse0 (+ |c_ldv_kobject_init_#in~kobj.offset| 4))) (store (store (store (select |c_old(#memory_$Pointer$.offset)| |c_ldv_kobject_init_#in~kobj.base|) (+ |c_ldv_kobject_init_#in~kobj.offset| 12) v_DerPreprocessor_2) .cse0 .cse0) (+ |c_ldv_kobject_init_#in~kobj.offset| 8) .cse0))) |c_#memory_$Pointer$.offset|)) is different from true [2018-02-04 18:55:24,093 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,094 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 152 treesize of output 130 [2018-02-04 18:55:24,103 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,104 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,106 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,107 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,107 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,111 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,111 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,116 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,116 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,119 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,122 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,122 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,123 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,123 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,124 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,126 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,131 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,131 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,133 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,134 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,134 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,136 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,136 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,137 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,137 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,138 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,138 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,139 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,139 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,140 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,140 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,141 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,141 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,144 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,144 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,145 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,145 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,146 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,147 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,147 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,148 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,148 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,149 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,150 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,150 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,151 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,151 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,152 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 18:55:24,152 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,153 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,154 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,155 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,155 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,156 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,156 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,157 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,157 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,158 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,158 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,159 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,159 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,160 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,160 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,161 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,161 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,162 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,163 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,163 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,164 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,164 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,165 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,166 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,166 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,167 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,167 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,168 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,168 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,169 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,170 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,170 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,171 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,171 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,172 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,172 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,173 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,174 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,175 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,175 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,176 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,176 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,177 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,177 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,178 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,179 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,179 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,180 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,181 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,181 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,182 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,183 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,183 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,185 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,185 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,186 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,186 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,187 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,187 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,188 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,188 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,189 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,189 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,190 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 18:55:24,207 INFO L303 Elim1Store]: Index analysis took 112 ms [2018-02-04 18:55:24,220 INFO L477 Elim1Store]: Elim1 applied some preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 136 disjoint index pairs (out of 136 index pairs), introduced 2 new quantified variables, introduced 2 case distinctions, treesize of input 130 treesize of output 1088 [2018-02-04 18:55:24,239 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,239 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,240 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,241 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,242 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,242 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,243 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,244 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,245 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,246 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,247 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,247 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,248 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,249 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,250 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,250 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,251 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,252 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,253 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,253 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,254 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,255 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,256 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,256 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,257 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,258 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,258 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,259 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,260 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,261 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,261 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,262 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,263 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,264 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,265 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,265 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,266 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,267 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,267 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,268 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,269 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,270 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,270 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,271 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,272 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,273 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,273 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,274 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,275 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,275 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 18:55:24,276 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,277 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,277 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,278 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,279 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,280 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,281 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,282 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,282 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,283 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,284 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,285 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,285 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,286 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,287 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,288 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,289 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,290 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,291 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,292 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,292 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,293 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,293 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,294 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,295 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,295 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,296 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,297 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,297 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,298 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,299 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,299 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,300 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,301 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,301 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,302 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,302 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,303 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,304 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,305 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,307 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 168 disjoint index pairs (out of 120 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 1031 treesize of output 1060 [2018-02-04 18:55:24,586 WARN L146 SmtUtils]: Spent 275ms on a formula simplification. DAG size of input: 230 DAG size of output 147 [2018-02-04 18:55:24,591 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,592 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,593 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,594 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,594 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,595 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,596 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,596 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,597 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,598 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,599 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,599 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,600 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,600 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,601 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,602 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,603 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,604 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,605 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,606 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,607 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,608 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,608 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,609 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,610 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,611 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,612 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,612 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,613 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,614 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,615 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,616 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,617 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,617 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,618 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,618 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,619 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,619 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,621 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,622 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,622 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,656 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,657 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,657 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,658 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,659 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,659 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,660 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 18:55:24,660 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,661 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,662 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,662 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,664 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,664 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,665 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,666 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,666 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,667 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,667 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:24,671 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 141 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 123 treesize of output 1030 [2018-02-04 18:55:24,673 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:25,104 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:25,620 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,623 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,627 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,630 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,634 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,637 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,641 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,646 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,649 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,652 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,656 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,660 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,663 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,666 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,670 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,674 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,677 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,681 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,685 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,689 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,693 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,696 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,700 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,704 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,709 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,713 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,717 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,721 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,725 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,729 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,733 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,737 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,740 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,744 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,748 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,752 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,756 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,760 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,763 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,768 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,772 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,775 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,779 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,782 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,786 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,790 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,794 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,797 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,801 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,805 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,808 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,812 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,816 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,824 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,827 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,830 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,833 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,838 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,841 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,845 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,845 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 18:55:25,849 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,853 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,857 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,861 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,865 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,869 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,873 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,877 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,881 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,885 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,888 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,892 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,896 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,900 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,904 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,908 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,912 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,916 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,920 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,924 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,928 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,931 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,935 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,939 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,959 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,963 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,966 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,970 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,974 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,978 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,982 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,986 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,990 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:25,998 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,002 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,005 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,009 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,013 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,017 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,021 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,025 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,029 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,033 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,037 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,041 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,049 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,060 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,065 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,069 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,103 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,107 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,128 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,136 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,140 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,143 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,147 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,151 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,154 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,158 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,162 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:26,281 INFO L303 Elim1Store]: Index analysis took 668 ms [2018-02-04 18:55:26,290 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 17 select indices, 17 select index equivalence classes, 136 disjoint index pairs (out of 136 index pairs), introduced 1 new quantified variables, introduced 2 case distinctions, treesize of input 131 treesize of output 1034 [2018-02-04 18:55:27,362 WARN L146 SmtUtils]: Spent 1068ms on a formula simplification. DAG size of input: 280 DAG size of output 196 [2018-02-04 18:55:27,368 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,369 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,369 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,370 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,371 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,371 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,372 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,372 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,373 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,373 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,374 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,375 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,375 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,376 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,376 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,377 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,377 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,378 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,378 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,379 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,379 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,380 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,380 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,381 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,381 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,382 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,383 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,383 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,384 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,384 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,385 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,386 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,386 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,387 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,387 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,388 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,388 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,389 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,389 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,390 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,390 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,391 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,391 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,392 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,393 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,393 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,394 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,394 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,395 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,396 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,396 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,397 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,397 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,398 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,398 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,399 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,400 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,400 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,401 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,401 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,402 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,402 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,403 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,403 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,404 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,404 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,405 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,405 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,406 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,406 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,407 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,408 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,408 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,409 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,409 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,410 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,410 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,411 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,411 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,412 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,412 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,413 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,413 INFO L682 Elim1Store]: detected equality via solver [2018-02-04 18:55:27,414 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,414 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,415 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,415 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,416 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,416 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,417 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,417 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,418 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,418 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,419 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,420 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,420 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,421 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,422 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,423 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,436 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 142 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 267 treesize of output 1152 [2018-02-04 18:55:27,437 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:27,989 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,990 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,991 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,991 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,992 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,993 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,995 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,996 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,997 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,998 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:27,999 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,000 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,000 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,001 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,002 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,002 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,003 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,004 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,005 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,005 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,007 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,008 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,010 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,011 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,011 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,012 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,013 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,014 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,014 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,015 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,016 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,017 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,019 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,020 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,021 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,022 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,023 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,023 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,024 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,025 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,025 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,026 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,027 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,028 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,029 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,029 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,030 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,031 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,032 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,032 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,033 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,034 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,035 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,035 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,036 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,037 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,038 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,040 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,040 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,041 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,042 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,043 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,043 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,044 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,045 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,047 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,048 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,049 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,050 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,051 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,052 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,053 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,054 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,055 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,056 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,057 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,058 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,059 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,060 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,061 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,062 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,064 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,066 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,068 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,070 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,071 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,072 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,084 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,084 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,088 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,091 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,091 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,092 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,093 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,095 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,095 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,096 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:28,114 INFO L303 Elim1Store]: Index analysis took 126 ms [2018-02-04 18:55:28,115 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 16 select indices, 16 select index equivalence classes, 121 disjoint index pairs (out of 120 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 112 treesize of output 992 [2018-02-04 18:55:28,117 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-02-04 18:55:28,480 INFO L267 ElimStorePlain]: Start of recursive call 6: 2 dim-1 vars, End of recursive call: and 2 xjuncts. [2018-02-04 18:55:28,559 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: and 3 xjuncts. [2018-02-04 18:55:28,602 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-02-04 18:55:28,635 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-02-04 18:55:28,636 INFO L202 ElimStorePlain]: Needed 8 recursive calls to eliminate 5 variables, input treesize:171, output treesize:142 [2018-02-04 18:55:30,062 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 141 treesize of output 108 [2018-02-04 18:55:30,066 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,073 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,074 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,075 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,076 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,077 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,077 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,078 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,079 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,080 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,081 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,082 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,083 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,084 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,084 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,085 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,086 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,087 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,088 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,089 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,090 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,091 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,092 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,092 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,092 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,093 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,093 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,094 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,095 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,095 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,096 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,096 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,097 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,098 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,098 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,098 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,099 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,099 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,100 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,101 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,102 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,102 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,103 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,103 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,104 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,104 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,105 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,106 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,107 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,107 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,108 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,109 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,110 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,112 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,113 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,114 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,115 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,116 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,117 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,118 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,119 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,119 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,120 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,121 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,122 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,123 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,123 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,124 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,125 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,126 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,126 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,127 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,128 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,128 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,129 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,130 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,130 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,131 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,132 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,133 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,135 INFO L700 Elim1Store]: detected not equals via solver [2018-02-04 18:55:30,242 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 15 select indices, 15 select index equivalence classes, 106 disjoint index pairs (out of 105 index pairs), introduced 0 new quantified variables, introduced 30 case distinctions, treesize of input 108 treesize of output 902 [2018-02-04 18:55:30,243 WARN L130 XnfTransformerHelper]: expecting exponential blowup for input size 15 [2018-02-04 18:55:30,819 WARN L152 XnfTransformerHelper]: Simplifying disjunction of 32768 conjuctions. This might take some time... Received shutdown request... [2018-02-04 18:58:35,828 INFO L175 TraceCheckSpWp]: Timeout while computing interpolants [2018-02-04 18:58:35,828 WARN L491 AbstractCegarLoop]: Verification canceled [2018-02-04 18:58:35,832 WARN L185 ceAbstractionStarter]: Timeout [2018-02-04 18:58:35,832 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 04.02 06:58:35 BoogieIcfgContainer [2018-02-04 18:58:35,832 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-02-04 18:58:35,832 INFO L168 Benchmark]: Toolchain (without parser) took 212508.87 ms. Allocated memory was 394.3 MB in the beginning and 1.3 GB in the end (delta: 888.1 MB). Free memory was 350.9 MB in the beginning and 818.9 MB in the end (delta: -467.9 MB). Peak memory consumption was 1.4 GB. Max. memory is 5.3 GB. [2018-02-04 18:58:35,834 INFO L168 Benchmark]: CDTParser took 0.19 ms. Allocated memory is still 394.3 MB. Free memory is still 356.2 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 18:58:35,834 INFO L168 Benchmark]: CACSL2BoogieTranslator took 167.97 ms. Allocated memory is still 394.3 MB. Free memory was 350.9 MB in the beginning and 335.1 MB in the end (delta: 15.9 MB). Peak memory consumption was 15.9 MB. Max. memory is 5.3 GB. [2018-02-04 18:58:35,834 INFO L168 Benchmark]: Boogie Preprocessor took 34.15 ms. Allocated memory is still 394.3 MB. Free memory is still 335.1 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-02-04 18:58:35,834 INFO L168 Benchmark]: RCFGBuilder took 327.60 ms. Allocated memory is still 394.3 MB. Free memory was 335.1 MB in the beginning and 302.0 MB in the end (delta: 33.1 MB). Peak memory consumption was 33.1 MB. Max. memory is 5.3 GB. [2018-02-04 18:58:35,834 INFO L168 Benchmark]: TraceAbstraction took 211976.15 ms. Allocated memory was 394.3 MB in the beginning and 1.3 GB in the end (delta: 888.1 MB). Free memory was 299.4 MB in the beginning and 818.9 MB in the end (delta: -519.5 MB). Peak memory consumption was 1.3 GB. Max. memory is 5.3 GB. [2018-02-04 18:58:35,836 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.19 ms. Allocated memory is still 394.3 MB. Free memory is still 356.2 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 167.97 ms. Allocated memory is still 394.3 MB. Free memory was 350.9 MB in the beginning and 335.1 MB in the end (delta: 15.9 MB). Peak memory consumption was 15.9 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 34.15 ms. Allocated memory is still 394.3 MB. Free memory is still 335.1 MB. There was no memory consumed. Max. memory is 5.3 GB. * RCFGBuilder took 327.60 ms. Allocated memory is still 394.3 MB. Free memory was 335.1 MB in the beginning and 302.0 MB in the end (delta: 33.1 MB). Peak memory consumption was 33.1 MB. Max. memory is 5.3 GB. * TraceAbstraction took 211976.15 ms. Allocated memory was 394.3 MB in the beginning and 1.3 GB in the end (delta: 888.1 MB). Free memory was 299.4 MB in the beginning and 818.9 MB in the end (delta: -519.5 MB). Peak memory consumption was 1.3 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1294). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: -1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1411). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1265). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1267). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1344). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that free always succeeds (line 1340). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1339). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1452]: Timeout (TraceAbstraction) Unable to prove that all allocated memory was freed (line 1452). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1100). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - TimeoutResultAtElement [Line: 1]: Timeout (TraceAbstraction) Unable to prove that pointer dereference always succeeds (line 1099). Cancelled while BasicCegarLoop was analyzing trace of length 97 with TraceHistMax 16, while TraceCheckSpWp was constructing forward predicates, while PartialQuantifierElimination was eliminating quantifiers from formula with 0 quantifier alternations, while DnfTransformerHelper was XNF transformer was simplifying 32768 conjuctions. . - StatisticsResult: Ultimate Automizer benchmark data CFG has 19 procedures, 123 locations, 19 error locations. TIMEOUT Result, 211.9s OverallTime, 30 OverallIterations, 16 TraceHistogramMax, 4.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3126 SDtfs, 709 SDslu, 28236 SDs, 0 SdLazy, 7990 SolverSat, 180 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.8s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 1521 GetRequests, 1060 SyntacticMatches, 6 SemanticMatches, 455 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1604 ImplicationChecksByTransitivity, 4.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=150occurred in iteration=29, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.1s AutomataMinimizationTime, 29 MinimizatonAttempts, 46 StatesRemovedByMinimization, 8 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.1s SsaConstructionTime, 0.6s SatisfiabilityAnalysisTime, 4.3s InterpolantComputationTime, 2807 NumberOfCodeBlocks, 2787 NumberOfCodeBlocksAsserted, 66 NumberOfCheckSat, 2763 ConstructedInterpolants, 91 QuantifiedInterpolants, 404692 SizeOfPredicates, 67 NumberOfNonLiveVariables, 5545 ConjunctsInSsa, 382 ConjunctsInUnsatCore, 44 InterpolantComputations, 18 PerfectInterpolantSequences, 187/1477 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_5_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-Benchmark-0-2018-02-04_18-58-35-842.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/memleaks_test22_5_false-valid-deref.i_svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-02-04_18-58-35-842.csv Completed graceful shutdown