java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf -i ../../../trunk/examples/svcomp/list-ext-properties/960521-1_1_true-valid-memsafety.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-666feb3-m [2018-04-11 16:15:28,392 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-11 16:15:28,393 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-11 16:15:28,407 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-11 16:15:28,407 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-11 16:15:28,408 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-11 16:15:28,409 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-11 16:15:28,411 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-11 16:15:28,412 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-11 16:15:28,413 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-11 16:15:28,414 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-11 16:15:28,414 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-11 16:15:28,415 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-11 16:15:28,416 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-11 16:15:28,417 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-11 16:15:28,418 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-11 16:15:28,420 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-11 16:15:28,421 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-11 16:15:28,422 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-11 16:15:28,423 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-11 16:15:28,425 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-11 16:15:28,425 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-11 16:15:28,425 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-11 16:15:28,426 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-11 16:15:28,427 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-11 16:15:28,428 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-11 16:15:28,428 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-11 16:15:28,429 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-11 16:15:28,429 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-11 16:15:28,429 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-11 16:15:28,430 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-11 16:15:28,430 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_SmtInterpol_NoArray.epf [2018-04-11 16:15:28,451 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-11 16:15:28,451 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-11 16:15:28,452 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-11 16:15:28,452 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-11 16:15:28,453 INFO L133 SettingsManager]: * Use SBE=true [2018-04-11 16:15:28,453 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-11 16:15:28,453 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-11 16:15:28,453 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-11 16:15:28,453 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-11 16:15:28,454 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-11 16:15:28,454 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-11 16:15:28,454 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-11 16:15:28,454 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-11 16:15:28,454 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-11 16:15:28,454 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-11 16:15:28,454 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-11 16:15:28,455 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-11 16:15:28,455 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-11 16:15:28,455 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-11 16:15:28,455 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 16:15:28,455 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-11 16:15:28,455 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-11 16:15:28,456 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-11 16:15:28,456 INFO L133 SettingsManager]: * Trace refinement strategy=SMTINTERPOL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-11 16:15:28,487 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-11 16:15:28,497 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-11 16:15:28,500 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-11 16:15:28,502 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-11 16:15:28,502 INFO L276 PluginConnector]: CDTParser initialized [2018-04-11 16:15:28,503 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/list-ext-properties/960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:28,875 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG969af5615 [2018-04-11 16:15:29,002 INFO L287 CDTParser]: IsIndexed: true [2018-04-11 16:15:29,003 INFO L288 CDTParser]: Found 1 translation units. [2018-04-11 16:15:29,003 INFO L168 CDTParser]: Scanning 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,011 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-11 16:15:29,012 INFO L215 ultiparseSymbolTable]: [2018-04-11 16:15:29,012 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-11 16:15:29,012 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,012 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_f___________true_valid_memsafety_i__foo ('foo') in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,012 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-11 16:15:29,012 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint8_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____daddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____key_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int8_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_int in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__loff_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____clockid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__clockid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____blkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,013 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fd_mask in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fsid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int16_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_cond_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_spinlock_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__id_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____clock_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____WAIT_STATUS in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,014 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__dev_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_condattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_attr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____pid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ushort in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsblkcnt64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__wchar_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,015 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__register_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____useconds_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____swblk_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_barrier_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____nlink_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__timer_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int32_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__sigset_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____gid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,016 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____sig_atomic_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__key_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____ssize_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____ino64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int32_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__nlink_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__uint in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ssize_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,017 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_rwlockattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____off_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____blkcnt64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fd_mask in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fsfilcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____suseconds_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__time_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____rlim64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__caddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____id_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,018 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_rwlock_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____qaddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____blksize_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__blksize_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int32_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__div_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint32_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fsblkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____timer_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____off64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____time_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,019 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____intptr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_mutexattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_quad_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__size_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsfilcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__n in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_char in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int16_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsblkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__int8_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_key_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,020 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__lldiv_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____rlim_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____socklen_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__uid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____pthread_list_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_barrierattr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__b in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__a in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ldiv_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsfilcnt64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_mutex_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,021 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ino_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_short in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__off_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__gid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int8_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_char in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__blkcnt_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_int64_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____uint16_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__daddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____mode_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pthread_once_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_long in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____int16_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____caddr_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,022 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____ino_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____dev_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____loff_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____sigset_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__fd_set in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____u_short in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i____fsid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__clock_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__suseconds_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__mode_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__ulong in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__u_long in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,023 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_f___________true_valid_memsafety_i__pid_t in 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,051 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAG969af5615 [2018-04-11 16:15:29,055 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-11 16:15:29,056 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-11 16:15:29,057 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-11 16:15:29,057 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-11 16:15:29,061 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-11 16:15:29,062 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,064 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@61da3f10 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29, skipping insertion in model container [2018-04-11 16:15:29,064 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,075 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 16:15:29,101 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 16:15:29,246 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 16:15:29,285 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 16:15:29,291 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-11 16:15:29,334 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29 WrapperNode [2018-04-11 16:15:29,334 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-11 16:15:29,334 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-11 16:15:29,335 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-11 16:15:29,335 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-11 16:15:29,346 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,346 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,358 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,359 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,367 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,372 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,374 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... [2018-04-11 16:15:29,377 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-11 16:15:29,377 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-11 16:15:29,377 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-11 16:15:29,377 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-11 16:15:29,378 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 16:15:29,471 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-11 16:15:29,472 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-11 16:15:29,472 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f___________true_valid_memsafety_i__foo [2018-04-11 16:15:29,472 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_error [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-11 16:15:29,472 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-11 16:15:29,473 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-11 16:15:29,474 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-11 16:15:29,475 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-11 16:15:29,476 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-11 16:15:29,477 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure __secure_getenv [2018-04-11 16:15:29,478 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-11 16:15:29,479 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-11 16:15:29,480 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-11 16:15:29,481 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_f___________true_valid_memsafety_i__foo [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-11 16:15:29,482 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-11 16:15:29,483 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-11 16:15:29,483 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-11 16:15:29,483 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-11 16:15:29,483 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-11 16:15:29,768 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-11 16:15:29,769 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 04:15:29 BoogieIcfgContainer [2018-04-11 16:15:29,769 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-11 16:15:29,770 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-11 16:15:29,770 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-11 16:15:29,772 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-11 16:15:29,772 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 11.04 04:15:29" (1/3) ... [2018-04-11 16:15:29,773 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@54880505 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 04:15:29, skipping insertion in model container [2018-04-11 16:15:29,773 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 04:15:29" (2/3) ... [2018-04-11 16:15:29,773 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@54880505 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 04:15:29, skipping insertion in model container [2018-04-11 16:15:29,773 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 04:15:29" (3/3) ... [2018-04-11 16:15:29,775 INFO L107 eAbstractionObserver]: Analyzing ICFG 960521-1_1_true-valid-memsafety.i [2018-04-11 16:15:29,781 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-11 16:15:29,787 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 19 error locations. [2018-04-11 16:15:29,813 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-11 16:15:29,813 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-11 16:15:29,813 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-11 16:15:29,813 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-11 16:15:29,813 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-11 16:15:29,814 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-11 16:15:29,814 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-11 16:15:29,814 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-11 16:15:29,814 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-11 16:15:29,814 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-11 16:15:29,824 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states. [2018-04-11 16:15:29,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 13 [2018-04-11 16:15:29,831 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:29,832 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:29,832 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:29,835 INFO L82 PathProgramCache]: Analyzing trace with hash 284919364, now seen corresponding path program 1 times [2018-04-11 16:15:29,836 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:29,836 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:29,866 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:29,866 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:29,866 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:29,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:29,901 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:29,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:29,926 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:29,927 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-11 16:15:29,928 INFO L442 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-04-11 16:15:29,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-04-11 16:15:29,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-04-11 16:15:29,939 INFO L87 Difference]: Start difference. First operand 67 states. Second operand 2 states. [2018-04-11 16:15:29,954 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:29,955 INFO L93 Difference]: Finished difference Result 67 states and 70 transitions. [2018-04-11 16:15:29,955 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-04-11 16:15:29,956 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 12 [2018-04-11 16:15:29,956 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:29,963 INFO L225 Difference]: With dead ends: 67 [2018-04-11 16:15:29,963 INFO L226 Difference]: Without dead ends: 64 [2018-04-11 16:15:29,964 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-04-11 16:15:29,976 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-04-11 16:15:29,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 64. [2018-04-11 16:15:29,989 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 64 states. [2018-04-11 16:15:29,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 64 states to 64 states and 67 transitions. [2018-04-11 16:15:29,992 INFO L78 Accepts]: Start accepts. Automaton has 64 states and 67 transitions. Word has length 12 [2018-04-11 16:15:29,992 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:29,992 INFO L459 AbstractCegarLoop]: Abstraction has 64 states and 67 transitions. [2018-04-11 16:15:29,992 INFO L460 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-04-11 16:15:29,992 INFO L276 IsEmpty]: Start isEmpty. Operand 64 states and 67 transitions. [2018-04-11 16:15:29,993 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-04-11 16:15:29,993 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:29,993 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:29,993 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:29,993 INFO L82 PathProgramCache]: Analyzing trace with hash 824267754, now seen corresponding path program 1 times [2018-04-11 16:15:29,993 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:29,993 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:29,994 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:29,994 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:29,994 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,015 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,015 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:30,062 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:30,063 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:30,063 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 16:15:30,064 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 16:15:30,064 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 16:15:30,065 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 16:15:30,065 INFO L87 Difference]: Start difference. First operand 64 states and 67 transitions. Second operand 4 states. [2018-04-11 16:15:30,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:30,148 INFO L93 Difference]: Finished difference Result 63 states and 66 transitions. [2018-04-11 16:15:30,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 16:15:30,148 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-04-11 16:15:30,148 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:30,149 INFO L225 Difference]: With dead ends: 63 [2018-04-11 16:15:30,149 INFO L226 Difference]: Without dead ends: 63 [2018-04-11 16:15:30,150 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 16:15:30,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-04-11 16:15:30,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-04-11 16:15:30,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-04-11 16:15:30,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 66 transitions. [2018-04-11 16:15:30,154 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 66 transitions. Word has length 14 [2018-04-11 16:15:30,155 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:30,155 INFO L459 AbstractCegarLoop]: Abstraction has 63 states and 66 transitions. [2018-04-11 16:15:30,155 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 16:15:30,155 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 66 transitions. [2018-04-11 16:15:30,155 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-04-11 16:15:30,155 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:30,155 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:30,155 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:30,156 INFO L82 PathProgramCache]: Analyzing trace with hash 824267755, now seen corresponding path program 1 times [2018-04-11 16:15:30,156 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:30,156 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:30,157 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:30,157 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,169 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,169 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:30,214 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:30,214 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:30,214 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 16:15:30,214 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 16:15:30,214 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 16:15:30,214 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 16:15:30,214 INFO L87 Difference]: Start difference. First operand 63 states and 66 transitions. Second operand 5 states. [2018-04-11 16:15:30,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:30,266 INFO L93 Difference]: Finished difference Result 62 states and 65 transitions. [2018-04-11 16:15:30,267 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 16:15:30,267 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-04-11 16:15:30,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:30,268 INFO L225 Difference]: With dead ends: 62 [2018-04-11 16:15:30,268 INFO L226 Difference]: Without dead ends: 62 [2018-04-11 16:15:30,268 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 6 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-11 16:15:30,268 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 62 states. [2018-04-11 16:15:30,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 62 to 62. [2018-04-11 16:15:30,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 62 states. [2018-04-11 16:15:30,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 62 states to 62 states and 65 transitions. [2018-04-11 16:15:30,273 INFO L78 Accepts]: Start accepts. Automaton has 62 states and 65 transitions. Word has length 14 [2018-04-11 16:15:30,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:30,273 INFO L459 AbstractCegarLoop]: Abstraction has 62 states and 65 transitions. [2018-04-11 16:15:30,273 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 16:15:30,273 INFO L276 IsEmpty]: Start isEmpty. Operand 62 states and 65 transitions. [2018-04-11 16:15:30,274 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-11 16:15:30,274 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:30,274 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:30,274 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:30,274 INFO L82 PathProgramCache]: Analyzing trace with hash 1288303895, now seen corresponding path program 1 times [2018-04-11 16:15:30,274 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:30,275 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:30,275 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,275 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:30,276 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,290 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:30,295 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:30,295 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:30,295 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:30,296 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:30,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,346 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:30,374 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:30,376 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,378 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,378 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-11 16:15:30,402 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:30,403 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:30,404 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-11 16:15:30,404 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,409 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:30,409 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:17, output treesize:15 [2018-04-11 16:15:30,437 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:30,437 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:30,438 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 16:15:30,438 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 16:15:30,438 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 16:15:30,438 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-04-11 16:15:30,438 INFO L87 Difference]: Start difference. First operand 62 states and 65 transitions. Second operand 5 states. [2018-04-11 16:15:30,511 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:30,511 INFO L93 Difference]: Finished difference Result 59 states and 62 transitions. [2018-04-11 16:15:30,512 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 16:15:30,512 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-04-11 16:15:30,512 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:30,513 INFO L225 Difference]: With dead ends: 59 [2018-04-11 16:15:30,513 INFO L226 Difference]: Without dead ends: 59 [2018-04-11 16:15:30,513 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 21 GetRequests, 16 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=18, Invalid=24, Unknown=0, NotChecked=0, Total=42 [2018-04-11 16:15:30,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-04-11 16:15:30,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-04-11 16:15:30,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-04-11 16:15:30,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 62 transitions. [2018-04-11 16:15:30,517 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 62 transitions. Word has length 20 [2018-04-11 16:15:30,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:30,517 INFO L459 AbstractCegarLoop]: Abstraction has 59 states and 62 transitions. [2018-04-11 16:15:30,517 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 16:15:30,518 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 62 transitions. [2018-04-11 16:15:30,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-04-11 16:15:30,518 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:30,518 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:30,518 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:30,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1288303896, now seen corresponding path program 1 times [2018-04-11 16:15:30,519 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:30,519 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:30,520 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,520 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:30,520 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,531 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,532 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:30,536 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:30,536 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:30,536 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:30,537 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:30,563 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,570 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:30,587 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 16:15:30,587 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,593 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:30,594 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,598 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,599 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-11 16:15:30,617 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:30,618 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-11 16:15:30,618 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,628 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:30,629 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:30,630 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:30,630 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:30,649 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:30,649 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-04-11 16:15:30,710 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:30,710 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:30,711 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-11 16:15:30,711 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 16:15:30,711 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 16:15:30,711 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-04-11 16:15:30,712 INFO L87 Difference]: Start difference. First operand 59 states and 62 transitions. Second operand 7 states. [2018-04-11 16:15:30,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:30,932 INFO L93 Difference]: Finished difference Result 69 states and 73 transitions. [2018-04-11 16:15:30,932 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 16:15:30,932 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 20 [2018-04-11 16:15:30,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:30,934 INFO L225 Difference]: With dead ends: 69 [2018-04-11 16:15:30,934 INFO L226 Difference]: Without dead ends: 69 [2018-04-11 16:15:30,935 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 24 GetRequests, 14 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-04-11 16:15:30,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-04-11 16:15:30,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 60. [2018-04-11 16:15:30,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-04-11 16:15:30,940 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 63 transitions. [2018-04-11 16:15:30,941 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 63 transitions. Word has length 20 [2018-04-11 16:15:30,941 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:30,941 INFO L459 AbstractCegarLoop]: Abstraction has 60 states and 63 transitions. [2018-04-11 16:15:30,941 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 16:15:30,941 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 63 transitions. [2018-04-11 16:15:30,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-04-11 16:15:30,942 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:30,942 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:30,942 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:30,942 INFO L82 PathProgramCache]: Analyzing trace with hash 1040443247, now seen corresponding path program 1 times [2018-04-11 16:15:30,942 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:30,943 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:30,943 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,943 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:30,944 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:30,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:30,953 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:31,007 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:31,008 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:31,008 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:31,009 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:31,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:31,030 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:31,058 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:31,059 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:31,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [7] total 9 [2018-04-11 16:15:31,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 16:15:31,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 16:15:31,060 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-11 16:15:31,060 INFO L87 Difference]: Start difference. First operand 60 states and 63 transitions. Second operand 9 states. [2018-04-11 16:15:31,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:31,141 INFO L93 Difference]: Finished difference Result 108 states and 112 transitions. [2018-04-11 16:15:31,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 16:15:31,142 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 24 [2018-04-11 16:15:31,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:31,143 INFO L225 Difference]: With dead ends: 108 [2018-04-11 16:15:31,143 INFO L226 Difference]: Without dead ends: 108 [2018-04-11 16:15:31,143 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 22 SyntacticMatches, 1 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=91, Unknown=0, NotChecked=0, Total=132 [2018-04-11 16:15:31,143 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108 states. [2018-04-11 16:15:31,149 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108 to 82. [2018-04-11 16:15:31,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-04-11 16:15:31,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 86 transitions. [2018-04-11 16:15:31,150 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 86 transitions. Word has length 24 [2018-04-11 16:15:31,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:31,150 INFO L459 AbstractCegarLoop]: Abstraction has 82 states and 86 transitions. [2018-04-11 16:15:31,150 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 16:15:31,150 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 86 transitions. [2018-04-11 16:15:31,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-04-11 16:15:31,151 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:31,151 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:31,151 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:31,151 INFO L82 PathProgramCache]: Analyzing trace with hash 1635534113, now seen corresponding path program 1 times [2018-04-11 16:15:31,151 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:31,151 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:31,152 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:31,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:31,152 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:31,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:31,163 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:31,174 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:31,174 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:31,174 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:31,175 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:31,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:31,200 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:31,212 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 16:15:31,212 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:31,217 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:31,218 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:31,225 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:31,225 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:21, output treesize:19 [2018-04-11 16:15:31,258 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:31,259 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-11 16:15:31,259 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:31,275 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:31,276 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:31,277 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:31,277 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:31,283 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:31,283 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:32, output treesize:25 [2018-04-11 16:15:31,386 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:31,386 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:31,386 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9] total 9 [2018-04-11 16:15:31,386 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-11 16:15:31,386 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-11 16:15:31,387 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=64, Unknown=0, NotChecked=0, Total=90 [2018-04-11 16:15:31,387 INFO L87 Difference]: Start difference. First operand 82 states and 86 transitions. Second operand 10 states. [2018-04-11 16:15:31,758 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:31,758 INFO L93 Difference]: Finished difference Result 119 states and 123 transitions. [2018-04-11 16:15:31,758 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-11 16:15:31,759 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 27 [2018-04-11 16:15:31,759 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:31,759 INFO L225 Difference]: With dead ends: 119 [2018-04-11 16:15:31,759 INFO L226 Difference]: Without dead ends: 119 [2018-04-11 16:15:31,759 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 33 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 39 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=83, Invalid=189, Unknown=0, NotChecked=0, Total=272 [2018-04-11 16:15:31,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-04-11 16:15:31,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 88. [2018-04-11 16:15:31,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 88 states. [2018-04-11 16:15:31,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 88 states to 88 states and 92 transitions. [2018-04-11 16:15:31,763 INFO L78 Accepts]: Start accepts. Automaton has 88 states and 92 transitions. Word has length 27 [2018-04-11 16:15:31,763 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:31,763 INFO L459 AbstractCegarLoop]: Abstraction has 88 states and 92 transitions. [2018-04-11 16:15:31,763 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-11 16:15:31,763 INFO L276 IsEmpty]: Start isEmpty. Operand 88 states and 92 transitions. [2018-04-11 16:15:31,764 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 16:15:31,764 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:31,764 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:31,764 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:31,764 INFO L82 PathProgramCache]: Analyzing trace with hash -1703872188, now seen corresponding path program 1 times [2018-04-11 16:15:31,764 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:31,764 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:31,765 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:31,765 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:31,765 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:31,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:31,770 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:31,827 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:31,827 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:31,827 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 16:15:31,827 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 16:15:31,827 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 16:15:31,827 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 16:15:31,828 INFO L87 Difference]: Start difference. First operand 88 states and 92 transitions. Second operand 4 states. [2018-04-11 16:15:31,856 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:31,857 INFO L93 Difference]: Finished difference Result 85 states and 89 transitions. [2018-04-11 16:15:31,857 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 16:15:31,857 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 29 [2018-04-11 16:15:31,857 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:31,857 INFO L225 Difference]: With dead ends: 85 [2018-04-11 16:15:31,857 INFO L226 Difference]: Without dead ends: 85 [2018-04-11 16:15:31,858 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 16:15:31,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-11 16:15:31,860 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-11 16:15:31,860 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-11 16:15:31,861 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 89 transitions. [2018-04-11 16:15:31,861 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 89 transitions. Word has length 29 [2018-04-11 16:15:31,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:31,861 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 89 transitions. [2018-04-11 16:15:31,861 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 16:15:31,861 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 89 transitions. [2018-04-11 16:15:31,862 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-04-11 16:15:31,862 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:31,862 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:31,862 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:31,862 INFO L82 PathProgramCache]: Analyzing trace with hash -1703872187, now seen corresponding path program 1 times [2018-04-11 16:15:31,862 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:31,862 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:31,863 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:31,863 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:31,863 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:31,871 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:31,871 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:31,935 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:31,936 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:31,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-11 16:15:31,936 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 16:15:31,936 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 16:15:31,936 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-04-11 16:15:31,937 INFO L87 Difference]: Start difference. First operand 85 states and 89 transitions. Second operand 7 states. [2018-04-11 16:15:32,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:32,015 INFO L93 Difference]: Finished difference Result 81 states and 84 transitions. [2018-04-11 16:15:32,015 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 16:15:32,015 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-04-11 16:15:32,015 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:32,016 INFO L225 Difference]: With dead ends: 81 [2018-04-11 16:15:32,016 INFO L226 Difference]: Without dead ends: 81 [2018-04-11 16:15:32,016 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=31, Invalid=41, Unknown=0, NotChecked=0, Total=72 [2018-04-11 16:15:32,016 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-04-11 16:15:32,018 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-04-11 16:15:32,018 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-11 16:15:32,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 84 transitions. [2018-04-11 16:15:32,020 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 84 transitions. Word has length 29 [2018-04-11 16:15:32,021 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:32,021 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 84 transitions. [2018-04-11 16:15:32,021 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 16:15:32,021 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 84 transitions. [2018-04-11 16:15:32,021 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-04-11 16:15:32,021 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:32,021 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:32,021 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:32,021 INFO L82 PathProgramCache]: Analyzing trace with hash -1280430239, now seen corresponding path program 1 times [2018-04-11 16:15:32,022 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:32,022 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:32,022 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,022 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:32,022 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:32,032 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:32,064 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:32,065 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:32,065 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-11 16:15:32,065 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 16:15:32,065 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 16:15:32,065 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 16:15:32,066 INFO L87 Difference]: Start difference. First operand 81 states and 84 transitions. Second operand 4 states. [2018-04-11 16:15:32,145 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:32,145 INFO L93 Difference]: Finished difference Result 100 states and 102 transitions. [2018-04-11 16:15:32,145 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 16:15:32,146 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2018-04-11 16:15:32,146 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:32,146 INFO L225 Difference]: With dead ends: 100 [2018-04-11 16:15:32,146 INFO L226 Difference]: Without dead ends: 100 [2018-04-11 16:15:32,146 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-11 16:15:32,146 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-04-11 16:15:32,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 83. [2018-04-11 16:15:32,149 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 83 states. [2018-04-11 16:15:32,150 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 83 states to 83 states and 86 transitions. [2018-04-11 16:15:32,150 INFO L78 Accepts]: Start accepts. Automaton has 83 states and 86 transitions. Word has length 30 [2018-04-11 16:15:32,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:32,150 INFO L459 AbstractCegarLoop]: Abstraction has 83 states and 86 transitions. [2018-04-11 16:15:32,150 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 16:15:32,150 INFO L276 IsEmpty]: Start isEmpty. Operand 83 states and 86 transitions. [2018-04-11 16:15:32,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-04-11 16:15:32,151 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:32,151 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:32,151 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:32,151 INFO L82 PathProgramCache]: Analyzing trace with hash 294456056, now seen corresponding path program 2 times [2018-04-11 16:15:32,151 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:32,152 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:32,152 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,152 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:32,152 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:32,161 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:32,214 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 8 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:32,214 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:32,215 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:32,215 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 16:15:32,236 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 16:15:32,236 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:32,238 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:32,270 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:32,271 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:32,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 7] total 12 [2018-04-11 16:15:32,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 16:15:32,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 16:15:32,272 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-04-11 16:15:32,272 INFO L87 Difference]: Start difference. First operand 83 states and 86 transitions. Second operand 12 states. [2018-04-11 16:15:32,491 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:32,491 INFO L93 Difference]: Finished difference Result 151 states and 153 transitions. [2018-04-11 16:15:32,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-11 16:15:32,491 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 31 [2018-04-11 16:15:32,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:32,492 INFO L225 Difference]: With dead ends: 151 [2018-04-11 16:15:32,492 INFO L226 Difference]: Without dead ends: 151 [2018-04-11 16:15:32,492 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 48 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 56 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=102, Invalid=278, Unknown=0, NotChecked=0, Total=380 [2018-04-11 16:15:32,492 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-04-11 16:15:32,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 113. [2018-04-11 16:15:32,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-11 16:15:32,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 118 transitions. [2018-04-11 16:15:32,499 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 118 transitions. Word has length 31 [2018-04-11 16:15:32,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:32,499 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 118 transitions. [2018-04-11 16:15:32,499 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 16:15:32,499 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 118 transitions. [2018-04-11 16:15:32,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-11 16:15:32,503 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:32,503 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:32,503 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:32,503 INFO L82 PathProgramCache]: Analyzing trace with hash 1815499577, now seen corresponding path program 1 times [2018-04-11 16:15:32,503 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:32,503 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:32,504 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,504 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:32,504 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:32,511 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:32,601 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-11 16:15:32,601 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:32,601 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 16:15:32,602 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 16:15:32,602 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 16:15:32,602 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=45, Unknown=0, NotChecked=0, Total=72 [2018-04-11 16:15:32,602 INFO L87 Difference]: Start difference. First operand 113 states and 118 transitions. Second operand 9 states. [2018-04-11 16:15:32,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:32,753 INFO L93 Difference]: Finished difference Result 132 states and 135 transitions. [2018-04-11 16:15:32,754 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 16:15:32,754 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-04-11 16:15:32,754 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:32,754 INFO L225 Difference]: With dead ends: 132 [2018-04-11 16:15:32,754 INFO L226 Difference]: Without dead ends: 132 [2018-04-11 16:15:32,755 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 10 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=41, Invalid=69, Unknown=0, NotChecked=0, Total=110 [2018-04-11 16:15:32,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 132 states. [2018-04-11 16:15:32,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 132 to 114. [2018-04-11 16:15:32,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-04-11 16:15:32,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 118 transitions. [2018-04-11 16:15:32,757 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 118 transitions. Word has length 34 [2018-04-11 16:15:32,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:32,757 INFO L459 AbstractCegarLoop]: Abstraction has 114 states and 118 transitions. [2018-04-11 16:15:32,757 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 16:15:32,757 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 118 transitions. [2018-04-11 16:15:32,758 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-11 16:15:32,758 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:32,758 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:32,758 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:32,758 INFO L82 PathProgramCache]: Analyzing trace with hash -1628225274, now seen corresponding path program 3 times [2018-04-11 16:15:32,758 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:32,758 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:32,759 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,759 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:32,759 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:32,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:32,767 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:32,771 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:32,771 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:32,772 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:32,772 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 16:15:32,791 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-04-11 16:15:32,791 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:32,793 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:32,823 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 16:15:32,823 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:32,829 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:32,829 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:32,833 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:32,833 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-11 16:15:32,847 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:32,848 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-11 16:15:32,848 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:32,857 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:32,858 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:32,858 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:32,859 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:32,864 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:32,864 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:29, output treesize:22 [2018-04-11 16:15:32,952 INFO L134 CoverageAnalysis]: Checked inductivity of 19 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-11 16:15:32,953 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:32,953 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7] total 7 [2018-04-11 16:15:32,953 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 16:15:32,953 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 16:15:32,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-04-11 16:15:32,954 INFO L87 Difference]: Start difference. First operand 114 states and 118 transitions. Second operand 8 states. [2018-04-11 16:15:33,167 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:33,167 INFO L93 Difference]: Finished difference Result 114 states and 118 transitions. [2018-04-11 16:15:33,168 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 16:15:33,168 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 34 [2018-04-11 16:15:33,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:33,168 INFO L225 Difference]: With dead ends: 114 [2018-04-11 16:15:33,168 INFO L226 Difference]: Without dead ends: 114 [2018-04-11 16:15:33,169 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=55, Invalid=127, Unknown=0, NotChecked=0, Total=182 [2018-04-11 16:15:33,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-04-11 16:15:33,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 112. [2018-04-11 16:15:33,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-04-11 16:15:33,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-04-11 16:15:33,171 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 34 [2018-04-11 16:15:33,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:33,172 INFO L459 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-04-11 16:15:33,172 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 16:15:33,172 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-04-11 16:15:33,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-11 16:15:33,173 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:33,173 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:33,173 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:33,173 INFO L82 PathProgramCache]: Analyzing trace with hash 1135421431, now seen corresponding path program 1 times [2018-04-11 16:15:33,173 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:33,173 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:33,174 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,174 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:33,174 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,181 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:33,227 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:33,227 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:33,227 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 16:15:33,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 16:15:33,228 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 16:15:33,228 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-11 16:15:33,228 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 6 states. [2018-04-11 16:15:33,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:33,275 INFO L93 Difference]: Finished difference Result 111 states and 115 transitions. [2018-04-11 16:15:33,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 16:15:33,275 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 35 [2018-04-11 16:15:33,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:33,276 INFO L225 Difference]: With dead ends: 111 [2018-04-11 16:15:33,276 INFO L226 Difference]: Without dead ends: 111 [2018-04-11 16:15:33,276 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=29, Invalid=43, Unknown=0, NotChecked=0, Total=72 [2018-04-11 16:15:33,276 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-04-11 16:15:33,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-04-11 16:15:33,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-04-11 16:15:33,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 115 transitions. [2018-04-11 16:15:33,279 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 115 transitions. Word has length 35 [2018-04-11 16:15:33,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:33,279 INFO L459 AbstractCegarLoop]: Abstraction has 111 states and 115 transitions. [2018-04-11 16:15:33,279 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 16:15:33,279 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 115 transitions. [2018-04-11 16:15:33,280 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-04-11 16:15:33,280 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:33,280 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:33,280 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:33,280 INFO L82 PathProgramCache]: Analyzing trace with hash 1123969771, now seen corresponding path program 1 times [2018-04-11 16:15:33,280 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:33,280 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:33,281 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,281 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:33,281 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,289 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:33,301 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:33,301 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:33,301 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:33,302 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:33,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,315 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:33,350 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 15 [2018-04-11 16:15:33,352 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 3 [2018-04-11 16:15:33,352 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,354 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,366 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,366 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:25, output treesize:3 [2018-04-11 16:15:33,370 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:33,370 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:33,370 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-11 16:15:33,370 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 16:15:33,370 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 16:15:33,370 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-04-11 16:15:33,370 INFO L87 Difference]: Start difference. First operand 111 states and 115 transitions. Second operand 7 states. [2018-04-11 16:15:33,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:33,424 INFO L93 Difference]: Finished difference Result 122 states and 125 transitions. [2018-04-11 16:15:33,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-11 16:15:33,424 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 35 [2018-04-11 16:15:33,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:33,425 INFO L225 Difference]: With dead ends: 122 [2018-04-11 16:15:33,425 INFO L226 Difference]: Without dead ends: 122 [2018-04-11 16:15:33,425 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 37 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=54, Unknown=0, NotChecked=0, Total=90 [2018-04-11 16:15:33,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-04-11 16:15:33,427 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 112. [2018-04-11 16:15:33,428 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 112 states. [2018-04-11 16:15:33,428 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112 states to 112 states and 116 transitions. [2018-04-11 16:15:33,429 INFO L78 Accepts]: Start accepts. Automaton has 112 states and 116 transitions. Word has length 35 [2018-04-11 16:15:33,429 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:33,429 INFO L459 AbstractCegarLoop]: Abstraction has 112 states and 116 transitions. [2018-04-11 16:15:33,429 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 16:15:33,429 INFO L276 IsEmpty]: Start isEmpty. Operand 112 states and 116 transitions. [2018-04-11 16:15:33,430 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-04-11 16:15:33,430 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:33,430 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:33,430 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:33,430 INFO L82 PathProgramCache]: Analyzing trace with hash 838326115, now seen corresponding path program 1 times [2018-04-11 16:15:33,430 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:33,430 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:33,431 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,431 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:33,431 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,437 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:33,440 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:33,440 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:33,440 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:33,441 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:33,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,460 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:33,464 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:33,465 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,466 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,466 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:6, output treesize:5 [2018-04-11 16:15:33,474 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:33,475 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:33,476 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:33,476 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,477 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,477 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:11, output treesize:4 [2018-04-11 16:15:33,504 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:33,505 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 2 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 21 [2018-04-11 16:15:33,505 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,508 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:33,509 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 2 variables, input treesize:16, output treesize:11 [2018-04-11 16:15:33,516 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:33,516 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:33,516 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-11 16:15:33,516 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 16:15:33,517 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 16:15:33,517 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-04-11 16:15:33,517 INFO L87 Difference]: Start difference. First operand 112 states and 116 transitions. Second operand 8 states. [2018-04-11 16:15:33,638 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:33,638 INFO L93 Difference]: Finished difference Result 111 states and 115 transitions. [2018-04-11 16:15:33,639 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-11 16:15:33,639 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 36 [2018-04-11 16:15:33,639 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:33,640 INFO L225 Difference]: With dead ends: 111 [2018-04-11 16:15:33,640 INFO L226 Difference]: Without dead ends: 111 [2018-04-11 16:15:33,640 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=68, Invalid=172, Unknown=0, NotChecked=0, Total=240 [2018-04-11 16:15:33,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111 states. [2018-04-11 16:15:33,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111 to 111. [2018-04-11 16:15:33,642 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-04-11 16:15:33,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 115 transitions. [2018-04-11 16:15:33,643 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 115 transitions. Word has length 36 [2018-04-11 16:15:33,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:33,653 INFO L459 AbstractCegarLoop]: Abstraction has 111 states and 115 transitions. [2018-04-11 16:15:33,653 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 16:15:33,653 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 115 transitions. [2018-04-11 16:15:33,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-04-11 16:15:33,654 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:33,654 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:33,654 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:33,654 INFO L82 PathProgramCache]: Analyzing trace with hash -661412069, now seen corresponding path program 1 times [2018-04-11 16:15:33,654 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:33,655 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:33,655 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,655 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:33,655 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:33,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,664 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:33,667 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:33,667 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:33,667 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:33,668 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:33,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:33,691 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:33,739 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:33,740 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 20 treesize of output 27 [2018-04-11 16:15:33,742 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 15 [2018-04-11 16:15:33,742 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,744 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,747 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:33,748 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:27, output treesize:19 [2018-04-11 16:15:33,771 WARN L1033 $PredicateComparison]: unable to prove that (and (not (= 0 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base)) (exists ((~__U_MULTI_f___________true_valid_memsafety_i__a~0.base Int)) (let ((.cse0 (store |c_old(#valid)| ~__U_MULTI_f___________true_valid_memsafety_i__a~0.base 1))) (and (= (store (store .cse0 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base 1) ~__U_MULTI_f___________true_valid_memsafety_i__a~0.base 0) |c_#valid|) (= 0 (select .cse0 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base)) (= (select |c_old(#valid)| ~__U_MULTI_f___________true_valid_memsafety_i__a~0.base) 0))))) is different from true [2018-04-11 16:15:33,803 WARN L1033 $PredicateComparison]: unable to prove that (exists ((~__U_MULTI_f___________true_valid_memsafety_i__b~0.base Int) (~__U_MULTI_f___________true_valid_memsafety_i__a~0.base Int)) (let ((.cse0 (store |c_old(#valid)| ~__U_MULTI_f___________true_valid_memsafety_i__a~0.base 1))) (and (not (= 0 ~__U_MULTI_f___________true_valid_memsafety_i__b~0.base)) (= 0 (select .cse0 ~__U_MULTI_f___________true_valid_memsafety_i__b~0.base)) (= (select |c_old(#valid)| ~__U_MULTI_f___________true_valid_memsafety_i__a~0.base) 0) (= (store (store (store .cse0 ~__U_MULTI_f___________true_valid_memsafety_i__b~0.base 1) ~__U_MULTI_f___________true_valid_memsafety_i__a~0.base 0) ~__U_MULTI_f___________true_valid_memsafety_i__b~0.base 0) |c_#valid|)))) is different from true [2018-04-11 16:15:33,810 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-11 16:15:33,811 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:33,811 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-04-11 16:15:33,811 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-11 16:15:33,812 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-11 16:15:33,812 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=57, Unknown=3, NotChecked=30, Total=110 [2018-04-11 16:15:33,812 INFO L87 Difference]: Start difference. First operand 111 states and 115 transitions. Second operand 11 states. [2018-04-11 16:15:34,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:34,035 INFO L93 Difference]: Finished difference Result 110 states and 114 transitions. [2018-04-11 16:15:34,035 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 16:15:34,036 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 39 [2018-04-11 16:15:34,036 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:34,036 INFO L225 Difference]: With dead ends: 110 [2018-04-11 16:15:34,036 INFO L226 Difference]: Without dead ends: 80 [2018-04-11 16:15:34,037 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 43 GetRequests, 29 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 2 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=36, Invalid=124, Unknown=4, NotChecked=46, Total=210 [2018-04-11 16:15:34,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-04-11 16:15:34,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-04-11 16:15:34,038 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-11 16:15:34,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 83 transitions. [2018-04-11 16:15:34,039 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 83 transitions. Word has length 39 [2018-04-11 16:15:34,039 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:34,039 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 83 transitions. [2018-04-11 16:15:34,039 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-11 16:15:34,039 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 83 transitions. [2018-04-11 16:15:34,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-04-11 16:15:34,039 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:34,040 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:34,040 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:34,040 INFO L82 PathProgramCache]: Analyzing trace with hash -1581570445, now seen corresponding path program 1 times [2018-04-11 16:15:34,040 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:34,040 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:34,040 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,041 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:34,041 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:34,048 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:34,107 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 5 proven. 0 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-11 16:15:34,107 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 16:15:34,107 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-11 16:15:34,107 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-11 16:15:34,107 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-11 16:15:34,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-11 16:15:34,107 INFO L87 Difference]: Start difference. First operand 80 states and 83 transitions. Second operand 9 states. [2018-04-11 16:15:34,166 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:34,167 INFO L93 Difference]: Finished difference Result 79 states and 82 transitions. [2018-04-11 16:15:34,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 16:15:34,167 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 41 [2018-04-11 16:15:34,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:34,167 INFO L225 Difference]: With dead ends: 79 [2018-04-11 16:15:34,167 INFO L226 Difference]: Without dead ends: 79 [2018-04-11 16:15:34,168 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=48, Invalid=108, Unknown=0, NotChecked=0, Total=156 [2018-04-11 16:15:34,168 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-04-11 16:15:34,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2018-04-11 16:15:34,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-04-11 16:15:34,169 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 82 transitions. [2018-04-11 16:15:34,169 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 82 transitions. Word has length 41 [2018-04-11 16:15:34,169 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:34,169 INFO L459 AbstractCegarLoop]: Abstraction has 79 states and 82 transitions. [2018-04-11 16:15:34,169 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-11 16:15:34,169 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 82 transitions. [2018-04-11 16:15:34,170 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-04-11 16:15:34,170 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:34,170 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:34,170 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:34,170 INFO L82 PathProgramCache]: Analyzing trace with hash -678674494, now seen corresponding path program 1 times [2018-04-11 16:15:34,170 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:34,170 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:34,170 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:34,171 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,177 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:34,177 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:34,222 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-11 16:15:34,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:34,222 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:34,223 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:34,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:34,234 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:34,270 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-11 16:15:34,271 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:34,271 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 11 [2018-04-11 16:15:34,271 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-11 16:15:34,271 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-11 16:15:34,271 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=62, Unknown=0, NotChecked=0, Total=110 [2018-04-11 16:15:34,272 INFO L87 Difference]: Start difference. First operand 79 states and 82 transitions. Second operand 11 states. [2018-04-11 16:15:34,427 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:34,427 INFO L93 Difference]: Finished difference Result 106 states and 109 transitions. [2018-04-11 16:15:34,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-11 16:15:34,427 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 41 [2018-04-11 16:15:34,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:34,428 INFO L225 Difference]: With dead ends: 106 [2018-04-11 16:15:34,428 INFO L226 Difference]: Without dead ends: 106 [2018-04-11 16:15:34,428 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 53 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 27 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=106, Invalid=134, Unknown=0, NotChecked=0, Total=240 [2018-04-11 16:15:34,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-04-11 16:15:34,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 86. [2018-04-11 16:15:34,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 86 states. [2018-04-11 16:15:34,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 86 states to 86 states and 89 transitions. [2018-04-11 16:15:34,431 INFO L78 Accepts]: Start accepts. Automaton has 86 states and 89 transitions. Word has length 41 [2018-04-11 16:15:34,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:34,431 INFO L459 AbstractCegarLoop]: Abstraction has 86 states and 89 transitions. [2018-04-11 16:15:34,431 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-11 16:15:34,431 INFO L276 IsEmpty]: Start isEmpty. Operand 86 states and 89 transitions. [2018-04-11 16:15:34,432 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-04-11 16:15:34,432 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:34,432 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:34,432 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:34,432 INFO L82 PathProgramCache]: Analyzing trace with hash -507390837, now seen corresponding path program 2 times [2018-04-11 16:15:34,432 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:34,432 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:34,433 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,433 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:34,433 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,440 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:34,441 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:34,542 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-04-11 16:15:34,543 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:34,543 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:34,543 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 16:15:34,558 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 16:15:34,559 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:34,561 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:34,568 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-11 16:15:34,569 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,577 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,577 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:12, output treesize:11 [2018-04-11 16:15:34,622 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 27 trivial. 0 not checked. [2018-04-11 16:15:34,622 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:34,622 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6] total 11 [2018-04-11 16:15:34,622 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 16:15:34,622 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 16:15:34,622 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=96, Unknown=0, NotChecked=0, Total=132 [2018-04-11 16:15:34,623 INFO L87 Difference]: Start difference. First operand 86 states and 89 transitions. Second operand 12 states. [2018-04-11 16:15:34,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:34,746 INFO L93 Difference]: Finished difference Result 85 states and 88 transitions. [2018-04-11 16:15:34,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 16:15:34,746 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 45 [2018-04-11 16:15:34,746 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:34,747 INFO L225 Difference]: With dead ends: 85 [2018-04-11 16:15:34,747 INFO L226 Difference]: Without dead ends: 85 [2018-04-11 16:15:34,747 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 40 SyntacticMatches, 1 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 28 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-04-11 16:15:34,747 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-04-11 16:15:34,748 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 85. [2018-04-11 16:15:34,748 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 85 states. [2018-04-11 16:15:34,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 85 states to 85 states and 88 transitions. [2018-04-11 16:15:34,749 INFO L78 Accepts]: Start accepts. Automaton has 85 states and 88 transitions. Word has length 45 [2018-04-11 16:15:34,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:34,749 INFO L459 AbstractCegarLoop]: Abstraction has 85 states and 88 transitions. [2018-04-11 16:15:34,749 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 16:15:34,749 INFO L276 IsEmpty]: Start isEmpty. Operand 85 states and 88 transitions. [2018-04-11 16:15:34,749 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-11 16:15:34,749 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:34,749 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:34,749 INFO L408 AbstractCegarLoop]: === Iteration 21 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:34,749 INFO L82 PathProgramCache]: Analyzing trace with hash -668266727, now seen corresponding path program 1 times [2018-04-11 16:15:34,749 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:34,750 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:34,750 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,750 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:34,750 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:34,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:34,757 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:34,760 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:34,760 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:34,760 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:34,760 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:34,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:34,773 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:34,783 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:34,783 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,786 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,786 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-11 16:15:34,796 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:34,797 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:34,797 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:34,797 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,800 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,801 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:11 [2018-04-11 16:15:34,827 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-11 16:15:34,828 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-11 16:15:34,828 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,830 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,835 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,835 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:27, output treesize:23 [2018-04-11 16:15:34,849 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-11 16:15:34,851 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-11 16:15:34,851 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,852 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,856 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:34,857 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:17 [2018-04-11 16:15:35,027 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-11 16:15:35,027 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,039 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 38 [2018-04-11 16:15:35,041 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 16 [2018-04-11 16:15:35,043 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:35,043 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-04-11 16:15:35,043 INFO L267 ElimStorePlain]: Start of recursive call 5: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,047 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,055 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 37 treesize of output 36 [2018-04-11 16:15:35,057 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:35,057 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 23 [2018-04-11 16:15:35,058 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,063 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,067 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,074 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-1 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:35,075 INFO L202 ElimStorePlain]: Needed 7 recursive calls to eliminate 3 variables, input treesize:65, output treesize:46 [2018-04-11 16:15:35,137 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 41 [2018-04-11 16:15:35,140 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:35,140 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 25 treesize of output 13 [2018-04-11 16:15:35,141 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,146 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:35,147 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 6 [2018-04-11 16:15:35,147 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,149 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,153 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,153 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:59, output treesize:7 [2018-04-11 16:15:35,170 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 0 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:35,170 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:35,170 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19] total 19 [2018-04-11 16:15:35,170 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-11 16:15:35,171 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-11 16:15:35,171 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=285, Unknown=0, NotChecked=0, Total=342 [2018-04-11 16:15:35,171 INFO L87 Difference]: Start difference. First operand 85 states and 88 transitions. Second operand 19 states. [2018-04-11 16:15:35,665 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:35,665 INFO L93 Difference]: Finished difference Result 88 states and 90 transitions. [2018-04-11 16:15:35,665 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 16:15:35,665 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 46 [2018-04-11 16:15:35,665 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:35,665 INFO L225 Difference]: With dead ends: 88 [2018-04-11 16:15:35,665 INFO L226 Difference]: Without dead ends: 58 [2018-04-11 16:15:35,666 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 60 GetRequests, 28 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 152 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=185, Invalid=937, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 16:15:35,666 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-04-11 16:15:35,667 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 58. [2018-04-11 16:15:35,667 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 58 states. [2018-04-11 16:15:35,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 58 states to 58 states and 60 transitions. [2018-04-11 16:15:35,667 INFO L78 Accepts]: Start accepts. Automaton has 58 states and 60 transitions. Word has length 46 [2018-04-11 16:15:35,667 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:35,667 INFO L459 AbstractCegarLoop]: Abstraction has 58 states and 60 transitions. [2018-04-11 16:15:35,667 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-11 16:15:35,668 INFO L276 IsEmpty]: Start isEmpty. Operand 58 states and 60 transitions. [2018-04-11 16:15:35,668 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 58 [2018-04-11 16:15:35,668 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:35,668 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:35,668 INFO L408 AbstractCegarLoop]: === Iteration 22 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:35,668 INFO L82 PathProgramCache]: Analyzing trace with hash -1049287317, now seen corresponding path program 2 times [2018-04-11 16:15:35,668 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:35,668 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:35,669 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:35,669 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:35,669 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:35,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:35,679 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:35,685 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:35,685 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:35,686 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:35,686 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 16:15:35,701 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 16:15:35,701 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:35,704 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:35,714 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:35,714 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,716 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,717 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-11 16:15:35,728 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:35,728 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:35,729 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:35,729 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,732 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,732 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:11 [2018-04-11 16:15:35,753 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-11 16:15:35,754 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-11 16:15:35,755 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,757 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,763 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,763 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:27, output treesize:23 [2018-04-11 16:15:35,774 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-11 16:15:35,775 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-11 16:15:35,775 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,777 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,787 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:35,788 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:17 [2018-04-11 16:15:36,154 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-11 16:15:36,155 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,183 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 58 treesize of output 62 [2018-04-11 16:15:36,186 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 26 treesize of output 29 [2018-04-11 16:15:36,189 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 40 [2018-04-11 16:15:36,194 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 31 treesize of output 43 [2018-04-11 16:15:36,194 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,199 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,204 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,217 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 64 [2018-04-11 16:15:36,220 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,220 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 27 treesize of output 39 [2018-04-11 16:15:36,223 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,223 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,224 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,225 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 29 treesize of output 64 [2018-04-11 16:15:36,225 INFO L267 ElimStorePlain]: Start of recursive call 9: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,231 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,239 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,245 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,260 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-1 vars, 1 dim-2 vars, End of recursive call: 7 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:36,260 INFO L202 ElimStorePlain]: Needed 9 recursive calls to eliminate 9 variables, input treesize:115, output treesize:91 [2018-04-11 16:15:36,348 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 133 treesize of output 107 [2018-04-11 16:15:36,350 INFO L682 Elim1Store]: detected equality via solver [2018-04-11 16:15:36,351 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,352 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,352 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:36,353 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 3 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 103 treesize of output 133 [2018-04-11 16:15:36,353 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,368 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 69 treesize of output 12 [2018-04-11 16:15:36,369 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,371 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,378 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:36,378 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 10 variables, input treesize:151, output treesize:10 [2018-04-11 16:15:36,405 INFO L134 CoverageAnalysis]: Checked inductivity of 35 backedges. 0 proven. 20 refuted. 15 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:36,406 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:36,406 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22] total 22 [2018-04-11 16:15:36,406 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 16:15:36,406 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 16:15:36,407 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=357, Unknown=34, NotChecked=0, Total=462 [2018-04-11 16:15:36,407 INFO L87 Difference]: Start difference. First operand 58 states and 60 transitions. Second operand 22 states. [2018-04-11 16:15:37,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:37,944 INFO L93 Difference]: Finished difference Result 132 states and 138 transitions. [2018-04-11 16:15:37,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 16:15:37,944 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 57 [2018-04-11 16:15:37,944 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:37,944 INFO L225 Difference]: With dead ends: 132 [2018-04-11 16:15:37,945 INFO L226 Difference]: Without dead ends: 109 [2018-04-11 16:15:37,945 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 77 GetRequests, 36 SyntacticMatches, 0 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 243 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=261, Invalid=1366, Unknown=179, NotChecked=0, Total=1806 [2018-04-11 16:15:37,945 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-04-11 16:15:37,947 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 100. [2018-04-11 16:15:37,947 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 100 states. [2018-04-11 16:15:37,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 100 states to 100 states and 105 transitions. [2018-04-11 16:15:37,947 INFO L78 Accepts]: Start accepts. Automaton has 100 states and 105 transitions. Word has length 57 [2018-04-11 16:15:37,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:37,947 INFO L459 AbstractCegarLoop]: Abstraction has 100 states and 105 transitions. [2018-04-11 16:15:37,947 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 16:15:37,947 INFO L276 IsEmpty]: Start isEmpty. Operand 100 states and 105 transitions. [2018-04-11 16:15:37,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-04-11 16:15:37,948 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:37,948 INFO L355 BasicCegarLoop]: trace histogram [4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:37,948 INFO L408 AbstractCegarLoop]: === Iteration 23 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:37,948 INFO L82 PathProgramCache]: Analyzing trace with hash -145570311, now seen corresponding path program 3 times [2018-04-11 16:15:37,948 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:37,948 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:37,948 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:37,949 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:37,949 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:37,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:37,955 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:37,994 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 18 proven. 18 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-11 16:15:37,995 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:37,995 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:37,995 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 16:15:38,015 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-04-11 16:15:38,015 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:38,018 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:38,046 INFO L134 CoverageAnalysis]: Checked inductivity of 44 backedges. 18 proven. 8 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-11 16:15:38,046 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:38,046 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9] total 14 [2018-04-11 16:15:38,046 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-11 16:15:38,047 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-11 16:15:38,047 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=122, Unknown=0, NotChecked=0, Total=182 [2018-04-11 16:15:38,047 INFO L87 Difference]: Start difference. First operand 100 states and 105 transitions. Second operand 14 states. [2018-04-11 16:15:38,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:38,194 INFO L93 Difference]: Finished difference Result 150 states and 156 transitions. [2018-04-11 16:15:38,194 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 16:15:38,194 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 60 [2018-04-11 16:15:38,194 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:38,195 INFO L225 Difference]: With dead ends: 150 [2018-04-11 16:15:38,195 INFO L226 Difference]: Without dead ends: 150 [2018-04-11 16:15:38,195 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 79 GetRequests, 57 SyntacticMatches, 1 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 95 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=156, Invalid=350, Unknown=0, NotChecked=0, Total=506 [2018-04-11 16:15:38,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 150 states. [2018-04-11 16:15:38,198 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 150 to 108. [2018-04-11 16:15:38,198 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-04-11 16:15:38,198 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 113 transitions. [2018-04-11 16:15:38,199 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 113 transitions. Word has length 60 [2018-04-11 16:15:38,199 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:38,199 INFO L459 AbstractCegarLoop]: Abstraction has 108 states and 113 transitions. [2018-04-11 16:15:38,199 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-11 16:15:38,199 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 113 transitions. [2018-04-11 16:15:38,200 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 62 [2018-04-11 16:15:38,200 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:38,200 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:38,200 INFO L408 AbstractCegarLoop]: === Iteration 24 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:38,200 INFO L82 PathProgramCache]: Analyzing trace with hash 1264715828, now seen corresponding path program 4 times [2018-04-11 16:15:38,200 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:38,200 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:38,201 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:38,201 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:38,201 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:38,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:38,210 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:38,352 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 21 proven. 20 refuted. 0 times theorem prover too weak. 8 trivial. 0 not checked. [2018-04-11 16:15:38,353 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:38,353 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:38,353 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 16:15:38,364 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 16:15:38,364 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:38,365 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:38,424 INFO L134 CoverageAnalysis]: Checked inductivity of 49 backedges. 18 proven. 22 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-11 16:15:38,424 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:38,424 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 10] total 20 [2018-04-11 16:15:38,425 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 16:15:38,425 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 16:15:38,425 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=60, Invalid=320, Unknown=0, NotChecked=0, Total=380 [2018-04-11 16:15:38,425 INFO L87 Difference]: Start difference. First operand 108 states and 113 transitions. Second operand 20 states. [2018-04-11 16:15:38,663 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:38,663 INFO L93 Difference]: Finished difference Result 93 states and 95 transitions. [2018-04-11 16:15:38,663 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 16:15:38,663 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 61 [2018-04-11 16:15:38,663 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:38,663 INFO L225 Difference]: With dead ends: 93 [2018-04-11 16:15:38,664 INFO L226 Difference]: Without dead ends: 71 [2018-04-11 16:15:38,664 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 61 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 320 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=221, Invalid=1111, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 16:15:38,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71 states. [2018-04-11 16:15:38,665 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71 to 69. [2018-04-11 16:15:38,665 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-04-11 16:15:38,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 71 transitions. [2018-04-11 16:15:38,665 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 71 transitions. Word has length 61 [2018-04-11 16:15:38,665 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:38,665 INFO L459 AbstractCegarLoop]: Abstraction has 69 states and 71 transitions. [2018-04-11 16:15:38,666 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 16:15:38,666 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 71 transitions. [2018-04-11 16:15:38,666 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-04-11 16:15:38,666 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:38,666 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:38,666 INFO L408 AbstractCegarLoop]: === Iteration 25 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:38,666 INFO L82 PathProgramCache]: Analyzing trace with hash 2046023961, now seen corresponding path program 5 times [2018-04-11 16:15:38,666 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:38,666 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:38,667 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:38,667 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:38,667 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:38,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:38,692 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:38,712 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:38,712 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:38,712 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:38,713 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 16:15:38,743 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-04-11 16:15:38,744 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:38,749 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:38,763 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:38,763 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,766 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,766 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:13 [2018-04-11 16:15:38,778 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:38,778 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:38,779 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:38,779 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,782 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,782 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:21, output treesize:15 [2018-04-11 16:15:38,818 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-11 16:15:38,820 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-11 16:15:38,820 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,821 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,827 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,827 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-04-11 16:15:38,843 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-11 16:15:38,845 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-11 16:15:38,845 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,846 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,852 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:38,852 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:30, output treesize:21 [2018-04-11 16:15:40,192 WARN L151 SmtUtils]: Spent 212ms on a formula simplification. DAG size of input: 81 DAG size of output 73 [2018-04-11 16:15:40,206 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 72 treesize of output 76 [2018-04-11 16:15:40,221 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 33 treesize of output 36 [2018-04-11 16:15:40,231 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,232 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 50 [2018-04-11 16:15:40,263 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,265 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,267 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,268 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 76 [2018-04-11 16:15:40,273 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,275 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,276 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,278 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,279 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,281 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,282 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 117 [2018-04-11 16:15:40,282 INFO L267 ElimStorePlain]: Start of recursive call 6: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,308 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,324 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,337 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,373 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 83 treesize of output 82 [2018-04-11 16:15:40,378 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,379 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 34 treesize of output 46 [2018-04-11 16:15:40,384 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,386 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,387 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,388 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 70 [2018-04-11 16:15:40,394 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,395 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,396 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,397 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,398 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,400 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,400 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 109 [2018-04-11 16:15:40,401 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,418 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,429 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,446 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,479 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,528 INFO L267 ElimStorePlain]: Start of recursive call 1: 7 dim-0 vars, 1 dim-2 vars, End of recursive call: 7 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:40,528 INFO L202 ElimStorePlain]: Needed 10 recursive calls to eliminate 8 variables, input treesize:170, output treesize:152 [2018-04-11 16:15:40,837 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 176 treesize of output 140 [2018-04-11 16:15:40,848 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,849 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,850 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,851 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,852 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,853 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,854 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 4 select indices, 4 select index equivalence classes, 6 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 53 treesize of output 73 [2018-04-11 16:15:40,854 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,891 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,892 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,893 INFO L682 Elim1Store]: detected equality via solver [2018-04-11 16:15:40,894 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,895 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,897 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,898 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:40,898 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 84 treesize of output 93 [2018-04-11 16:15:40,899 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,911 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:40,933 INFO L267 ElimStorePlain]: Start of recursive call 1: 9 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:40,933 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 10 variables, input treesize:230, output treesize:31 [2018-04-11 16:15:41,028 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 0 proven. 38 refuted. 30 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:41,029 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:41,029 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-04-11 16:15:41,029 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-11 16:15:41,029 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-11 16:15:41,030 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=92, Invalid=651, Unknown=127, NotChecked=0, Total=870 [2018-04-11 16:15:41,030 INFO L87 Difference]: Start difference. First operand 69 states and 71 transitions. Second operand 30 states. [2018-04-11 16:15:44,189 WARN L151 SmtUtils]: Spent 168ms on a formula simplification. DAG size of input: 96 DAG size of output 76 [2018-04-11 16:15:45,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:45,464 INFO L93 Difference]: Finished difference Result 155 states and 161 transitions. [2018-04-11 16:15:45,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-11 16:15:45,464 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 68 [2018-04-11 16:15:45,464 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:45,465 INFO L225 Difference]: With dead ends: 155 [2018-04-11 16:15:45,465 INFO L226 Difference]: Without dead ends: 128 [2018-04-11 16:15:45,465 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 94 GetRequests, 39 SyntacticMatches, 0 SemanticMatches, 55 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 372 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=323, Invalid=2442, Unknown=427, NotChecked=0, Total=3192 [2018-04-11 16:15:45,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-04-11 16:15:45,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 119. [2018-04-11 16:15:45,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-04-11 16:15:45,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 124 transitions. [2018-04-11 16:15:45,467 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 124 transitions. Word has length 68 [2018-04-11 16:15:45,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:45,467 INFO L459 AbstractCegarLoop]: Abstraction has 119 states and 124 transitions. [2018-04-11 16:15:45,467 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-11 16:15:45,467 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 124 transitions. [2018-04-11 16:15:45,468 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-04-11 16:15:45,468 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:45,468 INFO L355 BasicCegarLoop]: trace histogram [5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:45,468 INFO L408 AbstractCegarLoop]: === Iteration 26 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:45,468 INFO L82 PathProgramCache]: Analyzing trace with hash 870052811, now seen corresponding path program 6 times [2018-04-11 16:15:45,468 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:45,468 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:45,468 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:45,469 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:45,469 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:45,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:45,476 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:45,529 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 30 proven. 32 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-11 16:15:45,529 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:45,529 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:45,530 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 16:15:45,547 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-04-11 16:15:45,548 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:45,550 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:45,606 INFO L134 CoverageAnalysis]: Checked inductivity of 80 backedges. 30 proven. 32 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-11 16:15:45,606 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:45,606 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12] total 18 [2018-04-11 16:15:45,606 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-11 16:15:45,606 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-11 16:15:45,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=102, Invalid=204, Unknown=0, NotChecked=0, Total=306 [2018-04-11 16:15:45,607 INFO L87 Difference]: Start difference. First operand 119 states and 124 transitions. Second operand 18 states. [2018-04-11 16:15:45,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:45,811 INFO L93 Difference]: Finished difference Result 169 states and 175 transitions. [2018-04-11 16:15:45,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 16:15:45,811 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 71 [2018-04-11 16:15:45,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:45,812 INFO L225 Difference]: With dead ends: 169 [2018-04-11 16:15:45,812 INFO L226 Difference]: Without dead ends: 169 [2018-04-11 16:15:45,812 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 92 GetRequests, 66 SyntacticMatches, 1 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 145 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=218, Invalid=484, Unknown=0, NotChecked=0, Total=702 [2018-04-11 16:15:45,813 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-04-11 16:15:45,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 127. [2018-04-11 16:15:45,815 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-04-11 16:15:45,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 132 transitions. [2018-04-11 16:15:45,816 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 132 transitions. Word has length 71 [2018-04-11 16:15:45,816 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:45,816 INFO L459 AbstractCegarLoop]: Abstraction has 127 states and 132 transitions. [2018-04-11 16:15:45,816 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-11 16:15:45,816 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 132 transitions. [2018-04-11 16:15:45,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 73 [2018-04-11 16:15:45,817 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:45,817 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:45,817 INFO L408 AbstractCegarLoop]: === Iteration 27 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:45,817 INFO L82 PathProgramCache]: Analyzing trace with hash -1568543774, now seen corresponding path program 7 times [2018-04-11 16:15:45,818 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:45,818 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:45,818 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:45,818 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:15:45,819 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:45,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:45,828 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:45,917 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 35 proven. 33 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-11 16:15:45,918 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:45,918 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:45,918 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:45,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:45,927 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:46,002 INFO L134 CoverageAnalysis]: Checked inductivity of 86 backedges. 50 proven. 18 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-11 16:15:46,002 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:15:46,002 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 11] total 19 [2018-04-11 16:15:46,003 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-11 16:15:46,003 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-11 16:15:46,003 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=274, Unknown=0, NotChecked=0, Total=342 [2018-04-11 16:15:46,003 INFO L87 Difference]: Start difference. First operand 127 states and 132 transitions. Second operand 19 states. [2018-04-11 16:15:46,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:15:46,236 INFO L93 Difference]: Finished difference Result 106 states and 108 transitions. [2018-04-11 16:15:46,236 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-11 16:15:46,236 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 72 [2018-04-11 16:15:46,236 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:15:46,236 INFO L225 Difference]: With dead ends: 106 [2018-04-11 16:15:46,236 INFO L226 Difference]: Without dead ends: 80 [2018-04-11 16:15:46,237 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 103 GetRequests, 74 SyntacticMatches, 2 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 161 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=162, Invalid=650, Unknown=0, NotChecked=0, Total=812 [2018-04-11 16:15:46,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-04-11 16:15:46,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-04-11 16:15:46,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-11 16:15:46,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 82 transitions. [2018-04-11 16:15:46,238 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 82 transitions. Word has length 72 [2018-04-11 16:15:46,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:15:46,239 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 82 transitions. [2018-04-11 16:15:46,239 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-11 16:15:46,239 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 82 transitions. [2018-04-11 16:15:46,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 80 [2018-04-11 16:15:46,239 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:15:46,239 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:15:46,240 INFO L408 AbstractCegarLoop]: === Iteration 28 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:15:46,240 INFO L82 PathProgramCache]: Analyzing trace with hash 42879979, now seen corresponding path program 8 times [2018-04-11 16:15:46,240 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:15:46,240 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:15:46,241 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:46,241 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:15:46,241 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:15:46,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:15:46,283 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:15:46,314 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:15:46,315 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:15:46,315 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:15:46,315 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 16:15:46,332 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 16:15:46,332 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:15:46,335 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:15:46,348 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:15:46,349 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,351 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,352 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:13 [2018-04-11 16:15:46,365 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:46,365 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:46,365 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:15:46,366 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,369 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,369 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:21, output treesize:15 [2018-04-11 16:15:46,409 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-11 16:15:46,411 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-11 16:15:46,411 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,413 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,421 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,421 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-04-11 16:15:46,438 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-11 16:15:46,439 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-11 16:15:46,439 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,440 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,445 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:46,445 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:30, output treesize:21 [2018-04-11 16:15:48,513 WARN L151 SmtUtils]: Spent 233ms on a formula simplification. DAG size of input: 82 DAG size of output 73 [2018-04-11 16:15:48,540 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 86 treesize of output 90 [2018-04-11 16:15:48,543 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 43 [2018-04-11 16:15:48,548 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 54 [2018-04-11 16:15:48,558 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 56 [2018-04-11 16:15:48,573 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 58 [2018-04-11 16:15:48,591 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 49 treesize of output 65 [2018-04-11 16:15:48,592 INFO L267 ElimStorePlain]: Start of recursive call 7: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,605 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,619 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,632 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,644 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,672 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 101 treesize of output 100 [2018-04-11 16:15:48,677 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,677 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 41 treesize of output 53 [2018-04-11 16:15:48,682 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,683 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,684 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,685 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 43 treesize of output 77 [2018-04-11 16:15:48,688 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,689 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,690 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,691 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,692 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,693 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,694 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 45 treesize of output 113 [2018-04-11 16:15:48,697 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,698 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,699 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,700 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,701 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,701 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,702 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,703 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,704 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,705 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:48,705 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 47 treesize of output 166 [2018-04-11 16:15:48,706 INFO L267 ElimStorePlain]: Start of recursive call 12: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,723 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,733 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,743 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,759 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,780 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:48,817 INFO L267 ElimStorePlain]: Start of recursive call 1: 10 dim-0 vars, 1 dim-2 vars, End of recursive call: 10 dim-0 vars, and 1 xjuncts. [2018-04-11 16:15:48,818 INFO L202 ElimStorePlain]: Needed 12 recursive calls to eliminate 11 variables, input treesize:166, output treesize:149 [2018-04-11 16:15:49,084 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 201 treesize of output 159 [2018-04-11 16:15:49,087 INFO L682 Elim1Store]: detected equality via solver [2018-04-11 16:15:49,088 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,089 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,090 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,090 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,092 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,093 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,094 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,095 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,096 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,097 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:15:49,097 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 10 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 155 treesize of output 257 [2018-04-11 16:15:49,098 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:49,133 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 106 treesize of output 19 [2018-04-11 16:15:49,134 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 16:15:49,141 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:49,151 INFO L267 ElimStorePlain]: Start of recursive call 1: 12 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:15:49,151 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 13 variables, input treesize:233, output treesize:14 [2018-04-11 16:15:49,225 INFO L134 CoverageAnalysis]: Checked inductivity of 112 backedges. 0 proven. 50 refuted. 62 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:15:49,226 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:15:49,226 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30] total 30 [2018-04-11 16:15:49,226 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-11 16:15:49,226 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-11 16:15:49,226 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=94, Invalid=603, Unknown=173, NotChecked=0, Total=870 [2018-04-11 16:15:49,226 INFO L87 Difference]: Start difference. First operand 80 states and 82 transitions. Second operand 30 states. [2018-04-11 16:15:53,166 WARN L148 SmtUtils]: Spent 102ms on a formula simplification that was a NOOP. DAG size: 76 [2018-04-11 16:15:58,420 WARN L151 SmtUtils]: Spent 4508ms on a formula simplification. DAG size of input: 102 DAG size of output 92 [2018-04-11 16:16:00,750 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:00,750 INFO L93 Difference]: Finished difference Result 178 states and 184 transitions. [2018-04-11 16:16:00,750 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-11 16:16:00,750 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 79 [2018-04-11 16:16:00,750 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:00,751 INFO L225 Difference]: With dead ends: 178 [2018-04-11 16:16:00,751 INFO L226 Difference]: Without dead ends: 147 [2018-04-11 16:16:00,752 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 311 ImplicationChecksByTransitivity, 9.7s TimeCoverageRelationStatistics Valid=316, Invalid=2159, Unknown=605, NotChecked=0, Total=3080 [2018-04-11 16:16:00,752 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-04-11 16:16:00,754 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 138. [2018-04-11 16:16:00,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-04-11 16:16:00,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 143 transitions. [2018-04-11 16:16:00,755 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 143 transitions. Word has length 79 [2018-04-11 16:16:00,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:00,755 INFO L459 AbstractCegarLoop]: Abstraction has 138 states and 143 transitions. [2018-04-11 16:16:00,755 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-11 16:16:00,755 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 143 transitions. [2018-04-11 16:16:00,756 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 83 [2018-04-11 16:16:00,756 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:00,756 INFO L355 BasicCegarLoop]: trace histogram [6, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:00,756 INFO L408 AbstractCegarLoop]: === Iteration 29 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:00,757 INFO L82 PathProgramCache]: Analyzing trace with hash -336138759, now seen corresponding path program 9 times [2018-04-11 16:16:00,757 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:00,757 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:00,757 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:00,757 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:16:00,757 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:00,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:00,768 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:00,871 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 45 proven. 50 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-11 16:16:00,871 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:00,871 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:00,872 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 16:16:00,909 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-04-11 16:16:00,909 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:16:00,912 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:00,992 INFO L134 CoverageAnalysis]: Checked inductivity of 127 backedges. 45 proven. 50 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-11 16:16:00,993 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:16:00,993 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14] total 21 [2018-04-11 16:16:00,993 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-11 16:16:00,994 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-11 16:16:00,994 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=280, Unknown=0, NotChecked=0, Total=420 [2018-04-11 16:16:00,994 INFO L87 Difference]: Start difference. First operand 138 states and 143 transitions. Second operand 21 states. [2018-04-11 16:16:01,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:01,263 INFO L93 Difference]: Finished difference Result 188 states and 194 transitions. [2018-04-11 16:16:01,263 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 16:16:01,263 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 82 [2018-04-11 16:16:01,263 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:01,264 INFO L225 Difference]: With dead ends: 188 [2018-04-11 16:16:01,264 INFO L226 Difference]: Without dead ends: 188 [2018-04-11 16:16:01,264 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 106 GetRequests, 76 SyntacticMatches, 1 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 202 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=291, Invalid=639, Unknown=0, NotChecked=0, Total=930 [2018-04-11 16:16:01,264 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 188 states. [2018-04-11 16:16:01,267 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 188 to 146. [2018-04-11 16:16:01,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 146 states. [2018-04-11 16:16:01,268 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 146 states to 146 states and 151 transitions. [2018-04-11 16:16:01,268 INFO L78 Accepts]: Start accepts. Automaton has 146 states and 151 transitions. Word has length 82 [2018-04-11 16:16:01,268 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:01,268 INFO L459 AbstractCegarLoop]: Abstraction has 146 states and 151 transitions. [2018-04-11 16:16:01,268 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-11 16:16:01,268 INFO L276 IsEmpty]: Start isEmpty. Operand 146 states and 151 transitions. [2018-04-11 16:16:01,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-04-11 16:16:01,269 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:01,269 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:01,269 INFO L408 AbstractCegarLoop]: === Iteration 30 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:01,269 INFO L82 PathProgramCache]: Analyzing trace with hash -577905484, now seen corresponding path program 10 times [2018-04-11 16:16:01,269 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:01,269 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:01,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:01,270 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:16:01,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:01,280 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:01,281 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:01,417 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 53 proven. 49 refuted. 0 times theorem prover too weak. 32 trivial. 0 not checked. [2018-04-11 16:16:01,417 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:01,417 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:01,418 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 16:16:01,429 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 16:16:01,429 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:16:01,432 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:01,586 INFO L134 CoverageAnalysis]: Checked inductivity of 134 backedges. 50 proven. 54 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-04-11 16:16:01,586 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:16:01,587 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 14] total 28 [2018-04-11 16:16:01,587 INFO L442 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-04-11 16:16:01,587 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-04-11 16:16:01,587 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=110, Invalid=646, Unknown=0, NotChecked=0, Total=756 [2018-04-11 16:16:01,587 INFO L87 Difference]: Start difference. First operand 146 states and 151 transitions. Second operand 28 states. [2018-04-11 16:16:02,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:02,264 INFO L93 Difference]: Finished difference Result 123 states and 125 transitions. [2018-04-11 16:16:02,265 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 16:16:02,265 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 83 [2018-04-11 16:16:02,265 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:02,265 INFO L225 Difference]: With dead ends: 123 [2018-04-11 16:16:02,265 INFO L226 Difference]: Without dead ends: 93 [2018-04-11 16:16:02,267 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 83 SyntacticMatches, 2 SemanticMatches, 51 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 735 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=412, Invalid=2344, Unknown=0, NotChecked=0, Total=2756 [2018-04-11 16:16:02,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-04-11 16:16:02,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 91. [2018-04-11 16:16:02,268 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 91 states. [2018-04-11 16:16:02,269 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 91 states to 91 states and 93 transitions. [2018-04-11 16:16:02,269 INFO L78 Accepts]: Start accepts. Automaton has 91 states and 93 transitions. Word has length 83 [2018-04-11 16:16:02,269 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:02,269 INFO L459 AbstractCegarLoop]: Abstraction has 91 states and 93 transitions. [2018-04-11 16:16:02,269 INFO L460 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-04-11 16:16:02,269 INFO L276 IsEmpty]: Start isEmpty. Operand 91 states and 93 transitions. [2018-04-11 16:16:02,269 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-04-11 16:16:02,269 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:02,269 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:02,269 INFO L408 AbstractCegarLoop]: === Iteration 31 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:02,270 INFO L82 PathProgramCache]: Analyzing trace with hash 273870617, now seen corresponding path program 11 times [2018-04-11 16:16:02,270 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:02,270 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:02,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:02,270 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:16:02,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:02,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:02,289 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:02,294 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:16:02,294 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:02,294 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:02,295 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 16:16:02,328 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-04-11 16:16:02,328 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:16:02,335 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:02,366 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:16:02,366 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,370 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,371 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:13 [2018-04-11 16:16:02,395 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:02,396 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:02,396 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:16:02,396 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,400 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,400 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:21, output treesize:15 [2018-04-11 16:16:02,425 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-11 16:16:02,426 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-11 16:16:02,426 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,427 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,432 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,433 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:31, output treesize:27 [2018-04-11 16:16:02,448 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-11 16:16:02,449 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-11 16:16:02,449 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,450 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,456 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:02,456 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:30, output treesize:21 [2018-04-11 16:16:04,967 WARN L151 SmtUtils]: Spent 170ms on a formula simplification. DAG size of input: 76 DAG size of output 66 [2018-04-11 16:16:04,982 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 93 treesize of output 97 [2018-04-11 16:16:04,985 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 52 treesize of output 55 [2018-04-11 16:16:04,990 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:04,991 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 71 [2018-04-11 16:16:04,996 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:04,998 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,000 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,001 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 101 [2018-04-11 16:16:05,006 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,008 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,010 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,012 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,013 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,015 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,016 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 145 [2018-04-11 16:16:05,021 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,023 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,024 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,026 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,027 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,029 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,031 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,033 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,036 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,037 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,038 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 203 [2018-04-11 16:16:05,043 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,045 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,046 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,047 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,049 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,050 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,051 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,052 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,054 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,055 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,056 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,057 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,058 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,059 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,060 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,061 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 277 [2018-04-11 16:16:05,061 INFO L267 ElimStorePlain]: Start of recursive call 8: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,108 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,135 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,156 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,174 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,191 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,225 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 112 treesize of output 111 [2018-04-11 16:16:05,229 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,229 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 36 treesize of output 44 [2018-04-11 16:16:05,232 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,233 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,234 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,235 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 38 treesize of output 60 [2018-04-11 16:16:05,238 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,239 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,241 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,242 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,243 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,243 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,244 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 6 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 40 treesize of output 84 [2018-04-11 16:16:05,248 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,248 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,249 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,250 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,251 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,251 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,252 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,253 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,254 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,254 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,255 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 10 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 42 treesize of output 116 [2018-04-11 16:16:05,258 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,258 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,259 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,260 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,261 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,261 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,262 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,263 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,263 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,264 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,265 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,265 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,266 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,267 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,267 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,268 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 15 disjoint index pairs (out of 10 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 44 treesize of output 163 [2018-04-11 16:16:05,268 INFO L267 ElimStorePlain]: Start of recursive call 14: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,287 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,298 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,307 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,315 INFO L267 ElimStorePlain]: Start of recursive call 10: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,331 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,346 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,374 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 1 dim-2 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-11 16:16:05,374 INFO L202 ElimStorePlain]: Needed 14 recursive calls to eliminate 2 variables, input treesize:180, output treesize:159 [2018-04-11 16:16:05,637 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 237 treesize of output 185 [2018-04-11 16:16:05,640 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,643 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,643 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,644 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,644 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,645 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,645 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,647 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,648 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,648 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,649 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,649 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,650 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,650 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,651 INFO L682 Elim1Store]: detected equality via solver [2018-04-11 16:16:05,651 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,651 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,652 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,653 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 15 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 181 treesize of output 328 [2018-04-11 16:16:05,653 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,688 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,688 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,689 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,689 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,690 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,690 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,690 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,691 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,691 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,692 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,692 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,693 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,693 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,694 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,694 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:05,695 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 6 select indices, 6 select index equivalence classes, 15 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 144 treesize of output 227 [2018-04-11 16:16:05,695 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,710 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:05,719 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-11 16:16:05,719 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 4 variables, input treesize:261, output treesize:38 [2018-04-11 16:16:05,829 INFO L134 CoverageAnalysis]: Checked inductivity of 167 backedges. 0 proven. 167 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:16:05,830 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:16:05,830 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41] total 41 [2018-04-11 16:16:05,830 INFO L442 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-04-11 16:16:05,830 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-04-11 16:16:05,830 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=1471, Unknown=52, NotChecked=0, Total=1640 [2018-04-11 16:16:05,830 INFO L87 Difference]: Start difference. First operand 91 states and 93 transitions. Second operand 41 states. [2018-04-11 16:16:07,473 WARN L151 SmtUtils]: Spent 102ms on a formula simplification. DAG size of input: 46 DAG size of output 45 [2018-04-11 16:16:13,081 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:13,081 INFO L93 Difference]: Finished difference Result 201 states and 207 transitions. [2018-04-11 16:16:13,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-11 16:16:13,082 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 90 [2018-04-11 16:16:13,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:13,082 INFO L225 Difference]: With dead ends: 201 [2018-04-11 16:16:13,082 INFO L226 Difference]: Without dead ends: 166 [2018-04-11 16:16:13,083 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 50 SyntacticMatches, 0 SemanticMatches, 75 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 692 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=413, Invalid=5262, Unknown=177, NotChecked=0, Total=5852 [2018-04-11 16:16:13,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-04-11 16:16:13,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 157. [2018-04-11 16:16:13,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-04-11 16:16:13,086 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 162 transitions. [2018-04-11 16:16:13,086 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 162 transitions. Word has length 90 [2018-04-11 16:16:13,086 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:13,086 INFO L459 AbstractCegarLoop]: Abstraction has 157 states and 162 transitions. [2018-04-11 16:16:13,086 INFO L460 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-04-11 16:16:13,086 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 162 transitions. [2018-04-11 16:16:13,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 94 [2018-04-11 16:16:13,086 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:13,086 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 7, 6, 6, 6, 6, 6, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:13,087 INFO L408 AbstractCegarLoop]: === Iteration 32 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:13,087 INFO L82 PathProgramCache]: Analyzing trace with hash -1941432245, now seen corresponding path program 12 times [2018-04-11 16:16:13,087 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:13,087 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:13,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:13,087 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:16:13,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:13,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:13,098 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:13,206 INFO L134 CoverageAnalysis]: Checked inductivity of 185 backedges. 63 proven. 50 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-04-11 16:16:13,206 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:13,206 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:13,207 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 16:16:13,245 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-04-11 16:16:13,245 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:16:13,249 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:13,323 INFO L134 CoverageAnalysis]: Checked inductivity of 185 backedges. 63 proven. 50 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-04-11 16:16:13,324 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:16:13,324 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15] total 22 [2018-04-11 16:16:13,324 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 16:16:13,325 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 16:16:13,325 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=154, Invalid=308, Unknown=0, NotChecked=0, Total=462 [2018-04-11 16:16:13,325 INFO L87 Difference]: Start difference. First operand 157 states and 162 transitions. Second operand 22 states. [2018-04-11 16:16:13,531 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:13,532 INFO L93 Difference]: Finished difference Result 189 states and 193 transitions. [2018-04-11 16:16:13,532 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-04-11 16:16:13,532 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 93 [2018-04-11 16:16:13,532 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:13,532 INFO L225 Difference]: With dead ends: 189 [2018-04-11 16:16:13,533 INFO L226 Difference]: Without dead ends: 189 [2018-04-11 16:16:13,533 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 94 SyntacticMatches, 1 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 210 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=312, Invalid=680, Unknown=0, NotChecked=0, Total=992 [2018-04-11 16:16:13,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-04-11 16:16:13,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 161. [2018-04-11 16:16:13,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 161 states. [2018-04-11 16:16:13,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 161 states to 161 states and 166 transitions. [2018-04-11 16:16:13,535 INFO L78 Accepts]: Start accepts. Automaton has 161 states and 166 transitions. Word has length 93 [2018-04-11 16:16:13,536 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:13,536 INFO L459 AbstractCegarLoop]: Abstraction has 161 states and 166 transitions. [2018-04-11 16:16:13,536 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 16:16:13,536 INFO L276 IsEmpty]: Start isEmpty. Operand 161 states and 166 transitions. [2018-04-11 16:16:13,536 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-04-11 16:16:13,536 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:13,536 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:13,536 INFO L408 AbstractCegarLoop]: === Iteration 33 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:13,536 INFO L82 PathProgramCache]: Analyzing trace with hash -70717470, now seen corresponding path program 13 times [2018-04-11 16:16:13,536 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:13,536 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:13,537 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:13,537 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:16:13,537 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:13,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:13,544 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:13,659 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 75 proven. 68 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-04-11 16:16:13,660 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:13,660 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:13,660 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:16:13,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:13,675 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:13,788 INFO L134 CoverageAnalysis]: Checked inductivity of 193 backedges. 98 proven. 45 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-04-11 16:16:13,788 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:16:13,788 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 15] total 25 [2018-04-11 16:16:13,789 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-11 16:16:13,789 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-11 16:16:13,789 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=487, Unknown=0, NotChecked=0, Total=600 [2018-04-11 16:16:13,789 INFO L87 Difference]: Start difference. First operand 161 states and 166 transitions. Second operand 25 states. [2018-04-11 16:16:14,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:14,100 INFO L93 Difference]: Finished difference Result 173 states and 176 transitions. [2018-04-11 16:16:14,101 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 16:16:14,101 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 94 [2018-04-11 16:16:14,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:14,101 INFO L225 Difference]: With dead ends: 173 [2018-04-11 16:16:14,101 INFO L226 Difference]: Without dead ends: 139 [2018-04-11 16:16:14,101 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 135 GetRequests, 96 SyntacticMatches, 2 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 330 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=278, Invalid=1204, Unknown=0, NotChecked=0, Total=1482 [2018-04-11 16:16:14,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-04-11 16:16:14,102 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 98. [2018-04-11 16:16:14,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-04-11 16:16:14,103 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 100 transitions. [2018-04-11 16:16:14,103 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 100 transitions. Word has length 94 [2018-04-11 16:16:14,103 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:14,103 INFO L459 AbstractCegarLoop]: Abstraction has 98 states and 100 transitions. [2018-04-11 16:16:14,103 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-11 16:16:14,103 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 100 transitions. [2018-04-11 16:16:14,104 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 98 [2018-04-11 16:16:14,104 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:14,104 INFO L355 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:14,104 INFO L408 AbstractCegarLoop]: === Iteration 34 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:14,104 INFO L82 PathProgramCache]: Analyzing trace with hash -1369255134, now seen corresponding path program 14 times [2018-04-11 16:16:14,104 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:14,104 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:14,104 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:14,104 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 16:16:14,104 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:14,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:14,112 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:14,247 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 63 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-04-11 16:16:14,247 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:14,247 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:14,248 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 16:16:14,264 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 16:16:14,264 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:16:14,267 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:14,365 INFO L134 CoverageAnalysis]: Checked inductivity of 207 backedges. 63 proven. 72 refuted. 0 times theorem prover too weak. 72 trivial. 0 not checked. [2018-04-11 16:16:14,366 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 16:16:14,366 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16] total 24 [2018-04-11 16:16:14,366 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-11 16:16:14,366 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-11 16:16:14,366 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=184, Invalid=368, Unknown=0, NotChecked=0, Total=552 [2018-04-11 16:16:14,366 INFO L87 Difference]: Start difference. First operand 98 states and 100 transitions. Second operand 24 states. [2018-04-11 16:16:14,474 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 16:16:14,474 INFO L93 Difference]: Finished difference Result 112 states and 115 transitions. [2018-04-11 16:16:14,474 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 16:16:14,474 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 97 [2018-04-11 16:16:14,474 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 16:16:14,474 INFO L225 Difference]: With dead ends: 112 [2018-04-11 16:16:14,475 INFO L226 Difference]: Without dead ends: 112 [2018-04-11 16:16:14,475 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 90 SyntacticMatches, 1 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 149 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=211, Invalid=439, Unknown=0, NotChecked=0, Total=650 [2018-04-11 16:16:14,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-04-11 16:16:14,476 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 102. [2018-04-11 16:16:14,476 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-04-11 16:16:14,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 104 transitions. [2018-04-11 16:16:14,477 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 104 transitions. Word has length 97 [2018-04-11 16:16:14,477 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 16:16:14,477 INFO L459 AbstractCegarLoop]: Abstraction has 102 states and 104 transitions. [2018-04-11 16:16:14,477 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-11 16:16:14,477 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 104 transitions. [2018-04-11 16:16:14,477 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-04-11 16:16:14,477 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 16:16:14,477 INFO L355 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 16:16:14,477 INFO L408 AbstractCegarLoop]: === Iteration 35 === [mainErr5RequiresViolation, mainErr1RequiresViolation, mainErr6AssertViolationMEMORY_FREE, mainErr13AssertViolationMEMORY_FREE, mainErr10AssertViolationMEMORY_FREE, mainErr11AssertViolationMEMORY_FREE, mainErr0RequiresViolation, mainErr14EnsuresViolationMEMORY_LEAK, mainErr3RequiresViolation, mainErr7AssertViolationMEMORY_FREE, mainErr9AssertViolationMEMORY_FREE, mainErr2RequiresViolation, mainErr4RequiresViolation, mainErr8AssertViolationMEMORY_FREE, mainErr12AssertViolationMEMORY_FREE, __U_MULTI_f___________true_valid_memsafety_i__fooErr1RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr3RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr2RequiresViolation, __U_MULTI_f___________true_valid_memsafety_i__fooErr0RequiresViolation]=== [2018-04-11 16:16:14,477 INFO L82 PathProgramCache]: Analyzing trace with hash -569778581, now seen corresponding path program 15 times [2018-04-11 16:16:14,477 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS_NO_ARRAY [2018-04-11 16:16:14,477 INFO L68 tionRefinementEngine]: Using refinement strategy SmtInterpolRefinementStrategy [2018-04-11 16:16:14,478 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:14,478 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 16:16:14,478 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 16:16:14,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 16:16:14,495 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 16:16:14,506 INFO L431 seRefinementStrategy]: Interpolation failed due to KNOWN_IGNORE: Unknown lemma type! [2018-04-11 16:16:14,506 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 16:16:14,506 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_FP [2018-04-11 16:16:14,507 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 16:16:14,538 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-04-11 16:16:14,539 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 16:16:14,543 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 16:16:14,584 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-11 16:16:14,584 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,587 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,588 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-11 16:16:14,610 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:14,611 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:14,611 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-11 16:16:14,612 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,616 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,616 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:17, output treesize:11 [2018-04-11 16:16:14,650 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 13 treesize of output 10 [2018-04-11 16:16:14,651 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 10 treesize of output 9 [2018-04-11 16:16:14,652 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,653 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,658 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,658 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:27, output treesize:23 [2018-04-11 16:16:14,673 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 9 treesize of output 7 [2018-04-11 16:16:14,675 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 7 treesize of output 1 [2018-04-11 16:16:14,675 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,675 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,679 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:14,679 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:17 [2018-04-11 16:16:32,253 WARN L148 SmtUtils]: Spent 120ms on a formula simplification that was a NOOP. DAG size: 79 [2018-04-11 16:16:33,124 WARN L148 SmtUtils]: Spent 229ms on a formula simplification that was a NOOP. DAG size: 82 [2018-04-11 16:16:34,070 WARN L148 SmtUtils]: Spent 150ms on a formula simplification that was a NOOP. DAG size: 85 [2018-04-11 16:16:37,288 WARN L148 SmtUtils]: Spent 190ms on a formula simplification that was a NOOP. DAG size: 87 [2018-04-11 16:16:40,892 WARN L148 SmtUtils]: Spent 354ms on a formula simplification that was a NOOP. DAG size: 90 [2018-04-11 16:16:42,163 WARN L148 SmtUtils]: Spent 259ms on a formula simplification that was a NOOP. DAG size: 92 [2018-04-11 16:16:46,537 WARN L148 SmtUtils]: Spent 217ms on a formula simplification that was a NOOP. DAG size: 93 [2018-04-11 16:16:48,238 WARN L151 SmtUtils]: Spent 1694ms on a formula simplification. DAG size of input: 106 DAG size of output 95 [2018-04-11 16:16:48,250 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-11 16:16:48,250 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:48,953 INFO L303 Elim1Store]: Index analysis took 138 ms [2018-04-11 16:16:48,954 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 114 treesize of output 118 [2018-04-11 16:16:48,960 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 54 treesize of output 57 [2018-04-11 16:16:48,972 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 68 [2018-04-11 16:16:49,017 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 0 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 70 [2018-04-11 16:16:49,059 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 0 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 72 [2018-04-11 16:16:49,130 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 0 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 74 [2018-04-11 16:16:49,237 INFO L303 Elim1Store]: Index analysis took 105 ms [2018-04-11 16:16:49,238 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 0 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 76 [2018-04-11 16:16:49,380 INFO L303 Elim1Store]: Index analysis took 141 ms [2018-04-11 16:16:49,381 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 0 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 67 treesize of output 87 [2018-04-11 16:16:49,381 INFO L267 ElimStorePlain]: Start of recursive call 10: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,434 INFO L267 ElimStorePlain]: Start of recursive call 9: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,488 INFO L267 ElimStorePlain]: Start of recursive call 8: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,542 INFO L267 ElimStorePlain]: Start of recursive call 7: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,609 INFO L267 ElimStorePlain]: Start of recursive call 6: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,655 INFO L267 ElimStorePlain]: Start of recursive call 5: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,707 INFO L267 ElimStorePlain]: Start of recursive call 4: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:49,844 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 137 treesize of output 136 [2018-04-11 16:16:49,852 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,852 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 55 treesize of output 67 [2018-04-11 16:16:49,858 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,862 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,865 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,866 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 57 treesize of output 91 [2018-04-11 16:16:49,878 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,881 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,889 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,898 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,898 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 59 treesize of output 114 [2018-04-11 16:16:49,907 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,909 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,922 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,932 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,937 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,942 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 4 select indices, 4 select index equivalence classes, 5 disjoint index pairs (out of 6 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 61 treesize of output 126 [2018-04-11 16:16:49,955 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,958 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,969 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,977 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,986 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,988 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,991 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 5 select indices, 5 select index equivalence classes, 6 disjoint index pairs (out of 10 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 63 treesize of output 138 [2018-04-11 16:16:49,998 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:49,999 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:50,012 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:50,019 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:50,027 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:50,029 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:50,030 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:50,037 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 6 select indices, 6 select index equivalence classes, 7 disjoint index pairs (out of 15 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 65 treesize of output 159 [2018-04-11 16:16:50,037 INFO L267 ElimStorePlain]: Start of recursive call 17: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,058 INFO L267 ElimStorePlain]: Start of recursive call 16: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,075 INFO L267 ElimStorePlain]: Start of recursive call 15: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,091 INFO L267 ElimStorePlain]: Start of recursive call 14: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,105 INFO L267 ElimStorePlain]: Start of recursive call 13: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,116 INFO L267 ElimStorePlain]: Start of recursive call 12: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,139 INFO L267 ElimStorePlain]: Start of recursive call 11: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,160 INFO L267 ElimStorePlain]: Start of recursive call 3: 1 dim-1 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:50,206 INFO L267 ElimStorePlain]: Start of recursive call 1: 15 dim-0 vars, 1 dim-1 vars, 1 dim-2 vars, End of recursive call: 15 dim-0 vars, and 1 xjuncts. [2018-04-11 16:16:50,207 INFO L202 ElimStorePlain]: Needed 17 recursive calls to eliminate 17 variables, input treesize:219, output treesize:199 [2018-04-11 16:16:52,458 WARN L148 SmtUtils]: Spent 2023ms on a formula simplification that was a NOOP. DAG size: 107 [2018-04-11 16:16:54,861 WARN L148 SmtUtils]: Spent 2102ms on a formula simplification that was a NOOP. DAG size: 109 [2018-04-11 16:16:54,868 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 280 treesize of output 220 [2018-04-11 16:16:54,891 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 7 select indices, 7 select index equivalence classes, 0 disjoint index pairs (out of 21 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 92 treesize of output 1 [2018-04-11 16:16:54,892 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:54,910 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,911 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,916 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,919 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,923 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,924 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,925 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,925 INFO L700 Elim1Store]: detected not equals via solver [2018-04-11 16:16:54,930 INFO L682 Elim1Store]: detected equality via solver [2018-04-11 16:16:54,930 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 8 select indices, 8 select index equivalence classes, 7 disjoint index pairs (out of 28 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 125 treesize of output 112 [2018-04-11 16:16:54,931 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-11 16:16:54,943 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:54,954 INFO L267 ElimStorePlain]: Start of recursive call 1: 17 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-11 16:16:54,954 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 18 variables, input treesize:313, output treesize:7 [2018-04-11 16:16:55,177 INFO L134 CoverageAnalysis]: Checked inductivity of 233 backedges. 63 proven. 49 refuted. 121 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 16:16:55,177 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 1 imperfect interpolant sequences. [2018-04-11 16:16:55,177 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39] total 39 [2018-04-11 16:16:55,177 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-04-11 16:16:55,177 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-04-11 16:16:55,178 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=317, Invalid=878, Unknown=287, NotChecked=0, Total=1482 [2018-04-11 16:16:55,178 INFO L87 Difference]: Start difference. First operand 102 states and 104 transitions. Second operand 39 states. [2018-04-11 16:17:37,581 WARN L148 SmtUtils]: Spent 104ms on a formula simplification that was a NOOP. DAG size: 75 [2018-04-11 16:17:52,840 WARN L148 SmtUtils]: Spent 172ms on a formula simplification that was a NOOP. DAG size: 81 [2018-04-11 16:18:02,391 WARN L148 SmtUtils]: Spent 118ms on a formula simplification that was a NOOP. DAG size: 84 [2018-04-11 16:18:11,842 WARN L148 SmtUtils]: Spent 367ms on a formula simplification that was a NOOP. DAG size: 87 [2018-04-11 16:18:17,895 WARN L148 SmtUtils]: Spent 376ms on a formula simplification that was a NOOP. DAG size: 90 [2018-04-11 16:18:26,963 WARN L148 SmtUtils]: Spent 357ms on a formula simplification that was a NOOP. DAG size: 92 [2018-04-11 16:18:37,982 WARN L148 SmtUtils]: Spent 517ms on a formula simplification that was a NOOP. DAG size: 95 [2018-04-11 16:18:48,074 WARN L148 SmtUtils]: Spent 291ms on a formula simplification that was a NOOP. DAG size: 97 Received shutdown request... [2018-04-11 16:18:58,363 WARN L1011 $PredicateComparison]: unable to prove that (and (<= c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset 4) (= (select (select |c_#memory_int| c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (- 4))) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (<= 7 c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (<= 4 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset) (exists ((v_prenex_16 Int) (v_prenex_15 Int) (v_prenex_17 Int) (v_prenex_12 Int) (v_prenex_11 Int) (v_prenex_14 Int) (v_prenex_13 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 Int) (v_prenex_10 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_91 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92 Int)) (let ((.cse0 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 1))) (and (<= v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_91 1)) (<= v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93 1)) (<= 0 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90) (<= c___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0 .cse0) (< .cse0 c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (<= (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90 1) v_prenex_17) (= |c_#memory_int| (let ((.cse1 (store |c_old(#memory_int)| c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.base (store (store (store (store (store (store (store (select |c_old(#memory_int)| c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.base) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset (* 4 v_prenex_10)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_11) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_12) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_13) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_14) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_15) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_16) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0)))) (store .cse1 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base (store (store (store (store (store (store (select .cse1 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v_prenex_17)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_91)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0)))) (<= v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92 1))))) (exists ((v_prenex_16 Int) (v_prenex_15 Int) (v_prenex_17 Int) (v_prenex_12 Int) (v_prenex_11 Int) (v_prenex_14 Int) (v_prenex_13 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 Int) (v_prenex_10 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_91 Int) (v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92 Int)) (and (<= v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_91 1)) (<= v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93 1)) (<= 0 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90) (< (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 1) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (<= (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90 1) v_prenex_17) (= |c_#memory_int| (let ((.cse2 (store |c_old(#memory_int)| c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.base (store (store (store (store (store (store (store (select |c_old(#memory_int)| c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.base) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset (* 4 v_prenex_10)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_11) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_12) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_13) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_14) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_15) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ (* 4 v_prenex_16) c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.offset) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0)))) (store .cse2 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base (store (store (store (store (store (store (select .cse2 c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_90)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v_prenex_17)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_91)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0) (+ c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.offset (* 4 v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94)) c_~__U_MULTI_f___________true_valid_memsafety_i__n~0)))) (<= c_~__U_MULTI_f___________true_valid_memsafety_i__n~0 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_94 2)) (<= v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_93 (+ v___U_MULTI_f___________true_valid_memsafety_i__foo_~i~0_92 1)))) (not (= c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.base c_~__U_MULTI_f___________true_valid_memsafety_i__b~0.base)) (= 1 (select |c_#valid| c_~__U_MULTI_f___________true_valid_memsafety_i__a~0.base))) is different from false Cannot interrupt operation gracefully because timeout expired. Forcing shutdown