java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-666feb3-m [2018-04-11 23:06:16,094 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-11 23:06:16,096 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-11 23:06:16,109 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-04-11 23:06:16,109 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-04-11 23:06:16,110 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-04-11 23:06:16,110 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-04-11 23:06:16,112 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-04-11 23:06:16,113 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-04-11 23:06:16,114 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-04-11 23:06:16,115 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-04-11 23:06:16,115 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-04-11 23:06:16,116 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-04-11 23:06:16,116 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-04-11 23:06:16,117 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-04-11 23:06:16,119 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-04-11 23:06:16,120 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-04-11 23:06:16,122 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-04-11 23:06:16,122 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-04-11 23:06:16,123 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-04-11 23:06:16,125 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-04-11 23:06:16,125 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-04-11 23:06:16,125 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-04-11 23:06:16,126 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-04-11 23:06:16,127 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-04-11 23:06:16,128 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-04-11 23:06:16,128 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-04-11 23:06:16,128 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-04-11 23:06:16,129 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-04-11 23:06:16,129 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-04-11 23:06:16,129 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-04-11 23:06:16,130 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-04-11 23:06:16,150 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-11 23:06:16,150 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-11 23:06:16,151 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-11 23:06:16,151 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-11 23:06:16,151 INFO L133 SettingsManager]: * Use SBE=true [2018-04-11 23:06:16,151 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-11 23:06:16,151 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-11 23:06:16,152 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-11 23:06:16,152 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-11 23:06:16,153 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-11 23:06:16,153 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-11 23:06:16,153 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 23:06:16,153 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-11 23:06:16,153 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-11 23:06:16,153 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-11 23:06:16,153 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-11 23:06:16,181 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-11 23:06:16,189 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-11 23:06:16,192 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-11 23:06:16,193 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-11 23:06:16,193 INFO L276 PluginConnector]: CDTParser initialized [2018-04-11 23:06:16,194 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/ldv-memsafety/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-11 23:06:16,482 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGa4e949f0a [2018-04-11 23:06:16,563 INFO L287 CDTParser]: IsIndexed: true [2018-04-11 23:06:16,563 INFO L288 CDTParser]: Found 1 translation units. [2018-04-11 23:06:16,564 INFO L168 CDTParser]: Scanning ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-11 23:06:16,564 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-11 23:06:16,564 INFO L215 ultiparseSymbolTable]: [2018-04-11 23:06:16,564 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-11 23:06:16,565 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__foo ('foo') in ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-11 23:06:16,565 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-11 23:06:16,565 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-11 23:06:16,565 INFO L233 ultiparseSymbolTable]: [2018-04-11 23:06:16,576 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGa4e949f0a [2018-04-11 23:06:16,579 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-11 23:06:16,580 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-11 23:06:16,580 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-11 23:06:16,581 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-11 23:06:16,584 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-11 23:06:16,585 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,587 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@192eed8a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16, skipping insertion in model container [2018-04-11 23:06:16,587 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,598 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 23:06:16,606 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-11 23:06:16,707 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 23:06:16,728 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-11 23:06:16,733 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 9 non ball SCCs. Number of states in SCCs 9. [2018-04-11 23:06:16,740 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16 WrapperNode [2018-04-11 23:06:16,740 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-11 23:06:16,741 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-11 23:06:16,741 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-11 23:06:16,741 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-11 23:06:16,749 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,749 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,757 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,757 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,761 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,765 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,766 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... [2018-04-11 23:06:16,768 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-11 23:06:16,769 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-11 23:06:16,769 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-11 23:06:16,769 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-11 23:06:16,770 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-11 23:06:16,810 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-11 23:06:16,810 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-11 23:06:16,810 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__foo [2018-04-11 23:06:16,810 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__foo [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-11 23:06:16,811 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-11 23:06:17,062 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-11 23:06:17,062 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 11:06:17 BoogieIcfgContainer [2018-04-11 23:06:17,062 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-11 23:06:17,063 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-11 23:06:17,063 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-11 23:06:17,066 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-11 23:06:17,066 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 11.04 11:06:16" (1/3) ... [2018-04-11 23:06:17,067 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@52c5ec7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 11:06:17, skipping insertion in model container [2018-04-11 23:06:17,067 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 11.04 11:06:16" (2/3) ... [2018-04-11 23:06:17,068 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@52c5ec7d and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 11.04 11:06:17, skipping insertion in model container [2018-04-11 23:06:17,068 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 11.04 11:06:17" (3/3) ... [2018-04-11 23:06:17,069 INFO L107 eAbstractionObserver]: Analyzing ICFG ArraysWithLenghtAtDeclaration_false-valid-deref-write.c [2018-04-11 23:06:17,079 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-11 23:06:17,085 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 6 error locations. [2018-04-11 23:06:17,111 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-11 23:06:17,112 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-11 23:06:17,112 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-11 23:06:17,112 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-11 23:06:17,112 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-11 23:06:17,112 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-11 23:06:17,112 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-11 23:06:17,113 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-11 23:06:17,113 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-11 23:06:17,113 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-11 23:06:17,125 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states. [2018-04-11 23:06:17,131 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-04-11 23:06:17,131 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,132 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,132 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,136 INFO L82 PathProgramCache]: Analyzing trace with hash -895474378, now seen corresponding path program 1 times [2018-04-11 23:06:17,138 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,138 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,170 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,171 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,171 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,199 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,204 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:17,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,261 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 23:06:17,262 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-11 23:06:17,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-11 23:06:17,276 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-11 23:06:17,276 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 23:06:17,279 INFO L87 Difference]: Start difference. First operand 46 states. Second operand 3 states. [2018-04-11 23:06:17,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:17,334 INFO L93 Difference]: Finished difference Result 63 states and 68 transitions. [2018-04-11 23:06:17,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-11 23:06:17,336 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-04-11 23:06:17,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:17,344 INFO L225 Difference]: With dead ends: 63 [2018-04-11 23:06:17,344 INFO L226 Difference]: Without dead ends: 59 [2018-04-11 23:06:17,345 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 1 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 23:06:17,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-04-11 23:06:17,369 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 49. [2018-04-11 23:06:17,370 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-04-11 23:06:17,371 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 52 transitions. [2018-04-11 23:06:17,372 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 52 transitions. Word has length 11 [2018-04-11 23:06:17,372 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:17,373 INFO L459 AbstractCegarLoop]: Abstraction has 49 states and 52 transitions. [2018-04-11 23:06:17,373 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-11 23:06:17,373 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 52 transitions. [2018-04-11 23:06:17,373 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-04-11 23:06:17,373 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,373 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,373 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,374 INFO L82 PathProgramCache]: Analyzing trace with hash 1597342241, now seen corresponding path program 1 times [2018-04-11 23:06:17,374 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,374 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,375 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,375 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,375 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,389 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:17,418 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,418 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 23:06:17,418 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-04-11 23:06:17,420 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-11 23:06:17,420 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-11 23:06:17,420 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 23:06:17,421 INFO L87 Difference]: Start difference. First operand 49 states and 52 transitions. Second operand 3 states. [2018-04-11 23:06:17,453 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:17,453 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-04-11 23:06:17,454 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-11 23:06:17,454 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 16 [2018-04-11 23:06:17,454 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:17,456 INFO L225 Difference]: With dead ends: 60 [2018-04-11 23:06:17,457 INFO L226 Difference]: Without dead ends: 60 [2018-04-11 23:06:17,457 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-11 23:06:17,458 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-04-11 23:06:17,461 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 52. [2018-04-11 23:06:17,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-11 23:06:17,462 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 56 transitions. [2018-04-11 23:06:17,462 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 56 transitions. Word has length 16 [2018-04-11 23:06:17,463 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:17,463 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 56 transitions. [2018-04-11 23:06:17,463 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-11 23:06:17,463 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 56 transitions. [2018-04-11 23:06:17,463 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-11 23:06:17,464 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,464 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,464 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,464 INFO L82 PathProgramCache]: Analyzing trace with hash -2021997981, now seen corresponding path program 1 times [2018-04-11 23:06:17,464 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,464 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,465 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,466 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,478 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:17,513 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,513 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 23:06:17,513 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 23:06:17,513 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 23:06:17,514 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 23:06:17,514 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 23:06:17,514 INFO L87 Difference]: Start difference. First operand 52 states and 56 transitions. Second operand 5 states. [2018-04-11 23:06:17,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:17,571 INFO L93 Difference]: Finished difference Result 51 states and 55 transitions. [2018-04-11 23:06:17,571 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 23:06:17,571 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-04-11 23:06:17,572 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:17,572 INFO L225 Difference]: With dead ends: 51 [2018-04-11 23:06:17,572 INFO L226 Difference]: Without dead ends: 51 [2018-04-11 23:06:17,572 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-04-11 23:06:17,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-04-11 23:06:17,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-04-11 23:06:17,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-04-11 23:06:17,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 55 transitions. [2018-04-11 23:06:17,575 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 55 transitions. Word has length 17 [2018-04-11 23:06:17,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:17,575 INFO L459 AbstractCegarLoop]: Abstraction has 51 states and 55 transitions. [2018-04-11 23:06:17,575 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 23:06:17,575 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 55 transitions. [2018-04-11 23:06:17,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-04-11 23:06:17,576 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,576 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,576 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,576 INFO L82 PathProgramCache]: Analyzing trace with hash -2021997980, now seen corresponding path program 1 times [2018-04-11 23:06:17,576 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,576 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,577 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,577 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,584 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,585 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:17,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,642 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 23:06:17,642 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-11 23:06:17,642 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-11 23:06:17,643 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-11 23:06:17,643 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-11 23:06:17,643 INFO L87 Difference]: Start difference. First operand 51 states and 55 transitions. Second operand 6 states. [2018-04-11 23:06:17,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:17,709 INFO L93 Difference]: Finished difference Result 53 states and 57 transitions. [2018-04-11 23:06:17,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 23:06:17,709 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-04-11 23:06:17,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:17,711 INFO L225 Difference]: With dead ends: 53 [2018-04-11 23:06:17,711 INFO L226 Difference]: Without dead ends: 53 [2018-04-11 23:06:17,711 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-04-11 23:06:17,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53 states. [2018-04-11 23:06:17,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53 to 50. [2018-04-11 23:06:17,713 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 50 states. [2018-04-11 23:06:17,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 50 states to 50 states and 54 transitions. [2018-04-11 23:06:17,714 INFO L78 Accepts]: Start accepts. Automaton has 50 states and 54 transitions. Word has length 17 [2018-04-11 23:06:17,714 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:17,715 INFO L459 AbstractCegarLoop]: Abstraction has 50 states and 54 transitions. [2018-04-11 23:06:17,715 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-11 23:06:17,715 INFO L276 IsEmpty]: Start isEmpty. Operand 50 states and 54 transitions. [2018-04-11 23:06:17,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-04-11 23:06:17,715 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,715 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,715 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,715 INFO L82 PathProgramCache]: Analyzing trace with hash -869005287, now seen corresponding path program 1 times [2018-04-11 23:06:17,715 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,715 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,716 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,716 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,716 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,724 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,725 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:17,767 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,767 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:17,767 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:17,774 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,808 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:17,822 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 0 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,841 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:17,841 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [3, 3] total 3 [2018-04-11 23:06:17,841 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-11 23:06:17,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-11 23:06:17,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 23:06:17,842 INFO L87 Difference]: Start difference. First operand 50 states and 54 transitions. Second operand 4 states. [2018-04-11 23:06:17,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:17,864 INFO L93 Difference]: Finished difference Result 65 states and 70 transitions. [2018-04-11 23:06:17,864 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-11 23:06:17,864 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 22 [2018-04-11 23:06:17,864 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:17,864 INFO L225 Difference]: With dead ends: 65 [2018-04-11 23:06:17,865 INFO L226 Difference]: Without dead ends: 65 [2018-04-11 23:06:17,865 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 25 GetRequests, 21 SyntacticMatches, 2 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-11 23:06:17,865 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 65 states. [2018-04-11 23:06:17,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 65 to 56. [2018-04-11 23:06:17,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 56 states. [2018-04-11 23:06:17,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 56 states to 56 states and 61 transitions. [2018-04-11 23:06:17,868 INFO L78 Accepts]: Start accepts. Automaton has 56 states and 61 transitions. Word has length 22 [2018-04-11 23:06:17,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:17,868 INFO L459 AbstractCegarLoop]: Abstraction has 56 states and 61 transitions. [2018-04-11 23:06:17,868 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-11 23:06:17,868 INFO L276 IsEmpty]: Start isEmpty. Operand 56 states and 61 transitions. [2018-04-11 23:06:17,868 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-11 23:06:17,868 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,868 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,869 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,869 INFO L82 PathProgramCache]: Analyzing trace with hash -994035242, now seen corresponding path program 1 times [2018-04-11 23:06:17,869 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,869 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,869 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,869 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,870 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,875 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:17,905 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:17,905 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-11 23:06:17,906 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-11 23:06:17,906 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 23:06:17,906 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 23:06:17,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-11 23:06:17,906 INFO L87 Difference]: Start difference. First operand 56 states and 61 transitions. Second operand 5 states. [2018-04-11 23:06:17,934 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:17,934 INFO L93 Difference]: Finished difference Result 66 states and 71 transitions. [2018-04-11 23:06:17,934 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 23:06:17,934 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 23 [2018-04-11 23:06:17,934 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:17,935 INFO L225 Difference]: With dead ends: 66 [2018-04-11 23:06:17,935 INFO L226 Difference]: Without dead ends: 66 [2018-04-11 23:06:17,935 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=10, Invalid=10, Unknown=0, NotChecked=0, Total=20 [2018-04-11 23:06:17,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-04-11 23:06:17,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 52. [2018-04-11 23:06:17,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 52 states. [2018-04-11 23:06:17,937 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 52 states to 52 states and 57 transitions. [2018-04-11 23:06:17,937 INFO L78 Accepts]: Start accepts. Automaton has 52 states and 57 transitions. Word has length 23 [2018-04-11 23:06:17,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:17,938 INFO L459 AbstractCegarLoop]: Abstraction has 52 states and 57 transitions. [2018-04-11 23:06:17,938 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 23:06:17,938 INFO L276 IsEmpty]: Start isEmpty. Operand 52 states and 57 transitions. [2018-04-11 23:06:17,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-04-11 23:06:17,938 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:17,938 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:17,938 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:17,938 INFO L82 PathProgramCache]: Analyzing trace with hash -561761263, now seen corresponding path program 2 times [2018-04-11 23:06:17,939 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:17,939 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:17,939 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,939 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:17,939 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:17,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:17,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:18,008 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 7 proven. 5 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:18,008 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:18,008 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:18,016 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:18,028 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:18,029 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:18,030 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:18,088 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 12 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:18,115 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-11 23:06:18,115 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [8] total 12 [2018-04-11 23:06:18,115 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 23:06:18,115 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 23:06:18,116 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=95, Unknown=0, NotChecked=0, Total=132 [2018-04-11 23:06:18,116 INFO L87 Difference]: Start difference. First operand 52 states and 57 transitions. Second operand 12 states. [2018-04-11 23:06:18,239 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:18,240 INFO L93 Difference]: Finished difference Result 88 states and 95 transitions. [2018-04-11 23:06:18,240 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 23:06:18,240 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 28 [2018-04-11 23:06:18,240 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:18,241 INFO L225 Difference]: With dead ends: 88 [2018-04-11 23:06:18,241 INFO L226 Difference]: Without dead ends: 88 [2018-04-11 23:06:18,241 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 40 GetRequests, 24 SyntacticMatches, 1 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=87, Invalid=185, Unknown=0, NotChecked=0, Total=272 [2018-04-11 23:06:18,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-04-11 23:06:18,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 72. [2018-04-11 23:06:18,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-04-11 23:06:18,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 79 transitions. [2018-04-11 23:06:18,244 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 79 transitions. Word has length 28 [2018-04-11 23:06:18,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:18,245 INFO L459 AbstractCegarLoop]: Abstraction has 72 states and 79 transitions. [2018-04-11 23:06:18,245 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 23:06:18,245 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 79 transitions. [2018-04-11 23:06:18,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-04-11 23:06:18,245 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:18,245 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:18,246 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:18,246 INFO L82 PathProgramCache]: Analyzing trace with hash 701046357, now seen corresponding path program 1 times [2018-04-11 23:06:18,246 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:18,246 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:18,247 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,247 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:18,247 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:18,254 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:18,274 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:18,275 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:18,275 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:18,283 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:18,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:18,300 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:18,332 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-11 23:06:18,352 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-11 23:06:18,352 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [4] total 7 [2018-04-11 23:06:18,353 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 23:06:18,353 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 23:06:18,353 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-04-11 23:06:18,353 INFO L87 Difference]: Start difference. First operand 72 states and 79 transitions. Second operand 7 states. [2018-04-11 23:06:18,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:18,462 INFO L93 Difference]: Finished difference Result 104 states and 110 transitions. [2018-04-11 23:06:18,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 23:06:18,463 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 31 [2018-04-11 23:06:18,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:18,463 INFO L225 Difference]: With dead ends: 104 [2018-04-11 23:06:18,464 INFO L226 Difference]: Without dead ends: 98 [2018-04-11 23:06:18,464 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 29 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=22, Invalid=50, Unknown=0, NotChecked=0, Total=72 [2018-04-11 23:06:18,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 98 states. [2018-04-11 23:06:18,469 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 98 to 81. [2018-04-11 23:06:18,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-11 23:06:18,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 87 transitions. [2018-04-11 23:06:18,471 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 87 transitions. Word has length 31 [2018-04-11 23:06:18,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:18,471 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 87 transitions. [2018-04-11 23:06:18,471 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 23:06:18,471 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 87 transitions. [2018-04-11 23:06:18,472 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-11 23:06:18,472 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:18,473 INFO L355 BasicCegarLoop]: trace histogram [5, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:18,473 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:18,473 INFO L82 PathProgramCache]: Analyzing trace with hash -1559883415, now seen corresponding path program 1 times [2018-04-11 23:06:18,473 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:18,473 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:18,474 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,474 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:18,474 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:18,489 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:18,536 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 26 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-11 23:06:18,536 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:18,536 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:18,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:18,566 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:18,569 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:18,599 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 26 proven. 2 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-04-11 23:06:18,617 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:18,617 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 8 [2018-04-11 23:06:18,617 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-11 23:06:18,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-11 23:06:18,618 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-11 23:06:18,618 INFO L87 Difference]: Start difference. First operand 81 states and 87 transitions. Second operand 8 states. [2018-04-11 23:06:18,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:18,703 INFO L93 Difference]: Finished difference Result 90 states and 94 transitions. [2018-04-11 23:06:18,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 23:06:18,704 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-04-11 23:06:18,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:18,705 INFO L225 Difference]: With dead ends: 90 [2018-04-11 23:06:18,705 INFO L226 Difference]: Without dead ends: 84 [2018-04-11 23:06:18,705 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 45 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=24, Invalid=48, Unknown=0, NotChecked=0, Total=72 [2018-04-11 23:06:18,706 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-04-11 23:06:18,709 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 81. [2018-04-11 23:06:18,709 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-04-11 23:06:18,711 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 85 transitions. [2018-04-11 23:06:18,711 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 85 transitions. Word has length 46 [2018-04-11 23:06:18,711 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:18,711 INFO L459 AbstractCegarLoop]: Abstraction has 81 states and 85 transitions. [2018-04-11 23:06:18,711 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-11 23:06:18,712 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 85 transitions. [2018-04-11 23:06:18,712 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 53 [2018-04-11 23:06:18,713 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:18,713 INFO L355 BasicCegarLoop]: trace histogram [6, 5, 4, 4, 4, 4, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:18,713 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:18,713 INFO L82 PathProgramCache]: Analyzing trace with hash -250620575, now seen corresponding path program 2 times [2018-04-11 23:06:18,713 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:18,714 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:18,714 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,715 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:18,715 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:18,730 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:18,771 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-04-11 23:06:18,771 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:18,772 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:18,780 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:18,802 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:18,802 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:18,804 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:18,811 INFO L134 CoverageAnalysis]: Checked inductivity of 63 backedges. 36 proven. 12 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-04-11 23:06:18,833 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:18,833 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4] total 4 [2018-04-11 23:06:18,834 INFO L442 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-04-11 23:06:18,834 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-04-11 23:06:18,834 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 23:06:18,834 INFO L87 Difference]: Start difference. First operand 81 states and 85 transitions. Second operand 5 states. [2018-04-11 23:06:18,859 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:18,859 INFO L93 Difference]: Finished difference Result 93 states and 98 transitions. [2018-04-11 23:06:18,859 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-04-11 23:06:18,859 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 52 [2018-04-11 23:06:18,860 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:18,860 INFO L225 Difference]: With dead ends: 93 [2018-04-11 23:06:18,860 INFO L226 Difference]: Without dead ends: 93 [2018-04-11 23:06:18,860 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 56 GetRequests, 51 SyntacticMatches, 2 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-04-11 23:06:18,860 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-04-11 23:06:18,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 87. [2018-04-11 23:06:18,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-04-11 23:06:18,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 92 transitions. [2018-04-11 23:06:18,865 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 92 transitions. Word has length 52 [2018-04-11 23:06:18,865 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:18,865 INFO L459 AbstractCegarLoop]: Abstraction has 87 states and 92 transitions. [2018-04-11 23:06:18,865 INFO L460 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-04-11 23:06:18,866 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 92 transitions. [2018-04-11 23:06:18,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 59 [2018-04-11 23:06:18,867 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:18,867 INFO L355 BasicCegarLoop]: trace histogram [7, 6, 5, 5, 5, 5, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:18,867 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:18,867 INFO L82 PathProgramCache]: Analyzing trace with hash -246224039, now seen corresponding path program 3 times [2018-04-11 23:06:18,867 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:18,868 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:18,868 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,868 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:18,868 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:18,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:18,883 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:18,955 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 70 proven. 12 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-04-11 23:06:18,955 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:18,956 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:18,963 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:06:19,000 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-04-11 23:06:19,000 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:19,002 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:19,047 INFO L134 CoverageAnalysis]: Checked inductivity of 92 backedges. 63 proven. 7 refuted. 0 times theorem prover too weak. 22 trivial. 0 not checked. [2018-04-11 23:06:19,070 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:19,070 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8] total 14 [2018-04-11 23:06:19,070 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-11 23:06:19,071 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-11 23:06:19,071 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=142, Unknown=0, NotChecked=0, Total=182 [2018-04-11 23:06:19,071 INFO L87 Difference]: Start difference. First operand 87 states and 92 transitions. Second operand 14 states. [2018-04-11 23:06:19,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:19,268 INFO L93 Difference]: Finished difference Result 128 states and 133 transitions. [2018-04-11 23:06:19,268 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-11 23:06:19,268 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 58 [2018-04-11 23:06:19,269 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:19,270 INFO L225 Difference]: With dead ends: 128 [2018-04-11 23:06:19,270 INFO L226 Difference]: Without dead ends: 128 [2018-04-11 23:06:19,270 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 40 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=104, Invalid=276, Unknown=0, NotChecked=0, Total=380 [2018-04-11 23:06:19,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-04-11 23:06:19,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 113. [2018-04-11 23:06:19,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-11 23:06:19,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 119 transitions. [2018-04-11 23:06:19,275 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 119 transitions. Word has length 58 [2018-04-11 23:06:19,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:19,275 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 119 transitions. [2018-04-11 23:06:19,275 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-11 23:06:19,275 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 119 transitions. [2018-04-11 23:06:19,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-04-11 23:06:19,276 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:19,276 INFO L355 BasicCegarLoop]: trace histogram [6, 4, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:19,276 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:19,276 INFO L82 PathProgramCache]: Analyzing trace with hash 404087573, now seen corresponding path program 1 times [2018-04-11 23:06:19,277 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:19,277 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:19,277 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:19,277 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:19,278 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:19,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:19,290 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:19,347 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 43 proven. 7 refuted. 0 times theorem prover too weak. 18 trivial. 0 not checked. [2018-04-11 23:06:19,347 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:19,347 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:19,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:19,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:19,380 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:19,442 INFO L134 CoverageAnalysis]: Checked inductivity of 68 backedges. 47 proven. 10 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-04-11 23:06:19,459 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:19,459 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2018-04-11 23:06:19,460 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-11 23:06:19,460 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-11 23:06:19,460 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=41, Invalid=141, Unknown=0, NotChecked=0, Total=182 [2018-04-11 23:06:19,460 INFO L87 Difference]: Start difference. First operand 113 states and 119 transitions. Second operand 14 states. [2018-04-11 23:06:19,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:19,593 INFO L93 Difference]: Finished difference Result 108 states and 110 transitions. [2018-04-11 23:06:19,593 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 23:06:19,593 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 67 [2018-04-11 23:06:19,593 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:19,593 INFO L225 Difference]: With dead ends: 108 [2018-04-11 23:06:19,593 INFO L226 Difference]: Without dead ends: 102 [2018-04-11 23:06:19,594 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 87 GetRequests, 64 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 116 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=142, Invalid=458, Unknown=0, NotChecked=0, Total=600 [2018-04-11 23:06:19,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-04-11 23:06:19,596 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 92. [2018-04-11 23:06:19,596 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 92 states. [2018-04-11 23:06:19,596 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 92 states to 92 states and 93 transitions. [2018-04-11 23:06:19,596 INFO L78 Accepts]: Start accepts. Automaton has 92 states and 93 transitions. Word has length 67 [2018-04-11 23:06:19,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:19,596 INFO L459 AbstractCegarLoop]: Abstraction has 92 states and 93 transitions. [2018-04-11 23:06:19,596 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-11 23:06:19,596 INFO L276 IsEmpty]: Start isEmpty. Operand 92 states and 93 transitions. [2018-04-11 23:06:19,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 89 [2018-04-11 23:06:19,597 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:19,597 INFO L355 BasicCegarLoop]: trace histogram [11, 9, 8, 8, 8, 8, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:19,597 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:19,597 INFO L82 PathProgramCache]: Analyzing trace with hash -264260447, now seen corresponding path program 4 times [2018-04-11 23:06:19,597 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:19,597 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:19,598 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:19,598 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:19,598 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:19,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:19,607 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:19,650 INFO L134 CoverageAnalysis]: Checked inductivity of 250 backedges. 121 proven. 27 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2018-04-11 23:06:19,650 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:19,650 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:19,659 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:06:19,682 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:06:19,683 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:19,686 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:19,709 INFO L134 CoverageAnalysis]: Checked inductivity of 250 backedges. 121 proven. 27 refuted. 0 times theorem prover too weak. 102 trivial. 0 not checked. [2018-04-11 23:06:19,727 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:19,728 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5] total 9 [2018-04-11 23:06:19,728 INFO L442 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-04-11 23:06:19,728 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-04-11 23:06:19,728 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-04-11 23:06:19,729 INFO L87 Difference]: Start difference. First operand 92 states and 93 transitions. Second operand 10 states. [2018-04-11 23:06:19,775 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:19,775 INFO L93 Difference]: Finished difference Result 104 states and 106 transitions. [2018-04-11 23:06:19,775 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-11 23:06:19,775 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 88 [2018-04-11 23:06:19,776 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:19,776 INFO L225 Difference]: With dead ends: 104 [2018-04-11 23:06:19,776 INFO L226 Difference]: Without dead ends: 104 [2018-04-11 23:06:19,777 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 93 GetRequests, 85 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=30, Invalid=60, Unknown=0, NotChecked=0, Total=90 [2018-04-11 23:06:19,777 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 104 states. [2018-04-11 23:06:19,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 104 to 98. [2018-04-11 23:06:19,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 98 states. [2018-04-11 23:06:19,780 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 98 states to 98 states and 100 transitions. [2018-04-11 23:06:19,780 INFO L78 Accepts]: Start accepts. Automaton has 98 states and 100 transitions. Word has length 88 [2018-04-11 23:06:19,781 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:19,781 INFO L459 AbstractCegarLoop]: Abstraction has 98 states and 100 transitions. [2018-04-11 23:06:19,781 INFO L460 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-04-11 23:06:19,781 INFO L276 IsEmpty]: Start isEmpty. Operand 98 states and 100 transitions. [2018-04-11 23:06:19,782 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-04-11 23:06:19,782 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:19,782 INFO L355 BasicCegarLoop]: trace histogram [12, 10, 9, 9, 9, 9, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:19,782 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:19,782 INFO L82 PathProgramCache]: Analyzing trace with hash 1483627161, now seen corresponding path program 5 times [2018-04-11 23:06:19,783 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:19,783 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:19,783 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:19,783 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:19,784 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:19,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:19,797 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:19,895 INFO L134 CoverageAnalysis]: Checked inductivity of 305 backedges. 194 proven. 25 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-04-11 23:06:19,895 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:19,896 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:19,904 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:06:19,932 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 5 check-sat command(s) [2018-04-11 23:06:19,932 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:19,934 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:19,994 INFO L134 CoverageAnalysis]: Checked inductivity of 305 backedges. 205 proven. 14 refuted. 0 times theorem prover too weak. 86 trivial. 0 not checked. [2018-04-11 23:06:20,012 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:20,012 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12] total 18 [2018-04-11 23:06:20,012 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-11 23:06:20,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-11 23:06:20,013 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=79, Invalid=227, Unknown=0, NotChecked=0, Total=306 [2018-04-11 23:06:20,013 INFO L87 Difference]: Start difference. First operand 98 states and 100 transitions. Second operand 18 states. [2018-04-11 23:06:20,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:20,148 INFO L93 Difference]: Finished difference Result 139 states and 142 transitions. [2018-04-11 23:06:20,149 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-11 23:06:20,149 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 94 [2018-04-11 23:06:20,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:20,150 INFO L225 Difference]: With dead ends: 139 [2018-04-11 23:06:20,150 INFO L226 Difference]: Without dead ends: 139 [2018-04-11 23:06:20,150 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 112 GetRequests, 89 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 71 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=174, Invalid=426, Unknown=0, NotChecked=0, Total=600 [2018-04-11 23:06:20,150 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-04-11 23:06:20,153 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 134. [2018-04-11 23:06:20,153 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-04-11 23:06:20,154 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 137 transitions. [2018-04-11 23:06:20,154 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 137 transitions. Word has length 94 [2018-04-11 23:06:20,154 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:20,155 INFO L459 AbstractCegarLoop]: Abstraction has 134 states and 137 transitions. [2018-04-11 23:06:20,155 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-11 23:06:20,155 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 137 transitions. [2018-04-11 23:06:20,156 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-04-11 23:06:20,156 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:20,156 INFO L355 BasicCegarLoop]: trace histogram [16, 13, 12, 12, 12, 12, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:20,156 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:20,156 INFO L82 PathProgramCache]: Analyzing trace with hash -1650581535, now seen corresponding path program 6 times [2018-04-11 23:06:20,157 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:20,157 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:20,157 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:20,157 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:20,157 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:20,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:20,174 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:20,271 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 401 proven. 24 refuted. 0 times theorem prover too weak. 136 trivial. 0 not checked. [2018-04-11 23:06:20,271 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:20,272 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:20,279 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:06:20,322 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 6 check-sat command(s) [2018-04-11 23:06:20,322 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:20,326 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:20,628 INFO L134 CoverageAnalysis]: Checked inductivity of 561 backedges. 313 proven. 119 refuted. 0 times theorem prover too weak. 129 trivial. 0 not checked. [2018-04-11 23:06:20,647 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:20,674 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 13] total 21 [2018-04-11 23:06:20,674 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-11 23:06:20,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-11 23:06:20,675 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=72, Invalid=348, Unknown=0, NotChecked=0, Total=420 [2018-04-11 23:06:20,675 INFO L87 Difference]: Start difference. First operand 134 states and 137 transitions. Second operand 21 states. [2018-04-11 23:06:21,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:21,030 INFO L93 Difference]: Finished difference Result 145 states and 146 transitions. [2018-04-11 23:06:21,031 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-11 23:06:21,031 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 124 [2018-04-11 23:06:21,031 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:21,031 INFO L225 Difference]: With dead ends: 145 [2018-04-11 23:06:21,031 INFO L226 Difference]: Without dead ends: 139 [2018-04-11 23:06:21,032 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 114 SyntacticMatches, 0 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 333 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=254, Invalid=1078, Unknown=0, NotChecked=0, Total=1332 [2018-04-11 23:06:21,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-04-11 23:06:21,034 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 134. [2018-04-11 23:06:21,035 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 134 states. [2018-04-11 23:06:21,035 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 134 states to 134 states and 135 transitions. [2018-04-11 23:06:21,035 INFO L78 Accepts]: Start accepts. Automaton has 134 states and 135 transitions. Word has length 124 [2018-04-11 23:06:21,036 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:21,036 INFO L459 AbstractCegarLoop]: Abstraction has 134 states and 135 transitions. [2018-04-11 23:06:21,036 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-11 23:06:21,036 INFO L276 IsEmpty]: Start isEmpty. Operand 134 states and 135 transitions. [2018-04-11 23:06:21,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 131 [2018-04-11 23:06:21,037 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:21,037 INFO L355 BasicCegarLoop]: trace histogram [17, 14, 13, 13, 13, 13, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:21,037 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:21,038 INFO L82 PathProgramCache]: Analyzing trace with hash 1018374617, now seen corresponding path program 7 times [2018-04-11 23:06:21,038 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:21,038 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:21,038 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:21,038 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:21,038 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:21,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:21,052 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:21,108 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-04-11 23:06:21,108 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:21,108 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:21,113 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:21,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:21,147 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:21,166 INFO L134 CoverageAnalysis]: Checked inductivity of 642 backedges. 273 proven. 48 refuted. 0 times theorem prover too weak. 321 trivial. 0 not checked. [2018-04-11 23:06:21,194 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:21,194 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 6 [2018-04-11 23:06:21,194 INFO L442 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-04-11 23:06:21,195 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-04-11 23:06:21,195 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-04-11 23:06:21,195 INFO L87 Difference]: Start difference. First operand 134 states and 135 transitions. Second operand 7 states. [2018-04-11 23:06:21,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:21,271 INFO L93 Difference]: Finished difference Result 146 states and 148 transitions. [2018-04-11 23:06:21,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-11 23:06:21,271 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 130 [2018-04-11 23:06:21,271 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:21,271 INFO L225 Difference]: With dead ends: 146 [2018-04-11 23:06:21,272 INFO L226 Difference]: Without dead ends: 146 [2018-04-11 23:06:21,272 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 129 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=11, Invalid=31, Unknown=0, NotChecked=0, Total=42 [2018-04-11 23:06:21,272 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 146 states. [2018-04-11 23:06:21,273 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 146 to 140. [2018-04-11 23:06:21,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 140 states. [2018-04-11 23:06:21,274 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 140 states to 140 states and 142 transitions. [2018-04-11 23:06:21,274 INFO L78 Accepts]: Start accepts. Automaton has 140 states and 142 transitions. Word has length 130 [2018-04-11 23:06:21,274 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:21,274 INFO L459 AbstractCegarLoop]: Abstraction has 140 states and 142 transitions. [2018-04-11 23:06:21,274 INFO L460 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-04-11 23:06:21,274 INFO L276 IsEmpty]: Start isEmpty. Operand 140 states and 142 transitions. [2018-04-11 23:06:21,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-04-11 23:06:21,275 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:21,275 INFO L355 BasicCegarLoop]: trace histogram [18, 15, 14, 14, 14, 14, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:21,275 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:21,275 INFO L82 PathProgramCache]: Analyzing trace with hash 236127697, now seen corresponding path program 8 times [2018-04-11 23:06:21,275 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:21,275 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:21,276 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:21,276 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:21,276 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:21,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:21,295 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:21,443 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 397 proven. 44 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-04-11 23:06:21,443 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:21,443 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:21,451 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:21,487 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:21,487 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:21,491 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:21,593 INFO L134 CoverageAnalysis]: Checked inductivity of 729 backedges. 411 proven. 30 refuted. 0 times theorem prover too weak. 288 trivial. 0 not checked. [2018-04-11 23:06:21,611 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:21,611 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 21 [2018-04-11 23:06:21,611 INFO L442 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-04-11 23:06:21,611 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-04-11 23:06:21,611 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=106, Invalid=314, Unknown=0, NotChecked=0, Total=420 [2018-04-11 23:06:21,611 INFO L87 Difference]: Start difference. First operand 140 states and 142 transitions. Second operand 21 states. [2018-04-11 23:06:21,793 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:21,793 INFO L93 Difference]: Finished difference Result 187 states and 190 transitions. [2018-04-11 23:06:21,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 23:06:21,793 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 136 [2018-04-11 23:06:21,793 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:21,794 INFO L225 Difference]: With dead ends: 187 [2018-04-11 23:06:21,794 INFO L226 Difference]: Without dead ends: 187 [2018-04-11 23:06:21,794 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 158 GetRequests, 130 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 113 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=247, Invalid=623, Unknown=0, NotChecked=0, Total=870 [2018-04-11 23:06:21,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-04-11 23:06:21,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 182. [2018-04-11 23:06:21,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-04-11 23:06:21,797 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 185 transitions. [2018-04-11 23:06:21,797 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 185 transitions. Word has length 136 [2018-04-11 23:06:21,797 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:21,798 INFO L459 AbstractCegarLoop]: Abstraction has 182 states and 185 transitions. [2018-04-11 23:06:21,798 INFO L460 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-04-11 23:06:21,798 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 185 transitions. [2018-04-11 23:06:21,798 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 173 [2018-04-11 23:06:21,799 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:21,799 INFO L355 BasicCegarLoop]: trace histogram [23, 19, 18, 18, 18, 18, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:21,799 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:21,799 INFO L82 PathProgramCache]: Analyzing trace with hash -1774140143, now seen corresponding path program 9 times [2018-04-11 23:06:21,799 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:21,799 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:21,799 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:21,799 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:21,799 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:21,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:21,812 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:21,920 INFO L134 CoverageAnalysis]: Checked inductivity of 1216 backedges. 806 proven. 44 refuted. 0 times theorem prover too weak. 366 trivial. 0 not checked. [2018-04-11 23:06:21,920 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:21,920 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:21,925 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:06:21,949 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-04-11 23:06:21,949 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:21,951 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:22,058 INFO L134 CoverageAnalysis]: Checked inductivity of 1216 backedges. 503 proven. 57 refuted. 0 times theorem prover too weak. 656 trivial. 0 not checked. [2018-04-11 23:06:22,074 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:22,074 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 22 [2018-04-11 23:06:22,075 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 23:06:22,075 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 23:06:22,075 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=71, Invalid=391, Unknown=0, NotChecked=0, Total=462 [2018-04-11 23:06:22,075 INFO L87 Difference]: Start difference. First operand 182 states and 185 transitions. Second operand 22 states. [2018-04-11 23:06:22,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:22,521 INFO L93 Difference]: Finished difference Result 242 states and 244 transitions. [2018-04-11 23:06:22,521 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-04-11 23:06:22,521 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 172 [2018-04-11 23:06:22,521 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:22,522 INFO L225 Difference]: With dead ends: 242 [2018-04-11 23:06:22,522 INFO L226 Difference]: Without dead ends: 233 [2018-04-11 23:06:22,523 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 212 GetRequests, 168 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 480 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=365, Invalid=1705, Unknown=0, NotChecked=0, Total=2070 [2018-04-11 23:06:22,523 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 233 states. [2018-04-11 23:06:22,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 233 to 224. [2018-04-11 23:06:22,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 224 states. [2018-04-11 23:06:22,525 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 226 transitions. [2018-04-11 23:06:22,525 INFO L78 Accepts]: Start accepts. Automaton has 224 states and 226 transitions. Word has length 172 [2018-04-11 23:06:22,526 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:22,526 INFO L459 AbstractCegarLoop]: Abstraction has 224 states and 226 transitions. [2018-04-11 23:06:22,526 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 23:06:22,526 INFO L276 IsEmpty]: Start isEmpty. Operand 224 states and 226 transitions. [2018-04-11 23:06:22,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 221 [2018-04-11 23:06:22,526 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:22,526 INFO L355 BasicCegarLoop]: trace histogram [30, 25, 24, 24, 24, 24, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:22,527 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:22,527 INFO L82 PathProgramCache]: Analyzing trace with hash -696038847, now seen corresponding path program 10 times [2018-04-11 23:06:22,527 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:22,527 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:22,527 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:22,528 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:22,528 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:22,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:22,544 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:22,696 INFO L134 CoverageAnalysis]: Checked inductivity of 2123 backedges. 1280 proven. 70 refuted. 0 times theorem prover too weak. 773 trivial. 0 not checked. [2018-04-11 23:06:22,696 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:22,696 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:22,704 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:06:22,747 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:06:22,748 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:22,751 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:22,865 INFO L134 CoverageAnalysis]: Checked inductivity of 2123 backedges. 1280 proven. 70 refuted. 0 times theorem prover too weak. 773 trivial. 0 not checked. [2018-04-11 23:06:22,881 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:22,881 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14] total 20 [2018-04-11 23:06:22,882 INFO L442 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-04-11 23:06:22,882 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-04-11 23:06:22,882 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-04-11 23:06:22,882 INFO L87 Difference]: Start difference. First operand 224 states and 226 transitions. Second operand 20 states. [2018-04-11 23:06:23,033 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:23,034 INFO L93 Difference]: Finished difference Result 250 states and 252 transitions. [2018-04-11 23:06:23,034 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 23:06:23,034 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 220 [2018-04-11 23:06:23,034 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:23,035 INFO L225 Difference]: With dead ends: 250 [2018-04-11 23:06:23,035 INFO L226 Difference]: Without dead ends: 244 [2018-04-11 23:06:23,035 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 237 GetRequests, 215 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 145 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=141, Invalid=411, Unknown=0, NotChecked=0, Total=552 [2018-04-11 23:06:23,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 244 states. [2018-04-11 23:06:23,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 244 to 235. [2018-04-11 23:06:23,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 235 states. [2018-04-11 23:06:23,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235 states to 235 states and 237 transitions. [2018-04-11 23:06:23,038 INFO L78 Accepts]: Start accepts. Automaton has 235 states and 237 transitions. Word has length 220 [2018-04-11 23:06:23,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:23,038 INFO L459 AbstractCegarLoop]: Abstraction has 235 states and 237 transitions. [2018-04-11 23:06:23,038 INFO L460 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-04-11 23:06:23,038 INFO L276 IsEmpty]: Start isEmpty. Operand 235 states and 237 transitions. [2018-04-11 23:06:23,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-04-11 23:06:23,039 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:23,039 INFO L355 BasicCegarLoop]: trace histogram [31, 26, 25, 25, 25, 25, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:23,039 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:23,039 INFO L82 PathProgramCache]: Analyzing trace with hash 1622674489, now seen corresponding path program 11 times [2018-04-11 23:06:23,039 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:23,039 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:23,039 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:23,040 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:23,040 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:23,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:23,058 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:23,142 INFO L134 CoverageAnalysis]: Checked inductivity of 2280 backedges. 720 proven. 75 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-11 23:06:23,142 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:23,142 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:23,148 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:06:23,199 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-04-11 23:06:23,199 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:23,202 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:23,240 INFO L134 CoverageAnalysis]: Checked inductivity of 2280 backedges. 720 proven. 75 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-11 23:06:23,258 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:23,258 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8] total 14 [2018-04-11 23:06:23,258 INFO L442 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-04-11 23:06:23,258 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-04-11 23:06:23,258 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=63, Invalid=147, Unknown=0, NotChecked=0, Total=210 [2018-04-11 23:06:23,258 INFO L87 Difference]: Start difference. First operand 235 states and 237 transitions. Second operand 15 states. [2018-04-11 23:06:23,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:23,345 INFO L93 Difference]: Finished difference Result 243 states and 245 transitions. [2018-04-11 23:06:23,345 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-11 23:06:23,345 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 226 [2018-04-11 23:06:23,345 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:23,346 INFO L225 Difference]: With dead ends: 243 [2018-04-11 23:06:23,346 INFO L226 Difference]: Without dead ends: 243 [2018-04-11 23:06:23,346 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 219 SyntacticMatches, 1 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=63, Invalid=147, Unknown=0, NotChecked=0, Total=210 [2018-04-11 23:06:23,346 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-04-11 23:06:23,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 236. [2018-04-11 23:06:23,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 236 states. [2018-04-11 23:06:23,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 236 states to 236 states and 238 transitions. [2018-04-11 23:06:23,349 INFO L78 Accepts]: Start accepts. Automaton has 236 states and 238 transitions. Word has length 226 [2018-04-11 23:06:23,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:23,349 INFO L459 AbstractCegarLoop]: Abstraction has 236 states and 238 transitions. [2018-04-11 23:06:23,349 INFO L460 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-04-11 23:06:23,349 INFO L276 IsEmpty]: Start isEmpty. Operand 236 states and 238 transitions. [2018-04-11 23:06:23,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 233 [2018-04-11 23:06:23,350 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:23,350 INFO L355 BasicCegarLoop]: trace histogram [32, 27, 26, 26, 26, 26, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:23,350 INFO L408 AbstractCegarLoop]: === Iteration 21 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:23,350 INFO L82 PathProgramCache]: Analyzing trace with hash 901554225, now seen corresponding path program 12 times [2018-04-11 23:06:23,350 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:23,350 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:23,350 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:23,350 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:23,350 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:23,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:23,371 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:23,623 INFO L134 CoverageAnalysis]: Checked inductivity of 2443 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-11 23:06:23,623 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:23,623 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:23,628 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:06:23,688 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-04-11 23:06:23,688 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:23,691 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:23,728 INFO L134 CoverageAnalysis]: Checked inductivity of 2443 backedges. 850 proven. 108 refuted. 0 times theorem prover too weak. 1485 trivial. 0 not checked. [2018-04-11 23:06:23,745 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:23,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 13 [2018-04-11 23:06:23,746 INFO L442 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-04-11 23:06:23,746 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-04-11 23:06:23,746 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=56, Invalid=126, Unknown=0, NotChecked=0, Total=182 [2018-04-11 23:06:23,746 INFO L87 Difference]: Start difference. First operand 236 states and 238 transitions. Second operand 14 states. [2018-04-11 23:06:23,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:23,823 INFO L93 Difference]: Finished difference Result 261 states and 265 transitions. [2018-04-11 23:06:23,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-04-11 23:06:23,823 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 232 [2018-04-11 23:06:23,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:23,824 INFO L225 Difference]: With dead ends: 261 [2018-04-11 23:06:23,824 INFO L226 Difference]: Without dead ends: 261 [2018-04-11 23:06:23,824 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 245 GetRequests, 228 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 57 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=110, Invalid=232, Unknown=0, NotChecked=0, Total=342 [2018-04-11 23:06:23,824 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 261 states. [2018-04-11 23:06:23,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 261 to 242. [2018-04-11 23:06:23,826 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 242 states. [2018-04-11 23:06:23,827 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242 states to 242 states and 245 transitions. [2018-04-11 23:06:23,827 INFO L78 Accepts]: Start accepts. Automaton has 242 states and 245 transitions. Word has length 232 [2018-04-11 23:06:23,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:23,827 INFO L459 AbstractCegarLoop]: Abstraction has 242 states and 245 transitions. [2018-04-11 23:06:23,827 INFO L460 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-04-11 23:06:23,827 INFO L276 IsEmpty]: Start isEmpty. Operand 242 states and 245 transitions. [2018-04-11 23:06:23,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 239 [2018-04-11 23:06:23,828 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:23,828 INFO L355 BasicCegarLoop]: trace histogram [33, 28, 27, 27, 27, 27, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:23,828 INFO L408 AbstractCegarLoop]: === Iteration 22 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:23,828 INFO L82 PathProgramCache]: Analyzing trace with hash -1429186007, now seen corresponding path program 13 times [2018-04-11 23:06:23,828 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:23,828 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:23,828 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:23,828 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:23,829 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:23,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:23,843 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:24,061 INFO L134 CoverageAnalysis]: Checked inductivity of 2612 backedges. 1112 proven. 100 refuted. 0 times theorem prover too weak. 1400 trivial. 0 not checked. [2018-04-11 23:06:24,061 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:24,061 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:24,066 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:24,114 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:24,117 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:24,244 INFO L134 CoverageAnalysis]: Checked inductivity of 2612 backedges. 1132 proven. 80 refuted. 0 times theorem prover too weak. 1400 trivial. 0 not checked. [2018-04-11 23:06:24,262 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:24,262 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17] total 27 [2018-04-11 23:06:24,263 INFO L442 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-04-11 23:06:24,263 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-04-11 23:06:24,263 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=172, Invalid=530, Unknown=0, NotChecked=0, Total=702 [2018-04-11 23:06:24,263 INFO L87 Difference]: Start difference. First operand 242 states and 245 transitions. Second operand 27 states. [2018-04-11 23:06:24,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:24,530 INFO L93 Difference]: Finished difference Result 310 states and 314 transitions. [2018-04-11 23:06:24,530 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 23:06:24,530 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 238 [2018-04-11 23:06:24,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:24,531 INFO L225 Difference]: With dead ends: 310 [2018-04-11 23:06:24,531 INFO L226 Difference]: Without dead ends: 310 [2018-04-11 23:06:24,531 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 268 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=429, Invalid=1131, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 23:06:24,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 310 states. [2018-04-11 23:06:24,535 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 310 to 302. [2018-04-11 23:06:24,535 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-04-11 23:06:24,536 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 306 transitions. [2018-04-11 23:06:24,537 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 306 transitions. Word has length 238 [2018-04-11 23:06:24,537 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:24,537 INFO L459 AbstractCegarLoop]: Abstraction has 302 states and 306 transitions. [2018-04-11 23:06:24,537 INFO L460 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-04-11 23:06:24,537 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 306 transitions. [2018-04-11 23:06:24,538 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-04-11 23:06:24,539 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:24,539 INFO L355 BasicCegarLoop]: trace histogram [40, 34, 33, 33, 33, 33, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:24,539 INFO L408 AbstractCegarLoop]: === Iteration 23 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:24,539 INFO L82 PathProgramCache]: Analyzing trace with hash -1943743655, now seen corresponding path program 14 times [2018-04-11 23:06:24,539 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:24,539 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:24,539 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:24,539 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:24,540 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:24,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:24,565 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:24,927 INFO L134 CoverageAnalysis]: Checked inductivity of 3885 backedges. 2231 proven. 102 refuted. 0 times theorem prover too weak. 1552 trivial. 0 not checked. [2018-04-11 23:06:24,927 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:24,927 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:24,932 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:24,980 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:24,981 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:24,986 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:25,143 INFO L134 CoverageAnalysis]: Checked inductivity of 3885 backedges. 2231 proven. 102 refuted. 0 times theorem prover too weak. 1552 trivial. 0 not checked. [2018-04-11 23:06:25,171 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:25,171 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16] total 23 [2018-04-11 23:06:25,240 INFO L442 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-04-11 23:06:25,241 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-04-11 23:06:25,241 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=134, Invalid=372, Unknown=0, NotChecked=0, Total=506 [2018-04-11 23:06:25,241 INFO L87 Difference]: Start difference. First operand 302 states and 306 transitions. Second operand 23 states. [2018-04-11 23:06:25,485 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:25,485 INFO L93 Difference]: Finished difference Result 314 states and 316 transitions. [2018-04-11 23:06:25,485 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 23:06:25,486 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 286 [2018-04-11 23:06:25,486 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:25,486 INFO L225 Difference]: With dead ends: 314 [2018-04-11 23:06:25,487 INFO L226 Difference]: Without dead ends: 308 [2018-04-11 23:06:25,487 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 306 GetRequests, 280 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 211 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=189, Invalid=567, Unknown=0, NotChecked=0, Total=756 [2018-04-11 23:06:25,487 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 308 states. [2018-04-11 23:06:25,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 308 to 302. [2018-04-11 23:06:25,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 302 states. [2018-04-11 23:06:25,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 302 states to 302 states and 304 transitions. [2018-04-11 23:06:25,490 INFO L78 Accepts]: Start accepts. Automaton has 302 states and 304 transitions. Word has length 286 [2018-04-11 23:06:25,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:25,490 INFO L459 AbstractCegarLoop]: Abstraction has 302 states and 304 transitions. [2018-04-11 23:06:25,490 INFO L460 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-04-11 23:06:25,490 INFO L276 IsEmpty]: Start isEmpty. Operand 302 states and 304 transitions. [2018-04-11 23:06:25,491 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 293 [2018-04-11 23:06:25,491 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:25,491 INFO L355 BasicCegarLoop]: trace histogram [41, 35, 34, 34, 34, 34, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:25,491 INFO L408 AbstractCegarLoop]: === Iteration 24 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:25,491 INFO L82 PathProgramCache]: Analyzing trace with hash -1874435247, now seen corresponding path program 15 times [2018-04-11 23:06:25,491 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:25,491 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:25,492 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:25,492 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:25,492 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:25,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:25,507 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:25,688 INFO L134 CoverageAnalysis]: Checked inductivity of 4098 backedges. 1311 proven. 147 refuted. 0 times theorem prover too weak. 2640 trivial. 0 not checked. [2018-04-11 23:06:25,688 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:25,688 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:25,696 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:06:25,786 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 8 check-sat command(s) [2018-04-11 23:06:25,787 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:25,791 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:25,852 INFO L134 CoverageAnalysis]: Checked inductivity of 4098 backedges. 1311 proven. 147 refuted. 0 times theorem prover too weak. 2640 trivial. 0 not checked. [2018-04-11 23:06:25,883 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:25,883 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10] total 11 [2018-04-11 23:06:25,884 INFO L442 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-04-11 23:06:25,884 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-04-11 23:06:25,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=81, Unknown=0, NotChecked=0, Total=132 [2018-04-11 23:06:25,884 INFO L87 Difference]: Start difference. First operand 302 states and 304 transitions. Second operand 12 states. [2018-04-11 23:06:26,002 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:26,002 INFO L93 Difference]: Finished difference Result 317 states and 320 transitions. [2018-04-11 23:06:26,002 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-11 23:06:26,002 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 292 [2018-04-11 23:06:26,003 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:26,004 INFO L225 Difference]: With dead ends: 317 [2018-04-11 23:06:26,004 INFO L226 Difference]: Without dead ends: 317 [2018-04-11 23:06:26,004 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 307 GetRequests, 291 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 43 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=111, Invalid=195, Unknown=0, NotChecked=0, Total=306 [2018-04-11 23:06:26,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2018-04-11 23:06:26,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 308. [2018-04-11 23:06:26,009 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 308 states. [2018-04-11 23:06:26,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 308 states to 308 states and 311 transitions. [2018-04-11 23:06:26,010 INFO L78 Accepts]: Start accepts. Automaton has 308 states and 311 transitions. Word has length 292 [2018-04-11 23:06:26,011 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:26,011 INFO L459 AbstractCegarLoop]: Abstraction has 308 states and 311 transitions. [2018-04-11 23:06:26,011 INFO L460 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-04-11 23:06:26,011 INFO L276 IsEmpty]: Start isEmpty. Operand 308 states and 311 transitions. [2018-04-11 23:06:26,012 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 299 [2018-04-11 23:06:26,012 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:26,013 INFO L355 BasicCegarLoop]: trace histogram [42, 36, 35, 35, 35, 35, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:26,013 INFO L408 AbstractCegarLoop]: === Iteration 25 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:26,013 INFO L82 PathProgramCache]: Analyzing trace with hash 914572617, now seen corresponding path program 16 times [2018-04-11 23:06:26,013 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:26,013 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:26,014 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:26,014 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:26,014 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:26,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:26,041 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:26,505 INFO L134 CoverageAnalysis]: Checked inductivity of 4317 backedges. 1660 proven. 137 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-04-11 23:06:26,506 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:26,506 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:26,511 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:06:26,549 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:06:26,549 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:26,552 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:26,697 INFO L134 CoverageAnalysis]: Checked inductivity of 4317 backedges. 1683 proven. 114 refuted. 0 times theorem prover too weak. 2520 trivial. 0 not checked. [2018-04-11 23:06:26,714 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:26,714 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19] total 30 [2018-04-11 23:06:26,714 INFO L442 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-04-11 23:06:26,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-04-11 23:06:26,715 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=659, Unknown=0, NotChecked=0, Total=870 [2018-04-11 23:06:26,715 INFO L87 Difference]: Start difference. First operand 308 states and 311 transitions. Second operand 30 states. [2018-04-11 23:06:27,083 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:27,083 INFO L93 Difference]: Finished difference Result 376 states and 380 transitions. [2018-04-11 23:06:27,083 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-11 23:06:27,083 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 298 [2018-04-11 23:06:27,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:27,084 INFO L225 Difference]: With dead ends: 376 [2018-04-11 23:06:27,084 INFO L226 Difference]: Without dead ends: 376 [2018-04-11 23:06:27,085 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 332 GetRequests, 289 SyntacticMatches, 0 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 293 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=538, Invalid=1442, Unknown=0, NotChecked=0, Total=1980 [2018-04-11 23:06:27,085 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 376 states. [2018-04-11 23:06:27,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 376 to 368. [2018-04-11 23:06:27,089 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-04-11 23:06:27,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 372 transitions. [2018-04-11 23:06:27,091 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 372 transitions. Word has length 298 [2018-04-11 23:06:27,091 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:27,091 INFO L459 AbstractCegarLoop]: Abstraction has 368 states and 372 transitions. [2018-04-11 23:06:27,091 INFO L460 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-04-11 23:06:27,091 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 372 transitions. [2018-04-11 23:06:27,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 353 [2018-04-11 23:06:27,093 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:27,093 INFO L355 BasicCegarLoop]: trace histogram [50, 43, 42, 42, 42, 42, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:27,093 INFO L408 AbstractCegarLoop]: === Iteration 26 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:27,093 INFO L82 PathProgramCache]: Analyzing trace with hash -604052879, now seen corresponding path program 17 times [2018-04-11 23:06:27,094 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:27,094 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:27,094 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:27,094 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:27,094 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:27,121 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:27,123 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:27,478 INFO L134 CoverageAnalysis]: Checked inductivity of 6181 backedges. 3323 proven. 140 refuted. 0 times theorem prover too weak. 2718 trivial. 0 not checked. [2018-04-11 23:06:27,479 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:27,479 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:27,484 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:06:27,576 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 15 check-sat command(s) [2018-04-11 23:06:27,576 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:27,580 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:27,687 INFO L134 CoverageAnalysis]: Checked inductivity of 6181 backedges. 3323 proven. 140 refuted. 0 times theorem prover too weak. 2718 trivial. 0 not checked. [2018-04-11 23:06:27,705 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:27,705 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 26 [2018-04-11 23:06:27,705 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-11 23:06:27,706 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-11 23:06:27,706 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=169, Invalid=481, Unknown=0, NotChecked=0, Total=650 [2018-04-11 23:06:27,706 INFO L87 Difference]: Start difference. First operand 368 states and 372 transitions. Second operand 26 states. [2018-04-11 23:06:27,911 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:27,911 INFO L93 Difference]: Finished difference Result 380 states and 382 transitions. [2018-04-11 23:06:27,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 23:06:27,912 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 352 [2018-04-11 23:06:27,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:27,913 INFO L225 Difference]: With dead ends: 380 [2018-04-11 23:06:27,913 INFO L226 Difference]: Without dead ends: 374 [2018-04-11 23:06:27,913 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 375 GetRequests, 345 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 289 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=244, Invalid=748, Unknown=0, NotChecked=0, Total=992 [2018-04-11 23:06:27,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 374 states. [2018-04-11 23:06:27,917 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 374 to 368. [2018-04-11 23:06:27,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 368 states. [2018-04-11 23:06:27,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 368 states to 368 states and 370 transitions. [2018-04-11 23:06:27,919 INFO L78 Accepts]: Start accepts. Automaton has 368 states and 370 transitions. Word has length 352 [2018-04-11 23:06:27,919 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:27,919 INFO L459 AbstractCegarLoop]: Abstraction has 368 states and 370 transitions. [2018-04-11 23:06:27,919 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-11 23:06:27,919 INFO L276 IsEmpty]: Start isEmpty. Operand 368 states and 370 transitions. [2018-04-11 23:06:27,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 359 [2018-04-11 23:06:27,921 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:27,921 INFO L355 BasicCegarLoop]: trace histogram [51, 44, 43, 43, 43, 43, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:27,921 INFO L408 AbstractCegarLoop]: === Iteration 27 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:27,921 INFO L82 PathProgramCache]: Analyzing trace with hash 608157801, now seen corresponding path program 18 times [2018-04-11 23:06:27,921 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:27,922 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:27,922 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:27,922 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:27,922 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:27,950 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:27,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:28,396 INFO L134 CoverageAnalysis]: Checked inductivity of 6450 backedges. 1911 proven. 192 refuted. 0 times theorem prover too weak. 4347 trivial. 0 not checked. [2018-04-11 23:06:28,397 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:28,397 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:28,402 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:06:28,498 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-04-11 23:06:28,498 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:28,503 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:28,685 INFO L134 CoverageAnalysis]: Checked inductivity of 6450 backedges. 1955 proven. 162 refuted. 0 times theorem prover too weak. 4333 trivial. 0 not checked. [2018-04-11 23:06:28,702 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:28,702 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 14] total 23 [2018-04-11 23:06:28,702 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-11 23:06:28,702 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-11 23:06:28,702 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=84, Invalid=468, Unknown=0, NotChecked=0, Total=552 [2018-04-11 23:06:28,703 INFO L87 Difference]: Start difference. First operand 368 states and 370 transitions. Second operand 24 states. [2018-04-11 23:06:29,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:29,338 INFO L93 Difference]: Finished difference Result 458 states and 463 transitions. [2018-04-11 23:06:29,339 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-11 23:06:29,339 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 358 [2018-04-11 23:06:29,339 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:29,340 INFO L225 Difference]: With dead ends: 458 [2018-04-11 23:06:29,341 INFO L226 Difference]: Without dead ends: 458 [2018-04-11 23:06:29,341 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 380 GetRequests, 345 SyntacticMatches, 1 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=192, Invalid=1068, Unknown=0, NotChecked=0, Total=1260 [2018-04-11 23:06:29,341 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 458 states. [2018-04-11 23:06:29,346 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 458 to 434. [2018-04-11 23:06:29,346 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 434 states. [2018-04-11 23:06:29,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 434 states to 434 states and 438 transitions. [2018-04-11 23:06:29,348 INFO L78 Accepts]: Start accepts. Automaton has 434 states and 438 transitions. Word has length 358 [2018-04-11 23:06:29,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:29,348 INFO L459 AbstractCegarLoop]: Abstraction has 434 states and 438 transitions. [2018-04-11 23:06:29,348 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-11 23:06:29,348 INFO L276 IsEmpty]: Start isEmpty. Operand 434 states and 438 transitions. [2018-04-11 23:06:29,350 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 425 [2018-04-11 23:06:29,351 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:29,351 INFO L355 BasicCegarLoop]: trace histogram [61, 53, 52, 52, 52, 52, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:29,351 INFO L408 AbstractCegarLoop]: === Iteration 28 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:29,351 INFO L82 PathProgramCache]: Analyzing trace with hash -1036409983, now seen corresponding path program 19 times [2018-04-11 23:06:29,351 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:29,351 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:29,352 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:29,352 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:29,352 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:29,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:29,385 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:29,852 INFO L134 CoverageAnalysis]: Checked inductivity of 9336 backedges. 4716 proven. 184 refuted. 0 times theorem prover too weak. 4436 trivial. 0 not checked. [2018-04-11 23:06:29,853 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:29,853 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:29,858 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:29,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:29,930 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:30,196 INFO L134 CoverageAnalysis]: Checked inductivity of 9336 backedges. 4716 proven. 184 refuted. 0 times theorem prover too weak. 4436 trivial. 0 not checked. [2018-04-11 23:06:30,224 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:30,273 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 29 [2018-04-11 23:06:30,274 INFO L442 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-04-11 23:06:30,274 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-04-11 23:06:30,274 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=208, Invalid=604, Unknown=0, NotChecked=0, Total=812 [2018-04-11 23:06:30,274 INFO L87 Difference]: Start difference. First operand 434 states and 438 transitions. Second operand 29 states. [2018-04-11 23:06:30,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:30,569 INFO L93 Difference]: Finished difference Result 456 states and 459 transitions. [2018-04-11 23:06:30,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-11 23:06:30,569 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 424 [2018-04-11 23:06:30,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:30,570 INFO L225 Difference]: With dead ends: 456 [2018-04-11 23:06:30,571 INFO L226 Difference]: Without dead ends: 450 [2018-04-11 23:06:30,571 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 450 GetRequests, 416 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 379 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=306, Invalid=954, Unknown=0, NotChecked=0, Total=1260 [2018-04-11 23:06:30,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 450 states. [2018-04-11 23:06:30,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 450 to 440. [2018-04-11 23:06:30,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 440 states. [2018-04-11 23:06:30,574 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 440 states to 440 states and 443 transitions. [2018-04-11 23:06:30,574 INFO L78 Accepts]: Start accepts. Automaton has 440 states and 443 transitions. Word has length 424 [2018-04-11 23:06:30,575 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:30,575 INFO L459 AbstractCegarLoop]: Abstraction has 440 states and 443 transitions. [2018-04-11 23:06:30,575 INFO L460 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-04-11 23:06:30,575 INFO L276 IsEmpty]: Start isEmpty. Operand 440 states and 443 transitions. [2018-04-11 23:06:30,576 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 431 [2018-04-11 23:06:30,576 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:30,576 INFO L355 BasicCegarLoop]: trace histogram [62, 54, 53, 53, 53, 53, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:30,576 INFO L408 AbstractCegarLoop]: === Iteration 29 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:30,576 INFO L82 PathProgramCache]: Analyzing trace with hash 64648569, now seen corresponding path program 20 times [2018-04-11 23:06:30,576 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:30,577 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:30,577 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:30,577 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:30,577 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:30,596 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:30,597 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:30,884 INFO L134 CoverageAnalysis]: Checked inductivity of 9667 backedges. 2668 proven. 243 refuted. 0 times theorem prover too weak. 6756 trivial. 0 not checked. [2018-04-11 23:06:30,884 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:30,884 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:30,894 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:30,999 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:30,999 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:31,007 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:31,148 INFO L134 CoverageAnalysis]: Checked inductivity of 9667 backedges. 2668 proven. 243 refuted. 0 times theorem prover too weak. 6756 trivial. 0 not checked. [2018-04-11 23:06:31,167 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:31,167 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11] total 21 [2018-04-11 23:06:31,167 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 23:06:31,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 23:06:31,167 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=330, Unknown=0, NotChecked=0, Total=462 [2018-04-11 23:06:31,167 INFO L87 Difference]: Start difference. First operand 440 states and 443 transitions. Second operand 22 states. [2018-04-11 23:06:31,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:31,351 INFO L93 Difference]: Finished difference Result 468 states and 473 transitions. [2018-04-11 23:06:31,351 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-11 23:06:31,351 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 430 [2018-04-11 23:06:31,352 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:31,353 INFO L225 Difference]: With dead ends: 468 [2018-04-11 23:06:31,353 INFO L226 Difference]: Without dead ends: 468 [2018-04-11 23:06:31,353 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 441 GetRequests, 421 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 163 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=132, Invalid=330, Unknown=0, NotChecked=0, Total=462 [2018-04-11 23:06:31,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states. [2018-04-11 23:06:31,359 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 446. [2018-04-11 23:06:31,359 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 446 states. [2018-04-11 23:06:31,360 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 446 states to 446 states and 450 transitions. [2018-04-11 23:06:31,360 INFO L78 Accepts]: Start accepts. Automaton has 446 states and 450 transitions. Word has length 430 [2018-04-11 23:06:31,360 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:31,360 INFO L459 AbstractCegarLoop]: Abstraction has 446 states and 450 transitions. [2018-04-11 23:06:31,361 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 23:06:31,361 INFO L276 IsEmpty]: Start isEmpty. Operand 446 states and 450 transitions. [2018-04-11 23:06:31,363 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 437 [2018-04-11 23:06:31,363 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:31,363 INFO L355 BasicCegarLoop]: trace histogram [63, 55, 54, 54, 54, 54, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:31,363 INFO L408 AbstractCegarLoop]: === Iteration 30 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:31,363 INFO L82 PathProgramCache]: Analyzing trace with hash 523966833, now seen corresponding path program 21 times [2018-04-11 23:06:31,364 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:31,364 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:31,364 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:31,364 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:31,364 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:31,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:31,400 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:31,960 INFO L134 CoverageAnalysis]: Checked inductivity of 10004 backedges. 3227 proven. 229 refuted. 0 times theorem prover too weak. 6548 trivial. 0 not checked. [2018-04-11 23:06:31,960 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:31,960 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:31,965 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:06:32,061 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 11 check-sat command(s) [2018-04-11 23:06:32,061 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:32,065 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:32,265 INFO L134 CoverageAnalysis]: Checked inductivity of 10004 backedges. 2948 proven. 300 refuted. 0 times theorem prover too weak. 6756 trivial. 0 not checked. [2018-04-11 23:06:32,294 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:32,294 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 13] total 36 [2018-04-11 23:06:32,295 INFO L442 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-04-11 23:06:32,295 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-04-11 23:06:32,295 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=206, Invalid=1054, Unknown=0, NotChecked=0, Total=1260 [2018-04-11 23:06:32,295 INFO L87 Difference]: Start difference. First operand 446 states and 450 transitions. Second operand 36 states. [2018-04-11 23:06:33,161 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:33,162 INFO L93 Difference]: Finished difference Result 550 states and 556 transitions. [2018-04-11 23:06:33,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-04-11 23:06:33,163 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 436 [2018-04-11 23:06:33,163 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:33,164 INFO L225 Difference]: With dead ends: 550 [2018-04-11 23:06:33,164 INFO L226 Difference]: Without dead ends: 550 [2018-04-11 23:06:33,166 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 490 GetRequests, 425 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 978 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=898, Invalid=3524, Unknown=0, NotChecked=0, Total=4422 [2018-04-11 23:06:33,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 550 states. [2018-04-11 23:06:33,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 550 to 530. [2018-04-11 23:06:33,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2018-04-11 23:06:33,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 536 transitions. [2018-04-11 23:06:33,173 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 536 transitions. Word has length 436 [2018-04-11 23:06:33,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:33,174 INFO L459 AbstractCegarLoop]: Abstraction has 530 states and 536 transitions. [2018-04-11 23:06:33,174 INFO L460 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-04-11 23:06:33,174 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 536 transitions. [2018-04-11 23:06:33,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 509 [2018-04-11 23:06:33,177 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:33,177 INFO L355 BasicCegarLoop]: trace histogram [74, 65, 64, 64, 64, 64, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:33,177 INFO L408 AbstractCegarLoop]: === Iteration 31 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:33,177 INFO L82 PathProgramCache]: Analyzing trace with hash 1159814785, now seen corresponding path program 22 times [2018-04-11 23:06:33,177 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:33,177 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:33,178 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:33,178 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:33,178 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:33,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:33,221 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:33,911 INFO L134 CoverageAnalysis]: Checked inductivity of 13935 backedges. 6782 proven. 234 refuted. 0 times theorem prover too weak. 6919 trivial. 0 not checked. [2018-04-11 23:06:33,911 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:33,911 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:33,926 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:06:34,072 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:06:34,072 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:34,084 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:34,454 INFO L134 CoverageAnalysis]: Checked inductivity of 13935 backedges. 6782 proven. 234 refuted. 0 times theorem prover too weak. 6919 trivial. 0 not checked. [2018-04-11 23:06:34,486 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:34,487 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 32 [2018-04-11 23:06:34,487 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 23:06:34,488 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 23:06:34,488 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=251, Invalid=741, Unknown=0, NotChecked=0, Total=992 [2018-04-11 23:06:34,488 INFO L87 Difference]: Start difference. First operand 530 states and 536 transitions. Second operand 32 states. [2018-04-11 23:06:34,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:34,931 INFO L93 Difference]: Finished difference Result 542 states and 546 transitions. [2018-04-11 23:06:34,931 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-04-11 23:06:34,932 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 508 [2018-04-11 23:06:34,932 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:34,933 INFO L225 Difference]: With dead ends: 542 [2018-04-11 23:06:34,933 INFO L226 Difference]: Without dead ends: 536 [2018-04-11 23:06:34,933 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 537 GetRequests, 499 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 481 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=375, Invalid=1185, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 23:06:34,934 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 536 states. [2018-04-11 23:06:34,937 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 536 to 530. [2018-04-11 23:06:34,937 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 530 states. [2018-04-11 23:06:34,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 530 states to 530 states and 534 transitions. [2018-04-11 23:06:34,938 INFO L78 Accepts]: Start accepts. Automaton has 530 states and 534 transitions. Word has length 508 [2018-04-11 23:06:34,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:34,939 INFO L459 AbstractCegarLoop]: Abstraction has 530 states and 534 transitions. [2018-04-11 23:06:34,939 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 23:06:34,939 INFO L276 IsEmpty]: Start isEmpty. Operand 530 states and 534 transitions. [2018-04-11 23:06:34,940 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 515 [2018-04-11 23:06:34,940 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:34,941 INFO L355 BasicCegarLoop]: trace histogram [75, 66, 65, 65, 65, 65, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:34,941 INFO L408 AbstractCegarLoop]: === Iteration 32 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:34,941 INFO L82 PathProgramCache]: Analyzing trace with hash -265555847, now seen corresponding path program 23 times [2018-04-11 23:06:34,941 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:34,941 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:34,942 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:34,942 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:34,942 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:34,966 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:34,968 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:35,509 INFO L134 CoverageAnalysis]: Checked inductivity of 14340 backedges. 4282 proven. 284 refuted. 0 times theorem prover too weak. 9774 trivial. 0 not checked. [2018-04-11 23:06:35,509 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:35,510 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:35,514 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:06:35,708 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-04-11 23:06:35,708 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:35,714 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:36,168 INFO L134 CoverageAnalysis]: Checked inductivity of 14340 backedges. 4217 proven. 1477 refuted. 0 times theorem prover too weak. 8646 trivial. 0 not checked. [2018-04-11 23:06:36,187 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:36,187 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 30] total 43 [2018-04-11 23:06:36,188 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-04-11 23:06:36,188 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-04-11 23:06:36,188 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=357, Invalid=1449, Unknown=0, NotChecked=0, Total=1806 [2018-04-11 23:06:36,188 INFO L87 Difference]: Start difference. First operand 530 states and 534 transitions. Second operand 43 states. [2018-04-11 23:06:36,991 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:36,991 INFO L93 Difference]: Finished difference Result 619 states and 624 transitions. [2018-04-11 23:06:36,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-04-11 23:06:36,992 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 514 [2018-04-11 23:06:36,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:36,994 INFO L225 Difference]: With dead ends: 619 [2018-04-11 23:06:36,994 INFO L226 Difference]: Without dead ends: 619 [2018-04-11 23:06:36,995 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 563 GetRequests, 498 SyntacticMatches, 0 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 819 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=933, Invalid=3489, Unknown=0, NotChecked=0, Total=4422 [2018-04-11 23:06:36,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 619 states. [2018-04-11 23:06:37,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 619 to 608. [2018-04-11 23:06:37,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 608 states. [2018-04-11 23:06:37,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 608 states to 608 states and 613 transitions. [2018-04-11 23:06:37,003 INFO L78 Accepts]: Start accepts. Automaton has 608 states and 613 transitions. Word has length 514 [2018-04-11 23:06:37,003 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:37,004 INFO L459 AbstractCegarLoop]: Abstraction has 608 states and 613 transitions. [2018-04-11 23:06:37,004 INFO L460 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-04-11 23:06:37,004 INFO L276 IsEmpty]: Start isEmpty. Operand 608 states and 613 transitions. [2018-04-11 23:06:37,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 587 [2018-04-11 23:06:37,010 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:37,010 INFO L355 BasicCegarLoop]: trace histogram [86, 76, 75, 75, 75, 75, 11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:37,010 INFO L408 AbstractCegarLoop]: === Iteration 33 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:37,010 INFO L82 PathProgramCache]: Analyzing trace with hash -579703415, now seen corresponding path program 24 times [2018-04-11 23:06:37,010 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:37,011 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:37,011 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:37,011 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:37,011 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:37,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:37,053 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:37,710 INFO L134 CoverageAnalysis]: Checked inductivity of 18985 backedges. 8549 proven. 290 refuted. 0 times theorem prover too weak. 10146 trivial. 0 not checked. [2018-04-11 23:06:37,710 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:37,710 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:37,715 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:06:37,941 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-11 23:06:37,941 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:37,947 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:38,204 INFO L134 CoverageAnalysis]: Checked inductivity of 18985 backedges. 4718 proven. 321 refuted. 0 times theorem prover too weak. 13946 trivial. 0 not checked. [2018-04-11 23:06:38,222 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:38,223 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 17] total 40 [2018-04-11 23:06:38,223 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-04-11 23:06:38,223 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-04-11 23:06:38,224 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=236, Invalid=1324, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 23:06:38,224 INFO L87 Difference]: Start difference. First operand 608 states and 613 transitions. Second operand 40 states. [2018-04-11 23:06:39,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:39,326 INFO L93 Difference]: Finished difference Result 710 states and 714 transitions. [2018-04-11 23:06:39,326 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-04-11 23:06:39,326 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 586 [2018-04-11 23:06:39,327 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:39,328 INFO L225 Difference]: With dead ends: 710 [2018-04-11 23:06:39,328 INFO L226 Difference]: Without dead ends: 701 [2018-04-11 23:06:39,329 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 674 GetRequests, 582 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2481 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1403, Invalid=7339, Unknown=0, NotChecked=0, Total=8742 [2018-04-11 23:06:39,329 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 701 states. [2018-04-11 23:06:39,335 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 701 to 686. [2018-04-11 23:06:39,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 686 states. [2018-04-11 23:06:39,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 686 states to 686 states and 690 transitions. [2018-04-11 23:06:39,337 INFO L78 Accepts]: Start accepts. Automaton has 686 states and 690 transitions. Word has length 586 [2018-04-11 23:06:39,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:39,337 INFO L459 AbstractCegarLoop]: Abstraction has 686 states and 690 transitions. [2018-04-11 23:06:39,337 INFO L460 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-04-11 23:06:39,337 INFO L276 IsEmpty]: Start isEmpty. Operand 686 states and 690 transitions. [2018-04-11 23:06:39,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 671 [2018-04-11 23:06:39,342 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:39,342 INFO L355 BasicCegarLoop]: trace histogram [99, 88, 87, 87, 87, 87, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:39,342 INFO L408 AbstractCegarLoop]: === Iteration 34 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:39,343 INFO L82 PathProgramCache]: Analyzing trace with hash 1141281929, now seen corresponding path program 25 times [2018-04-11 23:06:39,343 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:39,343 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:39,344 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:39,344 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:39,344 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:39,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:39,387 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:40,172 INFO L134 CoverageAnalysis]: Checked inductivity of 25358 backedges. 10583 proven. 352 refuted. 0 times theorem prover too weak. 14423 trivial. 0 not checked. [2018-04-11 23:06:40,172 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:40,172 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:40,177 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:40,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:40,275 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:40,608 INFO L134 CoverageAnalysis]: Checked inductivity of 25358 backedges. 10583 proven. 352 refuted. 0 times theorem prover too weak. 14423 trivial. 0 not checked. [2018-04-11 23:06:40,625 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:40,626 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26] total 38 [2018-04-11 23:06:40,626 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-04-11 23:06:40,626 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-04-11 23:06:40,626 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=349, Invalid=1057, Unknown=0, NotChecked=0, Total=1406 [2018-04-11 23:06:40,626 INFO L87 Difference]: Start difference. First operand 686 states and 690 transitions. Second operand 38 states. [2018-04-11 23:06:41,112 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:41,112 INFO L93 Difference]: Finished difference Result 718 states and 722 transitions. [2018-04-11 23:06:41,112 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-04-11 23:06:41,112 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 670 [2018-04-11 23:06:41,112 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:41,114 INFO L225 Difference]: With dead ends: 718 [2018-04-11 23:06:41,114 INFO L226 Difference]: Without dead ends: 712 [2018-04-11 23:06:41,114 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 705 GetRequests, 659 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 721 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=534, Invalid=1722, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 23:06:41,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 712 states. [2018-04-11 23:06:41,120 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 712 to 697. [2018-04-11 23:06:41,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 697 states. [2018-04-11 23:06:41,121 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 697 states to 697 states and 701 transitions. [2018-04-11 23:06:41,121 INFO L78 Accepts]: Start accepts. Automaton has 697 states and 701 transitions. Word has length 670 [2018-04-11 23:06:41,121 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:41,121 INFO L459 AbstractCegarLoop]: Abstraction has 697 states and 701 transitions. [2018-04-11 23:06:41,121 INFO L460 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-04-11 23:06:41,122 INFO L276 IsEmpty]: Start isEmpty. Operand 697 states and 701 transitions. [2018-04-11 23:06:41,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 677 [2018-04-11 23:06:41,124 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:41,124 INFO L355 BasicCegarLoop]: trace histogram [100, 89, 88, 88, 88, 88, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:41,125 INFO L408 AbstractCegarLoop]: === Iteration 35 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:41,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1493008255, now seen corresponding path program 26 times [2018-04-11 23:06:41,125 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:41,125 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:41,125 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:41,126 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:41,126 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:41,158 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:41,159 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:41,658 INFO L134 CoverageAnalysis]: Checked inductivity of 25905 backedges. 5577 proven. 363 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-11 23:06:41,658 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:41,658 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:41,663 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:41,760 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:41,761 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:41,766 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:41,920 INFO L134 CoverageAnalysis]: Checked inductivity of 25905 backedges. 5577 proven. 363 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-11 23:06:41,938 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:41,938 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13] total 25 [2018-04-11 23:06:41,939 INFO L442 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-04-11 23:06:41,939 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-04-11 23:06:41,939 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=468, Unknown=0, NotChecked=0, Total=650 [2018-04-11 23:06:41,939 INFO L87 Difference]: Start difference. First operand 697 states and 701 transitions. Second operand 26 states. [2018-04-11 23:06:42,179 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:42,180 INFO L93 Difference]: Finished difference Result 711 states and 715 transitions. [2018-04-11 23:06:42,180 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-11 23:06:42,180 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 676 [2018-04-11 23:06:42,180 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:42,181 INFO L225 Difference]: With dead ends: 711 [2018-04-11 23:06:42,181 INFO L226 Difference]: Without dead ends: 711 [2018-04-11 23:06:42,181 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 689 GetRequests, 665 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 243 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=182, Invalid=468, Unknown=0, NotChecked=0, Total=650 [2018-04-11 23:06:42,182 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711 states. [2018-04-11 23:06:42,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711 to 698. [2018-04-11 23:06:42,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 698 states. [2018-04-11 23:06:42,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 698 states to 698 states and 702 transitions. [2018-04-11 23:06:42,187 INFO L78 Accepts]: Start accepts. Automaton has 698 states and 702 transitions. Word has length 676 [2018-04-11 23:06:42,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:42,188 INFO L459 AbstractCegarLoop]: Abstraction has 698 states and 702 transitions. [2018-04-11 23:06:42,188 INFO L460 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-04-11 23:06:42,188 INFO L276 IsEmpty]: Start isEmpty. Operand 698 states and 702 transitions. [2018-04-11 23:06:42,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 683 [2018-04-11 23:06:42,194 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:42,194 INFO L355 BasicCegarLoop]: trace histogram [101, 90, 89, 89, 89, 89, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:42,194 INFO L408 AbstractCegarLoop]: === Iteration 36 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:42,195 INFO L82 PathProgramCache]: Analyzing trace with hash 1344323193, now seen corresponding path program 27 times [2018-04-11 23:06:42,195 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:42,195 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:42,195 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:42,195 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:42,196 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:42,240 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:42,241 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:42,765 INFO L134 CoverageAnalysis]: Checked inductivity of 26458 backedges. 6061 proven. 432 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-11 23:06:42,765 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:42,765 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:42,771 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:06:42,940 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-04-11 23:06:42,940 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:42,945 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:43,108 INFO L134 CoverageAnalysis]: Checked inductivity of 26458 backedges. 6061 proven. 432 refuted. 0 times theorem prover too weak. 19965 trivial. 0 not checked. [2018-04-11 23:06:43,125 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:43,126 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15] total 21 [2018-04-11 23:06:43,126 INFO L442 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-04-11 23:06:43,126 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-04-11 23:06:43,126 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=140, Invalid=322, Unknown=0, NotChecked=0, Total=462 [2018-04-11 23:06:43,126 INFO L87 Difference]: Start difference. First operand 698 states and 702 transitions. Second operand 22 states. [2018-04-11 23:06:43,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:43,314 INFO L93 Difference]: Finished difference Result 729 states and 735 transitions. [2018-04-11 23:06:43,314 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-04-11 23:06:43,315 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 682 [2018-04-11 23:06:43,315 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:43,316 INFO L225 Difference]: With dead ends: 729 [2018-04-11 23:06:43,316 INFO L226 Difference]: Without dead ends: 729 [2018-04-11 23:06:43,316 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 707 GetRequests, 676 SyntacticMatches, 0 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 170 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=321, Invalid=735, Unknown=0, NotChecked=0, Total=1056 [2018-04-11 23:06:43,316 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 729 states. [2018-04-11 23:06:43,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 729 to 704. [2018-04-11 23:06:43,320 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 704 states. [2018-04-11 23:06:43,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 704 states to 704 states and 709 transitions. [2018-04-11 23:06:43,321 INFO L78 Accepts]: Start accepts. Automaton has 704 states and 709 transitions. Word has length 682 [2018-04-11 23:06:43,322 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:43,322 INFO L459 AbstractCegarLoop]: Abstraction has 704 states and 709 transitions. [2018-04-11 23:06:43,322 INFO L460 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-04-11 23:06:43,322 INFO L276 IsEmpty]: Start isEmpty. Operand 704 states and 709 transitions. [2018-04-11 23:06:43,326 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 689 [2018-04-11 23:06:43,327 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:43,327 INFO L355 BasicCegarLoop]: trace histogram [102, 91, 90, 90, 90, 90, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:43,327 INFO L408 AbstractCegarLoop]: === Iteration 37 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:43,327 INFO L82 PathProgramCache]: Analyzing trace with hash 1172742769, now seen corresponding path program 28 times [2018-04-11 23:06:43,327 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:43,327 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:43,328 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:43,328 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:43,328 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:43,365 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:43,367 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:44,222 INFO L134 CoverageAnalysis]: Checked inductivity of 27017 backedges. 7025 proven. 412 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-04-11 23:06:44,222 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:44,222 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:44,227 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:06:44,304 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:06:44,304 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:44,309 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:44,698 INFO L134 CoverageAnalysis]: Checked inductivity of 27017 backedges. 7063 proven. 374 refuted. 0 times theorem prover too weak. 19580 trivial. 0 not checked. [2018-04-11 23:06:44,717 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:44,717 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29] total 45 [2018-04-11 23:06:44,717 INFO L442 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-04-11 23:06:44,718 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-04-11 23:06:44,718 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=466, Invalid=1514, Unknown=0, NotChecked=0, Total=1980 [2018-04-11 23:06:44,718 INFO L87 Difference]: Start difference. First operand 704 states and 709 transitions. Second operand 45 states. [2018-04-11 23:06:45,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:45,462 INFO L93 Difference]: Finished difference Result 814 states and 820 transitions. [2018-04-11 23:06:45,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-04-11 23:06:45,462 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 688 [2018-04-11 23:06:45,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:45,463 INFO L225 Difference]: With dead ends: 814 [2018-04-11 23:06:45,463 INFO L226 Difference]: Without dead ends: 814 [2018-04-11 23:06:45,464 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 742 GetRequests, 674 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 773 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1263, Invalid=3567, Unknown=0, NotChecked=0, Total=4830 [2018-04-11 23:06:45,465 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 814 states. [2018-04-11 23:06:45,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 814 to 800. [2018-04-11 23:06:45,468 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 800 states. [2018-04-11 23:06:45,469 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 800 states to 800 states and 806 transitions. [2018-04-11 23:06:45,469 INFO L78 Accepts]: Start accepts. Automaton has 800 states and 806 transitions. Word has length 688 [2018-04-11 23:06:45,469 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:45,469 INFO L459 AbstractCegarLoop]: Abstraction has 800 states and 806 transitions. [2018-04-11 23:06:45,469 INFO L460 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-04-11 23:06:45,469 INFO L276 IsEmpty]: Start isEmpty. Operand 800 states and 806 transitions. [2018-04-11 23:06:45,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 773 [2018-04-11 23:06:45,473 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:45,473 INFO L355 BasicCegarLoop]: trace histogram [115, 103, 102, 102, 102, 102, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:45,473 INFO L408 AbstractCegarLoop]: === Iteration 38 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:45,473 INFO L82 PathProgramCache]: Analyzing trace with hash 409831793, now seen corresponding path program 29 times [2018-04-11 23:06:45,473 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:45,473 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:45,474 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:45,474 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:45,474 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:45,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:45,505 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:46,465 INFO L134 CoverageAnalysis]: Checked inductivity of 34536 backedges. 14018 proven. 420 refuted. 0 times theorem prover too weak. 20098 trivial. 0 not checked. [2018-04-11 23:06:46,465 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:46,465 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:46,470 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:06:46,783 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 27 check-sat command(s) [2018-04-11 23:06:46,783 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:46,791 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:47,208 INFO L134 CoverageAnalysis]: Checked inductivity of 34536 backedges. 13824 proven. 2224 refuted. 0 times theorem prover too weak. 18488 trivial. 0 not checked. [2018-04-11 23:06:47,228 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:47,228 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 32] total 46 [2018-04-11 23:06:47,228 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-04-11 23:06:47,228 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-04-11 23:06:47,229 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=420, Invalid=1650, Unknown=0, NotChecked=0, Total=2070 [2018-04-11 23:06:47,229 INFO L87 Difference]: Start difference. First operand 800 states and 806 transitions. Second operand 46 states. [2018-04-11 23:06:48,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:48,163 INFO L93 Difference]: Finished difference Result 818 states and 822 transitions. [2018-04-11 23:06:48,163 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-04-11 23:06:48,163 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 772 [2018-04-11 23:06:48,164 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:48,165 INFO L225 Difference]: With dead ends: 818 [2018-04-11 23:06:48,165 INFO L226 Difference]: Without dead ends: 812 [2018-04-11 23:06:48,166 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 828 GetRequests, 756 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1661 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1183, Invalid=4219, Unknown=0, NotChecked=0, Total=5402 [2018-04-11 23:06:48,166 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 812 states. [2018-04-11 23:06:48,171 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 812 to 800. [2018-04-11 23:06:48,171 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 800 states. [2018-04-11 23:06:48,172 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 800 states to 800 states and 804 transitions. [2018-04-11 23:06:48,172 INFO L78 Accepts]: Start accepts. Automaton has 800 states and 804 transitions. Word has length 772 [2018-04-11 23:06:48,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:48,172 INFO L459 AbstractCegarLoop]: Abstraction has 800 states and 804 transitions. [2018-04-11 23:06:48,172 INFO L460 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-04-11 23:06:48,172 INFO L276 IsEmpty]: Start isEmpty. Operand 800 states and 804 transitions. [2018-04-11 23:06:48,175 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 779 [2018-04-11 23:06:48,176 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:48,176 INFO L355 BasicCegarLoop]: trace histogram [116, 104, 103, 103, 103, 103, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:48,176 INFO L408 AbstractCegarLoop]: === Iteration 39 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:48,176 INFO L82 PathProgramCache]: Analyzing trace with hash -1167448215, now seen corresponding path program 30 times [2018-04-11 23:06:48,176 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:48,176 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:48,177 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:48,177 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:48,177 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:48,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:48,212 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:48,823 INFO L134 CoverageAnalysis]: Checked inductivity of 35175 backedges. 7626 proven. 507 refuted. 0 times theorem prover too weak. 27042 trivial. 0 not checked. [2018-04-11 23:06:48,824 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:48,824 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:48,829 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:06:49,094 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 22 check-sat command(s) [2018-04-11 23:06:49,094 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:49,101 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:49,383 INFO L134 CoverageAnalysis]: Checked inductivity of 35175 backedges. 7700 proven. 457 refuted. 0 times theorem prover too weak. 27018 trivial. 0 not checked. [2018-04-11 23:06:49,402 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:49,402 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 19] total 33 [2018-04-11 23:06:49,403 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-11 23:06:49,403 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-11 23:06:49,403 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=226, Invalid=896, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 23:06:49,403 INFO L87 Difference]: Start difference. First operand 800 states and 804 transitions. Second operand 34 states. [2018-04-11 23:06:50,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:50,043 INFO L93 Difference]: Finished difference Result 922 states and 929 transitions. [2018-04-11 23:06:50,043 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-04-11 23:06:50,043 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 778 [2018-04-11 23:06:50,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:50,045 INFO L225 Difference]: With dead ends: 922 [2018-04-11 23:06:50,045 INFO L226 Difference]: Without dead ends: 922 [2018-04-11 23:06:50,045 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 821 GetRequests, 761 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 716 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=812, Invalid=2970, Unknown=0, NotChecked=0, Total=3782 [2018-04-11 23:06:50,046 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 922 states. [2018-04-11 23:06:50,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 922 to 896. [2018-04-11 23:06:50,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 896 states. [2018-04-11 23:06:50,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 896 states to 896 states and 902 transitions. [2018-04-11 23:06:50,051 INFO L78 Accepts]: Start accepts. Automaton has 896 states and 902 transitions. Word has length 778 [2018-04-11 23:06:50,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:50,051 INFO L459 AbstractCegarLoop]: Abstraction has 896 states and 902 transitions. [2018-04-11 23:06:50,051 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-11 23:06:50,051 INFO L276 IsEmpty]: Start isEmpty. Operand 896 states and 902 transitions. [2018-04-11 23:06:50,055 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 875 [2018-04-11 23:06:50,055 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:50,056 INFO L355 BasicCegarLoop]: trace histogram [131, 118, 117, 117, 117, 117, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:50,056 INFO L408 AbstractCegarLoop]: === Iteration 40 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:50,056 INFO L82 PathProgramCache]: Analyzing trace with hash -165184423, now seen corresponding path program 31 times [2018-04-11 23:06:50,056 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:50,056 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:50,056 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:50,056 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:50,056 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:50,087 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:50,089 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:51,300 INFO L134 CoverageAnalysis]: Checked inductivity of 45136 backedges. 17456 proven. 494 refuted. 0 times theorem prover too weak. 27186 trivial. 0 not checked. [2018-04-11 23:06:51,300 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:51,300 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:51,305 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:51,424 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:51,431 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:51,809 INFO L134 CoverageAnalysis]: Checked inductivity of 45136 backedges. 17456 proven. 494 refuted. 0 times theorem prover too weak. 27186 trivial. 0 not checked. [2018-04-11 23:06:51,827 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:51,828 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 44 [2018-04-11 23:06:51,828 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-11 23:06:51,828 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-11 23:06:51,828 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=463, Invalid=1429, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 23:06:51,828 INFO L87 Difference]: Start difference. First operand 896 states and 902 transitions. Second operand 44 states. [2018-04-11 23:06:52,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:52,293 INFO L93 Difference]: Finished difference Result 924 states and 929 transitions. [2018-04-11 23:06:52,293 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-04-11 23:06:52,293 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 874 [2018-04-11 23:06:52,294 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:52,295 INFO L225 Difference]: With dead ends: 924 [2018-04-11 23:06:52,295 INFO L226 Difference]: Without dead ends: 918 [2018-04-11 23:06:52,296 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 915 GetRequests, 861 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1009 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=721, Invalid=2359, Unknown=0, NotChecked=0, Total=3080 [2018-04-11 23:06:52,296 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 918 states. [2018-04-11 23:06:52,302 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 918 to 902. [2018-04-11 23:06:52,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 902 states. [2018-04-11 23:06:52,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 902 states to 902 states and 907 transitions. [2018-04-11 23:06:52,304 INFO L78 Accepts]: Start accepts. Automaton has 902 states and 907 transitions. Word has length 874 [2018-04-11 23:06:52,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:52,305 INFO L459 AbstractCegarLoop]: Abstraction has 902 states and 907 transitions. [2018-04-11 23:06:52,305 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-11 23:06:52,305 INFO L276 IsEmpty]: Start isEmpty. Operand 902 states and 907 transitions. [2018-04-11 23:06:52,309 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 881 [2018-04-11 23:06:52,309 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:52,309 INFO L355 BasicCegarLoop]: trace histogram [132, 119, 118, 118, 118, 118, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:52,309 INFO L408 AbstractCegarLoop]: === Iteration 41 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:52,309 INFO L82 PathProgramCache]: Analyzing trace with hash -1508029359, now seen corresponding path program 32 times [2018-04-11 23:06:52,309 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:52,310 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:52,310 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:52,310 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:06:52,310 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:52,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:52,350 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:53,102 INFO L134 CoverageAnalysis]: Checked inductivity of 45867 backedges. 9438 proven. 588 refuted. 0 times theorem prover too weak. 35841 trivial. 0 not checked. [2018-04-11 23:06:53,102 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:53,102 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:53,108 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:06:53,234 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:06:53,234 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:53,240 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:53,501 INFO L134 CoverageAnalysis]: Checked inductivity of 45867 backedges. 9438 proven. 588 refuted. 0 times theorem prover too weak. 35841 trivial. 0 not checked. [2018-04-11 23:06:53,520 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:53,520 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16] total 31 [2018-04-11 23:06:53,520 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 23:06:53,521 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 23:06:53,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=257, Invalid=735, Unknown=0, NotChecked=0, Total=992 [2018-04-11 23:06:53,521 INFO L87 Difference]: Start difference. First operand 902 states and 907 transitions. Second operand 32 states. [2018-04-11 23:06:53,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:53,952 INFO L93 Difference]: Finished difference Result 936 states and 943 transitions. [2018-04-11 23:06:53,953 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-04-11 23:06:53,953 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 880 [2018-04-11 23:06:53,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:53,954 INFO L225 Difference]: With dead ends: 936 [2018-04-11 23:06:53,954 INFO L226 Difference]: Without dead ends: 936 [2018-04-11 23:06:53,955 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 896 GetRequests, 866 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 380 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=257, Invalid=735, Unknown=0, NotChecked=0, Total=992 [2018-04-11 23:06:53,955 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 936 states. [2018-04-11 23:06:53,959 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 936 to 908. [2018-04-11 23:06:53,959 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 908 states. [2018-04-11 23:06:53,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 908 states to 908 states and 914 transitions. [2018-04-11 23:06:53,960 INFO L78 Accepts]: Start accepts. Automaton has 908 states and 914 transitions. Word has length 880 [2018-04-11 23:06:53,960 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:53,960 INFO L459 AbstractCegarLoop]: Abstraction has 908 states and 914 transitions. [2018-04-11 23:06:53,960 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 23:06:53,960 INFO L276 IsEmpty]: Start isEmpty. Operand 908 states and 914 transitions. [2018-04-11 23:06:53,964 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 887 [2018-04-11 23:06:53,964 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:53,964 INFO L355 BasicCegarLoop]: trace histogram [133, 120, 119, 119, 119, 119, 14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:53,964 INFO L408 AbstractCegarLoop]: === Iteration 42 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:53,964 INFO L82 PathProgramCache]: Analyzing trace with hash -1614320055, now seen corresponding path program 33 times [2018-04-11 23:06:53,964 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:53,964 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:53,965 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:53,965 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:53,965 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:54,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:54,003 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:55,320 INFO L134 CoverageAnalysis]: Checked inductivity of 46604 backedges. 10732 proven. 564 refuted. 0 times theorem prover too weak. 35308 trivial. 0 not checked. [2018-04-11 23:06:55,320 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:55,320 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:55,327 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:06:55,537 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-04-11 23:06:55,537 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:55,544 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:56,040 INFO L134 CoverageAnalysis]: Checked inductivity of 46604 backedges. 13265 proven. 4191 refuted. 0 times theorem prover too weak. 29148 trivial. 0 not checked. [2018-04-11 23:06:56,059 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:56,059 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 24] total 50 [2018-04-11 23:06:56,060 INFO L442 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-04-11 23:06:56,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-04-11 23:06:56,060 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=381, Invalid=2069, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 23:06:56,060 INFO L87 Difference]: Start difference. First operand 908 states and 914 transitions. Second operand 50 states. [2018-04-11 23:06:57,312 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:06:57,312 INFO L93 Difference]: Finished difference Result 1027 states and 1034 transitions. [2018-04-11 23:06:57,312 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-04-11 23:06:57,312 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 886 [2018-04-11 23:06:57,312 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:06:57,314 INFO L225 Difference]: With dead ends: 1027 [2018-04-11 23:06:57,314 INFO L226 Difference]: Without dead ends: 1027 [2018-04-11 23:06:57,315 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 959 GetRequests, 871 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1700 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1620, Invalid=6390, Unknown=0, NotChecked=0, Total=8010 [2018-04-11 23:06:57,315 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1027 states. [2018-04-11 23:06:57,319 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1027 to 1016. [2018-04-11 23:06:57,319 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1016 states. [2018-04-11 23:06:57,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1016 states to 1016 states and 1023 transitions. [2018-04-11 23:06:57,321 INFO L78 Accepts]: Start accepts. Automaton has 1016 states and 1023 transitions. Word has length 886 [2018-04-11 23:06:57,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:06:57,321 INFO L459 AbstractCegarLoop]: Abstraction has 1016 states and 1023 transitions. [2018-04-11 23:06:57,321 INFO L460 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-04-11 23:06:57,321 INFO L276 IsEmpty]: Start isEmpty. Operand 1016 states and 1023 transitions. [2018-04-11 23:06:57,325 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 983 [2018-04-11 23:06:57,325 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:06:57,326 INFO L355 BasicCegarLoop]: trace histogram [148, 134, 133, 133, 133, 133, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:06:57,326 INFO L408 AbstractCegarLoop]: === Iteration 43 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:06:57,326 INFO L82 PathProgramCache]: Analyzing trace with hash 76312377, now seen corresponding path program 34 times [2018-04-11 23:06:57,326 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:06:57,326 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:06:57,327 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:57,327 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:06:57,327 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:06:57,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:06:57,369 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:06:58,949 INFO L134 CoverageAnalysis]: Checked inductivity of 57981 backedges. 21411 proven. 574 refuted. 0 times theorem prover too weak. 35996 trivial. 0 not checked. [2018-04-11 23:06:58,949 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:06:58,949 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:06:58,954 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:06:59,072 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:06:59,072 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:06:59,080 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:06:59,528 INFO L134 CoverageAnalysis]: Checked inductivity of 57981 backedges. 21411 proven. 574 refuted. 0 times theorem prover too weak. 35996 trivial. 0 not checked. [2018-04-11 23:06:59,546 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:06:59,546 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 47 [2018-04-11 23:06:59,547 INFO L442 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-04-11 23:06:59,548 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-04-11 23:06:59,548 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=526, Invalid=1636, Unknown=0, NotChecked=0, Total=2162 [2018-04-11 23:06:59,548 INFO L87 Difference]: Start difference. First operand 1016 states and 1023 transitions. Second operand 47 states. [2018-04-11 23:07:00,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:00,027 INFO L93 Difference]: Finished difference Result 1037 states and 1042 transitions. [2018-04-11 23:07:00,027 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-04-11 23:07:00,027 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 982 [2018-04-11 23:07:00,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:00,029 INFO L225 Difference]: With dead ends: 1037 [2018-04-11 23:07:00,029 INFO L226 Difference]: Without dead ends: 1031 [2018-04-11 23:07:00,029 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1026 GetRequests, 968 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1171 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=825, Invalid=2715, Unknown=0, NotChecked=0, Total=3540 [2018-04-11 23:07:00,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1031 states. [2018-04-11 23:07:00,033 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1031 to 1016. [2018-04-11 23:07:00,033 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1016 states. [2018-04-11 23:07:00,034 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1016 states to 1016 states and 1021 transitions. [2018-04-11 23:07:00,034 INFO L78 Accepts]: Start accepts. Automaton has 1016 states and 1021 transitions. Word has length 982 [2018-04-11 23:07:00,035 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:00,035 INFO L459 AbstractCegarLoop]: Abstraction has 1016 states and 1021 transitions. [2018-04-11 23:07:00,035 INFO L460 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-04-11 23:07:00,035 INFO L276 IsEmpty]: Start isEmpty. Operand 1016 states and 1021 transitions. [2018-04-11 23:07:00,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 989 [2018-04-11 23:07:00,039 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:00,039 INFO L355 BasicCegarLoop]: trace histogram [149, 135, 134, 134, 134, 134, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:00,040 INFO L408 AbstractCegarLoop]: === Iteration 44 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:00,040 INFO L82 PathProgramCache]: Analyzing trace with hash -1639344335, now seen corresponding path program 35 times [2018-04-11 23:07:00,040 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:00,040 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:00,040 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:00,040 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:00,040 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:00,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:00,079 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:01,037 INFO L134 CoverageAnalysis]: Checked inductivity of 58810 backedges. 11515 proven. 675 refuted. 0 times theorem prover too weak. 46620 trivial. 0 not checked. [2018-04-11 23:07:01,037 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:01,037 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:01,043 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:07:01,635 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2018-04-11 23:07:01,635 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:01,645 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:01,987 INFO L134 CoverageAnalysis]: Checked inductivity of 58810 backedges. 11515 proven. 675 refuted. 0 times theorem prover too weak. 46620 trivial. 0 not checked. [2018-04-11 23:07:02,007 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:02,007 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 34 [2018-04-11 23:07:02,008 INFO L442 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-04-11 23:07:02,008 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-04-11 23:07:02,008 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=323, Invalid=867, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 23:07:02,009 INFO L87 Difference]: Start difference. First operand 1016 states and 1021 transitions. Second operand 35 states. [2018-04-11 23:07:02,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:02,901 INFO L93 Difference]: Finished difference Result 1040 states and 1046 transitions. [2018-04-11 23:07:02,901 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-04-11 23:07:02,901 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 988 [2018-04-11 23:07:02,902 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:02,903 INFO L225 Difference]: With dead ends: 1040 [2018-04-11 23:07:02,904 INFO L226 Difference]: Without dead ends: 1040 [2018-04-11 23:07:02,904 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1005 GetRequests, 971 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 522 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=323, Invalid=867, Unknown=0, NotChecked=0, Total=1190 [2018-04-11 23:07:02,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1040 states. [2018-04-11 23:07:02,910 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1040 to 1022. [2018-04-11 23:07:02,910 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1022 states. [2018-04-11 23:07:02,911 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1022 states to 1022 states and 1028 transitions. [2018-04-11 23:07:02,911 INFO L78 Accepts]: Start accepts. Automaton has 1022 states and 1028 transitions. Word has length 988 [2018-04-11 23:07:02,911 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:02,911 INFO L459 AbstractCegarLoop]: Abstraction has 1022 states and 1028 transitions. [2018-04-11 23:07:02,911 INFO L460 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-04-11 23:07:02,911 INFO L276 IsEmpty]: Start isEmpty. Operand 1022 states and 1028 transitions. [2018-04-11 23:07:02,916 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 995 [2018-04-11 23:07:02,916 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:02,916 INFO L355 BasicCegarLoop]: trace histogram [150, 136, 135, 135, 135, 135, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:02,916 INFO L408 AbstractCegarLoop]: === Iteration 45 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:02,917 INFO L82 PathProgramCache]: Analyzing trace with hash -1652027095, now seen corresponding path program 36 times [2018-04-11 23:07:02,917 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:02,917 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:02,917 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:02,917 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:02,917 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:02,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:02,960 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:04,663 INFO L134 CoverageAnalysis]: Checked inductivity of 59645 backedges. 12992 proven. 649 refuted. 0 times theorem prover too weak. 46004 trivial. 0 not checked. [2018-04-11 23:07:04,663 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:04,663 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:04,668 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:07:05,071 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 24 check-sat command(s) [2018-04-11 23:07:05,071 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:05,080 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:05,379 INFO L134 CoverageAnalysis]: Checked inductivity of 59645 backedges. 12348 proven. 618 refuted. 0 times theorem prover too weak. 46679 trivial. 0 not checked. [2018-04-11 23:07:05,399 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:05,399 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 21] total 40 [2018-04-11 23:07:05,399 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-04-11 23:07:05,400 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-04-11 23:07:05,400 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=339, Invalid=1221, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 23:07:05,400 INFO L87 Difference]: Start difference. First operand 1022 states and 1028 transitions. Second operand 40 states. [2018-04-11 23:07:06,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:06,317 INFO L93 Difference]: Finished difference Result 1132 states and 1139 transitions. [2018-04-11 23:07:06,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-04-11 23:07:06,317 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 994 [2018-04-11 23:07:06,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:06,319 INFO L225 Difference]: With dead ends: 1132 [2018-04-11 23:07:06,319 INFO L226 Difference]: Without dead ends: 1132 [2018-04-11 23:07:06,319 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1061 GetRequests, 991 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 794 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1209, Invalid=3903, Unknown=0, NotChecked=0, Total=5112 [2018-04-11 23:07:06,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1132 states. [2018-04-11 23:07:06,325 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1132 to 1130. [2018-04-11 23:07:06,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1130 states. [2018-04-11 23:07:06,327 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 1130 states and 1137 transitions. [2018-04-11 23:07:06,327 INFO L78 Accepts]: Start accepts. Automaton has 1130 states and 1137 transitions. Word has length 994 [2018-04-11 23:07:06,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:06,328 INFO L459 AbstractCegarLoop]: Abstraction has 1130 states and 1137 transitions. [2018-04-11 23:07:06,328 INFO L460 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-04-11 23:07:06,328 INFO L276 IsEmpty]: Start isEmpty. Operand 1130 states and 1137 transitions. [2018-04-11 23:07:06,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1097 [2018-04-11 23:07:06,334 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:06,334 INFO L355 BasicCegarLoop]: trace histogram [166, 151, 150, 150, 150, 150, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:06,334 INFO L408 AbstractCegarLoop]: === Iteration 46 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:06,334 INFO L82 PathProgramCache]: Analyzing trace with hash 759381521, now seen corresponding path program 37 times [2018-04-11 23:07:06,334 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:06,334 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:06,335 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:06,335 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:06,335 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:06,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:06,378 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:08,333 INFO L134 CoverageAnalysis]: Checked inductivity of 73365 backedges. 25919 proven. 660 refuted. 0 times theorem prover too weak. 46786 trivial. 0 not checked. [2018-04-11 23:07:08,333 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:08,333 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:08,338 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:07:08,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:08,512 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:09,103 INFO L134 CoverageAnalysis]: Checked inductivity of 73365 backedges. 25919 proven. 660 refuted. 0 times theorem prover too weak. 46786 trivial. 0 not checked. [2018-04-11 23:07:09,121 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:09,121 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34] total 50 [2018-04-11 23:07:09,122 INFO L442 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-04-11 23:07:09,122 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-04-11 23:07:09,123 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=593, Invalid=1857, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 23:07:09,123 INFO L87 Difference]: Start difference. First operand 1130 states and 1137 transitions. Second operand 50 states. [2018-04-11 23:07:09,737 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:09,737 INFO L93 Difference]: Finished difference Result 1151 states and 1156 transitions. [2018-04-11 23:07:09,738 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-04-11 23:07:09,738 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 1096 [2018-04-11 23:07:09,738 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:09,740 INFO L225 Difference]: With dead ends: 1151 [2018-04-11 23:07:09,740 INFO L226 Difference]: Without dead ends: 1145 [2018-04-11 23:07:09,740 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1143 GetRequests, 1081 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1345 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=936, Invalid=3096, Unknown=0, NotChecked=0, Total=4032 [2018-04-11 23:07:09,741 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1145 states. [2018-04-11 23:07:09,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1145 to 1130. [2018-04-11 23:07:09,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1130 states. [2018-04-11 23:07:09,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1130 states to 1130 states and 1135 transitions. [2018-04-11 23:07:09,750 INFO L78 Accepts]: Start accepts. Automaton has 1130 states and 1135 transitions. Word has length 1096 [2018-04-11 23:07:09,751 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:09,751 INFO L459 AbstractCegarLoop]: Abstraction has 1130 states and 1135 transitions. [2018-04-11 23:07:09,751 INFO L460 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-04-11 23:07:09,751 INFO L276 IsEmpty]: Start isEmpty. Operand 1130 states and 1135 transitions. [2018-04-11 23:07:09,760 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1103 [2018-04-11 23:07:09,761 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:09,761 INFO L355 BasicCegarLoop]: trace histogram [167, 152, 151, 151, 151, 151, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:09,761 INFO L408 AbstractCegarLoop]: === Iteration 47 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:09,761 INFO L82 PathProgramCache]: Analyzing trace with hash -1560222711, now seen corresponding path program 38 times [2018-04-11 23:07:09,761 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:09,761 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:09,762 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:09,762 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:07:09,762 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:09,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:09,814 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:11,126 INFO L134 CoverageAnalysis]: Checked inductivity of 74298 backedges. 13875 proven. 768 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-11 23:07:11,126 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:11,126 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:11,132 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:07:11,290 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:07:11,290 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:11,297 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:11,629 INFO L134 CoverageAnalysis]: Checked inductivity of 74298 backedges. 13875 proven. 768 refuted. 0 times theorem prover too weak. 59655 trivial. 0 not checked. [2018-04-11 23:07:11,659 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:11,659 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18] total 18 [2018-04-11 23:07:11,660 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-11 23:07:11,660 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-11 23:07:11,660 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=35, Invalid=307, Unknown=0, NotChecked=0, Total=342 [2018-04-11 23:07:11,660 INFO L87 Difference]: Start difference. First operand 1130 states and 1135 transitions. Second operand 19 states. [2018-04-11 23:07:12,201 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:12,201 INFO L93 Difference]: Finished difference Result 1154 states and 1160 transitions. [2018-04-11 23:07:12,201 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-04-11 23:07:12,201 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 1102 [2018-04-11 23:07:12,202 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:12,203 INFO L225 Difference]: With dead ends: 1154 [2018-04-11 23:07:12,203 INFO L226 Difference]: Without dead ends: 1154 [2018-04-11 23:07:12,203 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1120 GetRequests, 1101 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=35, Invalid=307, Unknown=0, NotChecked=0, Total=342 [2018-04-11 23:07:12,204 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1154 states. [2018-04-11 23:07:12,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1154 to 1136. [2018-04-11 23:07:12,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1136 states. [2018-04-11 23:07:12,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1142 transitions. [2018-04-11 23:07:12,210 INFO L78 Accepts]: Start accepts. Automaton has 1136 states and 1142 transitions. Word has length 1102 [2018-04-11 23:07:12,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:12,210 INFO L459 AbstractCegarLoop]: Abstraction has 1136 states and 1142 transitions. [2018-04-11 23:07:12,210 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-11 23:07:12,210 INFO L276 IsEmpty]: Start isEmpty. Operand 1136 states and 1142 transitions. [2018-04-11 23:07:12,216 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1109 [2018-04-11 23:07:12,216 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:12,216 INFO L355 BasicCegarLoop]: trace histogram [168, 153, 152, 152, 152, 152, 16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:12,217 INFO L408 AbstractCegarLoop]: === Iteration 48 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:12,217 INFO L82 PathProgramCache]: Analyzing trace with hash -120038399, now seen corresponding path program 39 times [2018-04-11 23:07:12,217 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:12,217 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:12,217 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:12,217 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:12,217 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:12,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:12,290 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:14,540 INFO L134 CoverageAnalysis]: Checked inductivity of 75237 backedges. 15547 proven. 740 refuted. 0 times theorem prover too weak. 58950 trivial. 0 not checked. [2018-04-11 23:07:14,540 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:14,540 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:14,545 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:07:14,838 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-04-11 23:07:14,838 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:14,845 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:15,603 INFO L134 CoverageAnalysis]: Checked inductivity of 75237 backedges. 21670 proven. 4847 refuted. 0 times theorem prover too weak. 48720 trivial. 0 not checked. [2018-04-11 23:07:15,622 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:15,622 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 26] total 57 [2018-04-11 23:07:15,623 INFO L442 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-04-11 23:07:15,623 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-04-11 23:07:15,623 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=2696, Unknown=0, NotChecked=0, Total=3192 [2018-04-11 23:07:15,624 INFO L87 Difference]: Start difference. First operand 1136 states and 1142 transitions. Second operand 57 states. [2018-04-11 23:07:17,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:17,251 INFO L93 Difference]: Finished difference Result 1255 states and 1261 transitions. [2018-04-11 23:07:17,251 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-04-11 23:07:17,251 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 1108 [2018-04-11 23:07:17,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:17,253 INFO L225 Difference]: With dead ends: 1255 [2018-04-11 23:07:17,254 INFO L226 Difference]: Without dead ends: 1255 [2018-04-11 23:07:17,254 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1192 GetRequests, 1090 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2308 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2136, Invalid=8576, Unknown=0, NotChecked=0, Total=10712 [2018-04-11 23:07:17,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1255 states. [2018-04-11 23:07:17,261 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1255 to 1244. [2018-04-11 23:07:17,261 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1244 states. [2018-04-11 23:07:17,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1244 states to 1244 states and 1250 transitions. [2018-04-11 23:07:17,262 INFO L78 Accepts]: Start accepts. Automaton has 1244 states and 1250 transitions. Word has length 1108 [2018-04-11 23:07:17,262 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:17,262 INFO L459 AbstractCegarLoop]: Abstraction has 1244 states and 1250 transitions. [2018-04-11 23:07:17,262 INFO L460 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-04-11 23:07:17,262 INFO L276 IsEmpty]: Start isEmpty. Operand 1244 states and 1250 transitions. [2018-04-11 23:07:17,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1217 [2018-04-11 23:07:17,269 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:17,269 INFO L355 BasicCegarLoop]: trace histogram [185, 169, 168, 168, 168, 168, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:17,269 INFO L408 AbstractCegarLoop]: === Iteration 49 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:17,269 INFO L82 PathProgramCache]: Analyzing trace with hash 1881913057, now seen corresponding path program 40 times [2018-04-11 23:07:17,269 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:17,269 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:17,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:17,270 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:17,270 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:17,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:17,318 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:19,818 INFO L134 CoverageAnalysis]: Checked inductivity of 91600 backedges. 31016 proven. 752 refuted. 0 times theorem prover too weak. 59832 trivial. 0 not checked. [2018-04-11 23:07:19,818 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:19,818 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:19,825 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:07:20,002 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:07:20,002 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:20,015 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:20,693 INFO L134 CoverageAnalysis]: Checked inductivity of 91600 backedges. 31016 proven. 752 refuted. 0 times theorem prover too weak. 59832 trivial. 0 not checked. [2018-04-11 23:07:20,713 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:20,713 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36] total 53 [2018-04-11 23:07:20,713 INFO L442 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-04-11 23:07:20,714 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-04-11 23:07:20,714 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=664, Invalid=2092, Unknown=0, NotChecked=0, Total=2756 [2018-04-11 23:07:20,714 INFO L87 Difference]: Start difference. First operand 1244 states and 1250 transitions. Second operand 53 states. [2018-04-11 23:07:21,516 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:21,516 INFO L93 Difference]: Finished difference Result 1262 states and 1266 transitions. [2018-04-11 23:07:21,516 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-04-11 23:07:21,516 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 1216 [2018-04-11 23:07:21,517 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:21,519 INFO L225 Difference]: With dead ends: 1262 [2018-04-11 23:07:21,519 INFO L226 Difference]: Without dead ends: 1256 [2018-04-11 23:07:21,519 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1266 GetRequests, 1200 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1531 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1054, Invalid=3502, Unknown=0, NotChecked=0, Total=4556 [2018-04-11 23:07:21,519 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1256 states. [2018-04-11 23:07:21,525 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1256 to 1244. [2018-04-11 23:07:21,525 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1244 states. [2018-04-11 23:07:21,526 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1244 states to 1244 states and 1248 transitions. [2018-04-11 23:07:21,526 INFO L78 Accepts]: Start accepts. Automaton has 1244 states and 1248 transitions. Word has length 1216 [2018-04-11 23:07:21,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:21,527 INFO L459 AbstractCegarLoop]: Abstraction has 1244 states and 1248 transitions. [2018-04-11 23:07:21,527 INFO L460 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-04-11 23:07:21,527 INFO L276 IsEmpty]: Start isEmpty. Operand 1244 states and 1248 transitions. [2018-04-11 23:07:21,533 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1223 [2018-04-11 23:07:21,533 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:21,534 INFO L355 BasicCegarLoop]: trace histogram [186, 170, 169, 169, 169, 169, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:21,534 INFO L408 AbstractCegarLoop]: === Iteration 50 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:21,534 INFO L82 PathProgramCache]: Analyzing trace with hash -460291879, now seen corresponding path program 41 times [2018-04-11 23:07:21,534 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:21,534 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:21,535 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:21,535 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:21,535 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:21,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:21,591 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:23,158 INFO L134 CoverageAnalysis]: Checked inductivity of 92643 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75240 trivial. 0 not checked. [2018-04-11 23:07:23,159 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:23,159 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:23,164 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:07:24,010 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 33 check-sat command(s) [2018-04-11 23:07:24,010 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:24,024 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:24,473 INFO L134 CoverageAnalysis]: Checked inductivity of 92643 backedges. 16536 proven. 867 refuted. 0 times theorem prover too weak. 75240 trivial. 0 not checked. [2018-04-11 23:07:24,494 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:24,494 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20] total 38 [2018-04-11 23:07:24,495 INFO L442 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-04-11 23:07:24,495 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-04-11 23:07:24,495 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=399, Invalid=1083, Unknown=0, NotChecked=0, Total=1482 [2018-04-11 23:07:24,495 INFO L87 Difference]: Start difference. First operand 1244 states and 1248 transitions. Second operand 39 states. [2018-04-11 23:07:25,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:25,089 INFO L93 Difference]: Finished difference Result 1265 states and 1270 transitions. [2018-04-11 23:07:25,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-11 23:07:25,089 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 1222 [2018-04-11 23:07:25,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:25,093 INFO L225 Difference]: With dead ends: 1265 [2018-04-11 23:07:25,093 INFO L226 Difference]: Without dead ends: 1265 [2018-04-11 23:07:25,093 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1241 GetRequests, 1203 SyntacticMatches, 1 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 660 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=399, Invalid=1083, Unknown=0, NotChecked=0, Total=1482 [2018-04-11 23:07:25,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1265 states. [2018-04-11 23:07:25,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1265 to 1250. [2018-04-11 23:07:25,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1250 states. [2018-04-11 23:07:25,105 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1250 states to 1250 states and 1255 transitions. [2018-04-11 23:07:25,105 INFO L78 Accepts]: Start accepts. Automaton has 1250 states and 1255 transitions. Word has length 1222 [2018-04-11 23:07:25,106 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:25,106 INFO L459 AbstractCegarLoop]: Abstraction has 1250 states and 1255 transitions. [2018-04-11 23:07:25,106 INFO L460 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-04-11 23:07:25,106 INFO L276 IsEmpty]: Start isEmpty. Operand 1250 states and 1255 transitions. [2018-04-11 23:07:25,122 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1229 [2018-04-11 23:07:25,123 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:25,123 INFO L355 BasicCegarLoop]: trace histogram [187, 171, 170, 170, 170, 170, 17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:25,123 INFO L408 AbstractCegarLoop]: === Iteration 51 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:25,123 INFO L82 PathProgramCache]: Analyzing trace with hash -632087343, now seen corresponding path program 42 times [2018-04-11 23:07:25,123 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:25,123 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:25,124 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:25,124 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:25,124 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:25,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:25,186 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:27,915 INFO L134 CoverageAnalysis]: Checked inductivity of 93692 backedges. 18415 proven. 837 refuted. 0 times theorem prover too weak. 74440 trivial. 0 not checked. [2018-04-11 23:07:27,915 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:27,915 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:27,920 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:07:28,676 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 28 check-sat command(s) [2018-04-11 23:07:28,676 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:28,687 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:29,124 INFO L134 CoverageAnalysis]: Checked inductivity of 93692 backedges. 17583 proven. 802 refuted. 0 times theorem prover too weak. 75307 trivial. 0 not checked. [2018-04-11 23:07:29,145 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:29,146 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 23] total 44 [2018-04-11 23:07:29,146 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-11 23:07:29,147 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-11 23:07:29,147 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=415, Invalid=1477, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 23:07:29,147 INFO L87 Difference]: Start difference. First operand 1250 states and 1255 transitions. Second operand 44 states. [2018-04-11 23:07:30,243 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:30,243 INFO L93 Difference]: Finished difference Result 1372 states and 1378 transitions. [2018-04-11 23:07:30,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-04-11 23:07:30,243 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 1228 [2018-04-11 23:07:30,244 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:30,246 INFO L225 Difference]: With dead ends: 1372 [2018-04-11 23:07:30,246 INFO L226 Difference]: Without dead ends: 1372 [2018-04-11 23:07:30,246 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1303 GetRequests, 1225 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 985 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1484, Invalid=4836, Unknown=0, NotChecked=0, Total=6320 [2018-04-11 23:07:30,247 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1372 states. [2018-04-11 23:07:30,252 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1372 to 1370. [2018-04-11 23:07:30,253 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1370 states. [2018-04-11 23:07:30,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1370 states to 1370 states and 1376 transitions. [2018-04-11 23:07:30,254 INFO L78 Accepts]: Start accepts. Automaton has 1370 states and 1376 transitions. Word has length 1228 [2018-04-11 23:07:30,254 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:30,254 INFO L459 AbstractCegarLoop]: Abstraction has 1370 states and 1376 transitions. [2018-04-11 23:07:30,254 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-11 23:07:30,254 INFO L276 IsEmpty]: Start isEmpty. Operand 1370 states and 1376 transitions. [2018-04-11 23:07:30,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1343 [2018-04-11 23:07:30,262 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:30,263 INFO L355 BasicCegarLoop]: trace histogram [205, 188, 187, 187, 187, 187, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:30,263 INFO L408 AbstractCegarLoop]: === Iteration 52 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:30,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1642338729, now seen corresponding path program 43 times [2018-04-11 23:07:30,263 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:30,263 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:30,263 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:30,264 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:30,264 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:30,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:30,323 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:33,506 INFO L134 CoverageAnalysis]: Checked inductivity of 113016 backedges. 36738 proven. 850 refuted. 0 times theorem prover too weak. 75428 trivial. 0 not checked. [2018-04-11 23:07:33,506 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:33,506 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:33,511 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:07:33,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:33,714 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:34,448 INFO L134 CoverageAnalysis]: Checked inductivity of 113016 backedges. 36738 proven. 850 refuted. 0 times theorem prover too weak. 75428 trivial. 0 not checked. [2018-04-11 23:07:34,464 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:34,465 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38] total 56 [2018-04-11 23:07:34,465 INFO L442 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-04-11 23:07:34,466 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-04-11 23:07:34,466 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=739, Invalid=2341, Unknown=0, NotChecked=0, Total=3080 [2018-04-11 23:07:34,466 INFO L87 Difference]: Start difference. First operand 1370 states and 1376 transitions. Second operand 56 states. [2018-04-11 23:07:35,194 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:35,194 INFO L93 Difference]: Finished difference Result 1388 states and 1392 transitions. [2018-04-11 23:07:35,195 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-04-11 23:07:35,195 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 1342 [2018-04-11 23:07:35,196 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:35,198 INFO L225 Difference]: With dead ends: 1388 [2018-04-11 23:07:35,198 INFO L226 Difference]: Without dead ends: 1382 [2018-04-11 23:07:35,198 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1395 GetRequests, 1325 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1729 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1179, Invalid=3933, Unknown=0, NotChecked=0, Total=5112 [2018-04-11 23:07:35,198 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1382 states. [2018-04-11 23:07:35,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1382 to 1370. [2018-04-11 23:07:35,204 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1370 states. [2018-04-11 23:07:35,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1370 states to 1370 states and 1374 transitions. [2018-04-11 23:07:35,205 INFO L78 Accepts]: Start accepts. Automaton has 1370 states and 1374 transitions. Word has length 1342 [2018-04-11 23:07:35,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:35,205 INFO L459 AbstractCegarLoop]: Abstraction has 1370 states and 1374 transitions. [2018-04-11 23:07:35,205 INFO L460 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-04-11 23:07:35,205 INFO L276 IsEmpty]: Start isEmpty. Operand 1370 states and 1374 transitions. [2018-04-11 23:07:35,212 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1349 [2018-04-11 23:07:35,212 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:35,213 INFO L355 BasicCegarLoop]: trace histogram [206, 189, 188, 188, 188, 188, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:35,213 INFO L408 AbstractCegarLoop]: === Iteration 53 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:35,213 INFO L82 PathProgramCache]: Analyzing trace with hash -1478054495, now seen corresponding path program 44 times [2018-04-11 23:07:35,213 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:35,213 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:35,214 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:35,214 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:07:35,214 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:35,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:35,273 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:37,149 INFO L134 CoverageAnalysis]: Checked inductivity of 114175 backedges. 19516 proven. 972 refuted. 0 times theorem prover too weak. 93687 trivial. 0 not checked. [2018-04-11 23:07:37,149 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:37,149 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:37,154 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:07:37,345 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:07:37,345 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:37,356 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:37,867 INFO L134 CoverageAnalysis]: Checked inductivity of 114175 backedges. 19516 proven. 972 refuted. 0 times theorem prover too weak. 93687 trivial. 0 not checked. [2018-04-11 23:07:37,887 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:37,888 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20] total 39 [2018-04-11 23:07:37,888 INFO L442 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-04-11 23:07:37,888 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-04-11 23:07:37,888 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=401, Invalid=1159, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 23:07:37,889 INFO L87 Difference]: Start difference. First operand 1370 states and 1374 transitions. Second operand 40 states. [2018-04-11 23:07:38,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:38,374 INFO L93 Difference]: Finished difference Result 1391 states and 1396 transitions. [2018-04-11 23:07:38,374 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-04-11 23:07:38,374 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 1348 [2018-04-11 23:07:38,375 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:38,377 INFO L225 Difference]: With dead ends: 1391 [2018-04-11 23:07:38,377 INFO L226 Difference]: Without dead ends: 1391 [2018-04-11 23:07:38,377 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1368 GetRequests, 1330 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 632 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=401, Invalid=1159, Unknown=0, NotChecked=0, Total=1560 [2018-04-11 23:07:38,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1391 states. [2018-04-11 23:07:38,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1391 to 1376. [2018-04-11 23:07:38,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1376 states. [2018-04-11 23:07:38,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1376 states to 1376 states and 1381 transitions. [2018-04-11 23:07:38,386 INFO L78 Accepts]: Start accepts. Automaton has 1376 states and 1381 transitions. Word has length 1348 [2018-04-11 23:07:38,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:38,387 INFO L459 AbstractCegarLoop]: Abstraction has 1376 states and 1381 transitions. [2018-04-11 23:07:38,387 INFO L460 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-04-11 23:07:38,387 INFO L276 IsEmpty]: Start isEmpty. Operand 1376 states and 1381 transitions. [2018-04-11 23:07:38,394 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1355 [2018-04-11 23:07:38,395 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:38,395 INFO L355 BasicCegarLoop]: trace histogram [207, 190, 189, 189, 189, 189, 18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:38,395 INFO L408 AbstractCegarLoop]: === Iteration 54 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:38,395 INFO L82 PathProgramCache]: Analyzing trace with hash 724997017, now seen corresponding path program 45 times [2018-04-11 23:07:38,395 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:38,395 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:38,396 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:38,396 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:38,396 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:38,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:38,481 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:41,748 INFO L134 CoverageAnalysis]: Checked inductivity of 115340 backedges. 21614 proven. 940 refuted. 0 times theorem prover too weak. 92786 trivial. 0 not checked. [2018-04-11 23:07:41,748 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:41,749 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:41,764 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:07:42,214 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 20 check-sat command(s) [2018-04-11 23:07:42,214 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:42,223 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:43,135 INFO L134 CoverageAnalysis]: Checked inductivity of 115340 backedges. 31211 proven. 6205 refuted. 0 times theorem prover too weak. 77924 trivial. 0 not checked. [2018-04-11 23:07:43,154 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:43,155 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 28] total 63 [2018-04-11 23:07:43,155 INFO L442 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-04-11 23:07:43,156 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-04-11 23:07:43,156 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=609, Invalid=3297, Unknown=0, NotChecked=0, Total=3906 [2018-04-11 23:07:43,156 INFO L87 Difference]: Start difference. First operand 1376 states and 1381 transitions. Second operand 63 states. [2018-04-11 23:07:45,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:45,037 INFO L93 Difference]: Finished difference Result 1513 states and 1519 transitions. [2018-04-11 23:07:45,037 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 93 states. [2018-04-11 23:07:45,037 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 1354 [2018-04-11 23:07:45,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:45,039 INFO L225 Difference]: With dead ends: 1513 [2018-04-11 23:07:45,040 INFO L226 Difference]: Without dead ends: 1513 [2018-04-11 23:07:45,040 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1448 GetRequests, 1334 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2905 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2637, Invalid=10703, Unknown=0, NotChecked=0, Total=13340 [2018-04-11 23:07:45,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1513 states. [2018-04-11 23:07:45,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1513 to 1502. [2018-04-11 23:07:45,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1502 states. [2018-04-11 23:07:45,048 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1502 states to 1502 states and 1508 transitions. [2018-04-11 23:07:45,048 INFO L78 Accepts]: Start accepts. Automaton has 1502 states and 1508 transitions. Word has length 1354 [2018-04-11 23:07:45,048 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:45,048 INFO L459 AbstractCegarLoop]: Abstraction has 1502 states and 1508 transitions. [2018-04-11 23:07:45,048 INFO L460 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-04-11 23:07:45,048 INFO L276 IsEmpty]: Start isEmpty. Operand 1502 states and 1508 transitions. [2018-04-11 23:07:45,058 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1475 [2018-04-11 23:07:45,058 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:45,058 INFO L355 BasicCegarLoop]: trace histogram [226, 208, 207, 207, 207, 207, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:45,058 INFO L408 AbstractCegarLoop]: === Iteration 55 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:45,058 INFO L82 PathProgramCache]: Analyzing trace with hash -637855639, now seen corresponding path program 46 times [2018-04-11 23:07:45,058 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:45,059 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:45,059 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:45,059 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:45,059 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:45,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:45,119 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:48,892 INFO L134 CoverageAnalysis]: Checked inductivity of 137961 backedges. 43121 proven. 954 refuted. 0 times theorem prover too weak. 93886 trivial. 0 not checked. [2018-04-11 23:07:48,892 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:48,893 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:48,899 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:07:49,087 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:07:49,087 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:49,097 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:49,984 INFO L134 CoverageAnalysis]: Checked inductivity of 137961 backedges. 43121 proven. 954 refuted. 0 times theorem prover too weak. 93886 trivial. 0 not checked. [2018-04-11 23:07:50,003 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:50,003 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40] total 59 [2018-04-11 23:07:50,004 INFO L442 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-04-11 23:07:50,004 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-04-11 23:07:50,004 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=818, Invalid=2604, Unknown=0, NotChecked=0, Total=3422 [2018-04-11 23:07:50,004 INFO L87 Difference]: Start difference. First operand 1502 states and 1508 transitions. Second operand 59 states. [2018-04-11 23:07:50,748 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:50,748 INFO L93 Difference]: Finished difference Result 1520 states and 1524 transitions. [2018-04-11 23:07:50,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-04-11 23:07:50,748 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 1474 [2018-04-11 23:07:50,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:50,751 INFO L225 Difference]: With dead ends: 1520 [2018-04-11 23:07:50,751 INFO L226 Difference]: Without dead ends: 1514 [2018-04-11 23:07:50,752 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1530 GetRequests, 1456 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1939 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1311, Invalid=4389, Unknown=0, NotChecked=0, Total=5700 [2018-04-11 23:07:50,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1514 states. [2018-04-11 23:07:50,762 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1514 to 1502. [2018-04-11 23:07:50,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1502 states. [2018-04-11 23:07:50,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1502 states to 1502 states and 1506 transitions. [2018-04-11 23:07:50,764 INFO L78 Accepts]: Start accepts. Automaton has 1502 states and 1506 transitions. Word has length 1474 [2018-04-11 23:07:50,765 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:50,765 INFO L459 AbstractCegarLoop]: Abstraction has 1502 states and 1506 transitions. [2018-04-11 23:07:50,765 INFO L460 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-04-11 23:07:50,765 INFO L276 IsEmpty]: Start isEmpty. Operand 1502 states and 1506 transitions. [2018-04-11 23:07:50,780 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1481 [2018-04-11 23:07:50,780 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:50,780 INFO L355 BasicCegarLoop]: trace histogram [227, 209, 208, 208, 208, 208, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:50,780 INFO L408 AbstractCegarLoop]: === Iteration 56 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:50,781 INFO L82 PathProgramCache]: Analyzing trace with hash 121936993, now seen corresponding path program 47 times [2018-04-11 23:07:50,781 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:50,781 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:50,781 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:50,782 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:50,782 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:50,868 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:50,870 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:53,154 INFO L134 CoverageAnalysis]: Checked inductivity of 139242 backedges. 22833 proven. 1083 refuted. 0 times theorem prover too weak. 115326 trivial. 0 not checked. [2018-04-11 23:07:53,155 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:53,155 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:53,160 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:07:54,448 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 44 check-sat command(s) [2018-04-11 23:07:54,448 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:07:54,464 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:07:55,085 INFO L134 CoverageAnalysis]: Checked inductivity of 139242 backedges. 22833 proven. 1083 refuted. 0 times theorem prover too weak. 115326 trivial. 0 not checked. [2018-04-11 23:07:55,106 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:07:55,106 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22] total 42 [2018-04-11 23:07:55,107 INFO L442 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-04-11 23:07:55,107 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-04-11 23:07:55,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=483, Invalid=1323, Unknown=0, NotChecked=0, Total=1806 [2018-04-11 23:07:55,108 INFO L87 Difference]: Start difference. First operand 1502 states and 1506 transitions. Second operand 43 states. [2018-04-11 23:07:55,589 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:07:55,589 INFO L93 Difference]: Finished difference Result 1523 states and 1528 transitions. [2018-04-11 23:07:55,589 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-04-11 23:07:55,589 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 1480 [2018-04-11 23:07:55,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:07:55,592 INFO L225 Difference]: With dead ends: 1523 [2018-04-11 23:07:55,592 INFO L226 Difference]: Without dead ends: 1523 [2018-04-11 23:07:55,592 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1501 GetRequests, 1459 SyntacticMatches, 1 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 814 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=483, Invalid=1323, Unknown=0, NotChecked=0, Total=1806 [2018-04-11 23:07:55,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1523 states. [2018-04-11 23:07:55,597 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1523 to 1508. [2018-04-11 23:07:55,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1508 states. [2018-04-11 23:07:55,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1508 states to 1508 states and 1513 transitions. [2018-04-11 23:07:55,598 INFO L78 Accepts]: Start accepts. Automaton has 1508 states and 1513 transitions. Word has length 1480 [2018-04-11 23:07:55,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:07:55,599 INFO L459 AbstractCegarLoop]: Abstraction has 1508 states and 1513 transitions. [2018-04-11 23:07:55,599 INFO L460 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-04-11 23:07:55,599 INFO L276 IsEmpty]: Start isEmpty. Operand 1508 states and 1513 transitions. [2018-04-11 23:07:55,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1487 [2018-04-11 23:07:55,608 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:07:55,608 INFO L355 BasicCegarLoop]: trace histogram [228, 210, 209, 209, 209, 209, 19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:07:55,608 INFO L408 AbstractCegarLoop]: === Iteration 57 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:07:55,609 INFO L82 PathProgramCache]: Analyzing trace with hash -2003406247, now seen corresponding path program 48 times [2018-04-11 23:07:55,609 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:07:55,609 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:07:55,609 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:55,609 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:07:55,609 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:07:55,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:07:55,673 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:07:59,763 INFO L134 CoverageAnalysis]: Checked inductivity of 140529 backedges. 25162 proven. 1049 refuted. 0 times theorem prover too weak. 114318 trivial. 0 not checked. [2018-04-11 23:07:59,763 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:07:59,763 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:07:59,768 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:08:01,217 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 41 check-sat command(s) [2018-04-11 23:08:01,217 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:08:01,233 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:02,269 INFO L134 CoverageAnalysis]: Checked inductivity of 140529 backedges. 34640 proven. 8221 refuted. 0 times theorem prover too weak. 97668 trivial. 0 not checked. [2018-04-11 23:08:02,291 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:02,291 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 29] total 65 [2018-04-11 23:08:02,292 INFO L442 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-04-11 23:08:02,292 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-04-11 23:08:02,292 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=3509, Unknown=0, NotChecked=0, Total=4160 [2018-04-11 23:08:02,292 INFO L87 Difference]: Start difference. First operand 1508 states and 1513 transitions. Second operand 65 states. [2018-04-11 23:08:04,305 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:04,305 INFO L93 Difference]: Finished difference Result 1651 states and 1657 transitions. [2018-04-11 23:08:04,305 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 96 states. [2018-04-11 23:08:04,305 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 1486 [2018-04-11 23:08:04,306 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:04,308 INFO L225 Difference]: With dead ends: 1651 [2018-04-11 23:08:04,309 INFO L226 Difference]: Without dead ends: 1651 [2018-04-11 23:08:04,309 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1584 GetRequests, 1466 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3125 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2820, Invalid=11460, Unknown=0, NotChecked=0, Total=14280 [2018-04-11 23:08:04,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1651 states. [2018-04-11 23:08:04,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1651 to 1640. [2018-04-11 23:08:04,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1640 states. [2018-04-11 23:08:04,317 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1640 states to 1640 states and 1646 transitions. [2018-04-11 23:08:04,317 INFO L78 Accepts]: Start accepts. Automaton has 1640 states and 1646 transitions. Word has length 1486 [2018-04-11 23:08:04,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:04,317 INFO L459 AbstractCegarLoop]: Abstraction has 1640 states and 1646 transitions. [2018-04-11 23:08:04,317 INFO L460 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-04-11 23:08:04,317 INFO L276 IsEmpty]: Start isEmpty. Operand 1640 states and 1646 transitions. [2018-04-11 23:08:04,328 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1613 [2018-04-11 23:08:04,329 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:04,329 INFO L355 BasicCegarLoop]: trace histogram [248, 229, 228, 228, 228, 228, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:04,329 INFO L408 AbstractCegarLoop]: === Iteration 58 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:04,329 INFO L82 PathProgramCache]: Analyzing trace with hash -330410207, now seen corresponding path program 49 times [2018-04-11 23:08:04,329 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:04,329 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:04,330 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:04,330 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:08:04,330 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:04,416 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:04,420 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:09,064 INFO L134 CoverageAnalysis]: Checked inductivity of 166801 backedges. 50201 proven. 1064 refuted. 0 times theorem prover too weak. 115536 trivial. 0 not checked. [2018-04-11 23:08:09,064 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:09,064 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:09,069 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:08:09,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:09,297 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:10,254 INFO L134 CoverageAnalysis]: Checked inductivity of 166801 backedges. 50201 proven. 1064 refuted. 0 times theorem prover too weak. 115536 trivial. 0 not checked. [2018-04-11 23:08:10,273 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:10,273 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42] total 62 [2018-04-11 23:08:10,274 INFO L442 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-04-11 23:08:10,274 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-04-11 23:08:10,274 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=901, Invalid=2881, Unknown=0, NotChecked=0, Total=3782 [2018-04-11 23:08:10,274 INFO L87 Difference]: Start difference. First operand 1640 states and 1646 transitions. Second operand 62 states. [2018-04-11 23:08:11,177 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:11,177 INFO L93 Difference]: Finished difference Result 1658 states and 1662 transitions. [2018-04-11 23:08:11,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-04-11 23:08:11,177 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 1612 [2018-04-11 23:08:11,178 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:11,180 INFO L225 Difference]: With dead ends: 1658 [2018-04-11 23:08:11,180 INFO L226 Difference]: Without dead ends: 1652 [2018-04-11 23:08:11,180 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1671 GetRequests, 1593 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2161 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1450, Invalid=4870, Unknown=0, NotChecked=0, Total=6320 [2018-04-11 23:08:11,181 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1652 states. [2018-04-11 23:08:11,186 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1652 to 1640. [2018-04-11 23:08:11,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1640 states. [2018-04-11 23:08:11,187 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1640 states to 1640 states and 1644 transitions. [2018-04-11 23:08:11,187 INFO L78 Accepts]: Start accepts. Automaton has 1640 states and 1644 transitions. Word has length 1612 [2018-04-11 23:08:11,188 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:11,188 INFO L459 AbstractCegarLoop]: Abstraction has 1640 states and 1644 transitions. [2018-04-11 23:08:11,188 INFO L460 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-04-11 23:08:11,188 INFO L276 IsEmpty]: Start isEmpty. Operand 1640 states and 1644 transitions. [2018-04-11 23:08:11,198 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1619 [2018-04-11 23:08:11,198 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:11,198 INFO L355 BasicCegarLoop]: trace histogram [249, 230, 229, 229, 229, 229, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:11,198 INFO L408 AbstractCegarLoop]: === Iteration 59 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:11,198 INFO L82 PathProgramCache]: Analyzing trace with hash 180154649, now seen corresponding path program 50 times [2018-04-11 23:08:11,198 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:11,199 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:11,199 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:11,199 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:08:11,199 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:11,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:11,284 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:14,188 INFO L134 CoverageAnalysis]: Checked inductivity of 168210 backedges. 26505 proven. 1200 refuted. 0 times theorem prover too weak. 140505 trivial. 0 not checked. [2018-04-11 23:08:14,188 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:14,188 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:14,193 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:08:14,416 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:08:14,417 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:08:14,428 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:15,150 INFO L134 CoverageAnalysis]: Checked inductivity of 168210 backedges. 26505 proven. 1200 refuted. 0 times theorem prover too weak. 140505 trivial. 0 not checked. [2018-04-11 23:08:15,168 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:15,169 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22] total 43 [2018-04-11 23:08:15,169 INFO L442 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-04-11 23:08:15,169 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-04-11 23:08:15,169 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=443, Invalid=1449, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 23:08:15,169 INFO L87 Difference]: Start difference. First operand 1640 states and 1644 transitions. Second operand 44 states. [2018-04-11 23:08:15,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:15,666 INFO L93 Difference]: Finished difference Result 1661 states and 1666 transitions. [2018-04-11 23:08:15,667 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-04-11 23:08:15,667 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 1618 [2018-04-11 23:08:15,667 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:15,669 INFO L225 Difference]: With dead ends: 1661 [2018-04-11 23:08:15,669 INFO L226 Difference]: Without dead ends: 1661 [2018-04-11 23:08:15,669 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1640 GetRequests, 1598 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 741 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=443, Invalid=1449, Unknown=0, NotChecked=0, Total=1892 [2018-04-11 23:08:15,669 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1661 states. [2018-04-11 23:08:15,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1661 to 1646. [2018-04-11 23:08:15,675 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1646 states. [2018-04-11 23:08:15,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1646 states to 1646 states and 1651 transitions. [2018-04-11 23:08:15,676 INFO L78 Accepts]: Start accepts. Automaton has 1646 states and 1651 transitions. Word has length 1618 [2018-04-11 23:08:15,676 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:15,676 INFO L459 AbstractCegarLoop]: Abstraction has 1646 states and 1651 transitions. [2018-04-11 23:08:15,676 INFO L460 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-04-11 23:08:15,676 INFO L276 IsEmpty]: Start isEmpty. Operand 1646 states and 1651 transitions. [2018-04-11 23:08:15,686 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1625 [2018-04-11 23:08:15,686 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:15,687 INFO L355 BasicCegarLoop]: trace histogram [250, 231, 230, 230, 230, 230, 20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:15,687 INFO L408 AbstractCegarLoop]: === Iteration 60 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:15,687 INFO L82 PathProgramCache]: Analyzing trace with hash -1560650479, now seen corresponding path program 51 times [2018-04-11 23:08:15,687 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:15,687 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:15,688 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:15,688 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:08:15,688 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:15,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:15,770 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:20,736 INFO L134 CoverageAnalysis]: Checked inductivity of 169625 backedges. 29077 proven. 1164 refuted. 0 times theorem prover too weak. 139384 trivial. 0 not checked. [2018-04-11 23:08:20,736 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:20,737 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:20,742 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:08:21,106 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-04-11 23:08:21,106 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:08:21,116 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:22,301 INFO L134 CoverageAnalysis]: Checked inductivity of 169625 backedges. 49274 proven. 3825 refuted. 0 times theorem prover too weak. 116526 trivial. 0 not checked. [2018-04-11 23:08:22,321 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:22,321 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 30] total 71 [2018-04-11 23:08:22,322 INFO L442 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-04-11 23:08:22,322 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-04-11 23:08:22,322 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=777, Invalid=4193, Unknown=0, NotChecked=0, Total=4970 [2018-04-11 23:08:22,322 INFO L87 Difference]: Start difference. First operand 1646 states and 1651 transitions. Second operand 71 states. [2018-04-11 23:08:24,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:24,349 INFO L93 Difference]: Finished difference Result 1804 states and 1810 transitions. [2018-04-11 23:08:24,349 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 108 states. [2018-04-11 23:08:24,349 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 1624 [2018-04-11 23:08:24,350 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:24,352 INFO L225 Difference]: With dead ends: 1804 [2018-04-11 23:08:24,352 INFO L226 Difference]: Without dead ends: 1804 [2018-04-11 23:08:24,353 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1731 GetRequests, 1600 SyntacticMatches, 0 SemanticMatches, 131 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3849 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3427, Invalid=14129, Unknown=0, NotChecked=0, Total=17556 [2018-04-11 23:08:24,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1804 states. [2018-04-11 23:08:24,360 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1804 to 1790. [2018-04-11 23:08:24,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1790 states. [2018-04-11 23:08:24,361 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1790 states to 1790 states and 1796 transitions. [2018-04-11 23:08:24,361 INFO L78 Accepts]: Start accepts. Automaton has 1790 states and 1796 transitions. Word has length 1624 [2018-04-11 23:08:24,362 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:24,362 INFO L459 AbstractCegarLoop]: Abstraction has 1790 states and 1796 transitions. [2018-04-11 23:08:24,362 INFO L460 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-04-11 23:08:24,362 INFO L276 IsEmpty]: Start isEmpty. Operand 1790 states and 1796 transitions. [2018-04-11 23:08:24,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1763 [2018-04-11 23:08:24,374 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:24,374 INFO L355 BasicCegarLoop]: trace histogram [272, 252, 251, 251, 251, 251, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:24,375 INFO L408 AbstractCegarLoop]: === Iteration 61 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:24,375 INFO L82 PathProgramCache]: Analyzing trace with hash -1134640695, now seen corresponding path program 52 times [2018-04-11 23:08:24,375 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:24,375 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:24,375 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:24,375 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:08:24,375 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:24,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:24,469 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:27,878 INFO L134 CoverageAnalysis]: Checked inductivity of 201463 backedges. 30550 proven. 1323 refuted. 0 times theorem prover too weak. 169590 trivial. 0 not checked. [2018-04-11 23:08:27,878 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:27,878 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:27,883 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:08:28,261 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:08:28,261 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:08:28,276 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:29,071 INFO L134 CoverageAnalysis]: Checked inductivity of 201463 backedges. 30550 proven. 1323 refuted. 0 times theorem prover too weak. 169590 trivial. 0 not checked. [2018-04-11 23:08:29,091 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:29,091 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23] total 45 [2018-04-11 23:08:29,092 INFO L442 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-04-11 23:08:29,092 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-04-11 23:08:29,092 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=552, Invalid=1518, Unknown=0, NotChecked=0, Total=2070 [2018-04-11 23:08:29,092 INFO L87 Difference]: Start difference. First operand 1790 states and 1796 transitions. Second operand 46 states. [2018-04-11 23:08:29,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:29,678 INFO L93 Difference]: Finished difference Result 1811 states and 1818 transitions. [2018-04-11 23:08:29,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-04-11 23:08:29,678 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 1762 [2018-04-11 23:08:29,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:29,681 INFO L225 Difference]: With dead ends: 1811 [2018-04-11 23:08:29,681 INFO L226 Difference]: Without dead ends: 1811 [2018-04-11 23:08:29,681 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1785 GetRequests, 1741 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 883 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=552, Invalid=1518, Unknown=0, NotChecked=0, Total=2070 [2018-04-11 23:08:29,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1811 states. [2018-04-11 23:08:29,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1811 to 1796. [2018-04-11 23:08:29,688 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1796 states. [2018-04-11 23:08:29,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1796 states to 1796 states and 1803 transitions. [2018-04-11 23:08:29,689 INFO L78 Accepts]: Start accepts. Automaton has 1796 states and 1803 transitions. Word has length 1762 [2018-04-11 23:08:29,689 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:29,689 INFO L459 AbstractCegarLoop]: Abstraction has 1796 states and 1803 transitions. [2018-04-11 23:08:29,689 INFO L460 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-04-11 23:08:29,689 INFO L276 IsEmpty]: Start isEmpty. Operand 1796 states and 1803 transitions. [2018-04-11 23:08:29,702 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1769 [2018-04-11 23:08:29,702 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:29,702 INFO L355 BasicCegarLoop]: trace histogram [273, 253, 252, 252, 252, 252, 21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:29,702 INFO L408 AbstractCegarLoop]: === Iteration 62 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:29,703 INFO L82 PathProgramCache]: Analyzing trace with hash 1179183553, now seen corresponding path program 53 times [2018-04-11 23:08:29,703 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:29,703 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:29,703 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:29,703 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:08:29,703 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:29,791 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:29,795 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:35,722 INFO L134 CoverageAnalysis]: Checked inductivity of 203012 backedges. 33377 proven. 1285 refuted. 0 times theorem prover too weak. 168350 trivial. 0 not checked. [2018-04-11 23:08:35,723 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:35,723 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:35,729 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:08:37,394 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-04-11 23:08:37,394 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:08:37,417 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:38,913 INFO L134 CoverageAnalysis]: Checked inductivity of 203012 backedges. 33304 proven. 7511 refuted. 0 times theorem prover too weak. 162197 trivial. 0 not checked. [2018-04-11 23:08:38,936 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:38,936 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 52] total 77 [2018-04-11 23:08:38,937 INFO L442 AbstractCegarLoop]: Interpolant automaton has 77 states [2018-04-11 23:08:38,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 77 interpolants. [2018-04-11 23:08:38,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1177, Invalid=4675, Unknown=0, NotChecked=0, Total=5852 [2018-04-11 23:08:38,937 INFO L87 Difference]: Start difference. First operand 1796 states and 1803 transitions. Second operand 77 states. [2018-04-11 23:08:40,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:40,491 INFO L93 Difference]: Finished difference Result 2106 states and 2118 transitions. [2018-04-11 23:08:40,491 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-04-11 23:08:40,491 INFO L78 Accepts]: Start accepts. Automaton has 77 states. Word has length 1768 [2018-04-11 23:08:40,491 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:40,494 INFO L225 Difference]: With dead ends: 2106 [2018-04-11 23:08:40,494 INFO L226 Difference]: Without dead ends: 2106 [2018-04-11 23:08:40,495 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1862 GetRequests, 1740 SyntacticMatches, 0 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2942 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3229, Invalid=12023, Unknown=0, NotChecked=0, Total=15252 [2018-04-11 23:08:40,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2106 states. [2018-04-11 23:08:40,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2106 to 2090. [2018-04-11 23:08:40,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2090 states. [2018-04-11 23:08:40,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2090 states to 2090 states and 2102 transitions. [2018-04-11 23:08:40,505 INFO L78 Accepts]: Start accepts. Automaton has 2090 states and 2102 transitions. Word has length 1768 [2018-04-11 23:08:40,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:40,506 INFO L459 AbstractCegarLoop]: Abstraction has 2090 states and 2102 transitions. [2018-04-11 23:08:40,506 INFO L460 AbstractCegarLoop]: Interpolant automaton has 77 states. [2018-04-11 23:08:40,506 INFO L276 IsEmpty]: Start isEmpty. Operand 2090 states and 2102 transitions. [2018-04-11 23:08:40,523 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1901 [2018-04-11 23:08:40,524 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:40,524 INFO L355 BasicCegarLoop]: trace histogram [294, 273, 272, 272, 272, 272, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:40,524 INFO L408 AbstractCegarLoop]: === Iteration 63 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:40,524 INFO L82 PathProgramCache]: Analyzing trace with hash -1197311871, now seen corresponding path program 54 times [2018-04-11 23:08:40,524 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:40,524 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:40,525 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:40,525 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:08:40,525 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:40,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:40,645 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:47,340 INFO L134 CoverageAnalysis]: Checked inductivity of 236043 backedges. 66333 proven. 1302 refuted. 0 times theorem prover too weak. 168408 trivial. 0 not checked. [2018-04-11 23:08:47,341 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:47,341 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:47,346 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:08:48,277 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 45 check-sat command(s) [2018-04-11 23:08:48,277 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:08:48,291 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:49,637 INFO L134 CoverageAnalysis]: Checked inductivity of 236043 backedges. 58687 proven. 6561 refuted. 0 times theorem prover too weak. 170795 trivial. 0 not checked. [2018-04-11 23:08:49,659 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:49,659 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 31] total 76 [2018-04-11 23:08:49,660 INFO L442 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-04-11 23:08:49,660 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-04-11 23:08:49,660 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1081, Invalid=4619, Unknown=0, NotChecked=0, Total=5700 [2018-04-11 23:08:49,661 INFO L87 Difference]: Start difference. First operand 2090 states and 2102 transitions. Second operand 76 states. [2018-04-11 23:08:52,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:52,426 INFO L93 Difference]: Finished difference Result 1963 states and 1967 transitions. [2018-04-11 23:08:52,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 133 states. [2018-04-11 23:08:52,426 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 1900 [2018-04-11 23:08:52,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:52,428 INFO L225 Difference]: With dead ends: 1963 [2018-04-11 23:08:52,429 INFO L226 Difference]: Without dead ends: 1948 [2018-04-11 23:08:52,431 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2071 GetRequests, 1871 SyntacticMatches, 0 SemanticMatches, 200 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14486 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=6930, Invalid=33672, Unknown=0, NotChecked=0, Total=40602 [2018-04-11 23:08:52,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1948 states. [2018-04-11 23:08:52,442 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1948 to 1934. [2018-04-11 23:08:52,442 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1934 states. [2018-04-11 23:08:52,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1934 states to 1934 states and 1938 transitions. [2018-04-11 23:08:52,445 INFO L78 Accepts]: Start accepts. Automaton has 1934 states and 1938 transitions. Word has length 1900 [2018-04-11 23:08:52,445 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:52,445 INFO L459 AbstractCegarLoop]: Abstraction has 1934 states and 1938 transitions. [2018-04-11 23:08:52,445 INFO L460 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-04-11 23:08:52,445 INFO L276 IsEmpty]: Start isEmpty. Operand 1934 states and 1938 transitions. [2018-04-11 23:08:52,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1913 [2018-04-11 23:08:52,469 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:52,469 INFO L355 BasicCegarLoop]: trace histogram [296, 275, 274, 274, 274, 274, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:52,470 INFO L408 AbstractCegarLoop]: === Iteration 64 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:52,470 INFO L82 PathProgramCache]: Analyzing trace with hash 1548555889, now seen corresponding path program 55 times [2018-04-11 23:08:52,470 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:52,470 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:52,471 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:52,471 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:08:52,471 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:52,627 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:52,630 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:08:56,724 INFO L134 CoverageAnalysis]: Checked inductivity of 239403 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 202965 trivial. 0 not checked. [2018-04-11 23:08:56,724 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:08:56,724 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:08:56,729 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:08:56,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:56,994 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:08:57,925 INFO L134 CoverageAnalysis]: Checked inductivity of 239403 backedges. 34986 proven. 1452 refuted. 0 times theorem prover too weak. 202965 trivial. 0 not checked. [2018-04-11 23:08:57,945 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:08:57,945 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24] total 47 [2018-04-11 23:08:57,946 INFO L442 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-04-11 23:08:57,946 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-04-11 23:08:57,946 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=577, Invalid=1679, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 23:08:57,959 INFO L87 Difference]: Start difference. First operand 1934 states and 1938 transitions. Second operand 48 states. [2018-04-11 23:08:58,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:08:58,437 INFO L93 Difference]: Finished difference Result 1955 states and 1960 transitions. [2018-04-11 23:08:58,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-04-11 23:08:58,437 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 1912 [2018-04-11 23:08:58,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:08:58,440 INFO L225 Difference]: With dead ends: 1955 [2018-04-11 23:08:58,440 INFO L226 Difference]: Without dead ends: 1955 [2018-04-11 23:08:58,440 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 1936 GetRequests, 1890 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 948 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=577, Invalid=1679, Unknown=0, NotChecked=0, Total=2256 [2018-04-11 23:08:58,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1955 states. [2018-04-11 23:08:58,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1955 to 1940. [2018-04-11 23:08:58,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1940 states. [2018-04-11 23:08:58,449 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1940 states to 1940 states and 1945 transitions. [2018-04-11 23:08:58,449 INFO L78 Accepts]: Start accepts. Automaton has 1940 states and 1945 transitions. Word has length 1912 [2018-04-11 23:08:58,450 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:08:58,450 INFO L459 AbstractCegarLoop]: Abstraction has 1940 states and 1945 transitions. [2018-04-11 23:08:58,450 INFO L460 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-04-11 23:08:58,450 INFO L276 IsEmpty]: Start isEmpty. Operand 1940 states and 1945 transitions. [2018-04-11 23:08:58,464 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 1919 [2018-04-11 23:08:58,464 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:08:58,465 INFO L355 BasicCegarLoop]: trace histogram [297, 276, 275, 275, 275, 275, 22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:08:58,465 INFO L408 AbstractCegarLoop]: === Iteration 65 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:08:58,465 INFO L82 PathProgramCache]: Analyzing trace with hash -29417367, now seen corresponding path program 56 times [2018-04-11 23:08:58,465 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:08:58,465 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:08:58,466 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:58,466 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:08:58,466 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:08:58,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:08:58,561 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:09:05,760 INFO L134 CoverageAnalysis]: Checked inductivity of 241092 backedges. 38080 proven. 1412 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-04-11 23:09:05,760 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:09:05,761 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:09:05,766 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:09:06,030 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:09:06,030 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:09:06,043 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:09:07,571 INFO L134 CoverageAnalysis]: Checked inductivity of 241092 backedges. 38148 proven. 1344 refuted. 0 times theorem prover too weak. 201600 trivial. 0 not checked. [2018-04-11 23:09:07,589 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:09:07,590 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 49] total 75 [2018-04-11 23:09:07,590 INFO L442 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-04-11 23:09:07,590 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-04-11 23:09:07,591 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1276, Invalid=4274, Unknown=0, NotChecked=0, Total=5550 [2018-04-11 23:09:07,591 INFO L87 Difference]: Start difference. First operand 1940 states and 1945 transitions. Second operand 75 states. [2018-04-11 23:09:08,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:09:08,835 INFO L93 Difference]: Finished difference Result 2104 states and 2110 transitions. [2018-04-11 23:09:08,835 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-04-11 23:09:08,835 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 1918 [2018-04-11 23:09:08,836 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:09:08,837 INFO L225 Difference]: With dead ends: 2104 [2018-04-11 23:09:08,837 INFO L226 Difference]: Without dead ends: 2104 [2018-04-11 23:09:08,838 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2012 GetRequests, 1894 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2408 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=3613, Invalid=10667, Unknown=0, NotChecked=0, Total=14280 [2018-04-11 23:09:08,839 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2104 states. [2018-04-11 23:09:08,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2104 to 2090. [2018-04-11 23:09:08,846 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2090 states. [2018-04-11 23:09:08,847 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2090 states to 2090 states and 2096 transitions. [2018-04-11 23:09:08,847 INFO L78 Accepts]: Start accepts. Automaton has 2090 states and 2096 transitions. Word has length 1918 [2018-04-11 23:09:08,847 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:09:08,847 INFO L459 AbstractCegarLoop]: Abstraction has 2090 states and 2096 transitions. [2018-04-11 23:09:08,847 INFO L460 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-04-11 23:09:08,847 INFO L276 IsEmpty]: Start isEmpty. Operand 2090 states and 2096 transitions. [2018-04-11 23:09:08,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2063 [2018-04-11 23:09:08,863 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:09:08,864 INFO L355 BasicCegarLoop]: trace histogram [320, 298, 297, 297, 297, 297, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:09:08,864 INFO L408 AbstractCegarLoop]: === Iteration 66 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:09:08,864 INFO L82 PathProgramCache]: Analyzing trace with hash 1148758297, now seen corresponding path program 57 times [2018-04-11 23:09:08,864 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:09:08,864 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:09:08,865 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:08,865 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:09:08,865 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:08,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:09:08,951 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:09:17,067 INFO L134 CoverageAnalysis]: Checked inductivity of 280621 backedges. 75983 proven. 1430 refuted. 0 times theorem prover too weak. 203208 trivial. 0 not checked. [2018-04-11 23:09:17,067 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:09:17,104 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:09:17,110 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:09:17,780 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-04-11 23:09:17,780 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:09:17,793 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:09:19,257 INFO L134 CoverageAnalysis]: Checked inductivity of 280621 backedges. 71601 proven. 4603 refuted. 0 times theorem prover too weak. 204417 trivial. 0 not checked. [2018-04-11 23:09:19,275 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:09:19,276 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 32] total 78 [2018-04-11 23:09:19,276 INFO L442 AbstractCegarLoop]: Interpolant automaton has 78 states [2018-04-11 23:09:19,276 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 78 interpolants. [2018-04-11 23:09:19,277 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1193, Invalid=4813, Unknown=0, NotChecked=0, Total=6006 [2018-04-11 23:09:19,277 INFO L87 Difference]: Start difference. First operand 2090 states and 2096 transitions. Second operand 78 states. [2018-04-11 23:09:21,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:09:21,684 INFO L93 Difference]: Finished difference Result 2110 states and 2114 transitions. [2018-04-11 23:09:21,684 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 117 states. [2018-04-11 23:09:21,684 INFO L78 Accepts]: Start accepts. Automaton has 78 states. Word has length 2062 [2018-04-11 23:09:21,685 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:09:21,688 INFO L225 Difference]: With dead ends: 2110 [2018-04-11 23:09:21,688 INFO L226 Difference]: Without dead ends: 2104 [2018-04-11 23:09:21,691 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2220 GetRequests, 2033 SyntacticMatches, 0 SemanticMatches, 187 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12227 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=5973, Invalid=29559, Unknown=0, NotChecked=0, Total=35532 [2018-04-11 23:09:21,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2104 states. [2018-04-11 23:09:21,698 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2104 to 2090. [2018-04-11 23:09:21,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2090 states. [2018-04-11 23:09:21,699 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2090 states to 2090 states and 2094 transitions. [2018-04-11 23:09:21,699 INFO L78 Accepts]: Start accepts. Automaton has 2090 states and 2094 transitions. Word has length 2062 [2018-04-11 23:09:21,700 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:09:21,700 INFO L459 AbstractCegarLoop]: Abstraction has 2090 states and 2094 transitions. [2018-04-11 23:09:21,700 INFO L460 AbstractCegarLoop]: Interpolant automaton has 78 states. [2018-04-11 23:09:21,700 INFO L276 IsEmpty]: Start isEmpty. Operand 2090 states and 2094 transitions. [2018-04-11 23:09:21,715 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2069 [2018-04-11 23:09:21,716 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:09:21,716 INFO L355 BasicCegarLoop]: trace histogram [321, 299, 298, 298, 298, 298, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:09:21,716 INFO L408 AbstractCegarLoop]: === Iteration 67 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:09:21,716 INFO L82 PathProgramCache]: Analyzing trace with hash -1453135599, now seen corresponding path program 58 times [2018-04-11 23:09:21,717 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:09:21,717 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:09:21,717 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:21,717 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:09:21,717 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:21,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:09:21,809 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:09:26,723 INFO L134 CoverageAnalysis]: Checked inductivity of 282450 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241032 trivial. 0 not checked. [2018-04-11 23:09:26,723 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:09:26,723 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:09:26,728 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:09:27,231 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:09:27,231 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:09:27,253 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:09:28,317 INFO L134 CoverageAnalysis]: Checked inductivity of 282450 backedges. 39831 proven. 1587 refuted. 0 times theorem prover too weak. 241032 trivial. 0 not checked. [2018-04-11 23:09:28,341 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:09:28,342 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25] total 49 [2018-04-11 23:09:28,342 INFO L442 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-04-11 23:09:28,342 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-04-11 23:09:28,343 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=650, Invalid=1800, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 23:09:28,343 INFO L87 Difference]: Start difference. First operand 2090 states and 2094 transitions. Second operand 50 states. [2018-04-11 23:09:28,903 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:09:28,903 INFO L93 Difference]: Finished difference Result 2111 states and 2116 transitions. [2018-04-11 23:09:28,903 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-04-11 23:09:28,903 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 2068 [2018-04-11 23:09:28,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:09:28,906 INFO L225 Difference]: With dead ends: 2111 [2018-04-11 23:09:28,906 INFO L226 Difference]: Without dead ends: 2111 [2018-04-11 23:09:28,906 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2093 GetRequests, 2045 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1059 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=650, Invalid=1800, Unknown=0, NotChecked=0, Total=2450 [2018-04-11 23:09:28,907 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2111 states. [2018-04-11 23:09:28,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2111 to 2096. [2018-04-11 23:09:28,913 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2096 states. [2018-04-11 23:09:28,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2096 states to 2096 states and 2101 transitions. [2018-04-11 23:09:28,914 INFO L78 Accepts]: Start accepts. Automaton has 2096 states and 2101 transitions. Word has length 2068 [2018-04-11 23:09:28,915 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:09:28,915 INFO L459 AbstractCegarLoop]: Abstraction has 2096 states and 2101 transitions. [2018-04-11 23:09:28,915 INFO L460 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-04-11 23:09:28,915 INFO L276 IsEmpty]: Start isEmpty. Operand 2096 states and 2101 transitions. [2018-04-11 23:09:28,930 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2075 [2018-04-11 23:09:28,930 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:09:28,931 INFO L355 BasicCegarLoop]: trace histogram [322, 300, 299, 299, 299, 299, 23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:09:28,931 INFO L408 AbstractCegarLoop]: === Iteration 68 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:09:28,931 INFO L82 PathProgramCache]: Analyzing trace with hash 1410628361, now seen corresponding path program 59 times [2018-04-11 23:09:28,931 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:09:28,931 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:09:28,932 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:28,932 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:09:28,932 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:29,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:09:29,031 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:09:37,678 INFO L134 CoverageAnalysis]: Checked inductivity of 284285 backedges. 43204 proven. 1545 refuted. 0 times theorem prover too weak. 239536 trivial. 0 not checked. [2018-04-11 23:09:37,679 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:09:37,679 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:09:37,684 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:09:40,136 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 58 check-sat command(s) [2018-04-11 23:09:40,137 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:09:40,161 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:09:42,003 INFO L134 CoverageAnalysis]: Checked inductivity of 284285 backedges. 43117 proven. 8981 refuted. 0 times theorem prover too weak. 232187 trivial. 0 not checked. [2018-04-11 23:09:42,028 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:09:42,029 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 56] total 83 [2018-04-11 23:09:42,030 INFO L442 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-04-11 23:09:42,030 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-04-11 23:09:42,030 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1377, Invalid=5429, Unknown=0, NotChecked=0, Total=6806 [2018-04-11 23:09:42,030 INFO L87 Difference]: Start difference. First operand 2096 states and 2101 transitions. Second operand 83 states. [2018-04-11 23:09:44,006 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:09:44,006 INFO L93 Difference]: Finished difference Result 2266 states and 2272 transitions. [2018-04-11 23:09:44,006 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 84 states. [2018-04-11 23:09:44,006 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2074 [2018-04-11 23:09:44,007 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:09:44,009 INFO L225 Difference]: With dead ends: 2266 [2018-04-11 23:09:44,009 INFO L226 Difference]: Without dead ends: 2266 [2018-04-11 23:09:44,010 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2176 GetRequests, 2044 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3429 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=3799, Invalid=14023, Unknown=0, NotChecked=0, Total=17822 [2018-04-11 23:09:44,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2266 states. [2018-04-11 23:09:44,017 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2266 to 2252. [2018-04-11 23:09:44,017 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2252 states. [2018-04-11 23:09:44,018 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2252 states to 2252 states and 2258 transitions. [2018-04-11 23:09:44,018 INFO L78 Accepts]: Start accepts. Automaton has 2252 states and 2258 transitions. Word has length 2074 [2018-04-11 23:09:44,019 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:09:44,019 INFO L459 AbstractCegarLoop]: Abstraction has 2252 states and 2258 transitions. [2018-04-11 23:09:44,019 INFO L460 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-04-11 23:09:44,019 INFO L276 IsEmpty]: Start isEmpty. Operand 2252 states and 2258 transitions. [2018-04-11 23:09:44,037 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2225 [2018-04-11 23:09:44,038 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:09:44,038 INFO L355 BasicCegarLoop]: trace histogram [346, 323, 322, 322, 322, 322, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:09:44,038 INFO L408 AbstractCegarLoop]: === Iteration 69 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:09:44,038 INFO L82 PathProgramCache]: Analyzing trace with hash -1590184015, now seen corresponding path program 60 times [2018-04-11 23:09:44,038 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:09:44,039 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:09:44,039 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:44,039 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:09:44,039 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:09:44,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:09:44,150 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:09:54,285 INFO L134 CoverageAnalysis]: Checked inductivity of 329061 backedges. 86211 proven. 1564 refuted. 0 times theorem prover too weak. 241286 trivial. 0 not checked. [2018-04-11 23:09:54,285 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:09:54,285 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:09:54,291 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:09:55,948 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-04-11 23:09:55,948 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:09:55,975 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:09:57,643 INFO L134 CoverageAnalysis]: Checked inductivity of 329061 backedges. 81423 proven. 5019 refuted. 0 times theorem prover too weak. 242619 trivial. 0 not checked. [2018-04-11 23:09:57,664 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:09:57,664 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 33] total 81 [2018-04-11 23:09:57,665 INFO L442 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-04-11 23:09:57,665 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-04-11 23:09:57,665 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1292, Invalid=5188, Unknown=0, NotChecked=0, Total=6480 [2018-04-11 23:09:57,665 INFO L87 Difference]: Start difference. First operand 2252 states and 2258 transitions. Second operand 81 states. [2018-04-11 23:10:00,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:10:00,622 INFO L93 Difference]: Finished difference Result 2272 states and 2276 transitions. [2018-04-11 23:10:00,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 122 states. [2018-04-11 23:10:00,622 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2224 [2018-04-11 23:10:00,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:10:00,625 INFO L225 Difference]: With dead ends: 2272 [2018-04-11 23:10:00,625 INFO L226 Difference]: Without dead ends: 2266 [2018-04-11 23:10:00,628 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2389 GetRequests, 2194 SyntacticMatches, 0 SemanticMatches, 195 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13323 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=6484, Invalid=32128, Unknown=0, NotChecked=0, Total=38612 [2018-04-11 23:10:00,629 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2266 states. [2018-04-11 23:10:00,636 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2266 to 2252. [2018-04-11 23:10:00,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2252 states. [2018-04-11 23:10:00,637 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2252 states to 2252 states and 2256 transitions. [2018-04-11 23:10:00,637 INFO L78 Accepts]: Start accepts. Automaton has 2252 states and 2256 transitions. Word has length 2224 [2018-04-11 23:10:00,638 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:10:00,638 INFO L459 AbstractCegarLoop]: Abstraction has 2252 states and 2256 transitions. [2018-04-11 23:10:00,638 INFO L460 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-04-11 23:10:00,638 INFO L276 IsEmpty]: Start isEmpty. Operand 2252 states and 2256 transitions. [2018-04-11 23:10:00,656 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2231 [2018-04-11 23:10:00,656 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:10:00,657 INFO L355 BasicCegarLoop]: trace histogram [347, 324, 323, 323, 323, 323, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:10:00,657 INFO L408 AbstractCegarLoop]: === Iteration 70 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:10:00,657 INFO L82 PathProgramCache]: Analyzing trace with hash 1264821673, now seen corresponding path program 61 times [2018-04-11 23:10:00,657 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:10:00,657 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:10:00,657 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:00,658 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:10:00,658 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:00,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:10:00,757 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:10:06,699 INFO L134 CoverageAnalysis]: Checked inductivity of 331042 backedges. 45103 proven. 1728 refuted. 0 times theorem prover too weak. 284211 trivial. 0 not checked. [2018-04-11 23:10:06,699 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:10:06,699 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:10:06,704 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:10:07,007 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:10:07,025 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:10:08,291 INFO L134 CoverageAnalysis]: Checked inductivity of 331042 backedges. 45103 proven. 1728 refuted. 0 times theorem prover too weak. 284211 trivial. 0 not checked. [2018-04-11 23:10:08,310 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:10:08,311 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26] total 51 [2018-04-11 23:10:08,311 INFO L442 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-04-11 23:10:08,312 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-04-11 23:10:08,312 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=527, Invalid=2125, Unknown=0, NotChecked=0, Total=2652 [2018-04-11 23:10:08,312 INFO L87 Difference]: Start difference. First operand 2252 states and 2256 transitions. Second operand 52 states. [2018-04-11 23:10:09,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:10:09,135 INFO L93 Difference]: Finished difference Result 2273 states and 2278 transitions. [2018-04-11 23:10:09,135 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-04-11 23:10:09,135 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 2230 [2018-04-11 23:10:09,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:10:09,138 INFO L225 Difference]: With dead ends: 2273 [2018-04-11 23:10:09,138 INFO L226 Difference]: Without dead ends: 2273 [2018-04-11 23:10:09,138 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2256 GetRequests, 2206 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 971 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=527, Invalid=2125, Unknown=0, NotChecked=0, Total=2652 [2018-04-11 23:10:09,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2273 states. [2018-04-11 23:10:09,146 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2273 to 2258. [2018-04-11 23:10:09,146 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2258 states. [2018-04-11 23:10:09,147 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2258 states to 2258 states and 2263 transitions. [2018-04-11 23:10:09,148 INFO L78 Accepts]: Start accepts. Automaton has 2258 states and 2263 transitions. Word has length 2230 [2018-04-11 23:10:09,148 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:10:09,148 INFO L459 AbstractCegarLoop]: Abstraction has 2258 states and 2263 transitions. [2018-04-11 23:10:09,148 INFO L460 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-04-11 23:10:09,148 INFO L276 IsEmpty]: Start isEmpty. Operand 2258 states and 2263 transitions. [2018-04-11 23:10:09,166 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2237 [2018-04-11 23:10:09,166 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:10:09,167 INFO L355 BasicCegarLoop]: trace histogram [348, 325, 324, 324, 324, 324, 24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:10:09,167 INFO L408 AbstractCegarLoop]: === Iteration 71 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:10:09,167 INFO L82 PathProgramCache]: Analyzing trace with hash -229939807, now seen corresponding path program 62 times [2018-04-11 23:10:09,167 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:10:09,167 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:10:09,168 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:09,168 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:10:09,168 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:09,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:10:09,276 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:10:19,507 INFO L134 CoverageAnalysis]: Checked inductivity of 333029 backedges. 48767 proven. 1684 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-04-11 23:10:19,508 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:10:19,508 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:10:19,513 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:10:19,813 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:10:19,814 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:10:19,829 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:10:21,757 INFO L134 CoverageAnalysis]: Checked inductivity of 333029 backedges. 48841 proven. 1610 refuted. 0 times theorem prover too weak. 282578 trivial. 0 not checked. [2018-04-11 23:10:21,777 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:10:21,778 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 53] total 81 [2018-04-11 23:10:21,779 INFO L442 AbstractCegarLoop]: Interpolant automaton has 81 states [2018-04-11 23:10:21,779 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 81 interpolants. [2018-04-11 23:10:21,779 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1486, Invalid=4994, Unknown=0, NotChecked=0, Total=6480 [2018-04-11 23:10:21,779 INFO L87 Difference]: Start difference. First operand 2258 states and 2263 transitions. Second operand 81 states. [2018-04-11 23:10:23,483 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:10:23,484 INFO L93 Difference]: Finished difference Result 2434 states and 2440 transitions. [2018-04-11 23:10:23,484 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 77 states. [2018-04-11 23:10:23,484 INFO L78 Accepts]: Start accepts. Automaton has 81 states. Word has length 2236 [2018-04-11 23:10:23,485 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:10:23,487 INFO L225 Difference]: With dead ends: 2434 [2018-04-11 23:10:23,487 INFO L226 Difference]: Without dead ends: 2434 [2018-04-11 23:10:23,488 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2338 GetRequests, 2210 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2843 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=4227, Invalid=12543, Unknown=0, NotChecked=0, Total=16770 [2018-04-11 23:10:23,489 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2434 states. [2018-04-11 23:10:23,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2434 to 2420. [2018-04-11 23:10:23,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2420 states. [2018-04-11 23:10:23,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2420 states to 2420 states and 2426 transitions. [2018-04-11 23:10:23,502 INFO L78 Accepts]: Start accepts. Automaton has 2420 states and 2426 transitions. Word has length 2236 [2018-04-11 23:10:23,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:10:23,502 INFO L459 AbstractCegarLoop]: Abstraction has 2420 states and 2426 transitions. [2018-04-11 23:10:23,502 INFO L460 AbstractCegarLoop]: Interpolant automaton has 81 states. [2018-04-11 23:10:23,502 INFO L276 IsEmpty]: Start isEmpty. Operand 2420 states and 2426 transitions. [2018-04-11 23:10:23,524 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2393 [2018-04-11 23:10:23,525 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:10:23,525 INFO L355 BasicCegarLoop]: trace histogram [373, 349, 348, 348, 348, 348, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:10:23,525 INFO L408 AbstractCegarLoop]: === Iteration 72 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:10:23,526 INFO L82 PathProgramCache]: Analyzing trace with hash -1174542271, now seen corresponding path program 63 times [2018-04-11 23:10:23,526 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:10:23,526 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:10:23,526 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:23,526 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:10:23,527 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:23,652 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:10:23,657 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:10:35,115 INFO L134 CoverageAnalysis]: Checked inductivity of 383496 backedges. 97316 proven. 1704 refuted. 0 times theorem prover too weak. 284476 trivial. 0 not checked. [2018-04-11 23:10:35,115 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:10:35,116 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:10:35,121 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:10:36,001 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 26 check-sat command(s) [2018-04-11 23:10:36,001 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:10:36,018 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:10:37,923 INFO L134 CoverageAnalysis]: Checked inductivity of 383496 backedges. 92104 proven. 5453 refuted. 0 times theorem prover too weak. 285939 trivial. 0 not checked. [2018-04-11 23:10:37,944 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:10:37,944 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 34] total 84 [2018-04-11 23:10:37,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 84 states [2018-04-11 23:10:37,945 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 84 interpolants. [2018-04-11 23:10:37,945 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1395, Invalid=5577, Unknown=0, NotChecked=0, Total=6972 [2018-04-11 23:10:37,945 INFO L87 Difference]: Start difference. First operand 2420 states and 2426 transitions. Second operand 84 states. [2018-04-11 23:10:40,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:10:40,890 INFO L93 Difference]: Finished difference Result 2440 states and 2444 transitions. [2018-04-11 23:10:40,890 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 127 states. [2018-04-11 23:10:40,890 INFO L78 Accepts]: Start accepts. Automaton has 84 states. Word has length 2392 [2018-04-11 23:10:40,891 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:10:40,893 INFO L225 Difference]: With dead ends: 2440 [2018-04-11 23:10:40,893 INFO L226 Difference]: Without dead ends: 2434 [2018-04-11 23:10:40,896 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2564 GetRequests, 2361 SyntacticMatches, 0 SemanticMatches, 203 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14466 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=7016, Invalid=34804, Unknown=0, NotChecked=0, Total=41820 [2018-04-11 23:10:40,897 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2434 states. [2018-04-11 23:10:40,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2434 to 2420. [2018-04-11 23:10:40,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2420 states. [2018-04-11 23:10:40,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2420 states to 2420 states and 2424 transitions. [2018-04-11 23:10:40,905 INFO L78 Accepts]: Start accepts. Automaton has 2420 states and 2424 transitions. Word has length 2392 [2018-04-11 23:10:40,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:10:40,905 INFO L459 AbstractCegarLoop]: Abstraction has 2420 states and 2424 transitions. [2018-04-11 23:10:40,906 INFO L460 AbstractCegarLoop]: Interpolant automaton has 84 states. [2018-04-11 23:10:40,906 INFO L276 IsEmpty]: Start isEmpty. Operand 2420 states and 2424 transitions. [2018-04-11 23:10:40,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2399 [2018-04-11 23:10:40,938 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:10:40,939 INFO L355 BasicCegarLoop]: trace histogram [374, 350, 349, 349, 349, 349, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:10:40,939 INFO L408 AbstractCegarLoop]: === Iteration 73 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:10:40,939 INFO L82 PathProgramCache]: Analyzing trace with hash -1005049287, now seen corresponding path program 64 times [2018-04-11 23:10:40,939 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:10:40,940 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:10:40,940 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:40,940 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:10:40,940 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:41,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:10:41,054 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:10:47,990 INFO L134 CoverageAnalysis]: Checked inductivity of 385635 backedges. 50820 proven. 1875 refuted. 0 times theorem prover too weak. 332940 trivial. 0 not checked. [2018-04-11 23:10:47,990 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:10:47,990 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:10:47,995 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:10:48,644 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:10:48,644 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:10:48,665 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:10:50,047 INFO L134 CoverageAnalysis]: Checked inductivity of 385635 backedges. 50820 proven. 1875 refuted. 0 times theorem prover too weak. 332940 trivial. 0 not checked. [2018-04-11 23:10:50,071 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:10:50,071 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27] total 53 [2018-04-11 23:10:50,072 INFO L442 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-04-11 23:10:50,072 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-04-11 23:10:50,072 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=756, Invalid=2106, Unknown=0, NotChecked=0, Total=2862 [2018-04-11 23:10:50,072 INFO L87 Difference]: Start difference. First operand 2420 states and 2424 transitions. Second operand 54 states. [2018-04-11 23:10:51,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:10:51,091 INFO L93 Difference]: Finished difference Result 2441 states and 2446 transitions. [2018-04-11 23:10:51,092 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-04-11 23:10:51,092 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 2398 [2018-04-11 23:10:51,093 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:10:51,095 INFO L225 Difference]: With dead ends: 2441 [2018-04-11 23:10:51,095 INFO L226 Difference]: Without dead ends: 2441 [2018-04-11 23:10:51,095 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2425 GetRequests, 2373 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1251 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=756, Invalid=2106, Unknown=0, NotChecked=0, Total=2862 [2018-04-11 23:10:51,096 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2441 states. [2018-04-11 23:10:51,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2441 to 2426. [2018-04-11 23:10:51,103 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2426 states. [2018-04-11 23:10:51,104 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2426 states to 2426 states and 2431 transitions. [2018-04-11 23:10:51,104 INFO L78 Accepts]: Start accepts. Automaton has 2426 states and 2431 transitions. Word has length 2398 [2018-04-11 23:10:51,105 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:10:51,105 INFO L459 AbstractCegarLoop]: Abstraction has 2426 states and 2431 transitions. [2018-04-11 23:10:51,105 INFO L460 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-04-11 23:10:51,105 INFO L276 IsEmpty]: Start isEmpty. Operand 2426 states and 2431 transitions. [2018-04-11 23:10:51,124 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2405 [2018-04-11 23:10:51,124 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:10:51,125 INFO L355 BasicCegarLoop]: trace histogram [375, 351, 350, 350, 350, 350, 25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:10:51,125 INFO L408 AbstractCegarLoop]: === Iteration 74 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:10:51,125 INFO L82 PathProgramCache]: Analyzing trace with hash -1945223631, now seen corresponding path program 65 times [2018-04-11 23:10:51,125 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:10:51,125 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:10:51,125 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:51,125 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:10:51,126 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:10:51,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:10:51,267 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:11:03,556 INFO L134 CoverageAnalysis]: Checked inductivity of 387780 backedges. 54787 proven. 1829 refuted. 0 times theorem prover too weak. 331164 trivial. 0 not checked. [2018-04-11 23:11:03,557 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:11:03,557 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:11:03,563 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:11:07,892 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-04-11 23:11:07,893 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:11:07,931 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:11:10,481 INFO L134 CoverageAnalysis]: Checked inductivity of 387780 backedges. 54686 proven. 10579 refuted. 0 times theorem prover too weak. 322515 trivial. 0 not checked. [2018-04-11 23:11:10,519 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:11:10,519 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 60] total 89 [2018-04-11 23:11:10,520 INFO L442 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-04-11 23:11:10,520 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-04-11 23:11:10,521 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1593, Invalid=6239, Unknown=0, NotChecked=0, Total=7832 [2018-04-11 23:11:10,521 INFO L87 Difference]: Start difference. First operand 2426 states and 2431 transitions. Second operand 89 states. [2018-04-11 23:11:12,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:11:12,645 INFO L93 Difference]: Finished difference Result 2608 states and 2614 transitions. [2018-04-11 23:11:12,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 90 states. [2018-04-11 23:11:12,645 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 2404 [2018-04-11 23:11:12,646 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:11:12,648 INFO L225 Difference]: With dead ends: 2608 [2018-04-11 23:11:12,648 INFO L226 Difference]: Without dead ends: 2608 [2018-04-11 23:11:12,649 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2514 GetRequests, 2372 SyntacticMatches, 0 SemanticMatches, 142 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3952 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=4417, Invalid=16175, Unknown=0, NotChecked=0, Total=20592 [2018-04-11 23:11:12,649 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2608 states. [2018-04-11 23:11:12,660 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2608 to 2594. [2018-04-11 23:11:12,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2594 states. [2018-04-11 23:11:12,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2594 states to 2594 states and 2600 transitions. [2018-04-11 23:11:12,663 INFO L78 Accepts]: Start accepts. Automaton has 2594 states and 2600 transitions. Word has length 2404 [2018-04-11 23:11:12,664 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:11:12,664 INFO L459 AbstractCegarLoop]: Abstraction has 2594 states and 2600 transitions. [2018-04-11 23:11:12,664 INFO L460 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-04-11 23:11:12,664 INFO L276 IsEmpty]: Start isEmpty. Operand 2594 states and 2600 transitions. [2018-04-11 23:11:12,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2567 [2018-04-11 23:11:12,688 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:11:12,689 INFO L355 BasicCegarLoop]: trace histogram [401, 376, 375, 375, 375, 375, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:11:12,689 INFO L408 AbstractCegarLoop]: === Iteration 75 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:11:12,689 INFO L82 PathProgramCache]: Analyzing trace with hash -1971385655, now seen corresponding path program 66 times [2018-04-11 23:11:12,689 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:11:12,689 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:11:12,689 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:11:12,689 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:11:12,689 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:11:12,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:11:12,800 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:11:27,392 INFO L134 CoverageAnalysis]: Checked inductivity of 444400 backedges. 109334 proven. 1850 refuted. 0 times theorem prover too weak. 333216 trivial. 0 not checked. [2018-04-11 23:11:27,392 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:11:27,392 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:11:27,398 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:11:31,136 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 53 check-sat command(s) [2018-04-11 23:11:31,136 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:11:31,168 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:11:33,226 INFO L134 CoverageAnalysis]: Checked inductivity of 444400 backedges. 56841 proven. 2028 refuted. 0 times theorem prover too weak. 385531 trivial. 0 not checked. [2018-04-11 23:11:33,254 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:11:33,255 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 29] total 82 [2018-04-11 23:11:33,256 INFO L442 AbstractCegarLoop]: Interpolant automaton has 82 states [2018-04-11 23:11:33,256 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 82 interpolants. [2018-04-11 23:11:33,256 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1139, Invalid=5503, Unknown=0, NotChecked=0, Total=6642 [2018-04-11 23:11:33,256 INFO L87 Difference]: Start difference. First operand 2594 states and 2600 transitions. Second operand 82 states. [2018-04-11 23:11:35,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:11:35,509 INFO L93 Difference]: Finished difference Result 2621 states and 2626 transitions. [2018-04-11 23:11:35,509 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 78 states. [2018-04-11 23:11:35,509 INFO L78 Accepts]: Start accepts. Automaton has 82 states. Word has length 2566 [2018-04-11 23:11:35,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:11:35,514 INFO L225 Difference]: With dead ends: 2621 [2018-04-11 23:11:35,514 INFO L226 Difference]: Without dead ends: 2615 [2018-04-11 23:11:35,516 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2668 GetRequests, 2539 SyntacticMatches, 0 SemanticMatches, 129 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4675 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=3485, Invalid=13545, Unknown=0, NotChecked=0, Total=17030 [2018-04-11 23:11:35,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2615 states. [2018-04-11 23:11:35,528 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2615 to 2600. [2018-04-11 23:11:35,528 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2600 states. [2018-04-11 23:11:35,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2600 states to 2600 states and 2605 transitions. [2018-04-11 23:11:35,530 INFO L78 Accepts]: Start accepts. Automaton has 2600 states and 2605 transitions. Word has length 2566 [2018-04-11 23:11:35,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:11:35,531 INFO L459 AbstractCegarLoop]: Abstraction has 2600 states and 2605 transitions. [2018-04-11 23:11:35,531 INFO L460 AbstractCegarLoop]: Interpolant automaton has 82 states. [2018-04-11 23:11:35,531 INFO L276 IsEmpty]: Start isEmpty. Operand 2600 states and 2605 transitions. [2018-04-11 23:11:35,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2579 [2018-04-11 23:11:35,555 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:11:35,556 INFO L355 BasicCegarLoop]: trace histogram [403, 378, 377, 377, 377, 377, 26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:11:35,556 INFO L408 AbstractCegarLoop]: === Iteration 76 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:11:35,556 INFO L82 PathProgramCache]: Analyzing trace with hash 769184953, now seen corresponding path program 67 times [2018-04-11 23:11:35,556 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:11:35,556 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:11:35,557 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:11:35,557 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:11:35,557 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:11:35,716 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:11:35,720 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:11:51,123 INFO L134 CoverageAnalysis]: Checked inductivity of 449012 backedges. 61282 proven. 1980 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-04-11 23:11:51,123 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:11:51,123 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:11:51,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:11:51,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:11:51,562 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:11:54,255 INFO L134 CoverageAnalysis]: Checked inductivity of 449012 backedges. 61362 proven. 1900 refuted. 0 times theorem prover too weak. 385750 trivial. 0 not checked. [2018-04-11 23:11:54,279 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:11:54,280 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 57] total 87 [2018-04-11 23:11:54,281 INFO L442 AbstractCegarLoop]: Interpolant automaton has 87 states [2018-04-11 23:11:54,281 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 87 interpolants. [2018-04-11 23:11:54,281 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1712, Invalid=5770, Unknown=0, NotChecked=0, Total=7482 [2018-04-11 23:11:54,281 INFO L87 Difference]: Start difference. First operand 2600 states and 2605 transitions. Second operand 87 states. [2018-04-11 23:11:56,178 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:11:56,178 INFO L93 Difference]: Finished difference Result 2788 states and 2794 transitions. [2018-04-11 23:11:56,178 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-04-11 23:11:56,178 INFO L78 Accepts]: Start accepts. Automaton has 87 states. Word has length 2578 [2018-04-11 23:11:56,179 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:11:56,182 INFO L225 Difference]: With dead ends: 2788 [2018-04-11 23:11:56,182 INFO L226 Difference]: Without dead ends: 2788 [2018-04-11 23:11:56,183 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2688 GetRequests, 2550 SyntacticMatches, 0 SemanticMatches, 138 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3314 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=4889, Invalid=14571, Unknown=0, NotChecked=0, Total=19460 [2018-04-11 23:11:56,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2788 states. [2018-04-11 23:11:56,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2788 to 2774. [2018-04-11 23:11:56,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2774 states. [2018-04-11 23:11:56,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2774 states to 2774 states and 2780 transitions. [2018-04-11 23:11:56,197 INFO L78 Accepts]: Start accepts. Automaton has 2774 states and 2780 transitions. Word has length 2578 [2018-04-11 23:11:56,198 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:11:56,198 INFO L459 AbstractCegarLoop]: Abstraction has 2774 states and 2780 transitions. [2018-04-11 23:11:56,198 INFO L460 AbstractCegarLoop]: Interpolant automaton has 87 states. [2018-04-11 23:11:56,198 INFO L276 IsEmpty]: Start isEmpty. Operand 2774 states and 2780 transitions. [2018-04-11 23:11:56,227 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2747 [2018-04-11 23:11:56,227 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:11:56,227 INFO L355 BasicCegarLoop]: trace histogram [430, 404, 403, 403, 403, 403, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:11:56,227 INFO L408 AbstractCegarLoop]: === Iteration 77 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:11:56,227 INFO L82 PathProgramCache]: Analyzing trace with hash -1712234167, now seen corresponding path program 68 times [2018-04-11 23:11:56,228 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:11:56,228 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:11:56,228 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:11:56,228 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:11:56,228 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:11:56,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:11:56,393 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:12:12,789 INFO L134 CoverageAnalysis]: Checked inductivity of 512265 backedges. 122301 proven. 2002 refuted. 0 times theorem prover too weak. 387962 trivial. 0 not checked. [2018-04-11 23:12:12,789 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:12:12,789 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:12:12,794 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:12:13,273 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:12:13,273 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:12:13,293 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:12:15,726 INFO L134 CoverageAnalysis]: Checked inductivity of 512265 backedges. 122301 proven. 2002 refuted. 0 times theorem prover too weak. 387962 trivial. 0 not checked. [2018-04-11 23:12:15,746 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:12:15,746 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56] total 83 [2018-04-11 23:12:15,747 INFO L442 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-04-11 23:12:15,747 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-04-11 23:12:15,748 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1594, Invalid=5212, Unknown=0, NotChecked=0, Total=6806 [2018-04-11 23:12:15,748 INFO L87 Difference]: Start difference. First operand 2774 states and 2780 transitions. Second operand 83 states. [2018-04-11 23:12:17,069 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:12:17,070 INFO L93 Difference]: Finished difference Result 2792 states and 2796 transitions. [2018-04-11 23:12:17,070 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 80 states. [2018-04-11 23:12:17,070 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 2746 [2018-04-11 23:12:17,071 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:12:17,075 INFO L225 Difference]: With dead ends: 2792 [2018-04-11 23:12:17,075 INFO L226 Difference]: Without dead ends: 2786 [2018-04-11 23:12:17,075 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2826 GetRequests, 2720 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4051 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=2619, Invalid=8937, Unknown=0, NotChecked=0, Total=11556 [2018-04-11 23:12:17,077 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2786 states. [2018-04-11 23:12:17,092 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2786 to 2774. [2018-04-11 23:12:17,092 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2774 states. [2018-04-11 23:12:17,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2774 states to 2774 states and 2778 transitions. [2018-04-11 23:12:17,096 INFO L78 Accepts]: Start accepts. Automaton has 2774 states and 2778 transitions. Word has length 2746 [2018-04-11 23:12:17,097 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:12:17,097 INFO L459 AbstractCegarLoop]: Abstraction has 2774 states and 2778 transitions. [2018-04-11 23:12:17,097 INFO L460 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-04-11 23:12:17,098 INFO L276 IsEmpty]: Start isEmpty. Operand 2774 states and 2778 transitions. [2018-04-11 23:12:17,129 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2753 [2018-04-11 23:12:17,129 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:12:17,129 INFO L355 BasicCegarLoop]: trace histogram [431, 405, 404, 404, 404, 404, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:12:17,129 INFO L408 AbstractCegarLoop]: === Iteration 78 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:12:17,129 INFO L82 PathProgramCache]: Analyzing trace with hash 1214299457, now seen corresponding path program 69 times [2018-04-11 23:12:17,129 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:12:17,130 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:12:17,130 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:12:17,130 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:12:17,130 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:12:17,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:12:17,358 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:12:27,162 INFO L134 CoverageAnalysis]: Checked inductivity of 514738 backedges. 63661 proven. 2187 refuted. 0 times theorem prover too weak. 448890 trivial. 0 not checked. [2018-04-11 23:12:27,162 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:12:27,197 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:12:27,203 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:12:28,243 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-04-11 23:12:28,244 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:12:28,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:12:29,980 INFO L134 CoverageAnalysis]: Checked inductivity of 514738 backedges. 63661 proven. 2187 refuted. 0 times theorem prover too weak. 448890 trivial. 0 not checked. [2018-04-11 23:12:30,004 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:12:30,005 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30] total 31 [2018-04-11 23:12:30,005 INFO L442 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-04-11 23:12:30,005 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-04-11 23:12:30,005 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=441, Invalid=551, Unknown=0, NotChecked=0, Total=992 [2018-04-11 23:12:30,006 INFO L87 Difference]: Start difference. First operand 2774 states and 2778 transitions. Second operand 32 states. [2018-04-11 23:12:30,425 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:12:30,426 INFO L93 Difference]: Finished difference Result 2795 states and 2800 transitions. [2018-04-11 23:12:30,426 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-04-11 23:12:30,426 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 2752 [2018-04-11 23:12:30,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:12:30,431 INFO L225 Difference]: With dead ends: 2795 [2018-04-11 23:12:30,431 INFO L226 Difference]: Without dead ends: 2795 [2018-04-11 23:12:30,431 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2807 GetRequests, 2751 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 453 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1221, Invalid=2085, Unknown=0, NotChecked=0, Total=3306 [2018-04-11 23:12:30,432 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2795 states. [2018-04-11 23:12:30,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2795 to 2780. [2018-04-11 23:12:30,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2780 states. [2018-04-11 23:12:30,446 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2780 states to 2780 states and 2785 transitions. [2018-04-11 23:12:30,446 INFO L78 Accepts]: Start accepts. Automaton has 2780 states and 2785 transitions. Word has length 2752 [2018-04-11 23:12:30,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:12:30,447 INFO L459 AbstractCegarLoop]: Abstraction has 2780 states and 2785 transitions. [2018-04-11 23:12:30,447 INFO L460 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-04-11 23:12:30,447 INFO L276 IsEmpty]: Start isEmpty. Operand 2780 states and 2785 transitions. [2018-04-11 23:12:30,486 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2759 [2018-04-11 23:12:30,486 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:12:30,487 INFO L355 BasicCegarLoop]: trace histogram [432, 406, 405, 405, 405, 405, 27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:12:30,487 INFO L408 AbstractCegarLoop]: === Iteration 79 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:12:30,487 INFO L82 PathProgramCache]: Analyzing trace with hash -1785828551, now seen corresponding path program 70 times [2018-04-11 23:12:30,487 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:12:30,487 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:12:30,488 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:12:30,488 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:12:30,488 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:12:30,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:12:30,667 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:12:47,791 INFO L134 CoverageAnalysis]: Checked inductivity of 517217 backedges. 68270 proven. 2137 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-04-11 23:12:47,792 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:12:47,792 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:12:47,797 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:12:48,124 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:12:48,124 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:12:48,140 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:12:50,972 INFO L134 CoverageAnalysis]: Checked inductivity of 517217 backedges. 68353 proven. 2054 refuted. 0 times theorem prover too weak. 446810 trivial. 0 not checked. [2018-04-11 23:12:51,000 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:12:51,001 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 59] total 90 [2018-04-11 23:12:51,001 INFO L442 AbstractCegarLoop]: Interpolant automaton has 90 states [2018-04-11 23:12:51,002 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 90 interpolants. [2018-04-11 23:12:51,002 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1831, Invalid=6179, Unknown=0, NotChecked=0, Total=8010 [2018-04-11 23:12:51,002 INFO L87 Difference]: Start difference. First operand 2780 states and 2785 transitions. Second operand 90 states. [2018-04-11 23:12:53,017 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:12:53,017 INFO L93 Difference]: Finished difference Result 2974 states and 2980 transitions. [2018-04-11 23:12:53,017 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-04-11 23:12:53,018 INFO L78 Accepts]: Start accepts. Automaton has 90 states. Word has length 2758 [2018-04-11 23:12:53,019 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:12:53,023 INFO L225 Difference]: With dead ends: 2974 [2018-04-11 23:12:53,023 INFO L226 Difference]: Without dead ends: 2974 [2018-04-11 23:12:53,024 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2872 GetRequests, 2729 SyntacticMatches, 0 SemanticMatches, 143 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3563 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=5238, Invalid=15642, Unknown=0, NotChecked=0, Total=20880 [2018-04-11 23:12:53,026 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2974 states. [2018-04-11 23:12:53,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2974 to 2960. [2018-04-11 23:12:53,039 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2960 states. [2018-04-11 23:12:53,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2960 states to 2960 states and 2966 transitions. [2018-04-11 23:12:53,041 INFO L78 Accepts]: Start accepts. Automaton has 2960 states and 2966 transitions. Word has length 2758 [2018-04-11 23:12:53,042 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:12:53,043 INFO L459 AbstractCegarLoop]: Abstraction has 2960 states and 2966 transitions. [2018-04-11 23:12:53,043 INFO L460 AbstractCegarLoop]: Interpolant automaton has 90 states. [2018-04-11 23:12:53,043 INFO L276 IsEmpty]: Start isEmpty. Operand 2960 states and 2966 transitions. [2018-04-11 23:12:53,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2933 [2018-04-11 23:12:53,075 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:12:53,075 INFO L355 BasicCegarLoop]: trace histogram [460, 433, 432, 432, 432, 432, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:12:53,075 INFO L408 AbstractCegarLoop]: === Iteration 80 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:12:53,075 INFO L82 PathProgramCache]: Analyzing trace with hash 684728257, now seen corresponding path program 71 times [2018-04-11 23:12:53,075 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:12:53,076 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:12:53,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:12:53,076 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:12:53,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:12:53,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:12:53,288 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:13:12,571 INFO L134 CoverageAnalysis]: Checked inductivity of 587601 backedges. 136253 proven. 2160 refuted. 0 times theorem prover too weak. 449188 trivial. 0 not checked. [2018-04-11 23:13:12,571 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:13:12,571 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:13:12,577 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:13:22,591 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-04-11 23:13:22,592 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:13:22,622 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:13:25,796 INFO L134 CoverageAnalysis]: Checked inductivity of 587601 backedges. 136869 proven. 22807 refuted. 0 times theorem prover too weak. 427925 trivial. 0 not checked. [2018-04-11 23:13:25,828 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:13:25,828 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 62] total 97 [2018-04-11 23:13:25,829 INFO L442 AbstractCegarLoop]: Interpolant automaton has 97 states [2018-04-11 23:13:25,829 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 97 interpolants. [2018-04-11 23:13:25,829 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1776, Invalid=7536, Unknown=0, NotChecked=0, Total=9312 [2018-04-11 23:13:25,829 INFO L87 Difference]: Start difference. First operand 2960 states and 2966 transitions. Second operand 97 states. [2018-04-11 23:13:27,723 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:13:27,723 INFO L93 Difference]: Finished difference Result 2978 states and 2982 transitions. [2018-04-11 23:13:27,759 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 94 states. [2018-04-11 23:13:27,759 INFO L78 Accepts]: Start accepts. Automaton has 97 states. Word has length 2932 [2018-04-11 23:13:27,761 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:13:27,765 INFO L225 Difference]: With dead ends: 2978 [2018-04-11 23:13:27,765 INFO L226 Difference]: Without dead ends: 2972 [2018-04-11 23:13:27,767 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3054 GetRequests, 2895 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8558 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=5077, Invalid=20683, Unknown=0, NotChecked=0, Total=25760 [2018-04-11 23:13:27,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2972 states. [2018-04-11 23:13:27,781 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2972 to 2960. [2018-04-11 23:13:27,781 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2960 states. [2018-04-11 23:13:27,783 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2960 states to 2960 states and 2964 transitions. [2018-04-11 23:13:27,783 INFO L78 Accepts]: Start accepts. Automaton has 2960 states and 2964 transitions. Word has length 2932 [2018-04-11 23:13:27,784 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:13:27,784 INFO L459 AbstractCegarLoop]: Abstraction has 2960 states and 2964 transitions. [2018-04-11 23:13:27,784 INFO L460 AbstractCegarLoop]: Interpolant automaton has 97 states. [2018-04-11 23:13:27,784 INFO L276 IsEmpty]: Start isEmpty. Operand 2960 states and 2964 transitions. [2018-04-11 23:13:27,816 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2939 [2018-04-11 23:13:27,816 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:13:27,816 INFO L355 BasicCegarLoop]: trace histogram [461, 434, 433, 433, 433, 433, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:13:27,816 INFO L408 AbstractCegarLoop]: === Iteration 81 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:13:27,816 INFO L82 PathProgramCache]: Analyzing trace with hash 305512889, now seen corresponding path program 72 times [2018-04-11 23:13:27,817 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:13:27,817 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:13:27,817 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:13:27,817 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:13:27,817 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:13:27,982 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:13:27,984 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:13:39,522 INFO L134 CoverageAnalysis]: Checked inductivity of 590250 backedges. 70821 proven. 2352 refuted. 0 times theorem prover too weak. 517077 trivial. 0 not checked. [2018-04-11 23:13:39,523 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:13:39,523 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:13:39,529 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:13:44,993 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 57 check-sat command(s) [2018-04-11 23:13:44,993 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:13:45,016 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:13:46,891 INFO L134 CoverageAnalysis]: Checked inductivity of 590250 backedges. 70821 proven. 2352 refuted. 0 times theorem prover too weak. 517077 trivial. 0 not checked. [2018-04-11 23:13:46,925 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:13:46,925 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31] total 37 [2018-04-11 23:13:46,926 INFO L442 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-04-11 23:13:46,926 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-04-11 23:13:46,926 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=500, Invalid=906, Unknown=0, NotChecked=0, Total=1406 [2018-04-11 23:13:46,926 INFO L87 Difference]: Start difference. First operand 2960 states and 2964 transitions. Second operand 38 states. [2018-04-11 23:13:47,541 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:13:47,541 INFO L93 Difference]: Finished difference Result 2981 states and 2986 transitions. [2018-04-11 23:13:47,542 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-04-11 23:13:47,542 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 2938 [2018-04-11 23:13:47,543 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:13:47,547 INFO L225 Difference]: With dead ends: 2981 [2018-04-11 23:13:47,547 INFO L226 Difference]: Without dead ends: 2981 [2018-04-11 23:13:47,548 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 2995 GetRequests, 2932 SyntacticMatches, 0 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 626 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=1385, Invalid=2775, Unknown=0, NotChecked=0, Total=4160 [2018-04-11 23:13:47,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2981 states. [2018-04-11 23:13:47,562 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2981 to 2966. [2018-04-11 23:13:47,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 2966 states. [2018-04-11 23:13:47,565 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2966 states to 2966 states and 2971 transitions. [2018-04-11 23:13:47,565 INFO L78 Accepts]: Start accepts. Automaton has 2966 states and 2971 transitions. Word has length 2938 [2018-04-11 23:13:47,566 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:13:47,566 INFO L459 AbstractCegarLoop]: Abstraction has 2966 states and 2971 transitions. [2018-04-11 23:13:47,566 INFO L460 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-04-11 23:13:47,567 INFO L276 IsEmpty]: Start isEmpty. Operand 2966 states and 2971 transitions. [2018-04-11 23:13:47,599 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 2945 [2018-04-11 23:13:47,599 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:13:47,599 INFO L355 BasicCegarLoop]: trace histogram [462, 435, 434, 434, 434, 434, 28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:13:47,600 INFO L408 AbstractCegarLoop]: === Iteration 82 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:13:47,600 INFO L82 PathProgramCache]: Analyzing trace with hash 1350317489, now seen corresponding path program 73 times [2018-04-11 23:13:47,600 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:13:47,600 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:13:47,601 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:13:47,601 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:13:47,601 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:13:47,883 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:13:47,891 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:14:08,721 INFO L134 CoverageAnalysis]: Checked inductivity of 592905 backedges. 75769 proven. 2300 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-04-11 23:14:08,721 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:14:08,722 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:14:08,728 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:14:09,231 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:14:09,265 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:14:12,283 INFO L134 CoverageAnalysis]: Checked inductivity of 592905 backedges. 75855 proven. 2214 refuted. 0 times theorem prover too weak. 514836 trivial. 0 not checked. [2018-04-11 23:14:12,305 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:14:12,306 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 61] total 93 [2018-04-11 23:14:12,306 INFO L442 AbstractCegarLoop]: Interpolant automaton has 93 states [2018-04-11 23:14:12,307 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 93 interpolants. [2018-04-11 23:14:12,307 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1954, Invalid=6602, Unknown=0, NotChecked=0, Total=8556 [2018-04-11 23:14:12,307 INFO L87 Difference]: Start difference. First operand 2966 states and 2971 transitions. Second operand 93 states. [2018-04-11 23:14:14,465 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:14:14,465 INFO L93 Difference]: Finished difference Result 3166 states and 3172 transitions. [2018-04-11 23:14:14,465 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-04-11 23:14:14,465 INFO L78 Accepts]: Start accepts. Automaton has 93 states. Word has length 2944 [2018-04-11 23:14:14,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:14:14,471 INFO L225 Difference]: With dead ends: 3166 [2018-04-11 23:14:14,471 INFO L226 Difference]: Without dead ends: 3166 [2018-04-11 23:14:14,474 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3062 GetRequests, 2914 SyntacticMatches, 0 SemanticMatches, 148 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3821 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=5599, Invalid=16751, Unknown=0, NotChecked=0, Total=22350 [2018-04-11 23:14:14,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3166 states. [2018-04-11 23:14:14,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3166 to 3152. [2018-04-11 23:14:14,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3152 states. [2018-04-11 23:14:14,492 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3152 states to 3152 states and 3158 transitions. [2018-04-11 23:14:14,492 INFO L78 Accepts]: Start accepts. Automaton has 3152 states and 3158 transitions. Word has length 2944 [2018-04-11 23:14:14,493 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:14:14,493 INFO L459 AbstractCegarLoop]: Abstraction has 3152 states and 3158 transitions. [2018-04-11 23:14:14,493 INFO L460 AbstractCegarLoop]: Interpolant automaton has 93 states. [2018-04-11 23:14:14,493 INFO L276 IsEmpty]: Start isEmpty. Operand 3152 states and 3158 transitions. [2018-04-11 23:14:14,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3125 [2018-04-11 23:14:14,529 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:14:14,529 INFO L355 BasicCegarLoop]: trace histogram [491, 463, 462, 462, 462, 462, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:14:14,529 INFO L408 AbstractCegarLoop]: === Iteration 83 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:14:14,529 INFO L82 PathProgramCache]: Analyzing trace with hash -1842713551, now seen corresponding path program 74 times [2018-04-11 23:14:14,530 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:14:14,530 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:14:14,530 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:14:14,530 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:14:14,530 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:14:14,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:14:14,726 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:14:36,908 INFO L134 CoverageAnalysis]: Checked inductivity of 670936 backedges. 151226 proven. 2324 refuted. 0 times theorem prover too weak. 517386 trivial. 0 not checked. [2018-04-11 23:14:36,908 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:14:36,908 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:14:36,913 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:14:37,356 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:14:37,357 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:14:37,381 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:14:40,358 INFO L134 CoverageAnalysis]: Checked inductivity of 670936 backedges. 151226 proven. 2324 refuted. 0 times theorem prover too weak. 517386 trivial. 0 not checked. [2018-04-11 23:14:40,386 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:14:40,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60] total 89 [2018-04-11 23:14:40,387 INFO L442 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-04-11 23:14:40,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-04-11 23:14:40,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1828, Invalid=6004, Unknown=0, NotChecked=0, Total=7832 [2018-04-11 23:14:40,388 INFO L87 Difference]: Start difference. First operand 3152 states and 3158 transitions. Second operand 89 states. [2018-04-11 23:14:42,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:14:42,016 INFO L93 Difference]: Finished difference Result 3170 states and 3174 transitions. [2018-04-11 23:14:42,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 86 states. [2018-04-11 23:14:42,017 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 3124 [2018-04-11 23:14:42,018 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:14:42,022 INFO L225 Difference]: With dead ends: 3170 [2018-04-11 23:14:42,022 INFO L226 Difference]: Without dead ends: 3164 [2018-04-11 23:14:42,023 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3210 GetRequests, 3096 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4699 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=3016, Invalid=10324, Unknown=0, NotChecked=0, Total=13340 [2018-04-11 23:14:42,024 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3164 states. [2018-04-11 23:14:42,040 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3164 to 3152. [2018-04-11 23:14:42,041 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3152 states. [2018-04-11 23:14:42,043 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3152 states to 3152 states and 3156 transitions. [2018-04-11 23:14:42,043 INFO L78 Accepts]: Start accepts. Automaton has 3152 states and 3156 transitions. Word has length 3124 [2018-04-11 23:14:42,044 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:14:42,044 INFO L459 AbstractCegarLoop]: Abstraction has 3152 states and 3156 transitions. [2018-04-11 23:14:42,044 INFO L460 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-04-11 23:14:42,044 INFO L276 IsEmpty]: Start isEmpty. Operand 3152 states and 3156 transitions. [2018-04-11 23:14:42,080 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3131 [2018-04-11 23:14:42,080 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:14:42,080 INFO L355 BasicCegarLoop]: trace histogram [492, 464, 463, 463, 463, 463, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:14:42,080 INFO L408 AbstractCegarLoop]: === Iteration 84 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:14:42,081 INFO L82 PathProgramCache]: Analyzing trace with hash -1959658967, now seen corresponding path program 75 times [2018-04-11 23:14:42,081 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:14:42,081 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:14:42,081 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:14:42,081 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:14:42,081 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:14:42,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:14:42,371 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:14:55,485 INFO L134 CoverageAnalysis]: Checked inductivity of 673767 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 592746 trivial. 0 not checked. [2018-04-11 23:14:55,486 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:14:55,486 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:14:55,492 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:14:57,276 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-04-11 23:14:57,276 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:14:57,297 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:14:59,400 INFO L134 CoverageAnalysis]: Checked inductivity of 673767 backedges. 78498 proven. 2523 refuted. 0 times theorem prover too weak. 592746 trivial. 0 not checked. [2018-04-11 23:14:59,422 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:14:59,422 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32] total 33 [2018-04-11 23:14:59,423 INFO L442 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-04-11 23:14:59,423 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-04-11 23:14:59,423 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=502, Invalid=620, Unknown=0, NotChecked=0, Total=1122 [2018-04-11 23:14:59,423 INFO L87 Difference]: Start difference. First operand 3152 states and 3156 transitions. Second operand 34 states. [2018-04-11 23:14:59,907 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:14:59,908 INFO L93 Difference]: Finished difference Result 3173 states and 3178 transitions. [2018-04-11 23:14:59,908 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-11 23:14:59,908 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 3130 [2018-04-11 23:14:59,910 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:14:59,915 INFO L225 Difference]: With dead ends: 3173 [2018-04-11 23:14:59,916 INFO L226 Difference]: Without dead ends: 3173 [2018-04-11 23:14:59,916 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3189 GetRequests, 3129 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 516 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=1398, Invalid=2384, Unknown=0, NotChecked=0, Total=3782 [2018-04-11 23:14:59,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3173 states. [2018-04-11 23:14:59,940 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3173 to 3158. [2018-04-11 23:14:59,941 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3158 states. [2018-04-11 23:14:59,943 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3158 states to 3158 states and 3163 transitions. [2018-04-11 23:14:59,943 INFO L78 Accepts]: Start accepts. Automaton has 3158 states and 3163 transitions. Word has length 3130 [2018-04-11 23:14:59,944 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:14:59,945 INFO L459 AbstractCegarLoop]: Abstraction has 3158 states and 3163 transitions. [2018-04-11 23:14:59,945 INFO L460 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-04-11 23:14:59,945 INFO L276 IsEmpty]: Start isEmpty. Operand 3158 states and 3163 transitions. [2018-04-11 23:14:59,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3137 [2018-04-11 23:14:59,981 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:14:59,982 INFO L355 BasicCegarLoop]: trace histogram [493, 465, 464, 464, 464, 464, 29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:14:59,982 INFO L408 AbstractCegarLoop]: === Iteration 85 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:14:59,982 INFO L82 PathProgramCache]: Analyzing trace with hash -1641522655, now seen corresponding path program 76 times [2018-04-11 23:14:59,982 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:14:59,982 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:14:59,983 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:14:59,983 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:14:59,983 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:15:00,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:15:00,264 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:15:23,536 INFO L134 CoverageAnalysis]: Checked inductivity of 676604 backedges. 83797 proven. 2469 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-04-11 23:15:23,536 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:15:23,536 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:15:23,541 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:15:24,003 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:15:24,003 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:15:24,022 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:15:27,438 INFO L134 CoverageAnalysis]: Checked inductivity of 676604 backedges. 83886 proven. 2380 refuted. 0 times theorem prover too weak. 590338 trivial. 0 not checked. [2018-04-11 23:15:27,478 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:15:27,478 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 63] total 96 [2018-04-11 23:15:27,479 INFO L442 AbstractCegarLoop]: Interpolant automaton has 96 states [2018-04-11 23:15:27,479 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 96 interpolants. [2018-04-11 23:15:27,479 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2081, Invalid=7039, Unknown=0, NotChecked=0, Total=9120 [2018-04-11 23:15:27,480 INFO L87 Difference]: Start difference. First operand 3158 states and 3163 transitions. Second operand 96 states. [2018-04-11 23:15:29,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:15:29,812 INFO L93 Difference]: Finished difference Result 3364 states and 3370 transitions. [2018-04-11 23:15:29,812 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-04-11 23:15:29,812 INFO L78 Accepts]: Start accepts. Automaton has 96 states. Word has length 3136 [2018-04-11 23:15:29,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:15:29,817 INFO L225 Difference]: With dead ends: 3364 [2018-04-11 23:15:29,818 INFO L226 Difference]: Without dead ends: 3364 [2018-04-11 23:15:29,819 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3258 GetRequests, 3105 SyntacticMatches, 0 SemanticMatches, 153 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4088 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=5972, Invalid=17898, Unknown=0, NotChecked=0, Total=23870 [2018-04-11 23:15:29,820 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3364 states. [2018-04-11 23:15:29,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3364 to 3350. [2018-04-11 23:15:29,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3350 states. [2018-04-11 23:15:29,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3350 states to 3350 states and 3356 transitions. [2018-04-11 23:15:29,841 INFO L78 Accepts]: Start accepts. Automaton has 3350 states and 3356 transitions. Word has length 3136 [2018-04-11 23:15:29,843 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:15:29,843 INFO L459 AbstractCegarLoop]: Abstraction has 3350 states and 3356 transitions. [2018-04-11 23:15:29,843 INFO L460 AbstractCegarLoop]: Interpolant automaton has 96 states. [2018-04-11 23:15:29,844 INFO L276 IsEmpty]: Start isEmpty. Operand 3350 states and 3356 transitions. [2018-04-11 23:15:29,924 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3323 [2018-04-11 23:15:29,924 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:15:29,924 INFO L355 BasicCegarLoop]: trace histogram [523, 494, 493, 493, 493, 493, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:15:29,924 INFO L408 AbstractCegarLoop]: === Iteration 86 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:15:29,925 INFO L82 PathProgramCache]: Analyzing trace with hash 398384793, now seen corresponding path program 77 times [2018-04-11 23:15:29,925 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:15:29,925 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:15:29,926 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:15:29,926 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:15:29,926 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:15:30,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:15:30,134 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:15:55,642 INFO L134 CoverageAnalysis]: Checked inductivity of 762816 backedges. 167256 proven. 2494 refuted. 0 times theorem prover too weak. 593066 trivial. 0 not checked. [2018-04-11 23:15:55,642 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:15:55,642 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:15:55,648 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-04-11 23:16:10,361 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 74 check-sat command(s) [2018-04-11 23:16:10,361 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:16:10,402 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:16:13,775 INFO L134 CoverageAnalysis]: Checked inductivity of 762816 backedges. 166655 proven. 14656 refuted. 0 times theorem prover too weak. 581505 trivial. 0 not checked. [2018-04-11 23:16:13,809 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:16:13,810 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 66] total 98 [2018-04-11 23:16:13,810 INFO L442 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-04-11 23:16:13,811 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-04-11 23:16:13,811 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1973, Invalid=7533, Unknown=0, NotChecked=0, Total=9506 [2018-04-11 23:16:13,811 INFO L87 Difference]: Start difference. First operand 3350 states and 3356 transitions. Second operand 98 states. [2018-04-11 23:16:15,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:16:15,764 INFO L93 Difference]: Finished difference Result 3368 states and 3372 transitions. [2018-04-11 23:16:15,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-04-11 23:16:15,764 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 3322 [2018-04-11 23:16:15,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:16:15,767 INFO L225 Difference]: With dead ends: 3368 [2018-04-11 23:16:15,768 INFO L226 Difference]: Without dead ends: 3362 [2018-04-11 23:16:15,769 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3447 GetRequests, 3288 SyntacticMatches, 0 SemanticMatches, 159 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8856 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=5542, Invalid=20218, Unknown=0, NotChecked=0, Total=25760 [2018-04-11 23:16:15,769 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3362 states. [2018-04-11 23:16:15,779 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3362 to 3350. [2018-04-11 23:16:15,779 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3350 states. [2018-04-11 23:16:15,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3350 states to 3350 states and 3354 transitions. [2018-04-11 23:16:15,781 INFO L78 Accepts]: Start accepts. Automaton has 3350 states and 3354 transitions. Word has length 3322 [2018-04-11 23:16:15,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:16:15,782 INFO L459 AbstractCegarLoop]: Abstraction has 3350 states and 3354 transitions. [2018-04-11 23:16:15,782 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-04-11 23:16:15,782 INFO L276 IsEmpty]: Start isEmpty. Operand 3350 states and 3354 transitions. [2018-04-11 23:16:15,817 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3329 [2018-04-11 23:16:15,817 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:16:15,818 INFO L355 BasicCegarLoop]: trace histogram [524, 495, 494, 494, 494, 494, 30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:16:15,818 INFO L408 AbstractCegarLoop]: === Iteration 87 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:16:15,818 INFO L82 PathProgramCache]: Analyzing trace with hash 1908539025, now seen corresponding path program 78 times [2018-04-11 23:16:15,818 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:16:15,818 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:16:15,819 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:16:15,819 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:16:15,819 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:16:16,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:16:16,016 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:16:30,501 INFO L134 CoverageAnalysis]: Checked inductivity of 765835 backedges. 86710 proven. 2700 refuted. 0 times theorem prover too weak. 676425 trivial. 0 not checked. [2018-04-11 23:16:30,502 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:16:30,502 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:16:30,507 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-04-11 23:16:35,444 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 59 check-sat command(s) [2018-04-11 23:16:35,444 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:16:35,478 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:16:38,472 INFO L134 CoverageAnalysis]: Checked inductivity of 765835 backedges. 86886 proven. 2582 refuted. 0 times theorem prover too weak. 676367 trivial. 0 not checked. [2018-04-11 23:16:38,495 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:16:38,496 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 36] total 68 [2018-04-11 23:16:38,496 INFO L442 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-04-11 23:16:38,497 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-04-11 23:16:38,497 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=983, Invalid=3709, Unknown=0, NotChecked=0, Total=4692 [2018-04-11 23:16:38,497 INFO L87 Difference]: Start difference. First operand 3350 states and 3354 transitions. Second operand 69 states. [2018-04-11 23:16:40,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:16:40,656 INFO L93 Difference]: Finished difference Result 3578 states and 3585 transitions. [2018-04-11 23:16:40,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 98 states. [2018-04-11 23:16:40,656 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 3328 [2018-04-11 23:16:40,657 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:16:40,660 INFO L225 Difference]: With dead ends: 3578 [2018-04-11 23:16:40,660 INFO L226 Difference]: Without dead ends: 3578 [2018-04-11 23:16:40,661 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3423 GetRequests, 3293 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3300 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3599, Invalid=13693, Unknown=0, NotChecked=0, Total=17292 [2018-04-11 23:16:40,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3578 states. [2018-04-11 23:16:40,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3578 to 3548. [2018-04-11 23:16:40,672 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3548 states. [2018-04-11 23:16:40,674 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3548 states to 3548 states and 3554 transitions. [2018-04-11 23:16:40,674 INFO L78 Accepts]: Start accepts. Automaton has 3548 states and 3554 transitions. Word has length 3328 [2018-04-11 23:16:40,675 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:16:40,675 INFO L459 AbstractCegarLoop]: Abstraction has 3548 states and 3554 transitions. [2018-04-11 23:16:40,675 INFO L460 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-04-11 23:16:40,675 INFO L276 IsEmpty]: Start isEmpty. Operand 3548 states and 3554 transitions. [2018-04-11 23:16:40,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3527 [2018-04-11 23:16:40,716 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:16:40,716 INFO L355 BasicCegarLoop]: trace histogram [556, 526, 525, 525, 525, 525, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:16:40,716 INFO L408 AbstractCegarLoop]: === Iteration 88 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:16:40,717 INFO L82 PathProgramCache]: Analyzing trace with hash 1216577785, now seen corresponding path program 79 times [2018-04-11 23:16:40,717 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:16:40,717 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:16:40,717 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:16:40,717 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:16:40,717 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:16:40,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:16:40,983 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:17:09,546 INFO L134 CoverageAnalysis]: Checked inductivity of 863805 backedges. 184379 proven. 2670 refuted. 0 times theorem prover too weak. 676756 trivial. 0 not checked. [2018-04-11 23:17:09,546 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:17:09,546 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:17:09,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:17:10,069 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:17:10,097 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:17:13,739 INFO L134 CoverageAnalysis]: Checked inductivity of 863805 backedges. 184379 proven. 2670 refuted. 0 times theorem prover too weak. 676756 trivial. 0 not checked. [2018-04-11 23:17:13,761 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:17:13,761 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64] total 95 [2018-04-11 23:17:13,762 INFO L442 AbstractCegarLoop]: Interpolant automaton has 95 states [2018-04-11 23:17:13,762 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 95 interpolants. [2018-04-11 23:17:13,763 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2078, Invalid=6852, Unknown=0, NotChecked=0, Total=8930 [2018-04-11 23:17:13,763 INFO L87 Difference]: Start difference. First operand 3548 states and 3554 transitions. Second operand 95 states. [2018-04-11 23:17:15,466 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:17:15,467 INFO L93 Difference]: Finished difference Result 3576 states and 3581 transitions. [2018-04-11 23:17:15,467 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 92 states. [2018-04-11 23:17:15,467 INFO L78 Accepts]: Start accepts. Automaton has 95 states. Word has length 3526 [2018-04-11 23:17:15,468 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:17:15,470 INFO L225 Difference]: With dead ends: 3576 [2018-04-11 23:17:15,470 INFO L226 Difference]: Without dead ends: 3570 [2018-04-11 23:17:15,471 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3618 GetRequests, 3496 SyntacticMatches, 0 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5395 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=3441, Invalid=11811, Unknown=0, NotChecked=0, Total=15252 [2018-04-11 23:17:15,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3570 states. [2018-04-11 23:17:15,488 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3570 to 3554. [2018-04-11 23:17:15,488 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3554 states. [2018-04-11 23:17:15,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3554 states to 3554 states and 3559 transitions. [2018-04-11 23:17:15,490 INFO L78 Accepts]: Start accepts. Automaton has 3554 states and 3559 transitions. Word has length 3526 [2018-04-11 23:17:15,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:17:15,491 INFO L459 AbstractCegarLoop]: Abstraction has 3554 states and 3559 transitions. [2018-04-11 23:17:15,491 INFO L460 AbstractCegarLoop]: Interpolant automaton has 95 states. [2018-04-11 23:17:15,491 INFO L276 IsEmpty]: Start isEmpty. Operand 3554 states and 3559 transitions. [2018-04-11 23:17:15,531 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3533 [2018-04-11 23:17:15,531 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:17:15,531 INFO L355 BasicCegarLoop]: trace histogram [557, 527, 526, 526, 526, 526, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:17:15,531 INFO L408 AbstractCegarLoop]: === Iteration 89 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:17:15,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1387026673, now seen corresponding path program 80 times [2018-04-11 23:17:15,532 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:17:15,532 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:17:15,532 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:17:15,533 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-11 23:17:15,533 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:17:15,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:17:15,740 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:17:32,235 INFO L134 CoverageAnalysis]: Checked inductivity of 867018 backedges. 95475 proven. 2883 refuted. 0 times theorem prover too weak. 768660 trivial. 0 not checked. [2018-04-11 23:17:32,235 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:17:32,235 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:17:32,240 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-11 23:17:32,773 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-04-11 23:17:32,773 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:17:32,801 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:17:35,648 INFO L134 CoverageAnalysis]: Checked inductivity of 867018 backedges. 95475 proven. 2883 refuted. 0 times theorem prover too weak. 768660 trivial. 0 not checked. [2018-04-11 23:17:35,668 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:17:35,669 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33] total 65 [2018-04-11 23:17:35,669 INFO L442 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-04-11 23:17:35,669 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-04-11 23:17:35,670 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1122, Invalid=3168, Unknown=0, NotChecked=0, Total=4290 [2018-04-11 23:17:35,670 INFO L87 Difference]: Start difference. First operand 3554 states and 3559 transitions. Second operand 66 states. [2018-04-11 23:17:36,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:17:36,785 INFO L93 Difference]: Finished difference Result 3588 states and 3595 transitions. [2018-04-11 23:17:36,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-04-11 23:17:36,785 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 3532 [2018-04-11 23:17:36,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:17:36,789 INFO L225 Difference]: With dead ends: 3588 [2018-04-11 23:17:36,789 INFO L226 Difference]: Without dead ends: 3588 [2018-04-11 23:17:36,789 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3565 GetRequests, 3501 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1923 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=1122, Invalid=3168, Unknown=0, NotChecked=0, Total=4290 [2018-04-11 23:17:36,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3588 states. [2018-04-11 23:17:36,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3588 to 3560. [2018-04-11 23:17:36,801 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3560 states. [2018-04-11 23:17:36,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3560 states to 3560 states and 3566 transitions. [2018-04-11 23:17:36,804 INFO L78 Accepts]: Start accepts. Automaton has 3560 states and 3566 transitions. Word has length 3532 [2018-04-11 23:17:36,806 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:17:36,806 INFO L459 AbstractCegarLoop]: Abstraction has 3560 states and 3566 transitions. [2018-04-11 23:17:36,806 INFO L460 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-04-11 23:17:36,806 INFO L276 IsEmpty]: Start isEmpty. Operand 3560 states and 3566 transitions. [2018-04-11 23:17:36,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3539 [2018-04-11 23:17:36,848 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:17:36,848 INFO L355 BasicCegarLoop]: trace histogram [558, 528, 527, 527, 527, 527, 31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:17:36,848 INFO L408 AbstractCegarLoop]: === Iteration 90 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:17:36,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1069712105, now seen corresponding path program 81 times [2018-04-11 23:17:36,848 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:17:36,848 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:17:36,849 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:17:36,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:17:36,849 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:17:37,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:17:37,058 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:18:06,505 INFO L134 CoverageAnalysis]: Checked inductivity of 870237 backedges. 101512 proven. 2825 refuted. 0 times theorem prover too weak. 765900 trivial. 0 not checked. [2018-04-11 23:18:06,505 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:18:06,505 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:18:06,510 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-04-11 23:18:08,120 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-04-11 23:18:08,120 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:18:08,142 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:18:12,084 INFO L134 CoverageAnalysis]: Checked inductivity of 870237 backedges. 173928 proven. 14331 refuted. 0 times theorem prover too weak. 681978 trivial. 0 not checked. [2018-04-11 23:18:12,105 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:18:12,106 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 41] total 103 [2018-04-11 23:18:12,106 INFO L442 AbstractCegarLoop]: Interpolant automaton has 103 states [2018-04-11 23:18:12,106 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 103 interpolants. [2018-04-11 23:18:12,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1668, Invalid=8838, Unknown=0, NotChecked=0, Total=10506 [2018-04-11 23:18:12,107 INFO L87 Difference]: Start difference. First operand 3560 states and 3566 transitions. Second operand 103 states. [2018-04-11 23:18:16,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:18:16,493 INFO L93 Difference]: Finished difference Result 3787 states and 3794 transitions. [2018-04-11 23:18:16,494 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 160 states. [2018-04-11 23:18:16,494 INFO L78 Accepts]: Start accepts. Automaton has 103 states. Word has length 3538 [2018-04-11 23:18:16,495 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:18:16,497 INFO L225 Difference]: With dead ends: 3787 [2018-04-11 23:18:16,497 INFO L226 Difference]: Without dead ends: 3787 [2018-04-11 23:18:16,499 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3698 GetRequests, 3504 SyntacticMatches, 0 SemanticMatches, 194 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8607 ImplicationChecksByTransitivity, 4.3s TimeCoverageRelationStatistics Valid=7299, Invalid=30921, Unknown=0, NotChecked=0, Total=38220 [2018-04-11 23:18:16,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3787 states. [2018-04-11 23:18:16,510 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3787 to 3770. [2018-04-11 23:18:16,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3770 states. [2018-04-11 23:18:16,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3770 states to 3770 states and 3777 transitions. [2018-04-11 23:18:16,512 INFO L78 Accepts]: Start accepts. Automaton has 3770 states and 3777 transitions. Word has length 3538 [2018-04-11 23:18:16,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:18:16,513 INFO L459 AbstractCegarLoop]: Abstraction has 3770 states and 3777 transitions. [2018-04-11 23:18:16,513 INFO L460 AbstractCegarLoop]: Interpolant automaton has 103 states. [2018-04-11 23:18:16,513 INFO L276 IsEmpty]: Start isEmpty. Operand 3770 states and 3777 transitions. [2018-04-11 23:18:16,557 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3737 [2018-04-11 23:18:16,557 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:18:16,557 INFO L355 BasicCegarLoop]: trace histogram [590, 559, 558, 558, 558, 558, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:18:16,557 INFO L408 AbstractCegarLoop]: === Iteration 91 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:18:16,557 INFO L82 PathProgramCache]: Analyzing trace with hash 832196433, now seen corresponding path program 82 times [2018-04-11 23:18:16,557 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:18:16,557 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:18:16,558 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:18:16,558 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:18:16,558 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:18:16,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-11 23:18:16,843 WARN L137 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-11 23:18:49,270 INFO L134 CoverageAnalysis]: Checked inductivity of 974485 backedges. 202631 proven. 2852 refuted. 0 times theorem prover too weak. 769002 trivial. 0 not checked. [2018-04-11 23:18:49,270 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-11 23:18:49,270 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-11 23:18:49,275 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-04-11 23:18:49,743 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-04-11 23:18:49,743 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-11 23:18:49,768 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-11 23:18:53,886 INFO L134 CoverageAnalysis]: Checked inductivity of 974485 backedges. 202631 proven. 2852 refuted. 0 times theorem prover too weak. 769002 trivial. 0 not checked. [2018-04-11 23:18:53,908 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-11 23:18:53,908 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66] total 98 [2018-04-11 23:18:53,909 INFO L442 AbstractCegarLoop]: Interpolant automaton has 98 states [2018-04-11 23:18:53,909 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 98 interpolants. [2018-04-11 23:18:53,909 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2209, Invalid=7297, Unknown=0, NotChecked=0, Total=9506 [2018-04-11 23:18:53,909 INFO L87 Difference]: Start difference. First operand 3770 states and 3777 transitions. Second operand 98 states. [2018-04-11 23:18:55,577 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-11 23:18:55,578 INFO L93 Difference]: Finished difference Result 3791 states and 3796 transitions. [2018-04-11 23:18:55,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 95 states. [2018-04-11 23:18:55,578 INFO L78 Accepts]: Start accepts. Automaton has 98 states. Word has length 3736 [2018-04-11 23:18:55,579 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-11 23:18:55,581 INFO L225 Difference]: With dead ends: 3791 [2018-04-11 23:18:55,582 INFO L226 Difference]: Without dead ends: 3785 [2018-04-11 23:18:55,582 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3831 GetRequests, 3705 SyntacticMatches, 0 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5761 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=3664, Invalid=12592, Unknown=0, NotChecked=0, Total=16256 [2018-04-11 23:18:55,583 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3785 states. [2018-04-11 23:18:55,593 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3785 to 3770. [2018-04-11 23:18:55,594 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 3770 states. [2018-04-11 23:18:55,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3770 states to 3770 states and 3775 transitions. [2018-04-11 23:18:55,595 INFO L78 Accepts]: Start accepts. Automaton has 3770 states and 3775 transitions. Word has length 3736 [2018-04-11 23:18:55,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-11 23:18:55,596 INFO L459 AbstractCegarLoop]: Abstraction has 3770 states and 3775 transitions. [2018-04-11 23:18:55,596 INFO L460 AbstractCegarLoop]: Interpolant automaton has 98 states. [2018-04-11 23:18:55,596 INFO L276 IsEmpty]: Start isEmpty. Operand 3770 states and 3775 transitions. [2018-04-11 23:18:55,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 3743 [2018-04-11 23:18:55,640 INFO L347 BasicCegarLoop]: Found error trace [2018-04-11 23:18:55,640 INFO L355 BasicCegarLoop]: trace histogram [591, 560, 559, 559, 559, 559, 32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-11 23:18:55,640 INFO L408 AbstractCegarLoop]: === Iteration 92 === [mainErr1AssertViolationARRAY_INDEX, mainErr2EnsuresViolationMEMORY_LEAK, mainErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr2RequiresViolation, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr0AssertViolationARRAY_INDEX, __U_MULTI_fArraysWithLenghtAtDeclaration_false_valid_deref_write_c__fooErr1RequiresViolation]=== [2018-04-11 23:18:55,641 INFO L82 PathProgramCache]: Analyzing trace with hash 1353057609, now seen corresponding path program 83 times [2018-04-11 23:18:55,641 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-11 23:18:55,641 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-11 23:18:55,641 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:18:55,641 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-11 23:18:55,641 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-11 23:18:56,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-11 23:18:57,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-04-11 23:18:57,939 INFO L421 BasicCegarLoop]: Counterexample might be feasible [2018-04-11 23:18:58,380 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 11.04 11:18:58 BoogieIcfgContainer [2018-04-11 23:18:58,380 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-11 23:18:58,381 INFO L168 Benchmark]: Toolchain (without parser) took 761801.83 ms. Allocated memory was 319.8 MB in the beginning and 2.6 GB in the end (delta: 2.2 GB). Free memory was 267.6 MB in the beginning and 815.5 MB in the end (delta: -548.0 MB). Peak memory consumption was 1.7 GB. Max. memory is 5.3 GB. [2018-04-11 23:18:58,383 INFO L168 Benchmark]: CDTParser took 0.14 ms. Allocated memory is still 319.8 MB. Free memory is still 290.8 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-11 23:18:58,383 INFO L168 Benchmark]: CACSL2BoogieTranslator took 160.15 ms. Allocated memory is still 319.8 MB. Free memory was 267.6 MB in the beginning and 256.9 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. [2018-04-11 23:18:58,383 INFO L168 Benchmark]: Boogie Preprocessor took 27.50 ms. Allocated memory is still 319.8 MB. Free memory was 256.9 MB in the beginning and 255.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. [2018-04-11 23:18:58,384 INFO L168 Benchmark]: RCFGBuilder took 293.76 ms. Allocated memory was 319.8 MB in the beginning and 403.2 MB in the end (delta: 83.4 MB). Free memory was 255.6 MB in the beginning and 367.6 MB in the end (delta: -112.0 MB). Peak memory consumption was 34.7 MB. Max. memory is 5.3 GB. [2018-04-11 23:18:58,384 INFO L168 Benchmark]: TraceAbstraction took 761317.57 ms. Allocated memory was 403.2 MB in the beginning and 2.6 GB in the end (delta: 2.2 GB). Free memory was 366.3 MB in the beginning and 815.5 MB in the end (delta: -449.2 MB). Peak memory consumption was 1.7 GB. Max. memory is 5.3 GB. [2018-04-11 23:18:58,385 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.14 ms. Allocated memory is still 319.8 MB. Free memory is still 290.8 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 160.15 ms. Allocated memory is still 319.8 MB. Free memory was 267.6 MB in the beginning and 256.9 MB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 27.50 ms. Allocated memory is still 319.8 MB. Free memory was 256.9 MB in the beginning and 255.6 MB in the end (delta: 1.3 MB). Peak memory consumption was 1.3 MB. Max. memory is 5.3 GB. * RCFGBuilder took 293.76 ms. Allocated memory was 319.8 MB in the beginning and 403.2 MB in the end (delta: 83.4 MB). Free memory was 255.6 MB in the beginning and 367.6 MB in the end (delta: -112.0 MB). Peak memory consumption was 34.7 MB. Max. memory is 5.3 GB. * TraceAbstraction took 761317.57 ms. Allocated memory was 403.2 MB in the beginning and 2.6 GB in the end (delta: 2.2 GB). Free memory was 366.3 MB in the beginning and 815.5 MB in the end (delta: -449.2 MB). Peak memory consumption was 1.7 GB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 18]: array index can be out of bounds array index can be out of bounds We found a FailurePath: [L24] int i, b[32]; [L25] FCALL char mask[32]; VAL [mask={43:0}] [L26] i = 0 VAL [i=0, mask={43:0}] [L26] COND TRUE i < sizeof(mask) VAL [i=0, mask={43:0}] [L27] EXPR b[i] VAL [i=0, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=1, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=1, b={43:0}, b={43:0}, i=0, size=1] [L17] COND TRUE i <= size VAL [\old(size)=1, b={43:0}, b={43:0}, i=0, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={43:0}, b={43:0}, i=0, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={43:0}, b={43:0}, b[i]=53, i=0, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=1, b={43:0}, b={43:0}, i=1, size=1] [L18] EXPR a[i] VAL [\old(size)=1, b={43:0}, b={43:0}, i=1, size=1] [L18] EXPR, FCALL b[i] VAL [\old(size)=1, b={43:0}, b={43:0}, b[i]=50, i=1, size=1] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=1, b={43:0}, b={43:0}, i=2, size=1] [L20] RET return i; VAL [\old(size)=1, \result=2, b={43:0}, b={43:0}, i=2, size=1] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=2, i=0, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=1, mask={43:0}] [L27] EXPR b[i] VAL [i=1, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=2, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=2, b={43:0}, b={43:0}, i=0, size=2] [L17] COND TRUE i <= size VAL [\old(size)=2, b={43:0}, b={43:0}, i=0, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={43:0}, b={43:0}, i=0, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={43:0}, b={43:0}, b[i]=53, i=0, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=2, b={43:0}, b={43:0}, i=1, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={43:0}, b={43:0}, i=1, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={43:0}, b={43:0}, b[i]=50, i=1, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=2, b={43:0}, b={43:0}, i=2, size=2] [L18] EXPR a[i] VAL [\old(size)=2, b={43:0}, b={43:0}, i=2, size=2] [L18] EXPR, FCALL b[i] VAL [\old(size)=2, b={43:0}, b={43:0}, b[i]=59, i=2, size=2] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=2, b={43:0}, b={43:0}, i=3, size=2] [L20] RET return i; VAL [\old(size)=2, \result=3, b={43:0}, b={43:0}, i=3, size=2] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=3, i=1, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=2, mask={43:0}] [L27] EXPR b[i] VAL [i=2, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=3, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=3, b={43:0}, b={43:0}, i=0, size=3] [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=0, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=0, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=53, i=0, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=1, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=1, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=50, i=1, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=2, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=2, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=59, i=2, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=3, b={43:0}, b={43:0}, i=3, size=3] [L18] EXPR a[i] VAL [\old(size)=3, b={43:0}, b={43:0}, i=3, size=3] [L18] EXPR, FCALL b[i] VAL [\old(size)=3, b={43:0}, b={43:0}, b[i]=41, i=3, size=3] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=3, b={43:0}, b={43:0}, i=4, size=3] [L20] RET return i; VAL [\old(size)=3, \result=4, b={43:0}, b={43:0}, i=4, size=3] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=4, i=2, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=3, mask={43:0}] [L27] EXPR b[i] VAL [i=3, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=4, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=4, b={43:0}, b={43:0}, i=0, size=4] [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=0, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=0, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=53, i=0, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=1, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=1, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=50, i=1, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=2, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=2, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=59, i=2, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=3, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=3, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=41, i=3, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=4, b={43:0}, b={43:0}, i=4, size=4] [L18] EXPR a[i] VAL [\old(size)=4, b={43:0}, b={43:0}, i=4, size=4] [L18] EXPR, FCALL b[i] VAL [\old(size)=4, b={43:0}, b={43:0}, b[i]=52, i=4, size=4] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=4, b={43:0}, b={43:0}, i=5, size=4] [L20] RET return i; VAL [\old(size)=4, \result=5, b={43:0}, b={43:0}, i=5, size=4] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=5, i=3, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=4, mask={43:0}] [L27] EXPR b[i] VAL [i=4, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=5, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=5, b={43:0}, b={43:0}, i=0, size=5] [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=0, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=0, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=53, i=0, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=1, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=1, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=50, i=1, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=2, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=2, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=59, i=2, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=3, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=3, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=41, i=3, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=4, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=4, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=52, i=4, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=5, b={43:0}, b={43:0}, i=5, size=5] [L18] EXPR a[i] VAL [\old(size)=5, b={43:0}, b={43:0}, i=5, size=5] [L18] EXPR, FCALL b[i] VAL [\old(size)=5, b={43:0}, b={43:0}, b[i]=35, i=5, size=5] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=5, b={43:0}, b={43:0}, i=6, size=5] [L20] RET return i; VAL [\old(size)=5, \result=6, b={43:0}, b={43:0}, i=6, size=5] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=6, i=4, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=5, mask={43:0}] [L27] EXPR b[i] VAL [i=5, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=6, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=6, b={43:0}, b={43:0}, i=0, size=6] [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=0, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=0, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=53, i=0, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=1, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=1, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=50, i=1, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=2, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=2, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=59, i=2, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=3, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=3, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=41, i=3, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=4, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=4, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=52, i=4, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=5, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=5, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=35, i=5, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=6, b={43:0}, b={43:0}, i=6, size=6] [L18] EXPR a[i] VAL [\old(size)=6, b={43:0}, b={43:0}, i=6, size=6] [L18] EXPR, FCALL b[i] VAL [\old(size)=6, b={43:0}, b={43:0}, b[i]=34, i=6, size=6] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=6, b={43:0}, b={43:0}, i=7, size=6] [L20] RET return i; VAL [\old(size)=6, \result=7, b={43:0}, b={43:0}, i=7, size=6] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=7, i=5, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=6, mask={43:0}] [L27] EXPR b[i] VAL [i=6, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=7, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=7, b={43:0}, b={43:0}, i=0, size=7] [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=0, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=0, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=53, i=0, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=1, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=1, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=50, i=1, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=2, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=2, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=59, i=2, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=3, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=3, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=41, i=3, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=4, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=4, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=52, i=4, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=5, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=5, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=35, i=5, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=6, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=6, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=34, i=6, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=7, b={43:0}, b={43:0}, i=7, size=7] [L18] EXPR a[i] VAL [\old(size)=7, b={43:0}, b={43:0}, i=7, size=7] [L18] EXPR, FCALL b[i] VAL [\old(size)=7, b={43:0}, b={43:0}, b[i]=51, i=7, size=7] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=7, b={43:0}, b={43:0}, i=8, size=7] [L20] RET return i; VAL [\old(size)=7, \result=8, b={43:0}, b={43:0}, i=8, size=7] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=8, i=6, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=7, mask={43:0}] [L27] EXPR b[i] VAL [i=7, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=8, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=8, b={43:0}, b={43:0}, i=0, size=8] [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=0, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=0, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=53, i=0, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=1, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=1, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=50, i=1, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=2, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=2, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=59, i=2, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=3, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=3, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=41, i=3, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=4, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=4, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=52, i=4, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=5, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=5, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=35, i=5, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=6, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=6, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=34, i=6, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=7, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=7, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=51, i=7, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=8, b={43:0}, b={43:0}, i=8, size=8] [L18] EXPR a[i] VAL [\old(size)=8, b={43:0}, b={43:0}, i=8, size=8] [L18] EXPR, FCALL b[i] VAL [\old(size)=8, b={43:0}, b={43:0}, b[i]=36, i=8, size=8] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=8, b={43:0}, b={43:0}, i=9, size=8] [L20] RET return i; VAL [\old(size)=8, \result=9, b={43:0}, b={43:0}, i=9, size=8] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=9, i=7, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=8, mask={43:0}] [L27] EXPR b[i] VAL [i=8, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=9, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=9, b={43:0}, b={43:0}, i=0, size=9] [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=0, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=0, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=53, i=0, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=1, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=1, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=50, i=1, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=2, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=2, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=59, i=2, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=3, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=3, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=41, i=3, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=4, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=4, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=52, i=4, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=5, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=5, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=35, i=5, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=6, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=6, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=34, i=6, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=7, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=7, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=51, i=7, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=8, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=8, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=36, i=8, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=9, b={43:0}, b={43:0}, i=9, size=9] [L18] EXPR a[i] VAL [\old(size)=9, b={43:0}, b={43:0}, i=9, size=9] [L18] EXPR, FCALL b[i] VAL [\old(size)=9, b={43:0}, b={43:0}, b[i]=37, i=9, size=9] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=9, b={43:0}, b={43:0}, i=10, size=9] [L20] RET return i; VAL [\old(size)=9, \result=10, b={43:0}, b={43:0}, i=10, size=9] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=10, i=8, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=9, mask={43:0}] [L27] EXPR b[i] VAL [i=9, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=10, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=10, b={43:0}, b={43:0}, i=0, size=10] [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=0, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=0, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=53, i=0, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=1, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=1, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=50, i=1, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=2, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=2, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=59, i=2, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=3, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=3, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=41, i=3, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=4, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=4, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=52, i=4, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=5, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=5, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=35, i=5, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=6, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=6, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=34, i=6, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=7, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=7, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=51, i=7, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=8, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=8, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=36, i=8, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=9, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=9, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=37, i=9, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=10, b={43:0}, b={43:0}, i=10, size=10] [L18] EXPR a[i] VAL [\old(size)=10, b={43:0}, b={43:0}, i=10, size=10] [L18] EXPR, FCALL b[i] VAL [\old(size)=10, b={43:0}, b={43:0}, b[i]=42, i=10, size=10] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=10, b={43:0}, b={43:0}, i=11, size=10] [L20] RET return i; VAL [\old(size)=10, \result=11, b={43:0}, b={43:0}, i=11, size=10] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=11, i=9, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=10, mask={43:0}] [L27] EXPR b[i] VAL [i=10, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=11, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=11, b={43:0}, b={43:0}, i=0, size=11] [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=0, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=0, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=53, i=0, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=1, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=1, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=50, i=1, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=2, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=2, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=59, i=2, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=3, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=3, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=41, i=3, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=4, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=4, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=52, i=4, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=5, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=5, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=35, i=5, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=6, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=6, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=34, i=6, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=7, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=7, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=51, i=7, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=8, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=8, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=36, i=8, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=9, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=9, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=37, i=9, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=10, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=10, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=42, i=10, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=11, b={43:0}, b={43:0}, i=11, size=11] [L18] EXPR a[i] VAL [\old(size)=11, b={43:0}, b={43:0}, i=11, size=11] [L18] EXPR, FCALL b[i] VAL [\old(size)=11, b={43:0}, b={43:0}, b[i]=62, i=11, size=11] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=11, b={43:0}, b={43:0}, i=12, size=11] [L20] RET return i; VAL [\old(size)=11, \result=12, b={43:0}, b={43:0}, i=12, size=11] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=12, i=10, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=11, mask={43:0}] [L27] EXPR b[i] VAL [i=11, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=12, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=12, b={43:0}, b={43:0}, i=0, size=12] [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=0, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=0, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=53, i=0, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=1, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=1, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=50, i=1, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=2, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=2, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=59, i=2, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=3, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=3, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=41, i=3, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=4, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=4, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=52, i=4, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=5, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=5, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=35, i=5, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=6, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=6, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=34, i=6, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=7, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=7, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=51, i=7, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=8, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=8, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=36, i=8, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=9, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=9, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=37, i=9, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=10, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=10, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=42, i=10, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=11, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=11, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=62, i=11, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=12, b={43:0}, b={43:0}, i=12, size=12] [L18] EXPR a[i] VAL [\old(size)=12, b={43:0}, b={43:0}, i=12, size=12] [L18] EXPR, FCALL b[i] VAL [\old(size)=12, b={43:0}, b={43:0}, b[i]=61, i=12, size=12] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=12, b={43:0}, b={43:0}, i=13, size=12] [L20] RET return i; VAL [\old(size)=12, \result=13, b={43:0}, b={43:0}, i=13, size=12] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=13, i=11, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=12, mask={43:0}] [L27] EXPR b[i] VAL [i=12, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=13, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=13, b={43:0}, b={43:0}, i=0, size=13] [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=0, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=0, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=53, i=0, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=1, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=1, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=50, i=1, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=2, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=2, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=59, i=2, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=3, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=3, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=41, i=3, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=4, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=4, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=52, i=4, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=5, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=5, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=35, i=5, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=6, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=6, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=34, i=6, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=7, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=7, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=51, i=7, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=8, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=8, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=36, i=8, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=9, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=9, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=37, i=9, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=10, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=10, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=42, i=10, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=11, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=11, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=62, i=11, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=12, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=12, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=61, i=12, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=13, b={43:0}, b={43:0}, i=13, size=13] [L18] EXPR a[i] VAL [\old(size)=13, b={43:0}, b={43:0}, i=13, size=13] [L18] EXPR, FCALL b[i] VAL [\old(size)=13, b={43:0}, b={43:0}, b[i]=63, i=13, size=13] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=13, b={43:0}, b={43:0}, i=14, size=13] [L20] RET return i; VAL [\old(size)=13, \result=14, b={43:0}, b={43:0}, i=14, size=13] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=14, i=12, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=13, mask={43:0}] [L27] EXPR b[i] VAL [i=13, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=14, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=14, b={43:0}, b={43:0}, i=0, size=14] [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=0, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=0, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=53, i=0, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=1, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=1, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=50, i=1, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=2, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=2, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=59, i=2, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=3, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=3, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=41, i=3, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=4, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=4, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=52, i=4, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=5, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=5, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=35, i=5, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=6, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=6, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=34, i=6, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=7, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=7, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=51, i=7, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=8, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=8, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=36, i=8, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=9, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=9, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=37, i=9, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=10, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=10, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=42, i=10, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=11, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=11, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=62, i=11, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=12, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=12, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=61, i=12, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=13, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=13, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=63, i=13, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=14, b={43:0}, b={43:0}, i=14, size=14] [L18] EXPR a[i] VAL [\old(size)=14, b={43:0}, b={43:0}, i=14, size=14] [L18] EXPR, FCALL b[i] VAL [\old(size)=14, b={43:0}, b={43:0}, b[i]=40, i=14, size=14] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=14, b={43:0}, b={43:0}, i=15, size=14] [L20] RET return i; VAL [\old(size)=14, \result=15, b={43:0}, b={43:0}, i=15, size=14] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=15, i=13, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=14, mask={43:0}] [L27] EXPR b[i] VAL [i=14, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=15, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=15, b={43:0}, b={43:0}, i=0, size=15] [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=0, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=0, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=53, i=0, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=1, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=1, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=50, i=1, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=2, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=2, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=59, i=2, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=3, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=3, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=41, i=3, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=4, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=4, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=52, i=4, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=5, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=5, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=35, i=5, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=6, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=6, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=34, i=6, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=7, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=7, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=51, i=7, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=8, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=8, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=36, i=8, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=9, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=9, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=37, i=9, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=10, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=10, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=42, i=10, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=11, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=11, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=62, i=11, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=12, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=12, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=61, i=12, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=13, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=13, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=63, i=13, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=14, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=14, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=40, i=14, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=15, b={43:0}, b={43:0}, i=15, size=15] [L18] EXPR a[i] VAL [\old(size)=15, b={43:0}, b={43:0}, i=15, size=15] [L18] EXPR, FCALL b[i] VAL [\old(size)=15, b={43:0}, b={43:0}, b[i]=48, i=15, size=15] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=15, b={43:0}, b={43:0}, i=16, size=15] [L20] RET return i; VAL [\old(size)=15, \result=16, b={43:0}, b={43:0}, i=16, size=15] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=16, i=14, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=15, mask={43:0}] [L27] EXPR b[i] VAL [i=15, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=16, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=16, b={43:0}, b={43:0}, i=0, size=16] [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=0, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=0, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=53, i=0, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=1, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=1, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=50, i=1, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=2, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=2, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=59, i=2, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=3, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=3, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=41, i=3, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=4, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=4, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=52, i=4, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=5, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=5, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=35, i=5, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=6, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=6, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=34, i=6, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=7, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=7, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=51, i=7, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=8, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=8, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=36, i=8, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=9, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=9, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=37, i=9, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=10, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=10, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=42, i=10, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=11, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=11, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=62, i=11, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=12, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=12, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=61, i=12, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=13, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=13, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=63, i=13, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=14, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=14, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=40, i=14, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=15, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=15, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=48, i=15, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=16, b={43:0}, b={43:0}, i=16, size=16] [L18] EXPR a[i] VAL [\old(size)=16, b={43:0}, b={43:0}, i=16, size=16] [L18] EXPR, FCALL b[i] VAL [\old(size)=16, b={43:0}, b={43:0}, b[i]=54, i=16, size=16] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=16, b={43:0}, b={43:0}, i=17, size=16] [L20] RET return i; VAL [\old(size)=16, \result=17, b={43:0}, b={43:0}, i=17, size=16] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=17, i=15, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=16, mask={43:0}] [L27] EXPR b[i] VAL [i=16, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=17, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=17, b={43:0}, b={43:0}, i=0, size=17] [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=0, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=0, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=53, i=0, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=1, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=1, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=50, i=1, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=2, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=2, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=59, i=2, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=3, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=3, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=41, i=3, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=4, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=4, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=52, i=4, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=5, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=5, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=35, i=5, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=6, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=6, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=34, i=6, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=7, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=7, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=51, i=7, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=8, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=8, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=36, i=8, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=9, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=9, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=37, i=9, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=10, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=10, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=42, i=10, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=11, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=11, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=62, i=11, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=12, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=12, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=61, i=12, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=13, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=13, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=63, i=13, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=14, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=14, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=40, i=14, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=15, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=15, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=48, i=15, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=16, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=16, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=54, i=16, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=17, b={43:0}, b={43:0}, i=17, size=17] [L18] EXPR a[i] VAL [\old(size)=17, b={43:0}, b={43:0}, i=17, size=17] [L18] EXPR, FCALL b[i] VAL [\old(size)=17, b={43:0}, b={43:0}, b[i]=64, i=17, size=17] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=17, b={43:0}, b={43:0}, i=18, size=17] [L20] RET return i; VAL [\old(size)=17, \result=18, b={43:0}, b={43:0}, i=18, size=17] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=18, i=16, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=17, mask={43:0}] [L27] EXPR b[i] VAL [i=17, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=18, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=18, b={43:0}, b={43:0}, i=0, size=18] [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=0, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=0, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=53, i=0, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=1, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=1, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=50, i=1, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=2, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=2, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=59, i=2, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=3, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=3, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=41, i=3, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=4, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=4, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=52, i=4, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=5, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=5, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=35, i=5, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=6, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=6, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=34, i=6, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=7, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=7, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=51, i=7, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=8, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=8, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=36, i=8, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=9, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=9, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=37, i=9, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=10, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=10, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=42, i=10, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=11, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=11, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=62, i=11, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=12, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=12, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=61, i=12, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=13, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=13, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=63, i=13, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=14, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=14, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=40, i=14, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=15, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=15, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=48, i=15, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=16, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=16, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=54, i=16, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=17, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=17, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=64, i=17, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=18, b={43:0}, b={43:0}, i=18, size=18] [L18] EXPR a[i] VAL [\old(size)=18, b={43:0}, b={43:0}, i=18, size=18] [L18] EXPR, FCALL b[i] VAL [\old(size)=18, b={43:0}, b={43:0}, b[i]=44, i=18, size=18] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=18, b={43:0}, b={43:0}, i=19, size=18] [L20] RET return i; VAL [\old(size)=18, \result=19, b={43:0}, b={43:0}, i=19, size=18] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=19, i=17, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=18, mask={43:0}] [L27] EXPR b[i] VAL [i=18, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=19, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=19, b={43:0}, b={43:0}, i=0, size=19] [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=0, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=0, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=53, i=0, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=1, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=1, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=50, i=1, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=2, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=2, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=59, i=2, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=3, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=3, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=41, i=3, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=4, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=4, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=52, i=4, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=5, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=5, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=35, i=5, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=6, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=6, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=34, i=6, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=7, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=7, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=51, i=7, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=8, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=8, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=36, i=8, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=9, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=9, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=37, i=9, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=10, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=10, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=42, i=10, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=11, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=11, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=62, i=11, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=12, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=12, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=61, i=12, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=13, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=13, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=63, i=13, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=14, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=14, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=40, i=14, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=15, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=15, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=48, i=15, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=16, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=16, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=54, i=16, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=17, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=17, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=64, i=17, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=18, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=18, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=44, i=18, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=19, b={43:0}, b={43:0}, i=19, size=19] [L18] EXPR a[i] VAL [\old(size)=19, b={43:0}, b={43:0}, i=19, size=19] [L18] EXPR, FCALL b[i] VAL [\old(size)=19, b={43:0}, b={43:0}, b[i]=58, i=19, size=19] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=19, b={43:0}, b={43:0}, i=20, size=19] [L20] RET return i; VAL [\old(size)=19, \result=20, b={43:0}, b={43:0}, i=20, size=19] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=20, i=18, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=19, mask={43:0}] [L27] EXPR b[i] VAL [i=19, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=20, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=20, b={43:0}, b={43:0}, i=0, size=20] [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=0, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=0, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=53, i=0, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=1, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=1, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=50, i=1, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=2, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=2, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=59, i=2, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=3, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=3, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=41, i=3, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=4, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=4, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=52, i=4, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=5, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=5, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=35, i=5, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=6, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=6, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=34, i=6, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=7, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=7, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=51, i=7, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=8, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=8, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=36, i=8, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=9, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=9, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=37, i=9, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=10, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=10, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=42, i=10, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=11, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=11, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=62, i=11, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=12, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=12, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=61, i=12, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=13, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=13, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=63, i=13, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=14, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=14, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=40, i=14, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=15, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=15, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=48, i=15, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=16, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=16, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=54, i=16, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=17, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=17, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=64, i=17, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=18, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=18, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=44, i=18, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=19, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=19, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=58, i=19, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=20, b={43:0}, b={43:0}, i=20, size=20] [L18] EXPR a[i] VAL [\old(size)=20, b={43:0}, b={43:0}, i=20, size=20] [L18] EXPR, FCALL b[i] VAL [\old(size)=20, b={43:0}, b={43:0}, b[i]=55, i=20, size=20] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=20, b={43:0}, b={43:0}, i=21, size=20] [L20] RET return i; VAL [\old(size)=20, \result=21, b={43:0}, b={43:0}, i=21, size=20] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=21, i=19, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=20, mask={43:0}] [L27] EXPR b[i] VAL [i=20, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=21, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=21, b={43:0}, b={43:0}, i=0, size=21] [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=0, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=0, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=53, i=0, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=1, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=1, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=50, i=1, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=2, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=2, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=59, i=2, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=3, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=3, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=41, i=3, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=4, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=4, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=52, i=4, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=5, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=5, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=35, i=5, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=6, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=6, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=34, i=6, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=7, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=7, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=51, i=7, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=8, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=8, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=36, i=8, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=9, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=9, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=37, i=9, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=10, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=10, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=42, i=10, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=11, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=11, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=62, i=11, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=12, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=12, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=61, i=12, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=13, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=13, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=63, i=13, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=14, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=14, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=40, i=14, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=15, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=15, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=48, i=15, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=16, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=16, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=54, i=16, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=17, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=17, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=64, i=17, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=18, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=18, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=44, i=18, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=19, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=19, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=58, i=19, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=20, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=20, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=55, i=20, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=21, b={43:0}, b={43:0}, i=21, size=21] [L18] EXPR a[i] VAL [\old(size)=21, b={43:0}, b={43:0}, i=21, size=21] [L18] EXPR, FCALL b[i] VAL [\old(size)=21, b={43:0}, b={43:0}, b[i]=33, i=21, size=21] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=21, b={43:0}, b={43:0}, i=22, size=21] [L20] RET return i; VAL [\old(size)=21, \result=22, b={43:0}, b={43:0}, i=22, size=21] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=22, i=20, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=21, mask={43:0}] [L27] EXPR b[i] VAL [i=21, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=22, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=22, b={43:0}, b={43:0}, i=0, size=22] [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=0, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=0, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=53, i=0, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=1, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=1, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=50, i=1, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=2, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=2, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=59, i=2, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=3, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=3, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=41, i=3, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=4, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=4, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=52, i=4, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=5, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=5, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=35, i=5, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=6, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=6, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=34, i=6, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=7, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=7, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=51, i=7, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=8, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=8, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=36, i=8, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=9, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=9, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=37, i=9, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=10, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=10, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=42, i=10, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=11, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=11, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=62, i=11, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=12, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=12, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=61, i=12, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=13, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=13, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=63, i=13, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=14, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=14, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=40, i=14, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=15, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=15, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=48, i=15, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=16, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=16, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=54, i=16, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=17, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=17, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=64, i=17, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=18, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=18, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=44, i=18, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=19, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=19, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=58, i=19, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=20, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=20, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=55, i=20, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=21, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=21, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=33, i=21, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=22, b={43:0}, b={43:0}, i=22, size=22] [L18] EXPR a[i] VAL [\old(size)=22, b={43:0}, b={43:0}, i=22, size=22] [L18] EXPR, FCALL b[i] VAL [\old(size)=22, b={43:0}, b={43:0}, b[i]=47, i=22, size=22] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=22, b={43:0}, b={43:0}, i=23, size=22] [L20] RET return i; VAL [\old(size)=22, \result=23, b={43:0}, b={43:0}, i=23, size=22] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=23, i=21, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=22, mask={43:0}] [L27] EXPR b[i] VAL [i=22, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=23, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=23, b={43:0}, b={43:0}, i=0, size=23] [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=0, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=0, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=53, i=0, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=1, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=1, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=50, i=1, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=2, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=2, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=59, i=2, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=3, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=3, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=41, i=3, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=4, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=4, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=52, i=4, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=5, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=5, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=35, i=5, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=6, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=6, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=34, i=6, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=7, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=7, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=51, i=7, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=8, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=8, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=36, i=8, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=9, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=9, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=37, i=9, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=10, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=10, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=42, i=10, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=11, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=11, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=62, i=11, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=12, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=12, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=61, i=12, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=13, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=13, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=63, i=13, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=14, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=14, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=40, i=14, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=15, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=15, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=48, i=15, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=16, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=16, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=54, i=16, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=17, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=17, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=64, i=17, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=18, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=18, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=44, i=18, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=19, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=19, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=58, i=19, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=20, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=20, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=55, i=20, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=21, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=21, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=33, i=21, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=22, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=22, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=47, i=22, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=23, b={43:0}, b={43:0}, i=23, size=23] [L18] EXPR a[i] VAL [\old(size)=23, b={43:0}, b={43:0}, i=23, size=23] [L18] EXPR, FCALL b[i] VAL [\old(size)=23, b={43:0}, b={43:0}, b[i]=46, i=23, size=23] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=23, b={43:0}, b={43:0}, i=24, size=23] [L20] RET return i; VAL [\old(size)=23, \result=24, b={43:0}, b={43:0}, i=24, size=23] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=24, i=22, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=23, mask={43:0}] [L27] EXPR b[i] VAL [i=23, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=24, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=24, b={43:0}, b={43:0}, i=0, size=24] [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=0, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=0, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=53, i=0, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=1, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=1, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=50, i=1, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=2, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=2, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=59, i=2, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=3, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=3, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=41, i=3, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=4, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=4, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=52, i=4, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=5, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=5, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=35, i=5, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=6, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=6, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=34, i=6, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=7, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=7, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=51, i=7, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=8, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=8, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=36, i=8, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=9, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=9, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=37, i=9, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=10, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=10, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=42, i=10, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=11, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=11, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=62, i=11, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=12, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=12, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=61, i=12, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=13, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=13, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=63, i=13, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=14, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=14, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=40, i=14, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=15, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=15, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=48, i=15, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=16, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=16, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=54, i=16, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=17, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=17, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=64, i=17, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=18, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=18, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=44, i=18, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=19, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=19, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=58, i=19, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=20, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=20, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=55, i=20, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=21, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=21, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=33, i=21, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=22, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=22, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=47, i=22, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=23, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=23, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=46, i=23, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=24, b={43:0}, b={43:0}, i=24, size=24] [L18] EXPR a[i] VAL [\old(size)=24, b={43:0}, b={43:0}, i=24, size=24] [L18] EXPR, FCALL b[i] VAL [\old(size)=24, b={43:0}, b={43:0}, b[i]=67, i=24, size=24] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=24, b={43:0}, b={43:0}, i=25, size=24] [L20] RET return i; VAL [\old(size)=24, \result=25, b={43:0}, b={43:0}, i=25, size=24] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=25, i=23, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=24, mask={43:0}] [L27] EXPR b[i] VAL [i=24, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=25, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=25, b={43:0}, b={43:0}, i=0, size=25] [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=0, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=0, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=53, i=0, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=1, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=1, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=50, i=1, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=2, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=2, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=59, i=2, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=3, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=3, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=41, i=3, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=4, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=4, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=52, i=4, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=5, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=5, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=35, i=5, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=6, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=6, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=34, i=6, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=7, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=7, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=51, i=7, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=8, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=8, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=36, i=8, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=9, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=9, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=37, i=9, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=10, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=10, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=42, i=10, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=11, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=11, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=62, i=11, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=12, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=12, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=61, i=12, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=13, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=13, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=63, i=13, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=14, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=14, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=40, i=14, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=15, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=15, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=48, i=15, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=16, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=16, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=54, i=16, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=17, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=17, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=64, i=17, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=18, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=18, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=44, i=18, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=19, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=19, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=58, i=19, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=20, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=20, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=55, i=20, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=21, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=21, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=33, i=21, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=22, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=22, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=47, i=22, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=23, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=23, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=46, i=23, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=24, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=24, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=67, i=24, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=25, b={43:0}, b={43:0}, i=25, size=25] [L18] EXPR a[i] VAL [\old(size)=25, b={43:0}, b={43:0}, i=25, size=25] [L18] EXPR, FCALL b[i] VAL [\old(size)=25, b={43:0}, b={43:0}, b[i]=45, i=25, size=25] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=25, b={43:0}, b={43:0}, i=26, size=25] [L20] RET return i; VAL [\old(size)=25, \result=26, b={43:0}, b={43:0}, i=26, size=25] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=26, i=24, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=25, mask={43:0}] [L27] EXPR b[i] VAL [i=25, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=26, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=26, b={43:0}, b={43:0}, i=0, size=26] [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=0, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=0, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=53, i=0, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=1, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=1, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=50, i=1, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=2, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=2, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=59, i=2, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=3, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=3, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=41, i=3, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=4, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=4, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=52, i=4, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=5, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=5, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=35, i=5, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=6, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=6, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=34, i=6, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=7, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=7, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=51, i=7, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=8, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=8, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=36, i=8, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=9, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=9, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=37, i=9, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=10, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=10, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=42, i=10, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=11, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=11, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=62, i=11, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=12, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=12, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=61, i=12, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=13, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=13, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=63, i=13, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=14, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=14, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=40, i=14, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=15, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=15, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=48, i=15, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=16, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=16, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=54, i=16, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=17, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=17, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=64, i=17, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=18, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=18, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=44, i=18, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=19, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=19, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=58, i=19, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=20, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=20, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=55, i=20, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=21, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=21, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=33, i=21, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=22, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=22, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=47, i=22, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=23, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=23, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=46, i=23, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=24, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=24, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=67, i=24, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=25, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=25, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=45, i=25, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=26, b={43:0}, b={43:0}, i=26, size=26] [L18] EXPR a[i] VAL [\old(size)=26, b={43:0}, b={43:0}, i=26, size=26] [L18] EXPR, FCALL b[i] VAL [\old(size)=26, b={43:0}, b={43:0}, b[i]=56, i=26, size=26] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=26, b={43:0}, b={43:0}, i=27, size=26] [L20] RET return i; VAL [\old(size)=26, \result=27, b={43:0}, b={43:0}, i=27, size=26] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=27, i=25, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=26, mask={43:0}] [L27] EXPR b[i] VAL [i=26, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=27, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=27, b={43:0}, b={43:0}, i=0, size=27] [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=0, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=0, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=53, i=0, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=1, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=1, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=50, i=1, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=2, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=2, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=59, i=2, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=3, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=3, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=41, i=3, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=4, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=4, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=52, i=4, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=5, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=5, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=35, i=5, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=6, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=6, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=34, i=6, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=7, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=7, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=51, i=7, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=8, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=8, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=36, i=8, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=9, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=9, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=37, i=9, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=10, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=10, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=42, i=10, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=11, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=11, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=62, i=11, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=12, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=12, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=61, i=12, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=13, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=13, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=63, i=13, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=14, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=14, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=40, i=14, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=15, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=15, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=48, i=15, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=16, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=16, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=54, i=16, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=17, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=17, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=64, i=17, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=18, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=18, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=44, i=18, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=19, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=19, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=58, i=19, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=20, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=20, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=55, i=20, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=21, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=21, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=33, i=21, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=22, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=22, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=47, i=22, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=23, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=23, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=46, i=23, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=24, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=24, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=67, i=24, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=25, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=25, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=45, i=25, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=26, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=26, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=56, i=26, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=27, b={43:0}, b={43:0}, i=27, size=27] [L18] EXPR a[i] VAL [\old(size)=27, b={43:0}, b={43:0}, i=27, size=27] [L18] EXPR, FCALL b[i] VAL [\old(size)=27, b={43:0}, b={43:0}, b[i]=38, i=27, size=27] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=27, b={43:0}, b={43:0}, i=28, size=27] [L20] RET return i; VAL [\old(size)=27, \result=28, b={43:0}, b={43:0}, i=28, size=27] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=28, i=26, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=27, mask={43:0}] [L27] EXPR b[i] VAL [i=27, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=28, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=28, b={43:0}, b={43:0}, i=0, size=28] [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=0, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=0, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=53, i=0, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=1, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=1, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=50, i=1, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=2, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=2, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=59, i=2, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=3, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=3, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=41, i=3, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=4, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=4, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=52, i=4, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=5, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=5, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=35, i=5, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=6, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=6, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=34, i=6, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=7, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=7, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=51, i=7, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=8, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=8, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=36, i=8, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=9, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=9, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=37, i=9, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=10, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=10, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=42, i=10, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=11, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=11, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=62, i=11, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=12, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=12, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=61, i=12, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=13, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=13, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=63, i=13, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=14, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=14, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=40, i=14, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=15, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=15, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=48, i=15, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=16, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=16, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=54, i=16, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=17, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=17, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=64, i=17, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=18, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=18, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=44, i=18, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=19, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=19, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=58, i=19, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=20, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=20, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=55, i=20, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=21, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=21, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=33, i=21, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=22, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=22, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=47, i=22, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=23, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=23, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=46, i=23, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=24, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=24, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=67, i=24, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=25, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=25, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=45, i=25, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=26, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=26, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=56, i=26, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=27, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=27, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=38, i=27, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=28, b={43:0}, b={43:0}, i=28, size=28] [L18] EXPR a[i] VAL [\old(size)=28, b={43:0}, b={43:0}, i=28, size=28] [L18] EXPR, FCALL b[i] VAL [\old(size)=28, b={43:0}, b={43:0}, b[i]=65, i=28, size=28] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=28, b={43:0}, b={43:0}, i=29, size=28] [L20] RET return i; VAL [\old(size)=28, \result=29, b={43:0}, b={43:0}, i=29, size=28] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=29, i=27, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=28, mask={43:0}] [L27] EXPR b[i] VAL [i=28, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=29, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=29, b={43:0}, b={43:0}, i=0, size=29] [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=0, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=0, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=53, i=0, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=1, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=1, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=50, i=1, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=2, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=2, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=59, i=2, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=3, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=3, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=41, i=3, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=4, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=4, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=52, i=4, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=5, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=5, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=35, i=5, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=6, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=6, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=34, i=6, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=7, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=7, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=51, i=7, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=8, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=8, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=36, i=8, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=9, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=9, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=37, i=9, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=10, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=10, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=42, i=10, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=11, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=11, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=62, i=11, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=12, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=12, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=61, i=12, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=13, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=13, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=63, i=13, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=14, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=14, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=40, i=14, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=15, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=15, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=48, i=15, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=16, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=16, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=54, i=16, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=17, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=17, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=64, i=17, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=18, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=18, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=44, i=18, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=19, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=19, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=58, i=19, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=20, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=20, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=55, i=20, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=21, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=21, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=33, i=21, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=22, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=22, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=47, i=22, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=23, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=23, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=46, i=23, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=24, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=24, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=67, i=24, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=25, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=25, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=45, i=25, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=26, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=26, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=56, i=26, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=27, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=27, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=38, i=27, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=28, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=28, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=65, i=28, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=29, b={43:0}, b={43:0}, i=29, size=29] [L18] EXPR a[i] VAL [\old(size)=29, b={43:0}, b={43:0}, i=29, size=29] [L18] EXPR, FCALL b[i] VAL [\old(size)=29, b={43:0}, b={43:0}, b[i]=66, i=29, size=29] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=29, b={43:0}, b={43:0}, i=30, size=29] [L20] RET return i; VAL [\old(size)=29, \result=30, b={43:0}, b={43:0}, i=30, size=29] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=30, i=28, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=29, mask={43:0}] [L27] EXPR b[i] VAL [i=29, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=30, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=30, b={43:0}, b={43:0}, i=0, size=30] [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=0, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=0, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=53, i=0, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=1, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=1, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=50, i=1, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=2, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=2, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=59, i=2, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=3, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=3, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=41, i=3, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=4, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=4, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=52, i=4, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=5, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=5, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=35, i=5, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=6, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=6, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=34, i=6, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=7, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=7, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=51, i=7, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=8, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=8, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=36, i=8, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=9, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=9, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=37, i=9, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=10, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=10, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=42, i=10, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=11, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=11, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=62, i=11, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=12, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=12, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=61, i=12, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=13, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=13, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=63, i=13, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=14, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=14, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=40, i=14, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=15, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=15, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=48, i=15, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=16, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=16, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=54, i=16, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=17, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=17, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=64, i=17, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=18, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=18, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=44, i=18, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=19, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=19, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=58, i=19, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=20, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=20, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=55, i=20, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=21, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=21, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=33, i=21, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=22, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=22, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=47, i=22, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=23, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=23, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=46, i=23, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=24, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=24, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=67, i=24, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=25, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=25, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=45, i=25, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=26, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=26, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=56, i=26, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=27, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=27, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=38, i=27, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=28, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=28, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=65, i=28, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=29, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=29, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=66, i=29, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=30, b={43:0}, b={43:0}, i=30, size=30] [L18] EXPR a[i] VAL [\old(size)=30, b={43:0}, b={43:0}, i=30, size=30] [L18] EXPR, FCALL b[i] VAL [\old(size)=30, b={43:0}, b={43:0}, b[i]=39, i=30, size=30] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=30, b={43:0}, b={43:0}, i=31, size=30] [L20] RET return i; VAL [\old(size)=30, \result=31, b={43:0}, b={43:0}, i=31, size=30] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=31, i=29, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=30, mask={43:0}] [L27] EXPR b[i] VAL [i=30, mask={43:0}] [L27] CALL, EXPR foo(mask, i + 1) VAL [\old(size)=31, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=31, b={43:0}, b={43:0}, i=0, size=31] [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=0, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=0, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=53, i=0, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=1, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=1, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=50, i=1, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=2, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=2, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=59, i=2, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=3, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=3, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=41, i=3, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=4, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=4, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=52, i=4, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=5, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=5, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=35, i=5, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=6, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=6, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=34, i=6, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=7, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=7, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=51, i=7, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=8, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=8, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=36, i=8, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=9, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=9, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=37, i=9, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=10, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=10, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=42, i=10, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=11, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=11, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=62, i=11, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=12, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=12, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=61, i=12, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=13, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=13, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=63, i=13, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=14, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=14, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=40, i=14, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=15, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=15, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=48, i=15, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=16, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=16, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=54, i=16, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=17, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=17, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=64, i=17, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=18, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=18, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=44, i=18, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=19, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=19, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=58, i=19, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=20, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=20, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=55, i=20, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=21, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=21, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=33, i=21, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=22, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=22, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=47, i=22, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=23, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=23, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=46, i=23, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=24, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=24, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=67, i=24, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=25, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=25, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=45, i=25, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=26, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=26, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=56, i=26, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=27, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=27, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=38, i=27, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=28, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=28, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=65, i=28, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=29, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=29, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=66, i=29, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=30, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=30, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=39, i=30, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=31, b={43:0}, b={43:0}, i=31, size=31] [L18] EXPR a[i] VAL [\old(size)=31, b={43:0}, b={43:0}, i=31, size=31] [L18] EXPR, FCALL b[i] VAL [\old(size)=31, b={43:0}, b={43:0}, b[i]=57, i=31, size=31] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND FALSE !(i <= size) VAL [\old(size)=31, b={43:0}, b={43:0}, i=32, size=31] [L20] RET return i; VAL [\old(size)=31, \result=32, b={43:0}, b={43:0}, i=32, size=31] [L27] EXPR foo(mask, i + 1) VAL [foo(mask, i + 1)=32, i=30, mask={43:0}] [L27] b[i] = foo(mask, i + 1) [L26] i++ [L26] i++ [L26] COND TRUE i < sizeof(mask) VAL [i=31, mask={43:0}] [L27] b[i] VAL [i=31, mask={43:0}] [L27] CALL foo(mask, i + 1) VAL [\old(size)=32, b={43:0}] [L15] char a[32]; [L16] int i; [L17] i = 0 VAL [\old(size)=32, b={43:0}, b={43:0}, i=0, size=32] [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=0, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=0, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=53, i=0, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=1, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=1, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=50, i=1, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=2, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=2, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=59, i=2, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=3, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=3, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=41, i=3, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=4, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=4, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=52, i=4, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=5, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=5, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=35, i=5, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=6, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=6, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=34, i=6, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=7, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=7, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=51, i=7, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=8, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=8, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=36, i=8, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=9, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=9, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=37, i=9, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=10, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=10, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=42, i=10, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=11, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=11, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=62, i=11, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=12, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=12, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=61, i=12, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=13, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=13, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=63, i=13, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=14, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=14, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=40, i=14, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=15, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=15, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=48, i=15, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=16, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=16, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=54, i=16, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=17, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=17, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=64, i=17, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=18, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=18, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=44, i=18, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=19, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=19, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=58, i=19, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=20, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=20, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=55, i=20, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=21, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=21, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=33, i=21, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=22, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=22, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=47, i=22, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=23, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=23, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=46, i=23, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=24, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=24, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=67, i=24, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=25, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=25, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=45, i=25, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=26, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=26, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=56, i=26, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=27, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=27, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=38, i=27, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=28, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=28, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=65, i=28, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=29, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=29, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=66, i=29, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=30, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=30, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=39, i=30, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=31, size=32] [L18] EXPR a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=31, size=32] [L18] EXPR, FCALL b[i] VAL [\old(size)=32, b={43:0}, b={43:0}, b[i]=57, i=31, size=32] [L18] a[i] = b[i] [L17] i++ [L17] i++ [L17] COND TRUE i <= size VAL [\old(size)=32, b={43:0}, b={43:0}, i=32, size=32] [L18] a[i] VAL [\old(size)=32, b={43:0}, b={43:0}, i=32, size=32] - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 46 locations, 6 error locations. UNSAFE Result, 761.2s OverallTime, 92 OverallIterations, 591 TraceHistogramMax, 84.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 4106 SDtfs, 38754 SDslu, 53439 SDs, 0 SdLazy, 156531 SolverSat, 4721 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 37.6s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 123427 GetRequests, 117193 SyntacticMatches, 15 SemanticMatches, 6219 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 189906 ImplicationChecksByTransitivity, 77.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=3770occurred in iteration=90, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 91 MinimizatonAttempts, 1185 StatesRemovedByMinimization, 90 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 3.8s SsaConstructionTime, 77.9s SatisfiabilityAnalysisTime, 526.9s InterpolantComputationTime, 240950 NumberOfCodeBlocks, 223752 NumberOfCodeBlocksAsserted, 1335 NumberOfCheckSat, 237031 ConstructedInterpolants, 0 QuantifiedInterpolants, 723942881 SizeOfPredicates, 190 NumberOfNonLiveVariables, 229021 ConjunctsInSsa, 2748 ConjunctsInUnsatCore, 177 InterpolantComputations, 7 PerfectInterpolantSequences, 35364322/35642339 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-11_23-18-58-397.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/ArraysWithLenghtAtDeclaration_false-valid-deref-write.c_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-11_23-18-58-397.csv Received shutdown request...