java -Xmx6000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data ./data --generate-csv --csv-dir ../../../releaseScripts/default/UAutomizer-linux/csv --cacsl2boogietranslator.bitprecise.bitfields false -tc ../../../trunk/examples/toolchains/AutomizerC.xml -s ../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf -i ../../../trunk/examples/svcomp/array-memsafety/lis-alloca_true-valid-memsafety_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-408c70d-m [2018-04-12 10:19:25,520 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-04-12 10:19:25,521 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-04-12 10:19:25,533 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... 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[2018-04-12 10:19:25,556 INFO L98 SettingsManager]: Beginning loading settings from /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/cade18-smtinterpol/svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf [2018-04-12 10:19:25,565 INFO L110 SettingsManager]: Loading preferences was successful [2018-04-12 10:19:25,565 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-04-12 10:19:25,566 INFO L131 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2018-04-12 10:19:25,566 INFO L133 SettingsManager]: * Create parallel compositions if possible=false [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * Use SBE=true [2018-04-12 10:19:25,567 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * sizeof long=4 [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * Check unreachability of error function in SV-COMP mode=false [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * sizeof POINTER=4 [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * Check for the main procedure if all allocated memory was freed=true [2018-04-12 10:19:25,567 INFO L133 SettingsManager]: * Bitprecise bitfields=true [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * sizeof long double=12 [2018-04-12 10:19:25,568 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 10:19:25,568 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * Interpolant automaton=TWOTRACK [2018-04-12 10:19:25,568 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-04-12 10:19:25,569 INFO L133 SettingsManager]: * Trace refinement strategy=CAMEL Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Bitprecise bitfields -> false [2018-04-12 10:19:25,595 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-04-12 10:19:25,602 INFO L266 ainManager$Toolchain]: [Toolchain 1]: Parser(s) successfully (re)initialized [2018-04-12 10:19:25,605 INFO L222 ainManager$Toolchain]: [Toolchain 1]: Toolchain data selected. [2018-04-12 10:19:25,606 INFO L271 PluginConnector]: Initializing CDTParser... [2018-04-12 10:19:25,606 INFO L276 PluginConnector]: CDTParser initialized [2018-04-12 10:19:25,607 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/array-memsafety/lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,885 INFO L225 CDTParser]: Created temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGb5aa46dbb [2018-04-12 10:19:25,986 INFO L287 CDTParser]: IsIndexed: true [2018-04-12 10:19:25,987 INFO L288 CDTParser]: Found 1 translation units. [2018-04-12 10:19:25,987 INFO L168 CDTParser]: Scanning lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,996 INFO L210 ultiparseSymbolTable]: Include resolver: [2018-04-12 10:19:25,996 INFO L215 ultiparseSymbolTable]: [2018-04-12 10:19:25,996 INFO L218 ultiparseSymbolTable]: Function table: [2018-04-12 10:19:25,996 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 ('__bswap_32') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,996 INFO L221 ultiparseSymbolTable]: Function definition of null ('main') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,996 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 ('__bswap_64') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L221 ultiparseSymbolTable]: Function definition of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis ('lis') in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L227 ultiparseSymbolTable]: Global variable table: [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_char in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ulong in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_long in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__blkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_rwlockattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__daddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,997 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__clock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____pthread_list_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_barrierattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ino64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__blksize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_long in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____off_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____caddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ino_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__sigset_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____sigset_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____clockid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__clockid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_spinlock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____suseconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____rlim_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,998 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsblkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_cond_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__div_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fd_mask in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__wchar_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lldiv_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__uid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:25,999 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_char in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____gid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____off64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fd_mask in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____timer_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____id_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_barrier_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____syscall_ulong_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,000 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsblkcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____pid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_mutexattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__register_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__off_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ldiv_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__gid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,001 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsword_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blkcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsfilcnt64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int32_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_attr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__timer_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____ssize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____sig_atomic_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____socklen_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,002 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____nlink_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____mode_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__size_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__nlink_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsfilcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____intptr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__id_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ssize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_once_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__uint in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,003 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_short in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__caddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____clock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____daddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__mode_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__time_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fsid_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__dev_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____key_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____useconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__suseconds_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_short in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____u_int in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____loff_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,004 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__fd_set in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_mutex_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_rwlock_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____syscall_slong_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____dev_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsblkcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____blksize_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____qaddr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int8_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____time_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ino_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__ushort in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__pthread_condattr_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____rlim64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____WAIT_STATUS in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_quad_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__loff_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__u_int64_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,005 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____uint16_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,006 INFO L230 ultiparseSymbolTable]: Global variable declaration of __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____fsfilcnt_t in lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,018 INFO L330 CDTParser]: Deleted temporary CDT project at /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/data/FLAGb5aa46dbb [2018-04-12 10:19:26,021 INFO L304 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-04-12 10:19:26,021 INFO L131 ToolchainWalker]: Walking toolchain with 4 elements. [2018-04-12 10:19:26,022 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-04-12 10:19:26,022 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-04-12 10:19:26,026 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-04-12 10:19:26,026 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,028 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4efed0cb and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26, skipping insertion in model container [2018-04-12 10:19:26,028 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,039 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 10:19:26,057 INFO L167 Dispatcher]: Using SV-COMP mode [2018-04-12 10:19:26,178 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 10:19:26,215 INFO L175 PostProcessor]: Settings: Checked method=main [2018-04-12 10:19:26,221 INFO L100 SccComputation]: Graph consists of 0 InCaSumBalls and 112 non ball SCCs. Number of states in SCCs 112. [2018-04-12 10:19:26,251 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26 WrapperNode [2018-04-12 10:19:26,252 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-04-12 10:19:26,252 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-04-12 10:19:26,252 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-04-12 10:19:26,252 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-04-12 10:19:26,260 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,260 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,271 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,271 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,279 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,284 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,286 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... [2018-04-12 10:19:26,289 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-04-12 10:19:26,290 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-04-12 10:19:26,290 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-04-12 10:19:26,290 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-04-12 10:19:26,291 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (1/1) ... No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-04-12 10:19:26,384 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-04-12 10:19:26,385 INFO L136 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-04-12 10:19:26,385 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-12 10:19:26,385 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-12 10:19:26,385 INFO L136 BoogieDeclarations]: Found implementation of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis [2018-04-12 10:19:26,385 INFO L136 BoogieDeclarations]: Found implementation of procedure main [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_32 [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i____bswap_64 [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure __ctype_get_mb_cur_max [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure atof [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure atoi [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure atol [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure atoll [2018-04-12 10:19:26,385 INFO L128 BoogieDeclarations]: Found specification of procedure strtod [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtof [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtold [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtol [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtoul [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtoq [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtouq [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtoll [2018-04-12 10:19:26,386 INFO L128 BoogieDeclarations]: Found specification of procedure strtoull [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure l64a [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure a64l [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure select [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure pselect [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_major [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_minor [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure gnu_dev_makedev [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure random [2018-04-12 10:19:26,387 INFO L128 BoogieDeclarations]: Found specification of procedure srandom [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure initstate [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure setstate [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure random_r [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure srandom_r [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure initstate_r [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure setstate_r [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure rand [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure srand [2018-04-12 10:19:26,388 INFO L128 BoogieDeclarations]: Found specification of procedure rand_r [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure drand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure erand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure srand48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure seed48 [2018-04-12 10:19:26,389 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48 [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure drand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure erand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure lrand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure nrand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure mrand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure jrand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure srand48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure seed48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure lcong48_r [2018-04-12 10:19:26,390 INFO L128 BoogieDeclarations]: Found specification of procedure malloc [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure calloc [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure realloc [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure free [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure cfree [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure alloca [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure valloc [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure posix_memalign [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure abort [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure atexit [2018-04-12 10:19:26,391 INFO L128 BoogieDeclarations]: Found specification of procedure on_exit [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure exit [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure _Exit [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure getenv [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure putenv [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure setenv [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure unsetenv [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure clearenv [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure mktemp [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemp [2018-04-12 10:19:26,392 INFO L128 BoogieDeclarations]: Found specification of procedure mkstemps [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure mkdtemp [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure system [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure realpath [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure bsearch [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure qsort [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure abs [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure labs [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure llabs [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure div [2018-04-12 10:19:26,393 INFO L128 BoogieDeclarations]: Found specification of procedure ldiv [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure lldiv [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure gcvt [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure qgcvt [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure ecvt_r [2018-04-12 10:19:26,394 INFO L128 BoogieDeclarations]: Found specification of procedure fcvt_r [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure qecvt_r [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure qfcvt_r [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure mblen [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure mbtowc [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure wctomb [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure mbstowcs [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure wcstombs [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure rpmatch [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure getsubopt [2018-04-12 10:19:26,395 INFO L128 BoogieDeclarations]: Found specification of procedure getloadavg [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure __VERIFIER_nondet_int [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lis [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure #Ultimate.alloc [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure write~int [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure read~int [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.dealloc [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure main [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-04-12 10:19:26,396 INFO L128 BoogieDeclarations]: Found specification of procedure write~unchecked~int [2018-04-12 10:19:26,719 INFO L259 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-04-12 10:19:26,719 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 10:19:26 BoogieIcfgContainer [2018-04-12 10:19:26,719 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-04-12 10:19:26,720 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-04-12 10:19:26,720 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-04-12 10:19:26,721 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-04-12 10:19:26,722 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 12.04 10:19:26" (1/3) ... [2018-04-12 10:19:26,722 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a7a3da8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 10:19:26, skipping insertion in model container [2018-04-12 10:19:26,722 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 12.04 10:19:26" (2/3) ... [2018-04-12 10:19:26,722 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@2a7a3da8 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 12.04 10:19:26, skipping insertion in model container [2018-04-12 10:19:26,722 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 12.04 10:19:26" (3/3) ... [2018-04-12 10:19:26,724 INFO L107 eAbstractionObserver]: Analyzing ICFG lis-alloca_true-valid-memsafety_true-termination.i [2018-04-12 10:19:26,729 INFO L131 ceAbstractionStarter]: Automizer settings: Hoare:false NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-04-12 10:19:26,735 INFO L143 ceAbstractionStarter]: Appying trace abstraction to program that has 23 error locations. [2018-04-12 10:19:26,759 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-04-12 10:19:26,760 INFO L369 AbstractCegarLoop]: Interprodecural is true [2018-04-12 10:19:26,760 INFO L370 AbstractCegarLoop]: Hoare is false [2018-04-12 10:19:26,760 INFO L371 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-04-12 10:19:26,760 INFO L372 AbstractCegarLoop]: Backedges is TWOTRACK [2018-04-12 10:19:26,760 INFO L373 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-04-12 10:19:26,760 INFO L374 AbstractCegarLoop]: Difference is false [2018-04-12 10:19:26,760 INFO L375 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-04-12 10:19:26,760 INFO L380 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-04-12 10:19:26,761 INFO L87 2NestedWordAutomaton]: Mode: main mode - execution starts in main procedure [2018-04-12 10:19:26,771 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states. [2018-04-12 10:19:26,777 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-04-12 10:19:26,777 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:26,778 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:26,778 INFO L408 AbstractCegarLoop]: === Iteration 1 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:26,781 INFO L82 PathProgramCache]: Analyzing trace with hash 903315809, now seen corresponding path program 1 times [2018-04-12 10:19:26,782 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:26,782 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:26,811 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:26,812 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:26,812 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:26,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:26,858 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:26,941 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:26,943 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:26,944 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 10:19:26,945 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 10:19:26,953 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 10:19:26,954 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 10:19:26,956 INFO L87 Difference]: Start difference. First operand 84 states. Second operand 4 states. [2018-04-12 10:19:27,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:27,058 INFO L93 Difference]: Finished difference Result 77 states and 84 transitions. [2018-04-12 10:19:27,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 10:19:27,060 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 18 [2018-04-12 10:19:27,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:27,067 INFO L225 Difference]: With dead ends: 77 [2018-04-12 10:19:27,067 INFO L226 Difference]: Without dead ends: 74 [2018-04-12 10:19:27,068 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 10:19:27,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 74 states. [2018-04-12 10:19:27,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 74 to 74. [2018-04-12 10:19:27,097 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 74 states. [2018-04-12 10:19:27,099 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74 states to 74 states and 81 transitions. [2018-04-12 10:19:27,100 INFO L78 Accepts]: Start accepts. Automaton has 74 states and 81 transitions. Word has length 18 [2018-04-12 10:19:27,100 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:27,100 INFO L459 AbstractCegarLoop]: Abstraction has 74 states and 81 transitions. [2018-04-12 10:19:27,100 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 10:19:27,100 INFO L276 IsEmpty]: Start isEmpty. Operand 74 states and 81 transitions. [2018-04-12 10:19:27,101 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 19 [2018-04-12 10:19:27,101 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:27,101 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:27,101 INFO L408 AbstractCegarLoop]: === Iteration 2 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:27,101 INFO L82 PathProgramCache]: Analyzing trace with hash 903315810, now seen corresponding path program 1 times [2018-04-12 10:19:27,102 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:27,102 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:27,103 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,103 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:27,103 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:27,117 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:27,166 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:27,166 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:27,166 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-04-12 10:19:27,168 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 10:19:27,168 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 10:19:27,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-12 10:19:27,169 INFO L87 Difference]: Start difference. First operand 74 states and 81 transitions. Second operand 6 states. [2018-04-12 10:19:27,381 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:27,381 INFO L93 Difference]: Finished difference Result 96 states and 106 transitions. [2018-04-12 10:19:27,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-04-12 10:19:27,382 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 18 [2018-04-12 10:19:27,382 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:27,385 INFO L225 Difference]: With dead ends: 96 [2018-04-12 10:19:27,385 INFO L226 Difference]: Without dead ends: 96 [2018-04-12 10:19:27,386 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 9 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=28, Invalid=44, Unknown=0, NotChecked=0, Total=72 [2018-04-12 10:19:27,386 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-04-12 10:19:27,390 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 82. [2018-04-12 10:19:27,391 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 82 states. [2018-04-12 10:19:27,392 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 82 states to 82 states and 92 transitions. [2018-04-12 10:19:27,392 INFO L78 Accepts]: Start accepts. Automaton has 82 states and 92 transitions. Word has length 18 [2018-04-12 10:19:27,392 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:27,392 INFO L459 AbstractCegarLoop]: Abstraction has 82 states and 92 transitions. [2018-04-12 10:19:27,393 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 10:19:27,393 INFO L276 IsEmpty]: Start isEmpty. Operand 82 states and 92 transitions. [2018-04-12 10:19:27,393 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-04-12 10:19:27,393 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:27,393 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:27,394 INFO L408 AbstractCegarLoop]: === Iteration 3 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:27,394 INFO L82 PathProgramCache]: Analyzing trace with hash -2061980982, now seen corresponding path program 1 times [2018-04-12 10:19:27,394 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:27,394 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:27,395 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,395 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:27,395 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:27,407 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:27,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:27,435 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:27,435 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 10:19:27,435 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 10:19:27,436 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 10:19:27,436 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-04-12 10:19:27,436 INFO L87 Difference]: Start difference. First operand 82 states and 92 transitions. Second operand 4 states. [2018-04-12 10:19:27,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:27,475 INFO L93 Difference]: Finished difference Result 80 states and 90 transitions. [2018-04-12 10:19:27,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 10:19:27,476 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 19 [2018-04-12 10:19:27,476 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:27,476 INFO L225 Difference]: With dead ends: 80 [2018-04-12 10:19:27,477 INFO L226 Difference]: Without dead ends: 80 [2018-04-12 10:19:27,477 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=9, Invalid=11, Unknown=0, NotChecked=0, Total=20 [2018-04-12 10:19:27,477 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80 states. [2018-04-12 10:19:27,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80 to 80. [2018-04-12 10:19:27,480 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 80 states. [2018-04-12 10:19:27,480 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80 states to 80 states and 90 transitions. [2018-04-12 10:19:27,481 INFO L78 Accepts]: Start accepts. Automaton has 80 states and 90 transitions. Word has length 19 [2018-04-12 10:19:27,481 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:27,481 INFO L459 AbstractCegarLoop]: Abstraction has 80 states and 90 transitions. [2018-04-12 10:19:27,481 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 10:19:27,481 INFO L276 IsEmpty]: Start isEmpty. Operand 80 states and 90 transitions. [2018-04-12 10:19:27,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-04-12 10:19:27,481 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:27,481 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:27,482 INFO L408 AbstractCegarLoop]: === Iteration 4 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:27,482 INFO L82 PathProgramCache]: Analyzing trace with hash -2061980981, now seen corresponding path program 1 times [2018-04-12 10:19:27,482 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:27,482 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:27,482 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,483 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:27,483 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:27,491 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:27,548 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:27,548 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:27,548 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-12 10:19:27,548 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 10:19:27,548 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 10:19:27,548 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-04-12 10:19:27,549 INFO L87 Difference]: Start difference. First operand 80 states and 90 transitions. Second operand 8 states. [2018-04-12 10:19:27,712 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:27,712 INFO L93 Difference]: Finished difference Result 97 states and 110 transitions. [2018-04-12 10:19:27,713 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 10:19:27,713 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 19 [2018-04-12 10:19:27,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:27,713 INFO L225 Difference]: With dead ends: 97 [2018-04-12 10:19:27,713 INFO L226 Difference]: Without dead ends: 97 [2018-04-12 10:19:27,714 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=64, Invalid=118, Unknown=0, NotChecked=0, Total=182 [2018-04-12 10:19:27,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-04-12 10:19:27,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 78. [2018-04-12 10:19:27,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-04-12 10:19:27,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 88 transitions. [2018-04-12 10:19:27,719 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 88 transitions. Word has length 19 [2018-04-12 10:19:27,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:27,719 INFO L459 AbstractCegarLoop]: Abstraction has 78 states and 88 transitions. [2018-04-12 10:19:27,719 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 10:19:27,719 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 88 transitions. [2018-04-12 10:19:27,720 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 10:19:27,720 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:27,720 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:27,720 INFO L408 AbstractCegarLoop]: === Iteration 5 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:27,720 INFO L82 PathProgramCache]: Analyzing trace with hash 1233215310, now seen corresponding path program 1 times [2018-04-12 10:19:27,720 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:27,720 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:27,721 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:27,721 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:27,729 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:27,755 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:27,755 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:27,756 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 10:19:27,756 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 10:19:27,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 10:19:27,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9, Invalid=21, Unknown=0, NotChecked=0, Total=30 [2018-04-12 10:19:27,756 INFO L87 Difference]: Start difference. First operand 78 states and 88 transitions. Second operand 6 states. [2018-04-12 10:19:27,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:27,819 INFO L93 Difference]: Finished difference Result 128 states and 144 transitions. [2018-04-12 10:19:27,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 10:19:27,819 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-04-12 10:19:27,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:27,820 INFO L225 Difference]: With dead ends: 128 [2018-04-12 10:19:27,820 INFO L226 Difference]: Without dead ends: 128 [2018-04-12 10:19:27,820 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-12 10:19:27,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states. [2018-04-12 10:19:27,823 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 120. [2018-04-12 10:19:27,823 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-04-12 10:19:27,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 140 transitions. [2018-04-12 10:19:27,824 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 140 transitions. Word has length 23 [2018-04-12 10:19:27,824 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:27,824 INFO L459 AbstractCegarLoop]: Abstraction has 120 states and 140 transitions. [2018-04-12 10:19:27,824 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 10:19:27,825 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 140 transitions. [2018-04-12 10:19:27,825 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 10:19:27,825 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:27,825 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:27,825 INFO L408 AbstractCegarLoop]: === Iteration 6 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:27,825 INFO L82 PathProgramCache]: Analyzing trace with hash -1613164609, now seen corresponding path program 1 times [2018-04-12 10:19:27,825 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:27,825 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:27,826 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,826 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:27,826 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:27,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:27,834 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:27,887 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 1 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:27,888 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:27,888 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:27,893 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:27,914 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:27,920 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:27,972 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:27,990 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 1 imperfect interpolant sequences. [2018-04-12 10:19:27,990 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [9] total 11 [2018-04-12 10:19:27,990 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 10:19:27,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 10:19:27,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=25, Invalid=85, Unknown=0, NotChecked=0, Total=110 [2018-04-12 10:19:27,990 INFO L87 Difference]: Start difference. First operand 120 states and 140 transitions. Second operand 11 states. [2018-04-12 10:19:28,156 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:28,156 INFO L93 Difference]: Finished difference Result 126 states and 138 transitions. [2018-04-12 10:19:28,156 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-04-12 10:19:28,156 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 23 [2018-04-12 10:19:28,156 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:28,157 INFO L225 Difference]: With dead ends: 126 [2018-04-12 10:19:28,157 INFO L226 Difference]: Without dead ends: 126 [2018-04-12 10:19:28,158 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 39 GetRequests, 21 SyntacticMatches, 1 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=105, Invalid=237, Unknown=0, NotChecked=0, Total=342 [2018-04-12 10:19:28,158 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126 states. [2018-04-12 10:19:28,162 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126 to 113. [2018-04-12 10:19:28,163 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 10:19:28,164 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 126 transitions. [2018-04-12 10:19:28,164 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 126 transitions. Word has length 23 [2018-04-12 10:19:28,164 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:28,164 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 126 transitions. [2018-04-12 10:19:28,164 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 10:19:28,164 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 126 transitions. [2018-04-12 10:19:28,165 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 10:19:28,165 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:28,165 INFO L355 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:28,165 INFO L408 AbstractCegarLoop]: === Iteration 7 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:28,165 INFO L82 PathProgramCache]: Analyzing trace with hash -355132592, now seen corresponding path program 1 times [2018-04-12 10:19:28,165 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:28,165 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:28,166 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:28,166 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:28,167 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:28,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:28,174 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:28,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:28,211 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:28,211 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-04-12 10:19:28,211 INFO L442 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-04-12 10:19:28,211 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-04-12 10:19:28,211 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-04-12 10:19:28,212 INFO L87 Difference]: Start difference. First operand 113 states and 126 transitions. Second operand 6 states. [2018-04-12 10:19:28,261 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:28,261 INFO L93 Difference]: Finished difference Result 117 states and 126 transitions. [2018-04-12 10:19:28,261 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-04-12 10:19:28,261 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 23 [2018-04-12 10:19:28,261 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:28,262 INFO L225 Difference]: With dead ends: 117 [2018-04-12 10:19:28,262 INFO L226 Difference]: Without dead ends: 117 [2018-04-12 10:19:28,262 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 8 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=20, Invalid=36, Unknown=0, NotChecked=0, Total=56 [2018-04-12 10:19:28,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-04-12 10:19:28,266 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 113. [2018-04-12 10:19:28,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 113 states. [2018-04-12 10:19:28,267 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 113 states to 113 states and 122 transitions. [2018-04-12 10:19:28,267 INFO L78 Accepts]: Start accepts. Automaton has 113 states and 122 transitions. Word has length 23 [2018-04-12 10:19:28,267 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:28,267 INFO L459 AbstractCegarLoop]: Abstraction has 113 states and 122 transitions. [2018-04-12 10:19:28,267 INFO L460 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-04-12 10:19:28,267 INFO L276 IsEmpty]: Start isEmpty. Operand 113 states and 122 transitions. [2018-04-12 10:19:28,268 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-04-12 10:19:28,268 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:28,268 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:28,268 INFO L408 AbstractCegarLoop]: === Iteration 8 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:28,268 INFO L82 PathProgramCache]: Analyzing trace with hash 1093454785, now seen corresponding path program 1 times [2018-04-12 10:19:28,269 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:28,269 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:28,269 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:28,269 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:28,269 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:28,279 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:28,279 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:28,343 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:28,343 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:28,343 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:28,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:28,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:28,362 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:28,379 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 10:19:28,380 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:28,385 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 10:19:28,385 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:28,388 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:28,389 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-12 10:19:28,408 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:28,409 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:28,409 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 10:19:28,410 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:28,415 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 10:19:28,416 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:28,425 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:28,425 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:29, output treesize:22 [2018-04-12 10:19:28,539 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 2 proven. 1 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:28,567 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 10:19:28,567 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 7] total 12 [2018-04-12 10:19:28,567 INFO L442 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-04-12 10:19:28,568 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-04-12 10:19:28,568 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-04-12 10:19:28,568 INFO L87 Difference]: Start difference. First operand 113 states and 122 transitions. Second operand 13 states. [2018-04-12 10:19:28,916 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:28,916 INFO L93 Difference]: Finished difference Result 112 states and 121 transitions. [2018-04-12 10:19:28,916 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-04-12 10:19:28,917 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 23 [2018-04-12 10:19:28,917 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:28,917 INFO L225 Difference]: With dead ends: 112 [2018-04-12 10:19:28,917 INFO L226 Difference]: Without dead ends: 112 [2018-04-12 10:19:28,917 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 18 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 44 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=114, Invalid=266, Unknown=0, NotChecked=0, Total=380 [2018-04-12 10:19:28,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-04-12 10:19:28,920 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 104. [2018-04-12 10:19:28,920 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 104 states. [2018-04-12 10:19:28,921 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 104 states to 104 states and 112 transitions. [2018-04-12 10:19:28,921 INFO L78 Accepts]: Start accepts. Automaton has 104 states and 112 transitions. Word has length 23 [2018-04-12 10:19:28,922 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:28,922 INFO L459 AbstractCegarLoop]: Abstraction has 104 states and 112 transitions. [2018-04-12 10:19:28,922 INFO L460 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-04-12 10:19:28,922 INFO L276 IsEmpty]: Start isEmpty. Operand 104 states and 112 transitions. [2018-04-12 10:19:28,923 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-04-12 10:19:28,923 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:28,923 INFO L355 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:28,923 INFO L408 AbstractCegarLoop]: === Iteration 9 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:28,923 INFO L82 PathProgramCache]: Analyzing trace with hash -200886193, now seen corresponding path program 1 times [2018-04-12 10:19:28,923 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:28,923 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:28,924 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:28,924 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:28,924 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:28,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:28,932 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:28,958 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:28,958 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:28,959 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:28,964 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:28,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:28,982 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:28,998 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:29,025 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 10:19:29,025 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6] total 8 [2018-04-12 10:19:29,025 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 10:19:29,025 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 10:19:29,026 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-04-12 10:19:29,026 INFO L87 Difference]: Start difference. First operand 104 states and 112 transitions. Second operand 8 states. [2018-04-12 10:19:29,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:29,125 INFO L93 Difference]: Finished difference Result 176 states and 193 transitions. [2018-04-12 10:19:29,125 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 10:19:29,125 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 28 [2018-04-12 10:19:29,125 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:29,126 INFO L225 Difference]: With dead ends: 176 [2018-04-12 10:19:29,126 INFO L226 Difference]: Without dead ends: 176 [2018-04-12 10:19:29,127 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 36 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=36, Invalid=74, Unknown=0, NotChecked=0, Total=110 [2018-04-12 10:19:29,127 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 176 states. [2018-04-12 10:19:29,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 176 to 124. [2018-04-12 10:19:29,131 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 124 states. [2018-04-12 10:19:29,132 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 124 states to 124 states and 135 transitions. [2018-04-12 10:19:29,132 INFO L78 Accepts]: Start accepts. Automaton has 124 states and 135 transitions. Word has length 28 [2018-04-12 10:19:29,133 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:29,133 INFO L459 AbstractCegarLoop]: Abstraction has 124 states and 135 transitions. [2018-04-12 10:19:29,133 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 10:19:29,133 INFO L276 IsEmpty]: Start isEmpty. Operand 124 states and 135 transitions. [2018-04-12 10:19:29,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-12 10:19:29,134 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:29,134 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:29,134 INFO L408 AbstractCegarLoop]: === Iteration 10 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:29,134 INFO L82 PathProgramCache]: Analyzing trace with hash -392535376, now seen corresponding path program 2 times [2018-04-12 10:19:29,134 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:29,134 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:29,135 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:29,135 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:29,135 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:29,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:29,146 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:29,254 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-04-12 10:19:29,254 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:29,254 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-04-12 10:19:29,255 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 10:19:29,255 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 10:19:29,255 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-04-12 10:19:29,255 INFO L87 Difference]: Start difference. First operand 124 states and 135 transitions. Second operand 11 states. [2018-04-12 10:19:29,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:29,341 INFO L93 Difference]: Finished difference Result 122 states and 133 transitions. [2018-04-12 10:19:29,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-04-12 10:19:29,341 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 33 [2018-04-12 10:19:29,341 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:29,342 INFO L225 Difference]: With dead ends: 122 [2018-04-12 10:19:29,342 INFO L226 Difference]: Without dead ends: 122 [2018-04-12 10:19:29,343 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 2 SyntacticMatches, 2 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-04-12 10:19:29,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 122 states. [2018-04-12 10:19:29,345 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 122 to 122. [2018-04-12 10:19:29,345 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 122 states. [2018-04-12 10:19:29,346 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 122 states to 122 states and 133 transitions. [2018-04-12 10:19:29,346 INFO L78 Accepts]: Start accepts. Automaton has 122 states and 133 transitions. Word has length 33 [2018-04-12 10:19:29,346 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:29,346 INFO L459 AbstractCegarLoop]: Abstraction has 122 states and 133 transitions. [2018-04-12 10:19:29,346 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 10:19:29,347 INFO L276 IsEmpty]: Start isEmpty. Operand 122 states and 133 transitions. [2018-04-12 10:19:29,347 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-04-12 10:19:29,347 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:29,348 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:29,348 INFO L408 AbstractCegarLoop]: === Iteration 11 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:29,348 INFO L82 PathProgramCache]: Analyzing trace with hash -392535375, now seen corresponding path program 1 times [2018-04-12 10:19:29,348 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:29,348 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:29,349 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:29,349 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-04-12 10:19:29,349 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:29,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:29,362 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:29,559 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:29,559 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:29,559 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:29,565 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:29,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:29,579 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:29,581 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 10:19:29,582 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,587 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 10:19:29,587 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,593 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,593 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-12 10:19:29,696 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:29,697 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:29,697 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-12 10:19:29,697 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,707 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 10:19:29,707 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,714 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-0 vars, 2 dim-1 vars, End of recursive call: 1 dim-0 vars, and 1 xjuncts. [2018-04-12 10:19:29,714 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:38, output treesize:35 [2018-04-12 10:19:29,768 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:29,769 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:29,769 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:29,770 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-04-12 10:19:29,770 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,781 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 34 [2018-04-12 10:19:29,782 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:29,790 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 10:19:29,790 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:48, output treesize:40 [2018-04-12 10:19:30,035 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 2 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:30,054 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 10:19:30,054 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12] total 24 [2018-04-12 10:19:30,054 INFO L442 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-04-12 10:19:30,054 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-04-12 10:19:30,055 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=68, Invalid=532, Unknown=0, NotChecked=0, Total=600 [2018-04-12 10:19:30,055 INFO L87 Difference]: Start difference. First operand 122 states and 133 transitions. Second operand 25 states. [2018-04-12 10:19:31,349 WARN L151 SmtUtils]: Spent 328ms on a formula simplification. DAG size of input: 71 DAG size of output 56 [2018-04-12 10:19:31,790 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:31,790 INFO L93 Difference]: Finished difference Result 153 states and 167 transitions. [2018-04-12 10:19:31,807 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-04-12 10:19:31,807 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 33 [2018-04-12 10:19:31,808 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:31,808 INFO L225 Difference]: With dead ends: 153 [2018-04-12 10:19:31,808 INFO L226 Difference]: Without dead ends: 153 [2018-04-12 10:19:31,809 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 62 GetRequests, 22 SyntacticMatches, 1 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 290 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=330, Invalid=1310, Unknown=0, NotChecked=0, Total=1640 [2018-04-12 10:19:31,810 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 153 states. [2018-04-12 10:19:31,812 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 153 to 137. [2018-04-12 10:19:31,813 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-04-12 10:19:31,813 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 153 transitions. [2018-04-12 10:19:31,813 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 153 transitions. Word has length 33 [2018-04-12 10:19:31,813 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:31,813 INFO L459 AbstractCegarLoop]: Abstraction has 137 states and 153 transitions. [2018-04-12 10:19:31,814 INFO L460 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-04-12 10:19:31,814 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 153 transitions. [2018-04-12 10:19:31,814 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-04-12 10:19:31,815 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:31,815 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:31,815 INFO L408 AbstractCegarLoop]: === Iteration 12 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:31,815 INFO L82 PathProgramCache]: Analyzing trace with hash 716305274, now seen corresponding path program 1 times [2018-04-12 10:19:31,815 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:31,815 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:31,816 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:31,816 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:31,816 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:31,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:31,825 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:31,869 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 10:19:31,870 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:31,870 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [8] imperfect sequences [] total 8 [2018-04-12 10:19:31,870 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 10:19:31,870 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 10:19:31,870 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-04-12 10:19:31,870 INFO L87 Difference]: Start difference. First operand 137 states and 153 transitions. Second operand 9 states. [2018-04-12 10:19:31,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:31,946 INFO L93 Difference]: Finished difference Result 190 states and 217 transitions. [2018-04-12 10:19:31,946 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 10:19:31,946 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-04-12 10:19:31,947 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:31,947 INFO L225 Difference]: With dead ends: 190 [2018-04-12 10:19:31,947 INFO L226 Difference]: Without dead ends: 190 [2018-04-12 10:19:31,947 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=52, Invalid=130, Unknown=0, NotChecked=0, Total=182 [2018-04-12 10:19:31,948 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2018-04-12 10:19:31,949 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 145. [2018-04-12 10:19:31,949 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-04-12 10:19:31,950 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 164 transitions. [2018-04-12 10:19:31,950 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 164 transitions. Word has length 34 [2018-04-12 10:19:31,950 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:31,950 INFO L459 AbstractCegarLoop]: Abstraction has 145 states and 164 transitions. [2018-04-12 10:19:31,950 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 10:19:31,950 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 164 transitions. [2018-04-12 10:19:31,951 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 10:19:31,951 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:31,951 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:31,951 INFO L408 AbstractCegarLoop]: === Iteration 13 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:31,951 INFO L82 PathProgramCache]: Analyzing trace with hash -1431404189, now seen corresponding path program 1 times [2018-04-12 10:19:31,951 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:31,951 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:31,951 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:31,952 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:31,952 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:31,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:31,960 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:31,980 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 10:19:31,980 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:31,980 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [4] imperfect sequences [] total 4 [2018-04-12 10:19:31,980 INFO L442 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-04-12 10:19:31,981 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-04-12 10:19:31,981 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-04-12 10:19:31,981 INFO L87 Difference]: Start difference. First operand 145 states and 164 transitions. Second operand 4 states. [2018-04-12 10:19:32,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:32,033 INFO L93 Difference]: Finished difference Result 162 states and 179 transitions. [2018-04-12 10:19:32,033 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-04-12 10:19:32,033 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 38 [2018-04-12 10:19:32,033 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:32,034 INFO L225 Difference]: With dead ends: 162 [2018-04-12 10:19:32,034 INFO L226 Difference]: Without dead ends: 162 [2018-04-12 10:19:32,034 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 5 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=6, Invalid=6, Unknown=0, NotChecked=0, Total=12 [2018-04-12 10:19:32,035 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-04-12 10:19:32,037 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 145. [2018-04-12 10:19:32,037 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-04-12 10:19:32,038 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 163 transitions. [2018-04-12 10:19:32,038 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 163 transitions. Word has length 38 [2018-04-12 10:19:32,038 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:32,038 INFO L459 AbstractCegarLoop]: Abstraction has 145 states and 163 transitions. [2018-04-12 10:19:32,038 INFO L460 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-04-12 10:19:32,038 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 163 transitions. [2018-04-12 10:19:32,039 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 10:19:32,039 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:32,039 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:32,039 INFO L408 AbstractCegarLoop]: === Iteration 14 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:32,039 INFO L82 PathProgramCache]: Analyzing trace with hash -784439033, now seen corresponding path program 1 times [2018-04-12 10:19:32,039 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:32,040 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:32,040 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,040 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:32,040 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,047 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:32,047 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:32,061 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 10:19:32,061 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:32,061 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-04-12 10:19:32,061 INFO L442 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-04-12 10:19:32,061 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-04-12 10:19:32,062 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 10:19:32,062 INFO L87 Difference]: Start difference. First operand 145 states and 163 transitions. Second operand 3 states. [2018-04-12 10:19:32,068 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:32,068 INFO L93 Difference]: Finished difference Result 147 states and 165 transitions. [2018-04-12 10:19:32,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-04-12 10:19:32,068 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 38 [2018-04-12 10:19:32,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:32,069 INFO L225 Difference]: With dead ends: 147 [2018-04-12 10:19:32,069 INFO L226 Difference]: Without dead ends: 147 [2018-04-12 10:19:32,070 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-04-12 10:19:32,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-04-12 10:19:32,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-04-12 10:19:32,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-04-12 10:19:32,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 165 transitions. [2018-04-12 10:19:32,073 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 165 transitions. Word has length 38 [2018-04-12 10:19:32,074 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:32,074 INFO L459 AbstractCegarLoop]: Abstraction has 147 states and 165 transitions. [2018-04-12 10:19:32,074 INFO L460 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-04-12 10:19:32,074 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 165 transitions. [2018-04-12 10:19:32,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-04-12 10:19:32,074 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:32,075 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:32,075 INFO L408 AbstractCegarLoop]: === Iteration 15 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:32,075 INFO L82 PathProgramCache]: Analyzing trace with hash -784448064, now seen corresponding path program 1 times [2018-04-12 10:19:32,075 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:32,075 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:32,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:32,076 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,083 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:32,084 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:32,180 INFO L134 CoverageAnalysis]: Checked inductivity of 9 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 10:19:32,180 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:32,180 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [] total 10 [2018-04-12 10:19:32,181 INFO L442 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-04-12 10:19:32,181 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-04-12 10:19:32,181 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=23, Invalid=87, Unknown=0, NotChecked=0, Total=110 [2018-04-12 10:19:32,181 INFO L87 Difference]: Start difference. First operand 147 states and 165 transitions. Second operand 11 states. [2018-04-12 10:19:32,316 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:32,316 INFO L93 Difference]: Finished difference Result 147 states and 163 transitions. [2018-04-12 10:19:32,316 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-04-12 10:19:32,317 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 38 [2018-04-12 10:19:32,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:32,317 INFO L225 Difference]: With dead ends: 147 [2018-04-12 10:19:32,317 INFO L226 Difference]: Without dead ends: 147 [2018-04-12 10:19:32,318 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 18 GetRequests, 1 SyntacticMatches, 0 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-04-12 10:19:32,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-04-12 10:19:32,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 145. [2018-04-12 10:19:32,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 145 states. [2018-04-12 10:19:32,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 145 states to 145 states and 161 transitions. [2018-04-12 10:19:32,321 INFO L78 Accepts]: Start accepts. Automaton has 145 states and 161 transitions. Word has length 38 [2018-04-12 10:19:32,321 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:32,321 INFO L459 AbstractCegarLoop]: Abstraction has 145 states and 161 transitions. [2018-04-12 10:19:32,322 INFO L460 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-04-12 10:19:32,322 INFO L276 IsEmpty]: Start isEmpty. Operand 145 states and 161 transitions. [2018-04-12 10:19:32,322 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-04-12 10:19:32,322 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:32,322 INFO L355 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:32,323 INFO L408 AbstractCegarLoop]: === Iteration 16 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:32,323 INFO L82 PathProgramCache]: Analyzing trace with hash -545854832, now seen corresponding path program 1 times [2018-04-12 10:19:32,323 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:32,323 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:32,323 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,324 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:32,324 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:32,332 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:32,387 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 4 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-04-12 10:19:32,387 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:32,387 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [9] imperfect sequences [] total 9 [2018-04-12 10:19:32,388 INFO L442 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-04-12 10:19:32,388 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-04-12 10:19:32,388 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-04-12 10:19:32,388 INFO L87 Difference]: Start difference. First operand 145 states and 161 transitions. Second operand 9 states. [2018-04-12 10:19:32,455 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:32,455 INFO L93 Difference]: Finished difference Result 144 states and 158 transitions. [2018-04-12 10:19:32,455 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 10:19:32,455 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 42 [2018-04-12 10:19:32,455 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:32,456 INFO L225 Difference]: With dead ends: 144 [2018-04-12 10:19:32,456 INFO L226 Difference]: Without dead ends: 144 [2018-04-12 10:19:32,456 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 15 GetRequests, 1 SyntacticMatches, 2 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=53, Invalid=129, Unknown=0, NotChecked=0, Total=182 [2018-04-12 10:19:32,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144 states. [2018-04-12 10:19:32,458 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144 to 143. [2018-04-12 10:19:32,458 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-12 10:19:32,459 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 157 transitions. [2018-04-12 10:19:32,459 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 157 transitions. Word has length 42 [2018-04-12 10:19:32,459 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:32,459 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 157 transitions. [2018-04-12 10:19:32,459 INFO L460 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-04-12 10:19:32,459 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 157 transitions. [2018-04-12 10:19:32,459 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-04-12 10:19:32,459 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:32,460 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:32,460 INFO L408 AbstractCegarLoop]: === Iteration 17 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:32,460 INFO L82 PathProgramCache]: Analyzing trace with hash -192166533, now seen corresponding path program 1 times [2018-04-12 10:19:32,460 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:32,460 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:32,461 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,461 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:32,461 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:32,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:32,469 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:32,703 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:32,704 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:32,704 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:32,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:32,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:32,721 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:32,728 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 10:19:32,729 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,730 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,731 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:10, output treesize:9 [2018-04-12 10:19:32,750 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:32,750 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:32,751 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 4 [2018-04-12 10:19:32,751 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,753 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,753 INFO L202 ElimStorePlain]: Needed 2 recursive calls to eliminate 1 variables, input treesize:14, output treesize:8 [2018-04-12 10:19:32,774 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 15 treesize of output 12 [2018-04-12 10:19:32,776 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 12 treesize of output 11 [2018-04-12 10:19:32,776 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,777 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,780 INFO L267 ElimStorePlain]: Start of recursive call 1: 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,780 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 1 variables, input treesize:26, output treesize:22 [2018-04-12 10:19:32,799 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 1 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 1 new quantified variables, introduced 0 case distinctions, treesize of input 19 treesize of output 20 [2018-04-12 10:19:32,800 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 10:19:32,800 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,803 INFO L267 ElimStorePlain]: Start of recursive call 2: 1 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,807 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 1 dim-2 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 10:19:32,807 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 3 variables, input treesize:26, output treesize:22 [2018-04-12 10:19:32,852 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 2, 0 stores, 2 select indices, 2 select index equivalence classes, 1 disjoint index pairs (out of 1 index pairs), introduced 2 new quantified variables, introduced 0 case distinctions, treesize of input 22 treesize of output 20 [2018-04-12 10:19:32,855 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 5 treesize of output 1 [2018-04-12 10:19:32,855 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,859 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 1 select indices, 1 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 11 treesize of output 3 [2018-04-12 10:19:32,859 INFO L267 ElimStorePlain]: Start of recursive call 4: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,860 INFO L267 ElimStorePlain]: Start of recursive call 2: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,863 INFO L267 ElimStorePlain]: Start of recursive call 1: 4 dim-0 vars, 1 dim-2 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:32,863 INFO L202 ElimStorePlain]: Needed 4 recursive calls to eliminate 5 variables, input treesize:29, output treesize:7 [2018-04-12 10:19:32,884 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 2 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:32,902 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 10:19:32,903 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11] total 24 [2018-04-12 10:19:32,903 INFO L442 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-04-12 10:19:32,903 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-04-12 10:19:32,903 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=76, Invalid=476, Unknown=0, NotChecked=0, Total=552 [2018-04-12 10:19:32,903 INFO L87 Difference]: Start difference. First operand 143 states and 157 transitions. Second operand 24 states. [2018-04-12 10:19:34,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:34,078 INFO L93 Difference]: Finished difference Result 245 states and 272 transitions. [2018-04-12 10:19:34,078 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-04-12 10:19:34,078 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 44 [2018-04-12 10:19:34,078 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:34,080 INFO L225 Difference]: With dead ends: 245 [2018-04-12 10:19:34,080 INFO L226 Difference]: Without dead ends: 245 [2018-04-12 10:19:34,081 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 86 GetRequests, 37 SyntacticMatches, 1 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 505 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=606, Invalid=1844, Unknown=0, NotChecked=0, Total=2450 [2018-04-12 10:19:34,081 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245 states. [2018-04-12 10:19:34,085 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245 to 143. [2018-04-12 10:19:34,085 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 143 states. [2018-04-12 10:19:34,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 143 states to 143 states and 155 transitions. [2018-04-12 10:19:34,085 INFO L78 Accepts]: Start accepts. Automaton has 143 states and 155 transitions. Word has length 44 [2018-04-12 10:19:34,085 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:34,086 INFO L459 AbstractCegarLoop]: Abstraction has 143 states and 155 transitions. [2018-04-12 10:19:34,086 INFO L460 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-04-12 10:19:34,086 INFO L276 IsEmpty]: Start isEmpty. Operand 143 states and 155 transitions. [2018-04-12 10:19:34,086 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-12 10:19:34,086 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:34,086 INFO L355 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:34,086 INFO L408 AbstractCegarLoop]: === Iteration 18 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:34,086 INFO L82 PathProgramCache]: Analyzing trace with hash 2143854456, now seen corresponding path program 1 times [2018-04-12 10:19:34,086 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:34,086 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:34,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:34,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:34,087 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:34,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:34,096 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:34,217 INFO L134 CoverageAnalysis]: Checked inductivity of 4 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-04-12 10:19:34,217 INFO L320 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-04-12 10:19:34,217 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [7] imperfect sequences [] total 7 [2018-04-12 10:19:34,218 INFO L442 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-04-12 10:19:34,218 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-04-12 10:19:34,218 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=42, Unknown=0, NotChecked=0, Total=56 [2018-04-12 10:19:34,218 INFO L87 Difference]: Start difference. First operand 143 states and 155 transitions. Second operand 8 states. [2018-04-12 10:19:34,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:34,330 INFO L93 Difference]: Finished difference Result 142 states and 154 transitions. [2018-04-12 10:19:34,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-04-12 10:19:34,330 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 46 [2018-04-12 10:19:34,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:34,331 INFO L225 Difference]: With dead ends: 142 [2018-04-12 10:19:34,331 INFO L226 Difference]: Without dead ends: 73 [2018-04-12 10:19:34,331 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 13 GetRequests, 3 SyntacticMatches, 1 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-04-12 10:19:34,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-04-12 10:19:34,332 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 73. [2018-04-12 10:19:34,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 73 states. [2018-04-12 10:19:34,333 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73 states to 73 states and 81 transitions. [2018-04-12 10:19:34,333 INFO L78 Accepts]: Start accepts. Automaton has 73 states and 81 transitions. Word has length 46 [2018-04-12 10:19:34,333 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:34,333 INFO L459 AbstractCegarLoop]: Abstraction has 73 states and 81 transitions. [2018-04-12 10:19:34,333 INFO L460 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-04-12 10:19:34,333 INFO L276 IsEmpty]: Start isEmpty. Operand 73 states and 81 transitions. [2018-04-12 10:19:34,334 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-04-12 10:19:34,334 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:34,334 INFO L355 BasicCegarLoop]: trace histogram [3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:34,334 INFO L408 AbstractCegarLoop]: === Iteration 19 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:34,334 INFO L82 PathProgramCache]: Analyzing trace with hash -145359495, now seen corresponding path program 1 times [2018-04-12 10:19:34,334 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:34,334 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:34,335 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:34,335 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:34,335 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:34,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:34,343 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:34,436 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 5 proven. 13 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-04-12 10:19:34,437 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:34,437 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:34,443 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:34,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:34,455 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:34,513 INFO L134 CoverageAnalysis]: Checked inductivity of 18 backedges. 7 proven. 9 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-04-12 10:19:34,530 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 10:19:34,530 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 8] total 19 [2018-04-12 10:19:34,530 INFO L442 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-04-12 10:19:34,530 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-04-12 10:19:34,530 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=59, Invalid=283, Unknown=0, NotChecked=0, Total=342 [2018-04-12 10:19:34,530 INFO L87 Difference]: Start difference. First operand 73 states and 81 transitions. Second operand 19 states. [2018-04-12 10:19:34,703 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:34,703 INFO L93 Difference]: Finished difference Result 131 states and 146 transitions. [2018-04-12 10:19:34,703 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-12 10:19:34,703 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 46 [2018-04-12 10:19:34,703 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:34,704 INFO L225 Difference]: With dead ends: 131 [2018-04-12 10:19:34,704 INFO L226 Difference]: Without dead ends: 107 [2018-04-12 10:19:34,704 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 69 GetRequests, 41 SyntacticMatches, 1 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 123 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=165, Invalid=647, Unknown=0, NotChecked=0, Total=812 [2018-04-12 10:19:34,704 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-04-12 10:19:34,705 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 78. [2018-04-12 10:19:34,705 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-04-12 10:19:34,705 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 86 transitions. [2018-04-12 10:19:34,706 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 86 transitions. Word has length 46 [2018-04-12 10:19:34,706 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:34,706 INFO L459 AbstractCegarLoop]: Abstraction has 78 states and 86 transitions. [2018-04-12 10:19:34,706 INFO L460 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-04-12 10:19:34,706 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 86 transitions. [2018-04-12 10:19:34,706 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 52 [2018-04-12 10:19:34,706 INFO L347 BasicCegarLoop]: Found error trace [2018-04-12 10:19:34,706 INFO L355 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-04-12 10:19:34,706 INFO L408 AbstractCegarLoop]: === Iteration 20 === [mainErr0EnsuresViolationMEMORY_LEAK, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr1RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr11RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr20RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr16RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr15RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr12RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr10RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr14RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr0RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr19RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr5RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr13RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr3RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr17RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr8RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr7RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr2RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr6RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr9RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr18RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr21RequiresViolation, __U_MULTI_flis_alloca_true_valid_memsafety_true_termination_i__lisErr4RequiresViolation]=== [2018-04-12 10:19:34,706 INFO L82 PathProgramCache]: Analyzing trace with hash 530723226, now seen corresponding path program 2 times [2018-04-12 10:19:34,706 INFO L213 ckRefinementStrategy]: Switched to mode SMTINTERPOL_TREE_INTERPOLANTS [2018-04-12 10:19:34,706 INFO L68 tionRefinementEngine]: Using refinement strategy CamelRefinementStrategy [2018-04-12 10:19:34,707 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:34,707 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-04-12 10:19:34,707 INFO L119 rtionOrderModulation]: Craig nested/tree interpolation forces the following order [2018-04-12 10:19:34,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-04-12 10:19:34,716 WARN L250 erpolLogProxyWrapper]: Using partial proofs (cut at CNF-level). Set option :produce-proofs to true to get complete proofs. [2018-04-12 10:19:34,844 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 4 proven. 5 refuted. 0 times theorem prover too weak. 21 trivial. 0 not checked. [2018-04-12 10:19:34,844 INFO L308 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-04-12 10:19:34,844 INFO L213 ckRefinementStrategy]: Switched to mode Z3_FP No working directory specified, using /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-04-12 10:19:34,849 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-04-12 10:19:34,861 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-04-12 10:19:34,861 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-04-12 10:19:34,863 INFO L270 TraceCheckSpWp]: Computing forward predicates... [2018-04-12 10:19:34,865 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 8 treesize of output 7 [2018-04-12 10:19:34,865 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,870 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 0 select indices, 0 select index equivalence classes, 0 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 6 treesize of output 5 [2018-04-12 10:19:34,870 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,872 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-1 vars, End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,872 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 2 variables, input treesize:18, output treesize:16 [2018-04-12 10:19:34,917 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,918 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 1 select indices, 1 select index equivalence classes, 1 disjoint index pairs (out of 0 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 19 [2018-04-12 10:19:34,918 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,927 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,928 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,928 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 2 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 17 treesize of output 21 [2018-04-12 10:19:34,929 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,936 INFO L267 ElimStorePlain]: Start of recursive call 1: 2 dim-0 vars, 2 dim-1 vars, End of recursive call: 2 dim-0 vars, and 1 xjuncts. [2018-04-12 10:19:34,936 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 4 variables, input treesize:38, output treesize:35 [2018-04-12 10:19:34,960 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,961 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,963 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 1 stores, 2 select indices, 2 select index equivalence classes, 3 disjoint index pairs (out of 1 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 23 treesize of output 34 [2018-04-12 10:19:34,963 INFO L267 ElimStorePlain]: Start of recursive call 2: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,974 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,975 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,976 INFO L700 Elim1Store]: detected not equals via solver [2018-04-12 10:19:34,976 INFO L477 Elim1Store]: Elim1 did not use preprocessing eliminated variable of array dimension 1, 0 stores, 3 select indices, 3 select index equivalence classes, 4 disjoint index pairs (out of 3 index pairs), introduced 0 new quantified variables, introduced 0 case distinctions, treesize of input 16 treesize of output 13 [2018-04-12 10:19:34,977 INFO L267 ElimStorePlain]: Start of recursive call 3: End of recursive call: and 1 xjuncts. [2018-04-12 10:19:34,984 INFO L267 ElimStorePlain]: Start of recursive call 1: 3 dim-0 vars, 2 dim-1 vars, End of recursive call: 3 dim-0 vars, and 1 xjuncts. [2018-04-12 10:19:34,985 INFO L202 ElimStorePlain]: Needed 3 recursive calls to eliminate 5 variables, input treesize:48, output treesize:40 [2018-04-12 10:19:35,124 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 5 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-04-12 10:19:35,141 INFO L320 seRefinementStrategy]: Constructing automaton from 0 perfect and 2 imperfect interpolant sequences. [2018-04-12 10:19:35,141 INFO L335 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9] total 17 [2018-04-12 10:19:35,142 INFO L442 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-04-12 10:19:35,142 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-04-12 10:19:35,142 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=44, Invalid=262, Unknown=0, NotChecked=0, Total=306 [2018-04-12 10:19:35,142 INFO L87 Difference]: Start difference. First operand 78 states and 86 transitions. Second operand 18 states. [2018-04-12 10:19:36,385 WARN L151 SmtUtils]: Spent 540ms on a formula simplification. DAG size of input: 64 DAG size of output 59 [2018-04-12 10:19:36,462 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-04-12 10:19:36,462 INFO L93 Difference]: Finished difference Result 77 states and 83 transitions. [2018-04-12 10:19:36,462 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-04-12 10:19:36,462 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 51 [2018-04-12 10:19:36,462 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-04-12 10:19:36,463 INFO L225 Difference]: With dead ends: 77 [2018-04-12 10:19:36,463 INFO L226 Difference]: Without dead ends: 0 [2018-04-12 10:19:36,463 INFO L567 BasicCegarLoop]: 0 DeclaredPredicates, 75 GetRequests, 43 SyntacticMatches, 6 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 89 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=173, Invalid=583, Unknown=0, NotChecked=0, Total=756 [2018-04-12 10:19:36,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-04-12 10:19:36,463 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-04-12 10:19:36,463 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-04-12 10:19:36,463 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-04-12 10:19:36,464 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 51 [2018-04-12 10:19:36,464 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-04-12 10:19:36,464 INFO L459 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-04-12 10:19:36,464 INFO L460 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-04-12 10:19:36,464 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-04-12 10:19:36,464 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-04-12 10:19:36,468 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 12.04 10:19:36 BoogieIcfgContainer [2018-04-12 10:19:36,468 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-04-12 10:19:36,469 INFO L168 Benchmark]: Toolchain (without parser) took 10447.54 ms. Allocated memory was 403.2 MB in the beginning and 770.2 MB in the end (delta: 367.0 MB). Free memory was 341.1 MB in the beginning and 487.0 MB in the end (delta: -145.9 MB). Peak memory consumption was 221.1 MB. Max. memory is 5.3 GB. [2018-04-12 10:19:36,470 INFO L168 Benchmark]: CDTParser took 0.15 ms. Allocated memory is still 403.2 MB. Free memory is still 366.4 MB. There was no memory consumed. Max. memory is 5.3 GB. [2018-04-12 10:19:36,470 INFO L168 Benchmark]: CACSL2BoogieTranslator took 229.94 ms. Allocated memory is still 403.2 MB. Free memory was 341.1 MB in the beginning and 316.0 MB in the end (delta: 25.1 MB). Peak memory consumption was 25.1 MB. Max. memory is 5.3 GB. [2018-04-12 10:19:36,470 INFO L168 Benchmark]: Boogie Preprocessor took 37.53 ms. Allocated memory is still 403.2 MB. Free memory was 316.0 MB in the beginning and 313.3 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. [2018-04-12 10:19:36,470 INFO L168 Benchmark]: RCFGBuilder took 429.13 ms. Allocated memory was 403.2 MB in the beginning and 620.8 MB in the end (delta: 217.6 MB). Free memory was 313.3 MB in the beginning and 548.5 MB in the end (delta: -235.1 MB). Peak memory consumption was 22.9 MB. Max. memory is 5.3 GB. [2018-04-12 10:19:36,471 INFO L168 Benchmark]: TraceAbstraction took 9748.43 ms. Allocated memory was 620.8 MB in the beginning and 770.2 MB in the end (delta: 149.4 MB). Free memory was 548.5 MB in the beginning and 487.0 MB in the end (delta: 61.5 MB). Peak memory consumption was 210.9 MB. Max. memory is 5.3 GB. [2018-04-12 10:19:36,472 INFO L344 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.15 ms. Allocated memory is still 403.2 MB. Free memory is still 366.4 MB. There was no memory consumed. Max. memory is 5.3 GB. * CACSL2BoogieTranslator took 229.94 ms. Allocated memory is still 403.2 MB. Free memory was 341.1 MB in the beginning and 316.0 MB in the end (delta: 25.1 MB). Peak memory consumption was 25.1 MB. Max. memory is 5.3 GB. * Boogie Preprocessor took 37.53 ms. Allocated memory is still 403.2 MB. Free memory was 316.0 MB in the beginning and 313.3 MB in the end (delta: 2.6 MB). Peak memory consumption was 2.6 MB. Max. memory is 5.3 GB. * RCFGBuilder took 429.13 ms. Allocated memory was 403.2 MB in the beginning and 620.8 MB in the end (delta: 217.6 MB). Free memory was 313.3 MB in the beginning and 548.5 MB in the end (delta: -235.1 MB). Peak memory consumption was 22.9 MB. Max. memory is 5.3 GB. * TraceAbstraction took 9748.43 ms. Allocated memory was 620.8 MB in the beginning and 770.2 MB in the end (delta: 149.4 MB). Free memory was 548.5 MB in the beginning and 487.0 MB in the end (delta: 61.5 MB). Peak memory consumption was 210.9 MB. Max. memory is 5.3 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 556]: all allocated memory was freed For all program executions holds that all allocated memory was freed at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 553]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 552]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 550]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 546]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 552]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 553]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - PositiveResult [Line: 549]: pointer dereference always succeeds For all program executions holds that pointer dereference always succeeds at this location - AllSpecificationsHoldResult: All specifications hold 23 specifications checked. All of them hold - StatisticsResult: Ultimate Automizer benchmark data CFG has 6 procedures, 90 locations, 23 error locations. SAFE Result, 9.7s OverallTime, 20 OverallIterations, 4 TraceHistogramMax, 6.2s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 1066 SDtfs, 4627 SDslu, 3717 SDs, 0 SdLazy, 3159 SolverSat, 498 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 2.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 532 GetRequests, 231 SyntacticMatches, 16 SemanticMatches, 285 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1153 ImplicationChecksByTransitivity, 5.4s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=147occurred in iteration=14, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.0s AutomataMinimizationTime, 20 MinimizatonAttempts, 330 StatesRemovedByMinimization, 14 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.0s SsaConstructionTime, 0.2s SatisfiabilityAnalysisTime, 2.7s InterpolantComputationTime, 885 NumberOfCodeBlocks, 857 NumberOfCodeBlocksAsserted, 27 NumberOfCheckSat, 858 ConstructedInterpolants, 82 QuantifiedInterpolants, 310944 SizeOfPredicates, 48 NumberOfNonLiveVariables, 844 ConjunctsInSsa, 123 ConjunctsInUnsatCore, 27 InterpolantComputations, 14 PerfectInterpolantSequences, 142/204 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/lis-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-Benchmark-0-2018-04-12_10-19-36-478.csv Written .csv to /home/ultimate/work/ultimate/releaseScripts/default/UAutomizer-linux/../../../releaseScripts/default/UAutomizer-linux/csv/lis-alloca_true-valid-memsafety_true-termination.i_svcomp-DerefFreeMemtrack-32bit-Automizer_Camel.epf_AutomizerC.xml/Csv-TraceAbstractionBenchmarks-0-2018-04-12_10-19-36-478.csv Received shutdown request...