java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array_false-unreach-call1_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:46:36,020 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:46:36,022 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:46:36,038 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:46:36,039 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:46:36,040 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:46:36,041 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:46:36,043 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:46:36,044 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:46:36,045 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:46:36,046 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:46:36,046 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:46:36,047 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:46:36,048 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:46:36,050 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:46:36,050 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:46:36,051 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:46:36,053 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:46:36,055 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:46:36,057 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:46:36,058 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:46:36,059 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:46:36,061 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:46:36,062 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:46:36,062 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:46:36,063 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:46:36,064 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:46:36,065 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:46:36,066 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:46:36,067 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:46:36,067 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:46:36,068 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-07-24 10:46:36,070 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:46:36,086 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:46:36,086 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:46:36,087 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:46:36,087 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:46:36,087 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:46:36,087 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:46:36,088 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:46:36,088 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:46:36,088 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:46:36,088 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:46:36,088 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:46:36,089 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:46:36,090 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:46:36,091 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:46:36,091 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:46:36,091 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:46:36,091 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:46:36,091 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:46:36,091 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:46:36,092 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:46:36,092 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:46:36,092 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:46:36,093 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:46:36,094 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:46:36,094 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:46:36,094 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:46:36,094 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:46:36,094 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:46:36,095 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:46:36,095 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:46:36,095 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:46:36,096 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:46:36,096 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:46:36,160 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:46:36,176 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:46:36,185 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:46:36,187 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:46:36,187 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:46:36,188 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array_false-unreach-call1_true-termination.i [2018-07-24 10:46:36,550 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/590446b3a/afc88d4ed4694230b08fcf75bc78900e/FLAG2f49345d5 [2018-07-24 10:46:36,678 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:46:36,678 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_false-unreach-call1_true-termination.i [2018-07-24 10:46:36,684 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/590446b3a/afc88d4ed4694230b08fcf75bc78900e/FLAG2f49345d5 [2018-07-24 10:46:36,700 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/590446b3a/afc88d4ed4694230b08fcf75bc78900e [2018-07-24 10:46:36,714 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:46:36,716 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:46:36,718 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:46:36,719 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:46:36,728 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:46:36,729 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:46:36" (1/1) ... [2018-07-24 10:46:36,732 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@a2cf09 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:36, skipping insertion in model container [2018-07-24 10:46:36,732 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:46:36" (1/1) ... [2018-07-24 10:46:36,938 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:46:36,984 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:46:37,000 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:46:37,006 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:46:37,020 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37 WrapperNode [2018-07-24 10:46:37,020 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:46:37,021 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:46:37,021 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:46:37,021 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:46:37,031 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,037 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,045 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:46:37,046 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:46:37,046 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:46:37,046 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:46:37,057 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,057 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,058 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,058 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,059 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,066 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,068 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... [2018-07-24 10:46:37,070 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:46:37,070 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:46:37,071 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:46:37,071 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:46:37,072 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:46:37,125 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:46:37,126 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:46:37,126 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:46:37,127 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:46:37,127 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:46:37,127 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:46:37,127 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:46:37,127 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:46:37,380 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:46:37,381 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:46:37 BoogieIcfgContainer [2018-07-24 10:46:37,381 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:46:37,382 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:46:37,384 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:46:37,387 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:46:37,387 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:46:36" (1/3) ... [2018-07-24 10:46:37,388 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@440abef1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:46:37, skipping insertion in model container [2018-07-24 10:46:37,388 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:46:37" (2/3) ... [2018-07-24 10:46:37,389 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@440abef1 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:46:37, skipping insertion in model container [2018-07-24 10:46:37,389 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:46:37" (3/3) ... [2018-07-24 10:46:37,391 INFO L112 eAbstractionObserver]: Analyzing ICFG array_false-unreach-call1_true-termination.i [2018-07-24 10:46:37,402 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:46:37,412 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:46:37,459 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:46:37,460 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:46:37,460 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:46:37,460 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:46:37,460 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:46:37,461 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:46:37,461 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:46:37,461 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:46:37,461 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:46:37,476 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states. [2018-07-24 10:46:37,481 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:46:37,482 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:37,483 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:37,483 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:37,488 INFO L82 PathProgramCache]: Analyzing trace with hash -1545526514, now seen corresponding path program 1 times [2018-07-24 10:46:37,491 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:37,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:37,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:37,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:37,547 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:37,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:37,604 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:37,606 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:46:37,607 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:46:37,607 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:46:37,611 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:46:37,623 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:46:37,623 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:46:37,625 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 2 states. [2018-07-24 10:46:37,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:37,645 INFO L93 Difference]: Finished difference Result 30 states and 33 transitions. [2018-07-24 10:46:37,645 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:46:37,647 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:46:37,647 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:37,655 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:46:37,655 INFO L226 Difference]: Without dead ends: 13 [2018-07-24 10:46:37,658 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:46:37,676 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-24 10:46:37,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-24 10:46:37,692 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-24 10:46:37,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-07-24 10:46:37,695 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 10 [2018-07-24 10:46:37,696 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:37,696 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-07-24 10:46:37,696 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:46:37,696 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-07-24 10:46:37,697 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:46:37,697 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:37,697 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:37,697 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:37,698 INFO L82 PathProgramCache]: Analyzing trace with hash -936233585, now seen corresponding path program 1 times [2018-07-24 10:46:37,698 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:37,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:37,699 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:37,699 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:37,700 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:37,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:37,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:37,742 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:46:37,742 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:46:37,742 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:46:37,744 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:46:37,744 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:46:37,744 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:46:37,745 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 3 states. [2018-07-24 10:46:37,796 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:37,796 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-24 10:46:37,797 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:46:37,797 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:46:37,797 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:37,798 INFO L225 Difference]: With dead ends: 21 [2018-07-24 10:46:37,798 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:46:37,799 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:46:37,799 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:46:37,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2018-07-24 10:46:37,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-07-24 10:46:37,804 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-07-24 10:46:37,804 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2018-07-24 10:46:37,805 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:37,805 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-07-24 10:46:37,805 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:46:37,805 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-07-24 10:46:37,806 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:46:37,806 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:37,806 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:37,806 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:37,807 INFO L82 PathProgramCache]: Analyzing trace with hash -378716438, now seen corresponding path program 1 times [2018-07-24 10:46:37,807 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:37,808 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:37,808 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:37,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:37,809 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:37,817 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:37,967 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:37,968 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:37,968 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-07-24 10:46:37,982 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:37,983 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:38,006 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:38,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:38,034 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:38,122 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,145 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:38,146 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:38,163 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:38,163 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:38,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:38,186 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:38,192 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,192 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:38,208 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,210 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:38,210 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:46:38,210 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:38,211 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:46:38,211 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:46:38,211 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:46:38,211 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 4 states. [2018-07-24 10:46:38,280 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:38,281 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-07-24 10:46:38,282 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:46:38,282 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-07-24 10:46:38,283 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:38,284 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:46:38,285 INFO L226 Difference]: Without dead ends: 19 [2018-07-24 10:46:38,285 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:46:38,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-24 10:46:38,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-07-24 10:46:38,293 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:46:38,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-24 10:46:38,293 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2018-07-24 10:46:38,294 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:38,294 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-24 10:46:38,294 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:46:38,294 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-24 10:46:38,295 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:46:38,295 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:38,295 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:38,295 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:38,296 INFO L82 PathProgramCache]: Analyzing trace with hash -23923793, now seen corresponding path program 2 times [2018-07-24 10:46:38,296 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:38,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:38,297 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:38,297 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:38,297 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:38,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:38,387 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,387 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:38,387 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:38,397 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:38,397 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:38,418 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:38,419 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:38,420 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:38,427 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,428 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:38,766 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,794 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:38,794 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:38,810 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:38,810 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:38,827 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:38,827 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:38,831 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:38,837 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,838 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:38,859 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,861 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:38,861 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:46:38,861 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:38,862 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:46:38,862 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:46:38,862 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:46:38,863 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 5 states. [2018-07-24 10:46:38,899 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:38,899 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-24 10:46:38,900 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:46:38,900 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-07-24 10:46:38,900 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:38,901 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:46:38,901 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:46:38,902 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:46:38,902 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:46:38,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2018-07-24 10:46:38,905 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-07-24 10:46:38,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-07-24 10:46:38,906 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2018-07-24 10:46:38,907 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:38,907 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-07-24 10:46:38,907 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:46:38,907 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-07-24 10:46:38,908 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:46:38,908 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:38,908 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:38,908 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:38,908 INFO L82 PathProgramCache]: Analyzing trace with hash -310752054, now seen corresponding path program 3 times [2018-07-24 10:46:38,909 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:38,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:38,910 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:38,910 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:38,910 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:38,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:38,991 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:38,991 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:38,992 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:39,006 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:39,006 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:39,021 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:46:39,021 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:39,023 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:39,030 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:39,030 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:39,200 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:39,232 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:39,232 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:39,260 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:39,261 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:39,296 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:46:39,296 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:39,300 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:39,306 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:39,306 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:39,339 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:39,342 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:39,342 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:46:39,342 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:39,343 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:46:39,343 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:46:39,344 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:46:39,344 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 6 states. [2018-07-24 10:46:39,400 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:39,400 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-07-24 10:46:39,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:46:39,403 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-07-24 10:46:39,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:39,404 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:46:39,404 INFO L226 Difference]: Without dead ends: 25 [2018-07-24 10:46:39,404 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:46:39,405 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-07-24 10:46:39,407 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-07-24 10:46:39,407 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:46:39,408 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-24 10:46:39,409 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2018-07-24 10:46:39,409 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:39,409 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-24 10:46:39,409 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:46:39,409 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-24 10:46:39,410 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:46:39,410 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:39,410 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:39,411 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:39,411 INFO L82 PathProgramCache]: Analyzing trace with hash 1773443535, now seen corresponding path program 4 times [2018-07-24 10:46:39,411 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:39,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:39,412 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:39,412 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:39,413 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:39,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:39,516 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:39,517 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:39,517 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:39,526 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:46:39,526 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:46:39,537 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:46:39,537 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:39,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:39,545 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:39,545 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:40,059 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,080 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:40,080 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:40,098 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:46:40,098 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:46:40,114 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:46:40,115 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:40,118 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:40,124 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,124 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:40,141 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (9)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:46:40,144 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:40,145 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:46:40,145 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:40,145 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:46:40,146 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:46:40,146 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:46:40,147 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 7 states. [2018-07-24 10:46:40,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:40,198 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-24 10:46:40,198 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:46:40,198 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-07-24 10:46:40,199 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:40,199 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:46:40,199 INFO L226 Difference]: Without dead ends: 28 [2018-07-24 10:46:40,200 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:46:40,200 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-24 10:46:40,203 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2018-07-24 10:46:40,203 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:46:40,204 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-07-24 10:46:40,204 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 23 [2018-07-24 10:46:40,205 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:40,205 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-07-24 10:46:40,205 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:46:40,205 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-07-24 10:46:40,206 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:46:40,206 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:40,206 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:40,206 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:40,207 INFO L82 PathProgramCache]: Analyzing trace with hash -297962838, now seen corresponding path program 5 times [2018-07-24 10:46:40,207 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:40,208 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:40,208 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:40,209 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:40,209 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:40,219 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:40,321 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,321 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:40,321 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:40,336 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:46:40,336 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:40,365 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:46:40,366 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:40,368 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:40,375 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,376 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:40,521 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,541 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:40,542 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:40,557 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:46:40,558 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:40,592 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:46:40,592 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:40,596 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:40,603 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,603 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:40,621 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,623 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:40,623 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:46:40,624 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:40,624 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:46:40,625 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:46:40,625 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:46:40,625 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 8 states. [2018-07-24 10:46:40,677 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:40,677 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-07-24 10:46:40,678 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:46:40,679 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 26 [2018-07-24 10:46:40,679 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:40,680 INFO L225 Difference]: With dead ends: 36 [2018-07-24 10:46:40,680 INFO L226 Difference]: Without dead ends: 31 [2018-07-24 10:46:40,680 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 98 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:46:40,681 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-07-24 10:46:40,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-07-24 10:46:40,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:46:40,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-24 10:46:40,687 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 26 [2018-07-24 10:46:40,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:40,687 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-24 10:46:40,688 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:46:40,688 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-24 10:46:40,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:46:40,689 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:40,689 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:40,689 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:40,689 INFO L82 PathProgramCache]: Analyzing trace with hash 524888047, now seen corresponding path program 6 times [2018-07-24 10:46:40,689 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:40,690 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:40,690 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:40,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:40,691 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:40,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:40,804 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,805 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:40,805 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:40,813 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:46:40,814 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:46:40,832 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:46:40,832 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:40,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:40,844 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:40,844 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:41,108 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,129 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:41,129 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:41,146 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:46:41,146 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:46:41,190 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:46:41,191 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:41,194 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:41,201 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,202 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:41,260 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,264 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:41,264 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:46:41,264 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:41,265 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:46:41,265 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:46:41,267 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:46:41,267 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 9 states. [2018-07-24 10:46:41,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:41,414 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-24 10:46:41,416 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:46:41,417 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-07-24 10:46:41,417 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:41,417 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:46:41,418 INFO L226 Difference]: Without dead ends: 34 [2018-07-24 10:46:41,418 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:46:41,419 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-24 10:46:41,422 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-07-24 10:46:41,422 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-07-24 10:46:41,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-07-24 10:46:41,424 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 29 [2018-07-24 10:46:41,424 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:41,424 INFO L471 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-07-24 10:46:41,424 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:46:41,424 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-07-24 10:46:41,425 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 10:46:41,425 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:41,425 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:41,426 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:41,426 INFO L82 PathProgramCache]: Analyzing trace with hash -1597722486, now seen corresponding path program 7 times [2018-07-24 10:46:41,426 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:41,427 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:41,427 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:41,428 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:41,428 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:41,438 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:41,558 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,559 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:41,559 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:41,568 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:41,568 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:41,582 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:41,584 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:41,591 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,591 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:41,794 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,816 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:41,817 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:41,834 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:41,834 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:41,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:41,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:41,861 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,862 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:41,884 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:41,887 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:41,887 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:46:41,887 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:41,888 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:46:41,888 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:46:41,888 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:46:41,889 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 10 states. [2018-07-24 10:46:41,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:41,945 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-07-24 10:46:41,951 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:46:41,952 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 32 [2018-07-24 10:46:41,952 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:41,953 INFO L225 Difference]: With dead ends: 42 [2018-07-24 10:46:41,953 INFO L226 Difference]: Without dead ends: 37 [2018-07-24 10:46:41,953 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:46:41,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-24 10:46:41,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2018-07-24 10:46:41,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:46:41,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-24 10:46:41,959 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 32 [2018-07-24 10:46:41,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:41,959 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-24 10:46:41,959 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:46:41,960 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-24 10:46:41,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:46:41,961 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:41,961 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:41,961 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:41,961 INFO L82 PathProgramCache]: Analyzing trace with hash -1484612081, now seen corresponding path program 8 times [2018-07-24 10:46:41,961 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:41,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:41,962 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:41,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:41,963 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:41,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:42,203 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:42,204 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:42,204 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:42,215 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:42,216 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:42,255 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:42,256 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:42,258 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:42,270 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:42,270 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:42,570 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:42,590 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:42,591 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:42,606 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:42,607 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:42,628 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:42,628 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:42,632 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:42,640 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:42,641 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:42,702 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:42,704 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:42,704 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:46:42,705 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:42,705 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:46:42,705 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:46:42,706 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:46:42,706 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 11 states. [2018-07-24 10:46:42,879 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:42,879 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-24 10:46:42,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:46:42,886 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 35 [2018-07-24 10:46:42,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:42,887 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:46:42,887 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:46:42,887 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:46:42,888 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:46:42,892 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2018-07-24 10:46:42,893 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:46:42,893 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-07-24 10:46:42,894 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 35 [2018-07-24 10:46:42,894 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:42,894 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-07-24 10:46:42,894 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:46:42,894 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-07-24 10:46:42,895 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-24 10:46:42,895 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:42,896 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:42,896 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:42,896 INFO L82 PathProgramCache]: Analyzing trace with hash 933103210, now seen corresponding path program 9 times [2018-07-24 10:46:42,896 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:42,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:42,897 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:42,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:42,898 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:42,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:43,058 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,058 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:43,059 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:43,067 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:43,067 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:43,087 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:46:43,087 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:43,089 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:43,098 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,099 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:43,309 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,330 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:43,330 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:43,346 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:43,346 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:43,434 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:46:43,434 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:43,437 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:43,446 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,446 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:43,499 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,501 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:43,501 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:46:43,502 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:43,502 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:46:43,503 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:46:43,503 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:46:43,503 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 12 states. [2018-07-24 10:46:43,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:43,568 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-07-24 10:46:43,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:46:43,569 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-07-24 10:46:43,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:43,570 INFO L225 Difference]: With dead ends: 48 [2018-07-24 10:46:43,570 INFO L226 Difference]: Without dead ends: 43 [2018-07-24 10:46:43,570 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:46:43,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-07-24 10:46:43,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-07-24 10:46:43,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:46:43,575 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-24 10:46:43,575 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 38 [2018-07-24 10:46:43,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:43,576 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-24 10:46:43,576 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:46:43,576 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-24 10:46:43,577 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:46:43,577 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:43,577 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:43,577 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:43,578 INFO L82 PathProgramCache]: Analyzing trace with hash 487783471, now seen corresponding path program 10 times [2018-07-24 10:46:43,578 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:43,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:43,579 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:43,579 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:43,579 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:43,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:43,759 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,759 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:43,760 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:43,768 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:46:43,769 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:46:43,810 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:46:43,811 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:43,813 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:43,822 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:43,822 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:44,440 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:44,462 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:44,463 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:44,495 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:46:44,495 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:46:44,525 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:46:44,526 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:44,530 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:44,537 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:44,537 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:44,607 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:44,610 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:44,611 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:46:44,611 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:44,612 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:46:44,612 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:46:44,612 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:46:44,613 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 13 states. [2018-07-24 10:46:44,922 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:44,922 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-24 10:46:44,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:46:44,923 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 41 [2018-07-24 10:46:44,923 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:44,924 INFO L225 Difference]: With dead ends: 51 [2018-07-24 10:46:44,925 INFO L226 Difference]: Without dead ends: 46 [2018-07-24 10:46:44,926 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:46:44,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-24 10:46:44,930 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2018-07-24 10:46:44,930 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-07-24 10:46:44,931 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-07-24 10:46:44,931 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 41 [2018-07-24 10:46:44,931 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:44,932 INFO L471 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-07-24 10:46:44,932 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:46:44,932 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-07-24 10:46:44,933 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:46:44,933 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:44,933 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:44,933 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:44,933 INFO L82 PathProgramCache]: Analyzing trace with hash 1121416266, now seen corresponding path program 11 times [2018-07-24 10:46:44,934 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:44,934 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:44,935 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:44,935 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:44,935 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:44,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:45,153 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:45,153 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:45,153 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:45,163 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:46:45,163 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:45,194 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:46:45,194 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:45,196 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:45,205 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:45,205 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:45,628 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:45,649 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:45,649 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:45,664 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:46:45,664 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:45,777 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:46:45,777 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:45,781 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:45,788 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:45,788 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:45,806 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:45,807 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:45,807 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:46:45,807 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:45,808 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:46:45,808 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:46:45,809 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:46:45,809 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 14 states. [2018-07-24 10:46:45,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:45,905 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-07-24 10:46:45,906 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:46:45,906 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 44 [2018-07-24 10:46:45,906 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:45,907 INFO L225 Difference]: With dead ends: 54 [2018-07-24 10:46:45,908 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:46:45,909 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:46:45,909 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:46:45,912 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2018-07-24 10:46:45,912 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:46:45,913 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-07-24 10:46:45,913 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 44 [2018-07-24 10:46:45,914 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:45,914 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-07-24 10:46:45,914 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:46:45,914 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-07-24 10:46:45,915 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-24 10:46:45,915 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:45,915 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:45,915 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:45,915 INFO L82 PathProgramCache]: Analyzing trace with hash 1294746191, now seen corresponding path program 12 times [2018-07-24 10:46:45,915 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:45,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:45,916 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:45,916 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:45,917 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:45,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:46,077 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:46,078 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:46,078 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:46,087 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:46:46,088 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:46:46,118 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:46:46,118 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:46,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:46,127 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:46,127 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:46,476 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:46,496 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:46,497 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:46,512 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:46:46,513 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:46:46,698 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:46:46,699 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:46,702 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:46,710 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:46,711 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:46,773 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:46,775 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:46,775 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:46:46,775 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:46,775 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:46:46,776 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:46:46,776 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:46:46,776 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 15 states. [2018-07-24 10:46:46,885 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:46,885 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-07-24 10:46:46,885 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:46:46,885 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-07-24 10:46:46,886 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:46,886 INFO L225 Difference]: With dead ends: 57 [2018-07-24 10:46:46,886 INFO L226 Difference]: Without dead ends: 52 [2018-07-24 10:46:46,887 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:46:46,887 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-07-24 10:46:46,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-07-24 10:46:46,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-07-24 10:46:46,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-07-24 10:46:46,891 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 47 [2018-07-24 10:46:46,892 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:46,892 INFO L471 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-07-24 10:46:46,892 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:46:46,892 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-07-24 10:46:46,893 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-24 10:46:46,893 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:46,893 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:46,893 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:46,893 INFO L82 PathProgramCache]: Analyzing trace with hash -1879115222, now seen corresponding path program 13 times [2018-07-24 10:46:46,893 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:46,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:46,894 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:46,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:46,895 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:46,904 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:47,294 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:47,295 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:47,295 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:47,302 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:47,302 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:47,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:47,317 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:47,325 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:47,325 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:47,866 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:47,890 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:47,890 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:47,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:47,909 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:47,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:47,939 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:47,951 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:47,951 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:47,963 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:47,964 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:47,965 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:46:47,965 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:47,965 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:46:47,965 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:46:47,966 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:46:47,966 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 16 states. [2018-07-24 10:46:48,038 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:48,038 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-07-24 10:46:48,039 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:46:48,039 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 50 [2018-07-24 10:46:48,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:48,040 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:46:48,040 INFO L226 Difference]: Without dead ends: 55 [2018-07-24 10:46:48,041 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 186 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:46:48,042 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-07-24 10:46:48,045 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2018-07-24 10:46:48,045 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-24 10:46:48,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-07-24 10:46:48,046 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 50 [2018-07-24 10:46:48,046 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:48,046 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-07-24 10:46:48,047 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:46:48,047 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-07-24 10:46:48,047 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-07-24 10:46:48,047 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:48,048 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:48,048 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:48,048 INFO L82 PathProgramCache]: Analyzing trace with hash -679448465, now seen corresponding path program 14 times [2018-07-24 10:46:48,048 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:48,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:48,049 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:48,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:48,049 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:48,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:48,254 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:48,254 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:48,255 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:48,268 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:48,268 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:48,285 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:48,285 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:48,287 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:48,293 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:48,294 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:48,639 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:48,660 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:48,661 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:48,676 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:48,677 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:48,709 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:48,710 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:48,713 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:48,721 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:48,722 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:48,757 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:48,759 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:48,759 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:46:48,759 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:48,759 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:46:48,759 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:46:48,760 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:46:48,760 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 17 states. [2018-07-24 10:46:48,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:48,880 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-07-24 10:46:48,881 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:46:48,881 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 53 [2018-07-24 10:46:48,881 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:48,882 INFO L225 Difference]: With dead ends: 63 [2018-07-24 10:46:48,882 INFO L226 Difference]: Without dead ends: 58 [2018-07-24 10:46:48,883 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:46:48,884 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-07-24 10:46:48,888 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-07-24 10:46:48,888 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:46:48,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-07-24 10:46:48,889 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 53 [2018-07-24 10:46:48,889 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:48,889 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-07-24 10:46:48,889 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:46:48,889 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-07-24 10:46:48,890 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:46:48,890 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:48,891 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:48,891 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:48,891 INFO L82 PathProgramCache]: Analyzing trace with hash 170039306, now seen corresponding path program 15 times [2018-07-24 10:46:48,891 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:48,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:48,892 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:48,892 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:48,893 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:48,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:49,147 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:49,148 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:49,148 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:49,155 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:49,155 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:49,187 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:46:49,187 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:49,190 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:49,200 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:49,200 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:49,597 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:49,618 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:49,619 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:49,634 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:49,634 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:49,939 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:46:49,940 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:49,943 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:49,952 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:49,953 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:49,968 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:49,970 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:49,970 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:46:49,970 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:49,970 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:46:49,971 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:46:49,971 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:46:49,971 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 18 states. [2018-07-24 10:46:50,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:50,037 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-07-24 10:46:50,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:46:50,038 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-07-24 10:46:50,038 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:50,038 INFO L225 Difference]: With dead ends: 66 [2018-07-24 10:46:50,039 INFO L226 Difference]: Without dead ends: 61 [2018-07-24 10:46:50,040 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:46:50,040 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-07-24 10:46:50,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2018-07-24 10:46:50,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:46:50,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-07-24 10:46:50,045 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 56 [2018-07-24 10:46:50,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:50,045 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-07-24 10:46:50,045 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:46:50,046 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-07-24 10:46:50,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:46:50,047 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:50,047 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:50,047 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:50,047 INFO L82 PathProgramCache]: Analyzing trace with hash 1312917135, now seen corresponding path program 16 times [2018-07-24 10:46:50,047 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:50,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:50,048 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:50,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:50,048 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:50,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:50,607 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:50,607 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:50,607 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:50,615 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:46:50,615 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:46:50,632 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:46:50,633 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:50,634 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:50,644 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:50,644 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:51,271 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:51,293 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:51,293 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:51,308 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:46:51,308 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:46:51,344 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:46:51,344 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:51,349 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:51,357 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:51,358 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:51,407 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:51,408 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:51,408 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:46:51,408 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:51,409 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:46:51,409 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:46:51,409 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:46:51,410 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 19 states. [2018-07-24 10:46:51,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:51,477 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-07-24 10:46:51,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:46:51,481 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-07-24 10:46:51,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:51,481 INFO L225 Difference]: With dead ends: 69 [2018-07-24 10:46:51,481 INFO L226 Difference]: Without dead ends: 64 [2018-07-24 10:46:51,482 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:46:51,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-07-24 10:46:51,494 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2018-07-24 10:46:51,495 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:46:51,495 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-07-24 10:46:51,495 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 59 [2018-07-24 10:46:51,496 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:51,496 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-07-24 10:46:51,496 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:46:51,496 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-07-24 10:46:51,499 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-24 10:46:51,499 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:51,499 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:51,499 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:51,500 INFO L82 PathProgramCache]: Analyzing trace with hash -1714401814, now seen corresponding path program 17 times [2018-07-24 10:46:51,500 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:51,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:51,504 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:51,504 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:51,504 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:51,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:51,791 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:51,792 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:51,792 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:51,799 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:46:51,799 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:51,851 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:46:51,851 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:51,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:51,866 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:51,867 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:52,760 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:52,780 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:52,781 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:52,796 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:46:52,796 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:53,105 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:46:53,106 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:53,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:53,116 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:53,117 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:53,169 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:53,172 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:53,172 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:46:53,172 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:53,173 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:46:53,174 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:46:53,175 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:46:53,175 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 20 states. [2018-07-24 10:46:53,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:53,708 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-07-24 10:46:53,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:46:53,708 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 62 [2018-07-24 10:46:53,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:53,709 INFO L225 Difference]: With dead ends: 72 [2018-07-24 10:46:53,709 INFO L226 Difference]: Without dead ends: 67 [2018-07-24 10:46:53,711 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:46:53,711 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-24 10:46:53,714 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2018-07-24 10:46:53,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-24 10:46:53,715 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-07-24 10:46:53,715 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 62 [2018-07-24 10:46:53,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:53,715 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-07-24 10:46:53,716 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:46:53,716 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-07-24 10:46:53,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-07-24 10:46:53,716 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:53,717 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:53,717 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:53,717 INFO L82 PathProgramCache]: Analyzing trace with hash 1445037231, now seen corresponding path program 18 times [2018-07-24 10:46:53,717 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:53,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:53,718 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:53,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:53,718 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:53,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:54,471 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:54,471 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:54,471 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:54,483 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:46:54,483 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:46:54,527 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:46:54,527 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:54,528 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:54,540 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:54,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:55,090 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:55,111 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:55,111 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:55,127 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:46:55,127 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:46:55,701 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:46:55,701 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:55,705 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:55,713 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:55,713 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:55,722 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:55,723 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:55,723 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-07-24 10:46:55,724 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:55,724 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:46:55,724 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:46:55,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:46:55,725 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 21 states. [2018-07-24 10:46:55,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:55,830 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-07-24 10:46:55,831 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:46:55,831 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-07-24 10:46:55,831 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:55,832 INFO L225 Difference]: With dead ends: 75 [2018-07-24 10:46:55,832 INFO L226 Difference]: Without dead ends: 70 [2018-07-24 10:46:55,833 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:46:55,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-07-24 10:46:55,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-07-24 10:46:55,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:46:55,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-07-24 10:46:55,837 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 65 [2018-07-24 10:46:55,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:55,838 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-07-24 10:46:55,838 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:46:55,838 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-07-24 10:46:55,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-07-24 10:46:55,839 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:55,839 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:55,839 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:55,839 INFO L82 PathProgramCache]: Analyzing trace with hash 85334986, now seen corresponding path program 19 times [2018-07-24 10:46:55,839 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:55,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:55,840 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:55,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:55,840 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:55,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:56,079 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:56,079 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:56,079 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:56,087 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:56,087 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:56,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:56,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:56,120 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:56,121 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:56,640 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:56,660 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:56,660 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:56,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:56,676 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:46:56,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:56,715 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:56,723 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:56,723 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:56,771 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:56,772 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:56,772 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-07-24 10:46:56,772 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:56,772 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:46:56,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:46:56,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:46:56,773 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 22 states. [2018-07-24 10:46:56,869 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:56,869 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-07-24 10:46:56,870 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:46:56,870 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2018-07-24 10:46:56,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:56,871 INFO L225 Difference]: With dead ends: 78 [2018-07-24 10:46:56,871 INFO L226 Difference]: Without dead ends: 73 [2018-07-24 10:46:56,872 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 252 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:46:56,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-07-24 10:46:56,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2018-07-24 10:46:56,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-24 10:46:56,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-07-24 10:46:56,875 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 68 [2018-07-24 10:46:56,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:56,876 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-07-24 10:46:56,876 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:46:56,876 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-07-24 10:46:56,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:46:56,877 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:56,877 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:56,877 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:56,877 INFO L82 PathProgramCache]: Analyzing trace with hash -967677233, now seen corresponding path program 20 times [2018-07-24 10:46:56,877 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:56,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:56,878 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:46:56,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:56,878 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:56,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:57,192 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:57,192 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:57,192 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:57,200 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:57,200 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:57,240 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:57,241 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:57,243 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:57,257 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:57,258 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:58,259 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:58,279 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:58,279 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:58,296 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:46:58,296 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:46:58,337 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:46:58,337 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:58,341 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:58,352 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:58,352 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:58,374 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:58,375 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:46:58,375 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-07-24 10:46:58,375 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:46:58,376 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:46:58,376 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:46:58,377 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:46:58,377 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 23 states. [2018-07-24 10:46:58,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:46:58,493 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-07-24 10:46:58,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:46:58,496 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 71 [2018-07-24 10:46:58,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:46:58,497 INFO L225 Difference]: With dead ends: 81 [2018-07-24 10:46:58,498 INFO L226 Difference]: Without dead ends: 76 [2018-07-24 10:46:58,499 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:46:58,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-07-24 10:46:58,501 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2018-07-24 10:46:58,501 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-24 10:46:58,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-07-24 10:46:58,502 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 71 [2018-07-24 10:46:58,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:46:58,502 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-07-24 10:46:58,502 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:46:58,502 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-07-24 10:46:58,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:46:58,503 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:46:58,503 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:46:58,503 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:46:58,503 INFO L82 PathProgramCache]: Analyzing trace with hash -813563478, now seen corresponding path program 21 times [2018-07-24 10:46:58,504 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:46:58,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:58,505 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:46:58,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:46:58,505 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:46:58,513 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:46:59,320 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:59,320 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:59,320 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:46:59,329 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:59,329 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:46:59,384 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:46:59,385 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:46:59,387 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:46:59,397 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:59,398 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:46:59,957 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:46:59,978 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:46:59,978 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:46:59,994 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:46:59,995 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:00,848 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:47:00,848 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:00,852 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:00,862 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:00,862 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:00,878 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:00,880 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:00,880 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-07-24 10:47:00,880 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:00,881 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:47:00,881 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:47:00,882 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:47:00,882 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 24 states. [2018-07-24 10:47:00,964 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:00,965 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-07-24 10:47:00,965 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:47:00,965 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-07-24 10:47:00,965 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:00,966 INFO L225 Difference]: With dead ends: 84 [2018-07-24 10:47:00,966 INFO L226 Difference]: Without dead ends: 79 [2018-07-24 10:47:00,968 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 274 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:47:00,968 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-24 10:47:00,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2018-07-24 10:47:00,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-24 10:47:00,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-07-24 10:47:00,970 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 74 [2018-07-24 10:47:00,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:00,970 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-07-24 10:47:00,971 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:47:00,971 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-07-24 10:47:00,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 10:47:00,971 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:00,971 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:00,972 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:00,972 INFO L82 PathProgramCache]: Analyzing trace with hash -930727697, now seen corresponding path program 22 times [2018-07-24 10:47:00,972 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:00,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:00,973 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:00,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:00,973 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:00,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:01,949 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:01,949 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:01,949 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:01,957 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:01,957 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:01,976 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:01,977 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:01,978 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:01,989 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:01,989 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:02,703 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:02,734 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:02,734 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:02,757 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:02,757 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:02,801 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:02,801 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:02,805 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:02,816 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:02,816 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:02,872 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:02,874 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:02,875 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-07-24 10:47:02,875 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:02,875 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:47:02,876 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:47:02,876 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:47:02,877 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 25 states. [2018-07-24 10:47:03,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:03,074 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-07-24 10:47:03,081 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:47:03,082 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 77 [2018-07-24 10:47:03,082 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:03,082 INFO L225 Difference]: With dead ends: 87 [2018-07-24 10:47:03,083 INFO L226 Difference]: Without dead ends: 82 [2018-07-24 10:47:03,084 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:47:03,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-07-24 10:47:03,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2018-07-24 10:47:03,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-07-24 10:47:03,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-07-24 10:47:03,087 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 77 [2018-07-24 10:47:03,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:03,087 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-07-24 10:47:03,087 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:47:03,087 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-07-24 10:47:03,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-07-24 10:47:03,088 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:03,088 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:03,088 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:03,089 INFO L82 PathProgramCache]: Analyzing trace with hash 438435722, now seen corresponding path program 23 times [2018-07-24 10:47:03,089 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:03,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:03,089 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:03,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:03,090 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:03,097 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:03,531 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:03,532 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:03,532 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:03,540 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:03,540 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:03,626 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:47:03,626 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:03,630 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:03,638 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:03,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:04,314 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:04,335 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:04,336 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:04,350 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:04,350 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:05,039 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:47:05,039 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:05,043 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:05,051 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:05,051 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:05,115 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:05,117 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:05,117 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-07-24 10:47:05,118 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:05,118 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:47:05,118 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:47:05,119 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:47:05,120 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 26 states. [2018-07-24 10:47:05,274 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:05,275 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-07-24 10:47:05,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:47:05,275 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-07-24 10:47:05,275 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:05,276 INFO L225 Difference]: With dead ends: 90 [2018-07-24 10:47:05,276 INFO L226 Difference]: Without dead ends: 85 [2018-07-24 10:47:05,278 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:47:05,278 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-07-24 10:47:05,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2018-07-24 10:47:05,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-24 10:47:05,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-07-24 10:47:05,282 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 80 [2018-07-24 10:47:05,282 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:05,282 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-07-24 10:47:05,282 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:47:05,282 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-07-24 10:47:05,283 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-24 10:47:05,283 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:05,283 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:05,284 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:05,284 INFO L82 PathProgramCache]: Analyzing trace with hash -118558961, now seen corresponding path program 24 times [2018-07-24 10:47:05,284 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:05,284 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:05,285 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:05,285 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:05,285 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:05,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:05,632 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:05,633 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:05,633 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:05,641 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:05,642 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:05,714 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:47:05,714 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:05,716 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:05,729 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:05,729 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:06,463 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:06,483 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:06,483 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:06,499 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:06,499 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:08,127 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:47:08,127 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:08,132 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:08,145 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:08,145 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:08,174 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:08,175 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:08,175 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-07-24 10:47:08,176 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:08,176 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:47:08,177 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:47:08,177 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:47:08,178 INFO L87 Difference]: Start difference. First operand 84 states and 84 transitions. Second operand 27 states. [2018-07-24 10:47:08,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:08,294 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-07-24 10:47:08,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:47:08,295 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 83 [2018-07-24 10:47:08,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:08,296 INFO L225 Difference]: With dead ends: 93 [2018-07-24 10:47:08,296 INFO L226 Difference]: Without dead ends: 88 [2018-07-24 10:47:08,297 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 307 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:47:08,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-07-24 10:47:08,300 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2018-07-24 10:47:08,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-24 10:47:08,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-07-24 10:47:08,301 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 87 transitions. Word has length 83 [2018-07-24 10:47:08,301 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:08,301 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 87 transitions. [2018-07-24 10:47:08,301 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:47:08,301 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-07-24 10:47:08,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-07-24 10:47:08,302 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:08,302 INFO L353 BasicCegarLoop]: trace histogram [26, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:08,302 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:08,303 INFO L82 PathProgramCache]: Analyzing trace with hash -2088495766, now seen corresponding path program 25 times [2018-07-24 10:47:08,303 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:08,303 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:08,303 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:08,304 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:08,304 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:08,311 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:08,751 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:08,751 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:08,751 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:08,758 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:08,758 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:08,785 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:08,787 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:08,801 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:08,801 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:09,832 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:09,852 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:09,852 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:09,868 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:09,868 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:09,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:09,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:09,930 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:09,930 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:09,954 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:09,955 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:09,955 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 54 [2018-07-24 10:47:09,955 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:09,955 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:47:09,956 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:47:09,956 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:47:09,957 INFO L87 Difference]: Start difference. First operand 87 states and 87 transitions. Second operand 28 states. [2018-07-24 10:47:10,046 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:10,047 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-07-24 10:47:10,047 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:47:10,047 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 86 [2018-07-24 10:47:10,048 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:10,048 INFO L225 Difference]: With dead ends: 96 [2018-07-24 10:47:10,048 INFO L226 Difference]: Without dead ends: 91 [2018-07-24 10:47:10,050 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 318 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:47:10,050 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-07-24 10:47:10,052 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-07-24 10:47:10,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-07-24 10:47:10,053 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 90 transitions. [2018-07-24 10:47:10,053 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 90 transitions. Word has length 86 [2018-07-24 10:47:10,053 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:10,053 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 90 transitions. [2018-07-24 10:47:10,054 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:47:10,054 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 90 transitions. [2018-07-24 10:47:10,054 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:47:10,055 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:10,055 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:10,055 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:10,055 INFO L82 PathProgramCache]: Analyzing trace with hash -2042720977, now seen corresponding path program 26 times [2018-07-24 10:47:10,055 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:10,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:10,056 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:10,056 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:10,056 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:10,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:10,607 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:10,607 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:10,607 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:10,617 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:47:10,617 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:10,643 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:47:10,643 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:10,647 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:10,660 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:10,660 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:11,719 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:11,739 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:11,740 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:11,755 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:47:11,755 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:11,803 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:47:11,804 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:11,808 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:11,820 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:11,821 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:11,883 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:11,885 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:11,885 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-07-24 10:47:11,885 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:11,886 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:47:11,886 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:47:11,887 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:47:11,888 INFO L87 Difference]: Start difference. First operand 90 states and 90 transitions. Second operand 29 states. [2018-07-24 10:47:12,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:12,058 INFO L93 Difference]: Finished difference Result 99 states and 99 transitions. [2018-07-24 10:47:12,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:47:12,060 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-07-24 10:47:12,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:12,061 INFO L225 Difference]: With dead ends: 99 [2018-07-24 10:47:12,061 INFO L226 Difference]: Without dead ends: 94 [2018-07-24 10:47:12,062 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 329 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:47:12,062 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-07-24 10:47:12,064 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2018-07-24 10:47:12,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-07-24 10:47:12,065 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-07-24 10:47:12,065 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 93 transitions. Word has length 89 [2018-07-24 10:47:12,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:12,066 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 93 transitions. [2018-07-24 10:47:12,066 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:47:12,066 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-07-24 10:47:12,066 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-07-24 10:47:12,066 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:12,066 INFO L353 BasicCegarLoop]: trace histogram [28, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:12,067 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:12,067 INFO L82 PathProgramCache]: Analyzing trace with hash 129385290, now seen corresponding path program 27 times [2018-07-24 10:47:12,067 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:12,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:12,068 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:12,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:12,068 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:12,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:12,708 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:12,708 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:12,708 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:12,717 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:47:12,717 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:12,805 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-07-24 10:47:12,805 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:12,808 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:12,818 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:12,818 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:13,901 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:13,922 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:13,922 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:13,938 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:47:13,938 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:15,969 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-07-24 10:47:15,969 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:15,973 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:15,983 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:15,983 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:16,030 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:16,032 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:16,032 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-07-24 10:47:16,032 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:16,032 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:47:16,033 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:47:16,034 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:47:16,034 INFO L87 Difference]: Start difference. First operand 93 states and 93 transitions. Second operand 30 states. [2018-07-24 10:47:16,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:16,136 INFO L93 Difference]: Finished difference Result 102 states and 102 transitions. [2018-07-24 10:47:16,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-07-24 10:47:16,136 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 92 [2018-07-24 10:47:16,137 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:16,138 INFO L225 Difference]: With dead ends: 102 [2018-07-24 10:47:16,138 INFO L226 Difference]: Without dead ends: 97 [2018-07-24 10:47:16,139 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 340 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:47:16,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-07-24 10:47:16,141 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 96. [2018-07-24 10:47:16,141 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-07-24 10:47:16,142 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 96 transitions. [2018-07-24 10:47:16,142 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 96 transitions. Word has length 92 [2018-07-24 10:47:16,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:16,143 INFO L471 AbstractCegarLoop]: Abstraction has 96 states and 96 transitions. [2018-07-24 10:47:16,143 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:47:16,143 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 96 transitions. [2018-07-24 10:47:16,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-07-24 10:47:16,143 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:16,144 INFO L353 BasicCegarLoop]: trace histogram [29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:16,144 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:16,144 INFO L82 PathProgramCache]: Analyzing trace with hash 1369903951, now seen corresponding path program 28 times [2018-07-24 10:47:16,144 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:16,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:16,145 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:16,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:16,145 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:16,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:16,565 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:16,566 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:16,566 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:16,574 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:16,575 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:16,601 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:16,601 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:16,604 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:16,619 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:16,619 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:17,618 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:17,639 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:17,639 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:17,658 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:17,658 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:17,711 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:17,711 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:17,715 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:17,730 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:17,730 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:17,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:17,781 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:17,781 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 60 [2018-07-24 10:47:17,781 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:17,782 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:47:17,782 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:47:17,783 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:47:17,783 INFO L87 Difference]: Start difference. First operand 96 states and 96 transitions. Second operand 31 states. [2018-07-24 10:47:17,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:17,960 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2018-07-24 10:47:17,963 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:47:17,964 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 95 [2018-07-24 10:47:17,964 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:17,965 INFO L225 Difference]: With dead ends: 105 [2018-07-24 10:47:17,965 INFO L226 Difference]: Without dead ends: 100 [2018-07-24 10:47:17,967 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 351 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:47:17,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-07-24 10:47:17,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2018-07-24 10:47:17,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-24 10:47:17,970 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-07-24 10:47:17,970 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 99 transitions. Word has length 95 [2018-07-24 10:47:17,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:17,970 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 99 transitions. [2018-07-24 10:47:17,970 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:47:17,970 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-07-24 10:47:17,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-07-24 10:47:17,971 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:17,971 INFO L353 BasicCegarLoop]: trace histogram [30, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:17,971 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:17,971 INFO L82 PathProgramCache]: Analyzing trace with hash -532248278, now seen corresponding path program 29 times [2018-07-24 10:47:17,972 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:17,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:17,972 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:17,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:17,972 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:17,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:18,481 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:18,482 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:18,482 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:18,489 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:18,490 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:18,662 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-07-24 10:47:18,662 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:18,666 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:18,682 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:18,683 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:20,824 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:20,847 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:20,847 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:20,864 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:20,864 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:22,331 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-07-24 10:47:22,331 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:22,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:22,351 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:22,351 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:22,399 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:22,401 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:22,401 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-07-24 10:47:22,402 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:22,402 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:47:22,403 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:47:22,403 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:47:22,403 INFO L87 Difference]: Start difference. First operand 99 states and 99 transitions. Second operand 32 states. [2018-07-24 10:47:22,643 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:22,644 INFO L93 Difference]: Finished difference Result 108 states and 108 transitions. [2018-07-24 10:47:22,644 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:47:22,644 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 98 [2018-07-24 10:47:22,645 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:22,646 INFO L225 Difference]: With dead ends: 108 [2018-07-24 10:47:22,646 INFO L226 Difference]: Without dead ends: 103 [2018-07-24 10:47:22,647 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 422 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:47:22,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-07-24 10:47:22,650 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2018-07-24 10:47:22,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:47:22,651 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 102 transitions. [2018-07-24 10:47:22,651 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 102 transitions. Word has length 98 [2018-07-24 10:47:22,651 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:22,651 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 102 transitions. [2018-07-24 10:47:22,651 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:47:22,652 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 102 transitions. [2018-07-24 10:47:22,652 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-07-24 10:47:22,652 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:22,652 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:22,653 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:22,653 INFO L82 PathProgramCache]: Analyzing trace with hash 249201007, now seen corresponding path program 30 times [2018-07-24 10:47:22,653 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:22,653 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:22,654 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:22,654 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:22,654 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:22,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:23,328 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:23,328 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:23,328 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:23,336 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:23,336 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:23,452 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-07-24 10:47:23,452 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:23,454 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:23,466 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:23,466 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:24,513 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:24,533 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:24,534 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:24,548 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:24,549 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:28,894 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-07-24 10:47:28,894 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:28,899 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:28,915 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:28,915 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:28,943 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:28,945 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:28,945 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-07-24 10:47:28,945 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:28,946 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:47:28,947 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:47:28,948 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:47:28,948 INFO L87 Difference]: Start difference. First operand 102 states and 102 transitions. Second operand 33 states. [2018-07-24 10:47:29,165 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:29,166 INFO L93 Difference]: Finished difference Result 111 states and 111 transitions. [2018-07-24 10:47:29,166 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:47:29,166 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 101 [2018-07-24 10:47:29,167 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:29,168 INFO L225 Difference]: With dead ends: 111 [2018-07-24 10:47:29,168 INFO L226 Difference]: Without dead ends: 106 [2018-07-24 10:47:29,169 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 435 GetRequests, 373 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:47:29,169 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-07-24 10:47:29,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 105. [2018-07-24 10:47:29,172 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-07-24 10:47:29,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-07-24 10:47:29,173 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 101 [2018-07-24 10:47:29,173 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:29,173 INFO L471 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2018-07-24 10:47:29,173 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:47:29,173 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-07-24 10:47:29,174 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-07-24 10:47:29,174 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:29,174 INFO L353 BasicCegarLoop]: trace histogram [32, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:29,174 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:29,175 INFO L82 PathProgramCache]: Analyzing trace with hash 1682106122, now seen corresponding path program 31 times [2018-07-24 10:47:29,175 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:29,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:29,175 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:29,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:29,176 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:29,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:29,702 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:29,702 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:29,702 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:29,711 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:29,712 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:29,737 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:29,739 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:29,756 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:29,756 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:30,994 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:31,014 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:31,014 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:31,029 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:31,030 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:31,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:31,088 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:31,100 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:31,100 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:31,114 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:31,115 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:31,116 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 66 [2018-07-24 10:47:31,116 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:31,116 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:47:31,117 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:47:31,117 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:47:31,118 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand 34 states. [2018-07-24 10:47:31,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:31,257 INFO L93 Difference]: Finished difference Result 114 states and 114 transitions. [2018-07-24 10:47:31,257 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:47:31,258 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 104 [2018-07-24 10:47:31,258 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:31,259 INFO L225 Difference]: With dead ends: 114 [2018-07-24 10:47:31,259 INFO L226 Difference]: Without dead ends: 109 [2018-07-24 10:47:31,260 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:47:31,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-07-24 10:47:31,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 108. [2018-07-24 10:47:31,264 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-07-24 10:47:31,264 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 108 transitions. [2018-07-24 10:47:31,265 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 108 transitions. Word has length 104 [2018-07-24 10:47:31,265 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:31,265 INFO L471 AbstractCegarLoop]: Abstraction has 108 states and 108 transitions. [2018-07-24 10:47:31,265 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:47:31,265 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 108 transitions. [2018-07-24 10:47:31,266 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-07-24 10:47:31,266 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:31,266 INFO L353 BasicCegarLoop]: trace histogram [33, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:31,266 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:31,266 INFO L82 PathProgramCache]: Analyzing trace with hash 1678432143, now seen corresponding path program 32 times [2018-07-24 10:47:31,267 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:31,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:31,267 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:31,267 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:31,267 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:31,276 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:32,139 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:32,139 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:32,139 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:32,147 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:47:32,147 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:32,174 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:47:32,174 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:32,176 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:32,189 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:32,189 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:33,505 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:33,524 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:33,524 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:33,540 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:47:33,540 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:33,598 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:47:33,599 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:33,603 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:33,620 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:33,620 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:33,703 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:33,705 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:33,705 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 68 [2018-07-24 10:47:33,705 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:33,706 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:47:33,706 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:47:33,707 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:47:33,707 INFO L87 Difference]: Start difference. First operand 108 states and 108 transitions. Second operand 35 states. [2018-07-24 10:47:33,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:33,832 INFO L93 Difference]: Finished difference Result 117 states and 117 transitions. [2018-07-24 10:47:33,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:47:33,834 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 107 [2018-07-24 10:47:33,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:33,834 INFO L225 Difference]: With dead ends: 117 [2018-07-24 10:47:33,834 INFO L226 Difference]: Without dead ends: 112 [2018-07-24 10:47:33,835 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 461 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:47:33,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-07-24 10:47:33,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-07-24 10:47:33,837 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-07-24 10:47:33,838 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-07-24 10:47:33,838 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 111 transitions. Word has length 107 [2018-07-24 10:47:33,838 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:33,838 INFO L471 AbstractCegarLoop]: Abstraction has 111 states and 111 transitions. [2018-07-24 10:47:33,838 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:47:33,839 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-07-24 10:47:33,839 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-07-24 10:47:33,839 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:33,839 INFO L353 BasicCegarLoop]: trace histogram [34, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:33,840 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:33,840 INFO L82 PathProgramCache]: Analyzing trace with hash -398893846, now seen corresponding path program 33 times [2018-07-24 10:47:33,840 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:33,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:33,841 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:33,841 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:33,841 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:33,849 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:34,379 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:34,380 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:34,380 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:34,387 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:47:34,388 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:34,698 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-07-24 10:47:34,698 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:34,700 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:34,714 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:34,714 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:36,056 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:36,077 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:36,078 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:36,094 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:47:36,094 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:40,524 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-07-24 10:47:40,525 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:40,529 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:40,546 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:40,546 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:40,575 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:40,576 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:40,577 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 36] total 70 [2018-07-24 10:47:40,577 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:40,577 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:47:40,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:47:40,578 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:47:40,578 INFO L87 Difference]: Start difference. First operand 111 states and 111 transitions. Second operand 36 states. [2018-07-24 10:47:40,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:40,779 INFO L93 Difference]: Finished difference Result 120 states and 120 transitions. [2018-07-24 10:47:40,780 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-24 10:47:40,780 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 110 [2018-07-24 10:47:40,780 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:40,781 INFO L225 Difference]: With dead ends: 120 [2018-07-24 10:47:40,781 INFO L226 Difference]: Without dead ends: 115 [2018-07-24 10:47:40,782 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 474 GetRequests, 406 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:47:40,782 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-07-24 10:47:40,785 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 114. [2018-07-24 10:47:40,785 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-07-24 10:47:40,785 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 114 transitions. [2018-07-24 10:47:40,786 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 114 transitions. Word has length 110 [2018-07-24 10:47:40,786 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:40,786 INFO L471 AbstractCegarLoop]: Abstraction has 114 states and 114 transitions. [2018-07-24 10:47:40,786 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:47:40,786 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 114 transitions. [2018-07-24 10:47:40,787 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-07-24 10:47:40,787 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:40,787 INFO L353 BasicCegarLoop]: trace histogram [35, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:40,787 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:40,787 INFO L82 PathProgramCache]: Analyzing trace with hash 166335919, now seen corresponding path program 34 times [2018-07-24 10:47:40,788 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:40,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:40,788 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:40,788 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:40,788 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:40,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:41,382 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:41,382 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:41,382 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:41,390 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:41,390 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:41,419 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:41,419 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:41,421 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:41,440 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:41,440 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:42,998 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:43,018 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:43,018 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:43,033 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:43,033 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:43,094 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:43,095 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:43,099 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:43,112 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:43,113 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:43,130 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:43,131 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:43,132 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 72 [2018-07-24 10:47:43,132 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:43,132 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:47:43,132 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:47:43,133 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:47:43,133 INFO L87 Difference]: Start difference. First operand 114 states and 114 transitions. Second operand 37 states. [2018-07-24 10:47:43,301 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:43,301 INFO L93 Difference]: Finished difference Result 123 states and 123 transitions. [2018-07-24 10:47:43,302 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:47:43,302 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 113 [2018-07-24 10:47:43,302 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:43,303 INFO L225 Difference]: With dead ends: 123 [2018-07-24 10:47:43,303 INFO L226 Difference]: Without dead ends: 118 [2018-07-24 10:47:43,304 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:47:43,304 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-07-24 10:47:43,306 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 117. [2018-07-24 10:47:43,306 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-07-24 10:47:43,307 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-07-24 10:47:43,307 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 117 transitions. Word has length 113 [2018-07-24 10:47:43,307 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:43,307 INFO L471 AbstractCegarLoop]: Abstraction has 117 states and 117 transitions. [2018-07-24 10:47:43,307 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:47:43,308 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-07-24 10:47:43,308 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-07-24 10:47:43,308 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:43,308 INFO L353 BasicCegarLoop]: trace histogram [36, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:43,309 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:43,309 INFO L82 PathProgramCache]: Analyzing trace with hash -1640502582, now seen corresponding path program 35 times [2018-07-24 10:47:43,309 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:43,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:43,310 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:43,310 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:43,310 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:43,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:44,164 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:44,164 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:44,164 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:44,171 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:44,171 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:44,465 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-07-24 10:47:44,465 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:44,468 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:44,483 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:44,483 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:46,006 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:46,027 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:46,027 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:46,043 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:46,043 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:48,718 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-07-24 10:47:48,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:48,723 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:48,742 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:48,743 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:48,770 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:48,771 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:48,772 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 74 [2018-07-24 10:47:48,772 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:48,772 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:47:48,773 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:47:48,773 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:47:48,773 INFO L87 Difference]: Start difference. First operand 117 states and 117 transitions. Second operand 38 states. [2018-07-24 10:47:48,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:48,915 INFO L93 Difference]: Finished difference Result 126 states and 126 transitions. [2018-07-24 10:47:48,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:47:48,916 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 116 [2018-07-24 10:47:48,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:48,916 INFO L225 Difference]: With dead ends: 126 [2018-07-24 10:47:48,916 INFO L226 Difference]: Without dead ends: 121 [2018-07-24 10:47:48,917 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 428 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:47:48,917 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-07-24 10:47:48,919 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 120. [2018-07-24 10:47:48,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-07-24 10:47:48,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 120 transitions. [2018-07-24 10:47:48,920 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 120 transitions. Word has length 116 [2018-07-24 10:47:48,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:48,920 INFO L471 AbstractCegarLoop]: Abstraction has 120 states and 120 transitions. [2018-07-24 10:47:48,921 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:47:48,921 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 120 transitions. [2018-07-24 10:47:48,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:47:48,921 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:48,921 INFO L353 BasicCegarLoop]: trace histogram [37, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:48,922 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:48,922 INFO L82 PathProgramCache]: Analyzing trace with hash -341165105, now seen corresponding path program 36 times [2018-07-24 10:47:48,922 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:48,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:48,923 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:48,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:48,923 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:48,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:49,519 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:49,520 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:49,520 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:49,527 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:49,527 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:49,660 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-07-24 10:47:49,660 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:49,663 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:49,678 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:49,678 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:51,123 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:51,144 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:51,144 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:51,160 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:51,160 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:00,979 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-07-24 10:48:00,980 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:00,985 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:01,005 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,005 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:01,072 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,075 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:01,076 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 76 [2018-07-24 10:48:01,076 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:01,076 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:48:01,077 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:48:01,077 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:48:01,077 INFO L87 Difference]: Start difference. First operand 120 states and 120 transitions. Second operand 39 states. [2018-07-24 10:48:01,331 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:01,331 INFO L93 Difference]: Finished difference Result 129 states and 129 transitions. [2018-07-24 10:48:01,332 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:48:01,332 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 119 [2018-07-24 10:48:01,332 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:01,333 INFO L225 Difference]: With dead ends: 129 [2018-07-24 10:48:01,333 INFO L226 Difference]: Without dead ends: 124 [2018-07-24 10:48:01,334 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 439 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:48:01,334 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-07-24 10:48:01,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 123. [2018-07-24 10:48:01,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-07-24 10:48:01,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-07-24 10:48:01,337 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 123 transitions. Word has length 119 [2018-07-24 10:48:01,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:01,337 INFO L471 AbstractCegarLoop]: Abstraction has 123 states and 123 transitions. [2018-07-24 10:48:01,337 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:48:01,337 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-07-24 10:48:01,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-07-24 10:48:01,338 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:01,338 INFO L353 BasicCegarLoop]: trace histogram [38, 37, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:01,338 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:01,338 INFO L82 PathProgramCache]: Analyzing trace with hash 1976340650, now seen corresponding path program 37 times [2018-07-24 10:48:01,338 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:01,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:01,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:01,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:01,339 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:01,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:02,068 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,068 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:02,068 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:02,075 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:02,075 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:02,116 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:02,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:02,140 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,141 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:04,786 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,807 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:04,807 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:04,823 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:04,823 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:04,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:04,889 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:04,910 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,911 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:04,962 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,963 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:04,963 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 78 [2018-07-24 10:48:04,963 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:04,964 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:48:04,964 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:48:04,965 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:48:04,965 INFO L87 Difference]: Start difference. First operand 123 states and 123 transitions. Second operand 40 states. [2018-07-24 10:48:05,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:05,171 INFO L93 Difference]: Finished difference Result 132 states and 132 transitions. [2018-07-24 10:48:05,171 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 10:48:05,171 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 122 [2018-07-24 10:48:05,172 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:05,172 INFO L225 Difference]: With dead ends: 132 [2018-07-24 10:48:05,172 INFO L226 Difference]: Without dead ends: 127 [2018-07-24 10:48:05,173 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 526 GetRequests, 450 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:48:05,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-07-24 10:48:05,175 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 126. [2018-07-24 10:48:05,175 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-07-24 10:48:05,176 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 126 transitions. [2018-07-24 10:48:05,176 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 126 transitions. Word has length 122 [2018-07-24 10:48:05,177 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:05,177 INFO L471 AbstractCegarLoop]: Abstraction has 126 states and 126 transitions. [2018-07-24 10:48:05,177 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:48:05,177 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 126 transitions. [2018-07-24 10:48:05,177 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-07-24 10:48:05,178 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:05,178 INFO L353 BasicCegarLoop]: trace histogram [39, 38, 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:05,178 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:05,178 INFO L82 PathProgramCache]: Analyzing trace with hash 1191004655, now seen corresponding path program 38 times [2018-07-24 10:48:05,178 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:05,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:05,179 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:05,179 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:05,179 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:05,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:06,679 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,680 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:06,680 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:06,689 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:06,690 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:06,719 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:06,719 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:06,721 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:06,743 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,743 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:08,354 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:08,376 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:08,376 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:08,391 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:08,391 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:08,452 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:08,452 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:08,456 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:08,471 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:08,471 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:08,493 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:08,494 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:08,495 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 80 [2018-07-24 10:48:08,495 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:08,495 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:48:08,495 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:48:08,495 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:48:08,496 INFO L87 Difference]: Start difference. First operand 126 states and 126 transitions. Second operand 41 states. [2018-07-24 10:48:08,655 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:08,655 INFO L93 Difference]: Finished difference Result 135 states and 135 transitions. [2018-07-24 10:48:08,656 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:48:08,656 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 125 [2018-07-24 10:48:08,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:08,657 INFO L225 Difference]: With dead ends: 135 [2018-07-24 10:48:08,658 INFO L226 Difference]: Without dead ends: 130 [2018-07-24 10:48:08,658 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 539 GetRequests, 461 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:48:08,659 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-07-24 10:48:08,661 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 129. [2018-07-24 10:48:08,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-07-24 10:48:08,662 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-07-24 10:48:08,663 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 129 transitions. Word has length 125 [2018-07-24 10:48:08,663 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:08,663 INFO L471 AbstractCegarLoop]: Abstraction has 129 states and 129 transitions. [2018-07-24 10:48:08,663 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:48:08,663 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-07-24 10:48:08,664 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-07-24 10:48:08,664 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:08,664 INFO L353 BasicCegarLoop]: trace histogram [40, 39, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:08,664 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:08,664 INFO L82 PathProgramCache]: Analyzing trace with hash -66761078, now seen corresponding path program 39 times [2018-07-24 10:48:08,665 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:08,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:08,665 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:08,665 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:08,665 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:08,674 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:09,846 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:09,846 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:09,846 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:09,854 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:09,854 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:10,061 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-07-24 10:48:10,061 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:10,064 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:10,081 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:10,081 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:11,795 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:11,816 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:11,816 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:11,831 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:11,831 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:20,631 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-07-24 10:48:20,631 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:20,637 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:20,660 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,660 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:20,726 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,729 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:20,730 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42, 42, 42] total 82 [2018-07-24 10:48:20,730 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:20,730 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:48:20,731 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:48:20,731 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:48:20,732 INFO L87 Difference]: Start difference. First operand 129 states and 129 transitions. Second operand 42 states. [2018-07-24 10:48:21,041 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:21,041 INFO L93 Difference]: Finished difference Result 138 states and 138 transitions. [2018-07-24 10:48:21,041 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-07-24 10:48:21,042 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 128 [2018-07-24 10:48:21,042 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:21,043 INFO L225 Difference]: With dead ends: 138 [2018-07-24 10:48:21,043 INFO L226 Difference]: Without dead ends: 133 [2018-07-24 10:48:21,043 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 552 GetRequests, 472 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:48:21,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-07-24 10:48:21,046 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 132. [2018-07-24 10:48:21,046 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-07-24 10:48:21,046 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 132 transitions. [2018-07-24 10:48:21,047 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 132 transitions. Word has length 128 [2018-07-24 10:48:21,047 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:21,047 INFO L471 AbstractCegarLoop]: Abstraction has 132 states and 132 transitions. [2018-07-24 10:48:21,047 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:48:21,047 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 132 transitions. [2018-07-24 10:48:21,048 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-07-24 10:48:21,048 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:21,048 INFO L353 BasicCegarLoop]: trace histogram [41, 40, 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:21,048 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:21,048 INFO L82 PathProgramCache]: Analyzing trace with hash -871022577, now seen corresponding path program 40 times [2018-07-24 10:48:21,049 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:21,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:21,049 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:21,049 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:21,049 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:21,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:22,141 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:22,141 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:22,141 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:22,149 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:22,149 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:22,187 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:22,187 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:22,190 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:22,212 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:22,212 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:23,992 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:24,012 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:24,012 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:24,027 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:24,027 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:24,100 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:24,100 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:24,104 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:24,121 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:24,122 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:24,188 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:24,189 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:24,189 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 84 [2018-07-24 10:48:24,189 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:24,190 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:48:24,190 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:48:24,190 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:48:24,191 INFO L87 Difference]: Start difference. First operand 132 states and 132 transitions. Second operand 43 states. [2018-07-24 10:48:24,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:24,460 INFO L93 Difference]: Finished difference Result 141 states and 141 transitions. [2018-07-24 10:48:24,460 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:48:24,460 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 131 [2018-07-24 10:48:24,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:24,461 INFO L225 Difference]: With dead ends: 141 [2018-07-24 10:48:24,461 INFO L226 Difference]: Without dead ends: 136 [2018-07-24 10:48:24,462 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 565 GetRequests, 483 SyntacticMatches, 0 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:48:24,464 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-07-24 10:48:24,467 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 135. [2018-07-24 10:48:24,467 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-07-24 10:48:24,468 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-07-24 10:48:24,468 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 135 transitions. Word has length 131 [2018-07-24 10:48:24,468 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:24,468 INFO L471 AbstractCegarLoop]: Abstraction has 135 states and 135 transitions. [2018-07-24 10:48:24,468 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:48:24,468 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-07-24 10:48:24,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-07-24 10:48:24,469 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:24,469 INFO L353 BasicCegarLoop]: trace histogram [42, 41, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:24,469 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:24,470 INFO L82 PathProgramCache]: Analyzing trace with hash 997205098, now seen corresponding path program 41 times [2018-07-24 10:48:24,470 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:24,470 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:24,470 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:24,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:24,471 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:24,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:25,961 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:25,962 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:25,962 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:25,971 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:25,971 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:26,472 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-07-24 10:48:26,472 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:26,475 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:26,498 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:26,498 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:28,432 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:28,453 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:28,453 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:28,468 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:28,468 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:33,078 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-07-24 10:48:33,079 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:33,096 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:33,113 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:33,113 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:33,144 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:33,146 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:33,146 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 86 [2018-07-24 10:48:33,147 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:33,147 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:48:33,147 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:48:33,148 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:48:33,148 INFO L87 Difference]: Start difference. First operand 135 states and 135 transitions. Second operand 44 states. [2018-07-24 10:48:33,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:33,606 INFO L93 Difference]: Finished difference Result 144 states and 144 transitions. [2018-07-24 10:48:33,607 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-24 10:48:33,608 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 134 [2018-07-24 10:48:33,608 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:33,610 INFO L225 Difference]: With dead ends: 144 [2018-07-24 10:48:33,610 INFO L226 Difference]: Without dead ends: 139 [2018-07-24 10:48:33,611 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 578 GetRequests, 494 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:48:33,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-07-24 10:48:33,613 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 138. [2018-07-24 10:48:33,613 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-07-24 10:48:33,614 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 138 transitions. [2018-07-24 10:48:33,614 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 138 transitions. Word has length 134 [2018-07-24 10:48:33,615 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:33,615 INFO L471 AbstractCegarLoop]: Abstraction has 138 states and 138 transitions. [2018-07-24 10:48:33,615 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:48:33,615 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 138 transitions. [2018-07-24 10:48:33,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-07-24 10:48:33,616 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:33,616 INFO L353 BasicCegarLoop]: trace histogram [43, 42, 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:33,616 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:33,616 INFO L82 PathProgramCache]: Analyzing trace with hash -1113317841, now seen corresponding path program 42 times [2018-07-24 10:48:33,617 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:33,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:33,617 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:33,617 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:33,617 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:33,628 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:35,071 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:35,072 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:35,072 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:35,080 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:35,080 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:35,269 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-07-24 10:48:35,270 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:35,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:35,291 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:35,291 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:37,225 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:37,247 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:37,247 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:37,262 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:37,262 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:04,884 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-07-24 10:49:04,884 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:04,890 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:04,906 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:04,906 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:04,931 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:04,933 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:04,934 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 88 [2018-07-24 10:49:04,934 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:04,934 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:49:04,934 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:49:04,935 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:49:04,935 INFO L87 Difference]: Start difference. First operand 138 states and 138 transitions. Second operand 45 states. [2018-07-24 10:49:05,100 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:05,100 INFO L93 Difference]: Finished difference Result 147 states and 147 transitions. [2018-07-24 10:49:05,100 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-24 10:49:05,101 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 137 [2018-07-24 10:49:05,101 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:05,102 INFO L225 Difference]: With dead ends: 147 [2018-07-24 10:49:05,102 INFO L226 Difference]: Without dead ends: 142 [2018-07-24 10:49:05,103 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 505 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:49:05,103 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-07-24 10:49:05,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 141. [2018-07-24 10:49:05,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:49:05,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-07-24 10:49:05,107 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 141 transitions. Word has length 137 [2018-07-24 10:49:05,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:05,107 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 141 transitions. [2018-07-24 10:49:05,107 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:49:05,107 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-07-24 10:49:05,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-07-24 10:49:05,108 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:05,108 INFO L353 BasicCegarLoop]: trace histogram [44, 43, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:05,108 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:05,109 INFO L82 PathProgramCache]: Analyzing trace with hash -1675947446, now seen corresponding path program 43 times [2018-07-24 10:49:05,109 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:05,109 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:05,109 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:05,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:05,110 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:05,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:06,225 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,226 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:06,226 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:06,234 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:06,234 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:06,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:06,269 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:06,292 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:08,357 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,377 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:08,377 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:08,393 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:08,393 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:08,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:08,462 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:08,481 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,481 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:08,505 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,507 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:08,507 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 90 [2018-07-24 10:49:08,507 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:08,508 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-24 10:49:08,508 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-24 10:49:08,508 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:49:08,509 INFO L87 Difference]: Start difference. First operand 141 states and 141 transitions. Second operand 46 states. [2018-07-24 10:49:08,691 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:08,691 INFO L93 Difference]: Finished difference Result 150 states and 150 transitions. [2018-07-24 10:49:08,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-07-24 10:49:08,692 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 140 [2018-07-24 10:49:08,692 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:08,693 INFO L225 Difference]: With dead ends: 150 [2018-07-24 10:49:08,694 INFO L226 Difference]: Without dead ends: 145 [2018-07-24 10:49:08,694 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 604 GetRequests, 516 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:49:08,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-07-24 10:49:08,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 144. [2018-07-24 10:49:08,697 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-07-24 10:49:08,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 144 transitions. [2018-07-24 10:49:08,698 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 144 transitions. Word has length 140 [2018-07-24 10:49:08,698 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:08,698 INFO L471 AbstractCegarLoop]: Abstraction has 144 states and 144 transitions. [2018-07-24 10:49:08,698 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-24 10:49:08,699 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 144 transitions. [2018-07-24 10:49:08,699 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-07-24 10:49:08,699 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:08,699 INFO L353 BasicCegarLoop]: trace histogram [45, 44, 44, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:08,700 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:08,700 INFO L82 PathProgramCache]: Analyzing trace with hash 282846287, now seen corresponding path program 44 times [2018-07-24 10:49:08,700 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:08,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:08,701 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:08,701 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:08,701 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:08,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:09,692 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,693 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:09,693 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:09,702 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:09,703 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:09,748 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:09,748 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:09,750 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:09,770 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,770 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:12,273 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,295 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:12,295 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:12,310 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:12,310 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:12,387 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:12,387 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:12,391 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:12,411 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,412 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:12,438 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,439 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:12,440 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 92 [2018-07-24 10:49:12,440 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:12,440 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-24 10:49:12,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-24 10:49:12,441 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:49:12,441 INFO L87 Difference]: Start difference. First operand 144 states and 144 transitions. Second operand 47 states. [2018-07-24 10:49:12,601 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:12,601 INFO L93 Difference]: Finished difference Result 153 states and 153 transitions. [2018-07-24 10:49:12,601 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:49:12,601 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 143 [2018-07-24 10:49:12,602 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:12,603 INFO L225 Difference]: With dead ends: 153 [2018-07-24 10:49:12,603 INFO L226 Difference]: Without dead ends: 148 [2018-07-24 10:49:12,604 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 617 GetRequests, 527 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:49:12,604 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-07-24 10:49:12,607 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 147. [2018-07-24 10:49:12,607 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-07-24 10:49:12,608 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-07-24 10:49:12,608 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 147 transitions. Word has length 143 [2018-07-24 10:49:12,608 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:12,608 INFO L471 AbstractCegarLoop]: Abstraction has 147 states and 147 transitions. [2018-07-24 10:49:12,608 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-24 10:49:12,608 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-07-24 10:49:12,609 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-07-24 10:49:12,609 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:12,609 INFO L353 BasicCegarLoop]: trace histogram [46, 45, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:12,609 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:12,610 INFO L82 PathProgramCache]: Analyzing trace with hash -1013704662, now seen corresponding path program 45 times [2018-07-24 10:49:12,610 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:12,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:12,610 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:12,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:12,611 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:12,620 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:15,352 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:15,352 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:15,353 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:15,363 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:15,363 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:15,692 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-07-24 10:49:15,693 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:15,697 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:15,717 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:15,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:18,139 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:18,160 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:18,161 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:18,175 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:18,176 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:35,412 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-07-24 10:49:35,412 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:35,418 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:35,435 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:35,436 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:35,460 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:35,462 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:35,462 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48, 48, 48] total 94 [2018-07-24 10:49:35,463 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:35,463 INFO L450 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-07-24 10:49:35,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-07-24 10:49:35,463 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:49:35,464 INFO L87 Difference]: Start difference. First operand 147 states and 147 transitions. Second operand 48 states. [2018-07-24 10:49:35,642 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:35,642 INFO L93 Difference]: Finished difference Result 156 states and 156 transitions. [2018-07-24 10:49:35,643 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-07-24 10:49:35,643 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-07-24 10:49:35,643 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:35,643 INFO L225 Difference]: With dead ends: 156 [2018-07-24 10:49:35,644 INFO L226 Difference]: Without dead ends: 151 [2018-07-24 10:49:35,644 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 630 GetRequests, 538 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:49:35,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-07-24 10:49:35,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 150. [2018-07-24 10:49:35,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-07-24 10:49:35,647 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 150 transitions. [2018-07-24 10:49:35,647 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 150 transitions. Word has length 146 [2018-07-24 10:49:35,647 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:35,648 INFO L471 AbstractCegarLoop]: Abstraction has 150 states and 150 transitions. [2018-07-24 10:49:35,648 INFO L472 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-07-24 10:49:35,648 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 150 transitions. [2018-07-24 10:49:35,648 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-07-24 10:49:35,648 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:35,648 INFO L353 BasicCegarLoop]: trace histogram [47, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:35,649 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:35,649 INFO L82 PathProgramCache]: Analyzing trace with hash -1922133393, now seen corresponding path program 46 times [2018-07-24 10:49:35,649 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:35,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:35,649 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:35,649 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:35,650 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:35,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:36,879 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:36,880 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:36,880 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:36,888 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:36,888 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:36,920 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:36,920 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:36,923 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:36,942 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:36,942 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:39,281 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:39,303 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:39,303 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:39,318 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:39,318 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:39,400 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:39,401 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:39,405 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:39,426 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:39,426 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:39,449 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:39,450 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:39,451 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 96 [2018-07-24 10:49:39,451 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:39,451 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:49:39,452 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:49:39,452 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:49:39,452 INFO L87 Difference]: Start difference. First operand 150 states and 150 transitions. Second operand 49 states. [2018-07-24 10:49:39,680 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:39,680 INFO L93 Difference]: Finished difference Result 159 states and 159 transitions. [2018-07-24 10:49:39,681 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:49:39,681 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 149 [2018-07-24 10:49:39,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:39,682 INFO L225 Difference]: With dead ends: 159 [2018-07-24 10:49:39,682 INFO L226 Difference]: Without dead ends: 154 [2018-07-24 10:49:39,683 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 643 GetRequests, 549 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:49:39,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-07-24 10:49:39,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 153. [2018-07-24 10:49:39,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-07-24 10:49:39,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-07-24 10:49:39,687 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 153 transitions. Word has length 149 [2018-07-24 10:49:39,687 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:39,687 INFO L471 AbstractCegarLoop]: Abstraction has 153 states and 153 transitions. [2018-07-24 10:49:39,687 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-24 10:49:39,687 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-07-24 10:49:39,688 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-07-24 10:49:39,688 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:39,688 INFO L353 BasicCegarLoop]: trace histogram [48, 47, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:39,688 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:39,688 INFO L82 PathProgramCache]: Analyzing trace with hash 1961440778, now seen corresponding path program 47 times [2018-07-24 10:49:39,688 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:39,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:39,689 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:39,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:39,689 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:39,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:41,503 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:41,503 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:41,503 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:41,510 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:41,510 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:42,362 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-07-24 10:49:42,362 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:42,366 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:42,388 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:42,388 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:44,820 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:44,842 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:44,842 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:44,857 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:44,857 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:52,533 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-07-24 10:49:52,534 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:52,540 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:52,558 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:52,558 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:52,581 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:52,583 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:52,583 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 98 [2018-07-24 10:49:52,583 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:52,584 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-24 10:49:52,584 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-24 10:49:52,585 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:49:52,585 INFO L87 Difference]: Start difference. First operand 153 states and 153 transitions. Second operand 50 states. [2018-07-24 10:49:52,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:52,742 INFO L93 Difference]: Finished difference Result 162 states and 162 transitions. [2018-07-24 10:49:52,742 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-07-24 10:49:52,743 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 152 [2018-07-24 10:49:52,743 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:52,744 INFO L225 Difference]: With dead ends: 162 [2018-07-24 10:49:52,744 INFO L226 Difference]: Without dead ends: 157 [2018-07-24 10:49:52,746 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 560 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:49:52,746 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-07-24 10:49:52,749 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-07-24 10:49:52,749 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-07-24 10:49:52,750 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 156 transitions. [2018-07-24 10:49:52,750 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 156 transitions. Word has length 152 [2018-07-24 10:49:52,750 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:52,750 INFO L471 AbstractCegarLoop]: Abstraction has 156 states and 156 transitions. [2018-07-24 10:49:52,751 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-24 10:49:52,751 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 156 transitions. [2018-07-24 10:49:52,751 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-07-24 10:49:52,752 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:52,752 INFO L353 BasicCegarLoop]: trace histogram [49, 48, 48, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:52,752 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:52,752 INFO L82 PathProgramCache]: Analyzing trace with hash -309450609, now seen corresponding path program 48 times [2018-07-24 10:49:52,752 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:52,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:52,753 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:52,753 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:52,753 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:52,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:53,812 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:53,813 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:53,813 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:53,822 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:53,822 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:54,118 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-07-24 10:49:54,118 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:54,122 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:54,144 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:54,144 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:57,090 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:57,111 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:57,111 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:57,126 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:57,126 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:50:53,820 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-07-24 10:50:53,820 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:53,827 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:53,847 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:53,847 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:53,880 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:53,884 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:53,884 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 100 [2018-07-24 10:50:53,884 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:53,884 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:50:53,885 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:50:53,885 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2018-07-24 10:50:53,885 INFO L87 Difference]: Start difference. First operand 156 states and 156 transitions. Second operand 51 states. [2018-07-24 10:50:54,082 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:54,082 INFO L93 Difference]: Finished difference Result 165 states and 165 transitions. [2018-07-24 10:50:54,082 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:50:54,082 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 155 [2018-07-24 10:50:54,083 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:54,083 INFO L225 Difference]: With dead ends: 165 [2018-07-24 10:50:54,083 INFO L226 Difference]: Without dead ends: 160 [2018-07-24 10:50:54,084 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 669 GetRequests, 571 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.9s TimeCoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2018-07-24 10:50:54,084 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-07-24 10:50:54,087 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 159. [2018-07-24 10:50:54,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-07-24 10:50:54,088 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 159 transitions. [2018-07-24 10:50:54,088 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 159 transitions. Word has length 155 [2018-07-24 10:50:54,088 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:54,088 INFO L471 AbstractCegarLoop]: Abstraction has 159 states and 159 transitions. [2018-07-24 10:50:54,088 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:50:54,088 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 159 transitions. [2018-07-24 10:50:54,089 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-07-24 10:50:54,089 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:54,089 INFO L353 BasicCegarLoop]: trace histogram [50, 49, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:54,089 INFO L414 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:54,089 INFO L82 PathProgramCache]: Analyzing trace with hash 1890085866, now seen corresponding path program 49 times [2018-07-24 10:50:54,090 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:54,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:54,090 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:54,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:54,090 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:54,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat Received shutdown request... [2018-07-24 10:50:54,813 WARN L540 AbstractCegarLoop]: Verification canceled [2018-07-24 10:50:54,817 WARN L202 ceAbstractionStarter]: Timeout [2018-07-24 10:50:54,817 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 10:50:54 BoogieIcfgContainer [2018-07-24 10:50:54,817 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 10:50:54,818 INFO L168 Benchmark]: Toolchain (without parser) took 258103.80 ms. Allocated memory was 1.5 GB in the beginning and 2.5 GB in the end (delta: 1.0 GB). Free memory was 1.4 GB in the beginning and 2.0 GB in the end (delta: -539.0 MB). Peak memory consumption was 465.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:50:54,820 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:50:54,820 INFO L168 Benchmark]: CACSL2BoogieTranslator took 301.95 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:50:54,820 INFO L168 Benchmark]: Boogie Procedure Inliner took 24.52 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:50:54,821 INFO L168 Benchmark]: Boogie Preprocessor took 24.59 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:50:54,821 INFO L168 Benchmark]: RCFGBuilder took 310.90 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 730.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -780.1 MB). Peak memory consumption was 26.8 MB. Max. memory is 7.1 GB. [2018-07-24 10:50:54,824 INFO L168 Benchmark]: TraceAbstraction took 257435.26 ms. Allocated memory was 2.3 GB in the beginning and 2.5 GB in the end (delta: 274.2 MB). Free memory was 2.2 GB in the beginning and 2.0 GB in the end (delta: 230.6 MB). Peak memory consumption was 504.8 MB. Max. memory is 7.1 GB. [2018-07-24 10:50:54,826 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 301.95 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 24.52 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 24.59 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 310.90 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 730.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -780.1 MB). Peak memory consumption was 26.8 MB. Max. memory is 7.1 GB. * TraceAbstraction took 257435.26 ms. Allocated memory was 2.3 GB in the beginning and 2.5 GB in the end (delta: 274.2 MB). Free memory was 2.2 GB in the beginning and 2.0 GB in the end (delta: 230.6 MB). Peak memory consumption was 504.8 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 4]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 4). Cancelled while BasicCegarLoop was analyzing trace of length 159 with TraceHistMax 50, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while PredicateComparison was comparing new predicate (quantifier-free) to 27 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 19 locations, 1 error locations. TIMEOUT Result, 257.3s OverallTime, 51 OverallIterations, 50 TraceHistogramMax, 7.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 558 SDtfs, 1225 SDslu, 8609 SDs, 0 SdLazy, 3471 SolverSat, 70 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.0s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 17453 GetRequests, 15004 SyntacticMatches, 0 SemanticMatches, 2449 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 81.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=159occurred in iteration=50, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 50 MinimizatonAttempts, 49 StatesRemovedByMinimization, 49 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.5s SsaConstructionTime, 157.8s SatisfiabilityAnalysisTime, 86.9s InterpolantComputationTime, 12189 NumberOfCodeBlocks, 12189 NumberOfCodeBlocksAsserted, 1410 NumberOfCheckSat, 20059 ConstructedInterpolants, 0 QuantifiedInterpolants, 5943221 SizeOfPredicates, 96 NumberOfNonLiveVariables, 13968 ConjunctsInSsa, 2544 ConjunctsInUnsatCore, 242 InterpolantComputations, 2 PerfectInterpolantSequences, 0/288120 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/array_false-unreach-call1_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_10-50-54-835.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/array_false-unreach-call1_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_10-50-54-835.csv Completed graceful shutdown