java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array_false-unreach-call2_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:47:53,695 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:47:53,696 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:47:53,711 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:47:53,711 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:47:53,712 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:47:53,714 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:47:53,716 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:47:53,718 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:47:53,719 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:47:53,720 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:47:53,720 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:47:53,721 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:47:53,722 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:47:53,723 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:47:53,724 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:47:53,725 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:47:53,727 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:47:53,729 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:47:53,730 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:47:53,731 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:47:53,732 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:47:53,735 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:47:53,735 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:47:53,735 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:47:53,736 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:47:53,737 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:47:53,738 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:47:53,739 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:47:53,740 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:47:53,740 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:47:53,741 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-07-24 10:47:53,744 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:47:53,759 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:47:53,759 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:47:53,760 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:47:53,760 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:47:53,760 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:47:53,761 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:47:53,761 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:47:53,761 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:47:53,761 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:47:53,761 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:47:53,762 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:47:53,762 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:47:53,762 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:47:53,763 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:47:53,763 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:47:53,763 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:47:53,763 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:47:53,763 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:47:53,764 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:47:53,764 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:47:53,764 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:47:53,764 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:47:53,765 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:47:53,765 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:47:53,765 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:47:53,765 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:47:53,765 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:47:53,765 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:47:53,766 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:47:53,766 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:47:53,766 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:47:53,766 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:47:53,766 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:47:53,821 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:47:53,840 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:47:53,844 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:47:53,846 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:47:53,846 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:47:53,847 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array_false-unreach-call2_true-termination.i [2018-07-24 10:47:54,208 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f5ab13741/83b17abade3544d380cf735eaef71a47/FLAG8047a660c [2018-07-24 10:47:54,337 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:47:54,337 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_false-unreach-call2_true-termination.i [2018-07-24 10:47:54,344 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f5ab13741/83b17abade3544d380cf735eaef71a47/FLAG8047a660c [2018-07-24 10:47:54,358 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/f5ab13741/83b17abade3544d380cf735eaef71a47 [2018-07-24 10:47:54,368 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:47:54,369 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:47:54,371 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:47:54,371 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:47:54,378 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:47:54,379 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,383 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@47db165b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54, skipping insertion in model container [2018-07-24 10:47:54,384 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,588 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:47:54,628 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:47:54,644 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:47:54,649 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:47:54,665 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54 WrapperNode [2018-07-24 10:47:54,665 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:47:54,667 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:47:54,667 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:47:54,667 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:47:54,677 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,687 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,693 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:47:54,693 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:47:54,693 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:47:54,694 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:47:54,704 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,704 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,705 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,705 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,707 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,713 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,714 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... [2018-07-24 10:47:54,715 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:47:54,716 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:47:54,716 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:47:54,716 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:47:54,718 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:47:54,776 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:47:54,777 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:47:54,777 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:47:54,777 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:47:54,777 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:47:54,778 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:47:54,778 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:47:54,778 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:47:55,016 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:47:55,017 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:47:55 BoogieIcfgContainer [2018-07-24 10:47:55,017 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:47:55,018 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:47:55,018 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:47:55,021 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:47:55,022 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:47:54" (1/3) ... [2018-07-24 10:47:55,024 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3af8a62b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:47:55, skipping insertion in model container [2018-07-24 10:47:55,024 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:47:54" (2/3) ... [2018-07-24 10:47:55,024 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3af8a62b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:47:55, skipping insertion in model container [2018-07-24 10:47:55,025 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:47:55" (3/3) ... [2018-07-24 10:47:55,028 INFO L112 eAbstractionObserver]: Analyzing ICFG array_false-unreach-call2_true-termination.i [2018-07-24 10:47:55,038 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:47:55,050 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:47:55,093 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:47:55,094 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:47:55,094 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:47:55,094 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:47:55,094 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:47:55,094 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:47:55,094 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:47:55,095 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:47:55,095 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:47:55,110 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states. [2018-07-24 10:47:55,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:47:55,116 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:55,117 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:55,117 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:55,121 INFO L82 PathProgramCache]: Analyzing trace with hash -1545526514, now seen corresponding path program 1 times [2018-07-24 10:47:55,124 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:55,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:55,176 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:55,176 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:55,176 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:55,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:55,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,238 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:47:55,238 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:47:55,238 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:47:55,243 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:47:55,259 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:47:55,260 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:47:55,263 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 2 states. [2018-07-24 10:47:55,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:55,286 INFO L93 Difference]: Finished difference Result 30 states and 33 transitions. [2018-07-24 10:47:55,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:47:55,288 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:47:55,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:55,297 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:47:55,298 INFO L226 Difference]: Without dead ends: 13 [2018-07-24 10:47:55,301 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:47:55,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-24 10:47:55,337 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-24 10:47:55,338 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-24 10:47:55,339 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-07-24 10:47:55,341 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 10 [2018-07-24 10:47:55,341 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:55,342 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-07-24 10:47:55,342 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:47:55,342 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-07-24 10:47:55,342 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:47:55,343 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:55,343 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:55,343 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:55,343 INFO L82 PathProgramCache]: Analyzing trace with hash -936233585, now seen corresponding path program 1 times [2018-07-24 10:47:55,344 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:55,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:55,345 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:55,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:55,345 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:55,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:55,392 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,393 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:47:55,393 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:47:55,393 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:47:55,395 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:47:55,395 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:47:55,395 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:47:55,395 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 3 states. [2018-07-24 10:47:55,439 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:55,440 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-24 10:47:55,441 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:47:55,441 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:47:55,441 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:55,442 INFO L225 Difference]: With dead ends: 21 [2018-07-24 10:47:55,442 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:47:55,443 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:47:55,443 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:47:55,447 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2018-07-24 10:47:55,447 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-07-24 10:47:55,448 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-07-24 10:47:55,448 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2018-07-24 10:47:55,449 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:55,449 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-07-24 10:47:55,449 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:47:55,449 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-07-24 10:47:55,450 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:47:55,450 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:55,450 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:55,450 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:55,451 INFO L82 PathProgramCache]: Analyzing trace with hash -378716438, now seen corresponding path program 1 times [2018-07-24 10:47:55,451 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:55,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:55,452 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:55,452 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:55,453 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:55,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:55,678 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,678 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:55,679 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:55,709 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:55,709 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:55,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:55,759 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:55,784 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,791 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:55,872 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,896 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:55,896 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:55,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:55,913 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:55,926 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:55,931 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:55,937 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,937 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:55,957 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:55,959 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:55,959 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:47:55,959 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:55,960 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:47:55,960 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:47:55,960 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:47:55,962 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 4 states. [2018-07-24 10:47:56,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:56,058 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-07-24 10:47:56,059 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:47:56,060 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-07-24 10:47:56,060 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:56,061 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:47:56,061 INFO L226 Difference]: Without dead ends: 19 [2018-07-24 10:47:56,064 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:47:56,064 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-24 10:47:56,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-07-24 10:47:56,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:47:56,069 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-24 10:47:56,069 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2018-07-24 10:47:56,070 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:56,070 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-24 10:47:56,070 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:47:56,070 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-24 10:47:56,071 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:47:56,071 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:56,072 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:56,072 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:56,072 INFO L82 PathProgramCache]: Analyzing trace with hash -23923793, now seen corresponding path program 2 times [2018-07-24 10:47:56,072 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:56,075 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:56,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:56,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:56,076 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:56,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:56,177 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,177 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:56,177 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:56,191 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:47:56,191 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:56,218 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:47:56,219 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:56,221 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:56,233 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,233 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:56,489 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,516 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:56,516 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:56,533 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:47:56,534 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:56,554 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:47:56,555 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:56,558 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:56,564 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,564 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:56,617 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,618 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:56,618 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:47:56,618 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:56,619 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:47:56,619 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:47:56,620 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:47:56,620 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 5 states. [2018-07-24 10:47:56,651 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:56,652 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-24 10:47:56,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:47:56,653 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-07-24 10:47:56,653 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:56,654 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:47:56,654 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:47:56,654 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:47:56,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:47:56,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2018-07-24 10:47:56,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-07-24 10:47:56,658 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-07-24 10:47:56,659 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2018-07-24 10:47:56,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:56,659 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-07-24 10:47:56,659 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:47:56,659 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-07-24 10:47:56,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:47:56,660 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:56,660 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:56,660 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:56,661 INFO L82 PathProgramCache]: Analyzing trace with hash -310752054, now seen corresponding path program 3 times [2018-07-24 10:47:56,661 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:56,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:56,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:56,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:56,663 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:56,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:56,852 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,853 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:56,853 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:56,868 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:47:56,869 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:56,892 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:47:56,893 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:56,895 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:56,901 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:56,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:57,109 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,130 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:57,130 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:57,145 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:47:57,146 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:47:57,180 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:47:57,181 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:57,184 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:57,190 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,190 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:57,210 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,213 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:57,213 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:47:57,213 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:57,214 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:47:57,214 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:47:57,215 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:47:57,215 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 6 states. [2018-07-24 10:47:57,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:57,265 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-07-24 10:47:57,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:47:57,267 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-07-24 10:47:57,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:57,268 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:47:57,268 INFO L226 Difference]: Without dead ends: 25 [2018-07-24 10:47:57,269 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:47:57,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-07-24 10:47:57,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-07-24 10:47:57,273 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:47:57,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-24 10:47:57,274 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2018-07-24 10:47:57,274 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:57,274 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-24 10:47:57,274 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:47:57,274 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-24 10:47:57,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:47:57,275 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:57,276 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:57,276 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:57,276 INFO L82 PathProgramCache]: Analyzing trace with hash 1773443535, now seen corresponding path program 4 times [2018-07-24 10:47:57,276 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:57,277 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:57,277 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:57,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:57,278 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:57,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:57,396 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,396 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:57,396 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:57,407 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:57,407 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:57,418 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:57,418 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:57,420 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:57,426 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,426 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:57,836 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,856 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:57,856 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:57,872 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:47:57,873 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:47:57,891 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:47:57,891 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:57,895 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:57,902 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:57,920 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:57,923 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:57,923 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:47:57,923 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:57,924 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:47:57,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:47:57,925 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:47:57,925 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 7 states. [2018-07-24 10:47:57,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:57,969 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-24 10:47:57,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:47:57,970 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-07-24 10:47:57,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:57,972 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:47:57,972 INFO L226 Difference]: Without dead ends: 28 [2018-07-24 10:47:57,973 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:47:57,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-24 10:47:57,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2018-07-24 10:47:57,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:47:57,977 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-07-24 10:47:57,978 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 23 [2018-07-24 10:47:57,978 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:57,978 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-07-24 10:47:57,978 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:47:57,978 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-07-24 10:47:57,979 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:47:57,979 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:57,979 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:57,980 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:57,980 INFO L82 PathProgramCache]: Analyzing trace with hash -297962838, now seen corresponding path program 5 times [2018-07-24 10:47:57,980 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:57,981 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:57,981 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:57,981 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:57,982 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:57,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:58,066 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,067 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:58,067 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) [2018-07-24 10:47:58,082 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:58,083 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:58,113 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:47:58,113 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:58,116 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:58,122 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,123 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:58,297 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,318 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:58,318 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:58,336 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:47:58,337 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:47:58,380 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:47:58,380 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:58,384 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:58,392 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,393 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:58,415 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,417 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:58,417 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:47:58,417 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:58,418 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:47:58,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:47:58,419 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:47:58,419 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 8 states. [2018-07-24 10:47:58,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:58,507 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-07-24 10:47:58,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:47:58,511 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 26 [2018-07-24 10:47:58,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:58,512 INFO L225 Difference]: With dead ends: 36 [2018-07-24 10:47:58,512 INFO L226 Difference]: Without dead ends: 31 [2018-07-24 10:47:58,513 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 98 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:47:58,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-07-24 10:47:58,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-07-24 10:47:58,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:47:58,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-24 10:47:58,518 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 26 [2018-07-24 10:47:58,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:58,518 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-24 10:47:58,518 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:47:58,518 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-24 10:47:58,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:47:58,519 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:58,519 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:58,520 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:58,520 INFO L82 PathProgramCache]: Analyzing trace with hash 524888047, now seen corresponding path program 6 times [2018-07-24 10:47:58,520 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:58,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:58,521 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:58,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:58,521 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:58,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:58,657 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,658 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:58,658 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:58,667 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:58,668 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:58,738 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:47:58,738 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:58,740 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:58,748 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:58,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:59,097 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,118 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:59,118 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:59,134 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:47:59,134 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:47:59,188 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:47:59,188 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:47:59,192 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:59,199 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:59,219 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,221 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:59,221 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:47:59,221 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:59,222 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:47:59,222 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:47:59,222 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:47:59,223 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 9 states. [2018-07-24 10:47:59,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:59,272 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-24 10:47:59,275 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:47:59,276 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-07-24 10:47:59,276 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:59,276 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:47:59,276 INFO L226 Difference]: Without dead ends: 34 [2018-07-24 10:47:59,277 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:47:59,277 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-24 10:47:59,281 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-07-24 10:47:59,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-07-24 10:47:59,282 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-07-24 10:47:59,283 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 29 [2018-07-24 10:47:59,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:59,283 INFO L471 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-07-24 10:47:59,283 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:47:59,283 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-07-24 10:47:59,284 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 10:47:59,284 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:59,284 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:59,285 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:59,285 INFO L82 PathProgramCache]: Analyzing trace with hash -1597722486, now seen corresponding path program 7 times [2018-07-24 10:47:59,285 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:59,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:59,286 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:47:59,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:59,287 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:59,298 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:59,398 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,399 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:59,399 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:47:59,411 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:59,411 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:59,437 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:59,440 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:59,448 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,448 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:59,616 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,637 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:59,637 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:47:59,654 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:59,654 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:47:59,676 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:59,680 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:47:59,688 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,688 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:47:59,725 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,733 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:47:59,733 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:47:59,733 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:47:59,734 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:47:59,734 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:47:59,735 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:47:59,735 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 10 states. [2018-07-24 10:47:59,818 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:47:59,819 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-07-24 10:47:59,819 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:47:59,820 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 32 [2018-07-24 10:47:59,820 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:47:59,821 INFO L225 Difference]: With dead ends: 42 [2018-07-24 10:47:59,821 INFO L226 Difference]: Without dead ends: 37 [2018-07-24 10:47:59,822 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:47:59,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-24 10:47:59,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2018-07-24 10:47:59,825 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:47:59,826 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-24 10:47:59,826 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 32 [2018-07-24 10:47:59,827 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:47:59,827 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-24 10:47:59,827 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:47:59,827 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-24 10:47:59,828 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:47:59,828 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:47:59,828 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:47:59,829 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:47:59,829 INFO L82 PathProgramCache]: Analyzing trace with hash -1484612081, now seen corresponding path program 8 times [2018-07-24 10:47:59,829 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:47:59,830 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:59,830 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:47:59,830 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:47:59,830 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:47:59,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:47:59,997 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:47:59,998 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:47:59,998 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:00,006 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:00,006 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:00,034 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:00,034 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:00,037 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:00,045 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:00,046 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:00,291 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:00,312 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:00,312 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:00,327 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:00,327 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:00,360 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:00,360 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:00,364 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:00,372 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:00,373 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:00,398 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:00,400 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:00,400 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:48:00,401 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:00,401 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:48:00,402 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:48:00,402 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:48:00,403 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 11 states. [2018-07-24 10:48:00,571 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:00,571 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-24 10:48:00,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:48:00,576 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 35 [2018-07-24 10:48:00,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:00,577 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:48:00,577 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:48:00,577 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:48:00,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:48:00,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2018-07-24 10:48:00,582 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:48:00,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-07-24 10:48:00,583 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 35 [2018-07-24 10:48:00,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:00,583 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-07-24 10:48:00,583 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:48:00,583 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-07-24 10:48:00,585 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-24 10:48:00,585 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:00,585 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:00,586 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:00,586 INFO L82 PathProgramCache]: Analyzing trace with hash 933103210, now seen corresponding path program 9 times [2018-07-24 10:48:00,586 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:00,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:00,587 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:00,587 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:00,587 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:00,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:00,732 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:00,733 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:00,733 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:00,740 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:00,741 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:00,883 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:48:00,884 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:00,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:00,895 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:00,895 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:01,220 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,240 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:01,240 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:01,256 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:01,256 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:01,358 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:48:01,358 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:01,362 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:01,374 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,375 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:01,427 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,430 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:01,431 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:48:01,431 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:01,431 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:48:01,432 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:48:01,432 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:48:01,432 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 12 states. [2018-07-24 10:48:01,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:01,497 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-07-24 10:48:01,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:48:01,498 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-07-24 10:48:01,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:01,499 INFO L225 Difference]: With dead ends: 48 [2018-07-24 10:48:01,499 INFO L226 Difference]: Without dead ends: 43 [2018-07-24 10:48:01,500 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:48:01,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-07-24 10:48:01,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-07-24 10:48:01,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:48:01,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-24 10:48:01,505 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 38 [2018-07-24 10:48:01,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:01,505 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-24 10:48:01,505 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:48:01,505 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-24 10:48:01,506 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:48:01,506 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:01,506 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:01,507 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:01,507 INFO L82 PathProgramCache]: Analyzing trace with hash 487783471, now seen corresponding path program 10 times [2018-07-24 10:48:01,507 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:01,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:01,508 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:01,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:01,508 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:01,518 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:01,753 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,754 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:01,754 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:01,762 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:01,762 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:01,787 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:01,788 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:01,789 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:01,798 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:01,798 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:02,236 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,257 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:02,257 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:02,286 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:02,286 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:02,316 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:02,316 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:02,320 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:02,328 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,328 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:02,351 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,352 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:02,353 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:48:02,353 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:02,353 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:48:02,353 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:48:02,354 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:48:02,354 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 13 states. [2018-07-24 10:48:02,551 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:02,552 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-24 10:48:02,554 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:48:02,554 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 41 [2018-07-24 10:48:02,555 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:02,555 INFO L225 Difference]: With dead ends: 51 [2018-07-24 10:48:02,556 INFO L226 Difference]: Without dead ends: 46 [2018-07-24 10:48:02,556 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:48:02,556 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-24 10:48:02,560 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2018-07-24 10:48:02,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-07-24 10:48:02,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-07-24 10:48:02,561 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 41 [2018-07-24 10:48:02,561 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:02,561 INFO L471 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-07-24 10:48:02,561 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:48:02,562 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-07-24 10:48:02,562 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:48:02,563 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:02,563 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:02,563 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:02,563 INFO L82 PathProgramCache]: Analyzing trace with hash 1121416266, now seen corresponding path program 11 times [2018-07-24 10:48:02,563 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:02,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:02,564 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:02,564 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:02,564 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:02,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:02,758 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,759 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:02,759 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:02,767 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:02,767 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:02,795 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:48:02,795 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:02,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:02,806 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:02,806 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:03,126 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:03,146 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:03,146 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:03,161 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:03,161 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:03,336 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:48:03,336 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:03,339 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:03,346 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:03,347 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:03,407 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:03,409 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:03,409 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:48:03,409 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:03,410 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:48:03,410 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:48:03,410 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:48:03,411 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 14 states. [2018-07-24 10:48:03,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:03,491 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-07-24 10:48:03,492 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:48:03,492 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 44 [2018-07-24 10:48:03,492 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:03,493 INFO L225 Difference]: With dead ends: 54 [2018-07-24 10:48:03,493 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:48:03,494 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:48:03,495 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:48:03,498 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2018-07-24 10:48:03,498 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:48:03,499 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-07-24 10:48:03,499 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 44 [2018-07-24 10:48:03,499 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:03,499 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-07-24 10:48:03,500 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:48:03,500 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-07-24 10:48:03,500 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-24 10:48:03,500 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:03,501 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:03,501 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:03,501 INFO L82 PathProgramCache]: Analyzing trace with hash 1294746191, now seen corresponding path program 12 times [2018-07-24 10:48:03,501 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:03,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:03,502 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:03,502 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:03,502 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:03,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:03,663 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:03,664 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:03,664 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:03,672 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:03,673 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:03,704 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:48:03,704 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:03,706 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:03,713 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:03,713 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:04,226 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,246 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:04,246 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:04,261 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:04,261 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:04,444 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:48:04,444 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:04,448 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:04,456 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,457 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:04,517 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,518 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:04,519 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:48:04,519 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:04,519 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:48:04,519 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:48:04,520 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:48:04,520 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 15 states. [2018-07-24 10:48:04,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:04,747 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-07-24 10:48:04,747 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:48:04,747 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-07-24 10:48:04,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:04,748 INFO L225 Difference]: With dead ends: 57 [2018-07-24 10:48:04,748 INFO L226 Difference]: Without dead ends: 52 [2018-07-24 10:48:04,748 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:48:04,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-07-24 10:48:04,752 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-07-24 10:48:04,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-07-24 10:48:04,753 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-07-24 10:48:04,753 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 47 [2018-07-24 10:48:04,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:04,754 INFO L471 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-07-24 10:48:04,754 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:48:04,754 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-07-24 10:48:04,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-24 10:48:04,755 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:04,755 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:04,755 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:04,755 INFO L82 PathProgramCache]: Analyzing trace with hash -1879115222, now seen corresponding path program 13 times [2018-07-24 10:48:04,756 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:04,756 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:04,757 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:04,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:04,757 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:04,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:04,947 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,947 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:04,947 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:04,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:04,954 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:04,970 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:04,971 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:04,978 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:04,978 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:05,307 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:05,333 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:05,333 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:05,349 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:05,349 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:05,382 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:05,387 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:05,395 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:05,395 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:05,433 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:05,436 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:05,436 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:48:05,437 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:05,437 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:48:05,437 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:48:05,437 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:48:05,438 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 16 states. [2018-07-24 10:48:05,495 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:05,496 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-07-24 10:48:05,496 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:48:05,496 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 50 [2018-07-24 10:48:05,497 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:05,497 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:48:05,497 INFO L226 Difference]: Without dead ends: 55 [2018-07-24 10:48:05,499 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 186 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:48:05,499 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-07-24 10:48:05,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2018-07-24 10:48:05,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-24 10:48:05,503 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-07-24 10:48:05,504 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 50 [2018-07-24 10:48:05,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:05,504 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-07-24 10:48:05,504 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:48:05,504 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-07-24 10:48:05,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-07-24 10:48:05,505 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:05,505 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:05,505 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:05,506 INFO L82 PathProgramCache]: Analyzing trace with hash -679448465, now seen corresponding path program 14 times [2018-07-24 10:48:05,506 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:05,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:05,507 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:05,507 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:05,507 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:05,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:05,767 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:05,768 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:05,768 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:05,778 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:05,778 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:05,794 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:05,795 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:05,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:05,807 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:05,808 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:06,132 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,152 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:06,153 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:06,167 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:06,167 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:06,205 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:06,205 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:06,208 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:06,215 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,215 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:06,266 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,268 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:06,268 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:48:06,268 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:06,268 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:48:06,269 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:48:06,269 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:48:06,269 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 17 states. [2018-07-24 10:48:06,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:06,376 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-07-24 10:48:06,378 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:48:06,378 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 53 [2018-07-24 10:48:06,378 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:06,379 INFO L225 Difference]: With dead ends: 63 [2018-07-24 10:48:06,379 INFO L226 Difference]: Without dead ends: 58 [2018-07-24 10:48:06,380 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:48:06,380 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-07-24 10:48:06,384 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-07-24 10:48:06,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:48:06,385 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-07-24 10:48:06,385 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 53 [2018-07-24 10:48:06,385 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:06,386 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-07-24 10:48:06,386 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:48:06,386 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-07-24 10:48:06,386 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:48:06,387 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:06,387 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:06,387 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:06,387 INFO L82 PathProgramCache]: Analyzing trace with hash 170039306, now seen corresponding path program 15 times [2018-07-24 10:48:06,387 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:06,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:06,388 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:06,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:06,388 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:06,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:06,678 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,679 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:06,679 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:06,686 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:06,686 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:06,724 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:48:06,725 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:06,726 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:06,735 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:06,735 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:07,170 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:07,190 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:07,190 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:07,205 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:07,205 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:07,517 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:48:07,518 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:07,521 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:07,533 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:07,533 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:07,552 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:07,554 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:07,554 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:48:07,554 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:07,554 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:48:07,555 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:48:07,555 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:48:07,555 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 18 states. [2018-07-24 10:48:07,631 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:07,631 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-07-24 10:48:07,632 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:48:07,632 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-07-24 10:48:07,633 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:07,633 INFO L225 Difference]: With dead ends: 66 [2018-07-24 10:48:07,634 INFO L226 Difference]: Without dead ends: 61 [2018-07-24 10:48:07,635 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:48:07,635 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-07-24 10:48:07,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2018-07-24 10:48:07,639 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:48:07,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-07-24 10:48:07,639 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 56 [2018-07-24 10:48:07,640 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:07,640 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-07-24 10:48:07,640 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:48:07,640 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-07-24 10:48:07,641 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:48:07,641 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:07,641 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:07,641 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:07,642 INFO L82 PathProgramCache]: Analyzing trace with hash 1312917135, now seen corresponding path program 16 times [2018-07-24 10:48:07,642 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:07,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:07,643 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:07,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:07,644 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:07,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:08,721 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:08,721 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:08,721 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:08,744 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:08,745 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:08,763 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:08,764 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:08,766 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:08,773 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:08,773 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:09,476 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:09,496 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:09,496 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:09,511 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:09,511 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:09,553 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:09,553 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:09,557 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:09,563 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:09,563 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:09,572 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:09,573 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:09,574 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:48:09,574 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:09,574 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:48:09,574 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:48:09,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:48:09,575 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 19 states. [2018-07-24 10:48:09,649 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:09,649 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-07-24 10:48:09,655 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:48:09,656 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-07-24 10:48:09,656 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:09,656 INFO L225 Difference]: With dead ends: 69 [2018-07-24 10:48:09,657 INFO L226 Difference]: Without dead ends: 64 [2018-07-24 10:48:09,658 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:48:09,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-07-24 10:48:09,666 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2018-07-24 10:48:09,669 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:48:09,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-07-24 10:48:09,670 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 59 [2018-07-24 10:48:09,670 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:09,671 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-07-24 10:48:09,671 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:48:09,671 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-07-24 10:48:09,671 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-24 10:48:09,672 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:09,672 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:09,672 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:09,672 INFO L82 PathProgramCache]: Analyzing trace with hash -1714401814, now seen corresponding path program 17 times [2018-07-24 10:48:09,675 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:09,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:09,676 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:09,676 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:09,676 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:09,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:10,031 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:10,032 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:10,032 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:10,039 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:10,040 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:10,089 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:48:10,089 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:10,091 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:10,102 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:10,102 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:10,863 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:10,883 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:10,883 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:10,898 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:10,898 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:11,264 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:48:11,264 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:11,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:11,275 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:11,275 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:11,332 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:11,336 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:11,336 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:48:11,337 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:11,337 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:48:11,337 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:48:11,338 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:48:11,339 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 20 states. [2018-07-24 10:48:11,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:11,888 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-07-24 10:48:11,888 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:48:11,889 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 62 [2018-07-24 10:48:11,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:11,890 INFO L225 Difference]: With dead ends: 72 [2018-07-24 10:48:11,890 INFO L226 Difference]: Without dead ends: 67 [2018-07-24 10:48:11,891 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:48:11,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-24 10:48:11,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2018-07-24 10:48:11,894 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-24 10:48:11,895 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-07-24 10:48:11,895 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 62 [2018-07-24 10:48:11,895 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:11,895 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-07-24 10:48:11,895 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:48:11,896 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-07-24 10:48:11,896 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-07-24 10:48:11,896 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:11,896 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:11,897 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:11,897 INFO L82 PathProgramCache]: Analyzing trace with hash 1445037231, now seen corresponding path program 18 times [2018-07-24 10:48:11,897 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:11,897 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:11,898 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:11,898 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:11,898 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:11,906 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:12,617 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:12,618 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:12,618 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:12,630 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:12,630 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:12,681 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:48:12,682 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:12,684 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:12,693 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:12,693 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:13,176 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:13,196 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:13,196 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:13,212 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:13,213 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:14,087 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:48:14,088 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:14,092 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:14,101 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:14,102 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:14,117 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:14,119 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:14,119 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-07-24 10:48:14,119 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:14,119 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:48:14,120 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:48:14,120 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:48:14,121 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 21 states. [2018-07-24 10:48:14,272 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:14,272 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-07-24 10:48:14,272 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:48:14,272 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-07-24 10:48:14,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:14,273 INFO L225 Difference]: With dead ends: 75 [2018-07-24 10:48:14,273 INFO L226 Difference]: Without dead ends: 70 [2018-07-24 10:48:14,274 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:48:14,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-07-24 10:48:14,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-07-24 10:48:14,277 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:48:14,278 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-07-24 10:48:14,278 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 65 [2018-07-24 10:48:14,278 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:14,278 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-07-24 10:48:14,278 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:48:14,278 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-07-24 10:48:14,279 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-07-24 10:48:14,279 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:14,279 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:14,279 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:14,280 INFO L82 PathProgramCache]: Analyzing trace with hash 85334986, now seen corresponding path program 19 times [2018-07-24 10:48:14,280 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:14,280 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:14,280 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:14,281 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:14,281 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:14,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:14,682 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:14,682 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:14,682 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:14,689 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:14,689 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:14,711 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:14,712 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:14,723 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:14,723 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:15,190 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:15,210 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:15,210 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:15,225 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:15,225 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:15,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:15,277 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:15,288 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:15,288 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:15,305 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:15,306 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:15,306 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-07-24 10:48:15,307 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:15,307 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:48:15,307 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:48:15,308 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:48:15,308 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 22 states. [2018-07-24 10:48:15,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:15,413 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-07-24 10:48:15,414 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:48:15,414 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2018-07-24 10:48:15,414 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:15,415 INFO L225 Difference]: With dead ends: 78 [2018-07-24 10:48:15,415 INFO L226 Difference]: Without dead ends: 73 [2018-07-24 10:48:15,416 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 252 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:48:15,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-07-24 10:48:15,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2018-07-24 10:48:15,419 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-24 10:48:15,420 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-07-24 10:48:15,420 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 68 [2018-07-24 10:48:15,420 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:15,420 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-07-24 10:48:15,420 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:48:15,420 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-07-24 10:48:15,421 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:48:15,421 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:15,421 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:15,421 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:15,422 INFO L82 PathProgramCache]: Analyzing trace with hash -967677233, now seen corresponding path program 20 times [2018-07-24 10:48:15,422 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:15,422 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:15,422 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:15,423 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:15,423 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:15,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:15,760 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:15,760 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:15,760 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:15,768 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:15,768 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:15,795 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:15,795 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:15,797 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:15,826 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:15,826 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:16,460 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:16,480 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:16,480 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:16,495 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:16,495 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:16,547 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:16,547 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:16,551 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:16,561 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:16,562 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:16,583 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:16,585 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:16,585 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-07-24 10:48:16,585 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:16,585 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:48:16,586 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:48:16,586 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:48:16,587 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 23 states. [2018-07-24 10:48:16,679 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:16,679 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-07-24 10:48:16,680 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:48:16,681 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 71 [2018-07-24 10:48:16,681 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:16,681 INFO L225 Difference]: With dead ends: 81 [2018-07-24 10:48:16,681 INFO L226 Difference]: Without dead ends: 76 [2018-07-24 10:48:16,682 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:48:16,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-07-24 10:48:16,685 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2018-07-24 10:48:16,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-24 10:48:16,686 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-07-24 10:48:16,686 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 71 [2018-07-24 10:48:16,686 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:16,686 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-07-24 10:48:16,686 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:48:16,686 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-07-24 10:48:16,687 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:48:16,687 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:16,687 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:16,687 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:16,688 INFO L82 PathProgramCache]: Analyzing trace with hash -813563478, now seen corresponding path program 21 times [2018-07-24 10:48:16,688 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:16,688 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:16,689 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:16,689 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:16,689 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:16,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:16,951 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:16,952 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:16,952 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:16,961 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:16,961 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:17,023 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:48:17,023 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:17,025 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:17,035 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:17,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:17,584 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:17,604 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:17,604 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:17,619 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:17,620 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:18,456 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:48:18,456 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:18,460 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:18,470 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:18,471 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:18,483 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:18,485 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:18,485 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-07-24 10:48:18,485 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:18,485 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:48:18,486 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:48:18,486 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:48:18,487 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 24 states. [2018-07-24 10:48:18,574 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:18,575 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-07-24 10:48:18,575 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:48:18,575 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-07-24 10:48:18,576 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:18,576 INFO L225 Difference]: With dead ends: 84 [2018-07-24 10:48:18,576 INFO L226 Difference]: Without dead ends: 79 [2018-07-24 10:48:18,578 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 274 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:48:18,578 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-24 10:48:18,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2018-07-24 10:48:18,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-24 10:48:18,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-07-24 10:48:18,580 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 74 [2018-07-24 10:48:18,580 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:18,581 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-07-24 10:48:18,581 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:48:18,581 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-07-24 10:48:18,581 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 10:48:18,582 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:18,582 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:18,582 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:18,582 INFO L82 PathProgramCache]: Analyzing trace with hash -930727697, now seen corresponding path program 22 times [2018-07-24 10:48:18,582 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:18,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:18,583 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:18,583 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:18,583 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:18,591 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:18,957 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:18,958 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:18,958 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:18,967 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:18,967 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:18,991 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:18,992 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:18,994 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:19,006 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:19,006 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:19,985 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,013 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:20,014 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:20,033 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:20,033 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:20,088 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:20,088 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:20,092 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:20,102 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,102 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:20,154 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,157 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:20,158 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-07-24 10:48:20,158 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:20,158 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:48:20,159 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:48:20,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:48:20,160 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 25 states. [2018-07-24 10:48:20,373 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:20,374 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-07-24 10:48:20,380 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:48:20,381 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 77 [2018-07-24 10:48:20,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:20,381 INFO L225 Difference]: With dead ends: 87 [2018-07-24 10:48:20,382 INFO L226 Difference]: Without dead ends: 82 [2018-07-24 10:48:20,383 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:48:20,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-07-24 10:48:20,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2018-07-24 10:48:20,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-07-24 10:48:20,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-07-24 10:48:20,386 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 77 [2018-07-24 10:48:20,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:20,386 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-07-24 10:48:20,388 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:48:20,388 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-07-24 10:48:20,389 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-07-24 10:48:20,389 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:20,389 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:20,389 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:20,389 INFO L82 PathProgramCache]: Analyzing trace with hash 438435722, now seen corresponding path program 23 times [2018-07-24 10:48:20,389 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:20,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:20,390 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:20,390 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:20,390 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:20,402 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:20,728 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,728 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:20,728 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:20,735 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:20,736 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:20,831 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:48:20,831 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:20,833 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:20,842 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:20,842 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:21,505 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:21,525 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:21,526 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:21,541 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:21,541 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:22,370 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:48:22,371 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:22,375 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:22,385 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:22,386 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:22,453 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:22,455 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:22,455 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-07-24 10:48:22,455 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:22,456 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:48:22,456 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:48:22,457 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:48:22,457 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 26 states. [2018-07-24 10:48:22,608 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:22,608 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-07-24 10:48:22,608 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:48:22,609 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-07-24 10:48:22,609 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:22,610 INFO L225 Difference]: With dead ends: 90 [2018-07-24 10:48:22,610 INFO L226 Difference]: Without dead ends: 85 [2018-07-24 10:48:22,611 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:48:22,612 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-07-24 10:48:22,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2018-07-24 10:48:22,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-24 10:48:22,615 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-07-24 10:48:22,615 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 80 [2018-07-24 10:48:22,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:22,616 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-07-24 10:48:22,616 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:48:22,616 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-07-24 10:48:22,616 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-24 10:48:22,616 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:22,617 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:22,617 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:22,617 INFO L82 PathProgramCache]: Analyzing trace with hash -118558961, now seen corresponding path program 24 times [2018-07-24 10:48:22,617 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:22,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:22,618 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:22,618 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:22,618 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:22,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:23,434 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:23,434 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:23,434 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:23,444 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:23,444 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:23,528 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:48:23,528 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:23,530 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:23,543 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:23,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:24,277 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:24,297 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:24,297 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:24,312 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:24,312 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:27,686 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:48:27,686 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:27,691 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:27,704 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:27,704 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:27,728 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:27,729 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:27,730 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-07-24 10:48:27,730 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:27,730 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:48:27,730 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:48:27,732 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:48:27,732 INFO L87 Difference]: Start difference. First operand 84 states and 84 transitions. Second operand 27 states. [2018-07-24 10:48:27,811 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:27,811 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-07-24 10:48:27,811 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:48:27,811 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 83 [2018-07-24 10:48:27,812 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:27,812 INFO L225 Difference]: With dead ends: 93 [2018-07-24 10:48:27,813 INFO L226 Difference]: Without dead ends: 88 [2018-07-24 10:48:27,814 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 307 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:48:27,814 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-07-24 10:48:27,816 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2018-07-24 10:48:27,817 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-24 10:48:27,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-07-24 10:48:27,818 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 87 transitions. Word has length 83 [2018-07-24 10:48:27,818 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:27,818 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 87 transitions. [2018-07-24 10:48:27,818 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:48:27,818 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-07-24 10:48:27,819 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-07-24 10:48:27,819 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:27,819 INFO L353 BasicCegarLoop]: trace histogram [26, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:27,819 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:27,819 INFO L82 PathProgramCache]: Analyzing trace with hash -2088495766, now seen corresponding path program 25 times [2018-07-24 10:48:27,820 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:27,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:27,820 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:27,820 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:27,820 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:27,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:28,270 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:28,270 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:28,270 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:28,278 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:28,278 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:28,306 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:28,308 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:28,322 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:28,322 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:29,350 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:29,370 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:29,370 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:29,386 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:29,387 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:29,446 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:29,451 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:29,463 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:29,464 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:29,487 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:29,489 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:29,489 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 54 [2018-07-24 10:48:29,489 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:29,489 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:48:29,490 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:48:29,490 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:48:29,491 INFO L87 Difference]: Start difference. First operand 87 states and 87 transitions. Second operand 28 states. [2018-07-24 10:48:29,596 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:29,596 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-07-24 10:48:29,596 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:48:29,596 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 86 [2018-07-24 10:48:29,597 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:29,597 INFO L225 Difference]: With dead ends: 96 [2018-07-24 10:48:29,597 INFO L226 Difference]: Without dead ends: 91 [2018-07-24 10:48:29,598 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 318 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:48:29,599 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-07-24 10:48:29,601 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-07-24 10:48:29,601 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-07-24 10:48:29,602 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 90 transitions. [2018-07-24 10:48:29,602 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 90 transitions. Word has length 86 [2018-07-24 10:48:29,602 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:29,602 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 90 transitions. [2018-07-24 10:48:29,603 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:48:29,603 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 90 transitions. [2018-07-24 10:48:29,603 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:48:29,603 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:29,603 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:29,604 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:29,604 INFO L82 PathProgramCache]: Analyzing trace with hash -2042720977, now seen corresponding path program 26 times [2018-07-24 10:48:29,604 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:29,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:29,605 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:29,605 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:29,605 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:29,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:30,540 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:30,540 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:30,540 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:30,563 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:30,563 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:30,600 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:30,600 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:30,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:30,615 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:30,615 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:31,512 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:31,531 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:31,531 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:31,546 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:31,546 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:31,609 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:31,609 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:31,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:31,629 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:31,629 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:31,672 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:31,673 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:31,673 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-07-24 10:48:31,673 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:31,674 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:48:31,674 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:48:31,675 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:48:31,675 INFO L87 Difference]: Start difference. First operand 90 states and 90 transitions. Second operand 29 states. [2018-07-24 10:48:31,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:31,802 INFO L93 Difference]: Finished difference Result 99 states and 99 transitions. [2018-07-24 10:48:31,802 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:48:31,803 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-07-24 10:48:31,803 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:31,803 INFO L225 Difference]: With dead ends: 99 [2018-07-24 10:48:31,803 INFO L226 Difference]: Without dead ends: 94 [2018-07-24 10:48:31,805 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 329 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:48:31,805 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-07-24 10:48:31,808 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2018-07-24 10:48:31,808 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-07-24 10:48:31,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-07-24 10:48:31,809 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 93 transitions. Word has length 89 [2018-07-24 10:48:31,809 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:31,809 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 93 transitions. [2018-07-24 10:48:31,809 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:48:31,809 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-07-24 10:48:31,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-07-24 10:48:31,810 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:31,810 INFO L353 BasicCegarLoop]: trace histogram [28, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:31,810 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:31,810 INFO L82 PathProgramCache]: Analyzing trace with hash 129385290, now seen corresponding path program 27 times [2018-07-24 10:48:31,810 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:31,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:31,811 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:31,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:31,811 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:31,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:32,495 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:32,495 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:32,495 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:32,503 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:32,504 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:32,610 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-07-24 10:48:32,610 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:32,613 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:32,626 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:32,626 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:33,479 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:33,499 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:33,499 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:33,514 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:33,514 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:48:35,580 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-07-24 10:48:35,580 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:35,586 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:35,600 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:35,600 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:35,635 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:35,636 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:35,636 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-07-24 10:48:35,636 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:35,637 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:48:35,637 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:48:35,639 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:48:35,639 INFO L87 Difference]: Start difference. First operand 93 states and 93 transitions. Second operand 30 states. [2018-07-24 10:48:35,747 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:35,747 INFO L93 Difference]: Finished difference Result 102 states and 102 transitions. [2018-07-24 10:48:35,748 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-07-24 10:48:35,748 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 92 [2018-07-24 10:48:35,749 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:35,750 INFO L225 Difference]: With dead ends: 102 [2018-07-24 10:48:35,750 INFO L226 Difference]: Without dead ends: 97 [2018-07-24 10:48:35,751 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 340 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:48:35,751 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-07-24 10:48:35,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 96. [2018-07-24 10:48:35,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-07-24 10:48:35,754 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 96 transitions. [2018-07-24 10:48:35,754 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 96 transitions. Word has length 92 [2018-07-24 10:48:35,754 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:35,755 INFO L471 AbstractCegarLoop]: Abstraction has 96 states and 96 transitions. [2018-07-24 10:48:35,755 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:48:35,755 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 96 transitions. [2018-07-24 10:48:35,755 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-07-24 10:48:35,755 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:35,756 INFO L353 BasicCegarLoop]: trace histogram [29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:35,756 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:35,756 INFO L82 PathProgramCache]: Analyzing trace with hash 1369903951, now seen corresponding path program 28 times [2018-07-24 10:48:35,756 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:35,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:35,757 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:35,757 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:35,757 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:35,765 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:36,312 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:36,312 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:36,313 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:36,320 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:36,320 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:36,352 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:36,352 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:36,355 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:36,370 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:36,370 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:38,437 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:38,457 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:38,457 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:38,474 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:48:38,474 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:48:38,553 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:48:38,553 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:38,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:38,577 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:38,577 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:38,637 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:38,639 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:38,639 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 60 [2018-07-24 10:48:38,639 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:38,640 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:48:38,640 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:48:38,641 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:48:38,641 INFO L87 Difference]: Start difference. First operand 96 states and 96 transitions. Second operand 31 states. [2018-07-24 10:48:38,868 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:38,868 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2018-07-24 10:48:38,869 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:48:38,869 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 95 [2018-07-24 10:48:38,869 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:38,870 INFO L225 Difference]: With dead ends: 105 [2018-07-24 10:48:38,870 INFO L226 Difference]: Without dead ends: 100 [2018-07-24 10:48:38,871 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 351 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:48:38,872 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-07-24 10:48:38,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2018-07-24 10:48:38,875 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-24 10:48:38,876 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-07-24 10:48:38,876 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 99 transitions. Word has length 95 [2018-07-24 10:48:38,876 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:38,876 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 99 transitions. [2018-07-24 10:48:38,876 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:48:38,877 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-07-24 10:48:38,877 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-07-24 10:48:38,877 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:38,877 INFO L353 BasicCegarLoop]: trace histogram [30, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:38,878 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:38,878 INFO L82 PathProgramCache]: Analyzing trace with hash -532248278, now seen corresponding path program 29 times [2018-07-24 10:48:38,878 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:38,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:38,879 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:38,879 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:38,879 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:38,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:39,307 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:39,307 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:39,307 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:39,316 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:39,316 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:39,498 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-07-24 10:48:39,498 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:39,501 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:39,512 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:39,512 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:40,674 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:40,695 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:40,695 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:40,711 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:48:40,712 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:42,422 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-07-24 10:48:42,422 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:42,428 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:42,442 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:42,443 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:42,482 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:42,485 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:42,485 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-07-24 10:48:42,485 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:42,486 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:48:42,486 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:48:42,487 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:48:42,487 INFO L87 Difference]: Start difference. First operand 99 states and 99 transitions. Second operand 32 states. [2018-07-24 10:48:42,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:42,761 INFO L93 Difference]: Finished difference Result 108 states and 108 transitions. [2018-07-24 10:48:42,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:48:42,761 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 98 [2018-07-24 10:48:42,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:42,763 INFO L225 Difference]: With dead ends: 108 [2018-07-24 10:48:42,763 INFO L226 Difference]: Without dead ends: 103 [2018-07-24 10:48:42,764 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 422 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:48:42,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-07-24 10:48:42,766 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2018-07-24 10:48:42,767 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:48:42,767 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 102 transitions. [2018-07-24 10:48:42,767 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 102 transitions. Word has length 98 [2018-07-24 10:48:42,768 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:42,768 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 102 transitions. [2018-07-24 10:48:42,768 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:48:42,768 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 102 transitions. [2018-07-24 10:48:42,768 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-07-24 10:48:42,768 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:42,769 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:42,769 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:42,769 INFO L82 PathProgramCache]: Analyzing trace with hash 249201007, now seen corresponding path program 30 times [2018-07-24 10:48:42,769 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:42,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:42,770 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:42,770 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:42,770 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:42,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:43,337 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:43,338 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:43,338 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:43,345 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:43,346 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:43,461 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-07-24 10:48:43,461 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:43,464 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:43,477 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:43,478 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:44,713 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:44,733 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:44,733 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:44,748 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:48:44,748 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:48:54,604 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-07-24 10:48:54,604 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:54,610 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:54,626 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:54,626 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:54,664 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:54,667 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:54,668 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-07-24 10:48:54,668 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:54,668 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:48:54,669 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:48:54,669 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:48:54,669 INFO L87 Difference]: Start difference. First operand 102 states and 102 transitions. Second operand 33 states. [2018-07-24 10:48:54,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:54,861 INFO L93 Difference]: Finished difference Result 111 states and 111 transitions. [2018-07-24 10:48:54,861 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:48:54,861 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 101 [2018-07-24 10:48:54,862 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:54,863 INFO L225 Difference]: With dead ends: 111 [2018-07-24 10:48:54,863 INFO L226 Difference]: Without dead ends: 106 [2018-07-24 10:48:54,864 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 435 GetRequests, 373 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:48:54,864 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-07-24 10:48:54,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 105. [2018-07-24 10:48:54,868 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-07-24 10:48:54,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-07-24 10:48:54,868 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 101 [2018-07-24 10:48:54,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:54,869 INFO L471 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2018-07-24 10:48:54,869 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:48:54,869 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-07-24 10:48:54,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-07-24 10:48:54,870 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:54,870 INFO L353 BasicCegarLoop]: trace histogram [32, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:54,870 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:54,870 INFO L82 PathProgramCache]: Analyzing trace with hash 1682106122, now seen corresponding path program 31 times [2018-07-24 10:48:54,870 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:54,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:54,871 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:54,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:54,871 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:54,879 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:55,715 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:55,715 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:55,715 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:55,725 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:55,725 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:55,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:55,761 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:55,773 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:55,773 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:56,864 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:56,884 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:56,884 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:56,899 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:56,899 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:48:56,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:56,974 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:56,990 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:56,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:57,051 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:57,053 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:57,054 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 66 [2018-07-24 10:48:57,054 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:57,054 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:48:57,055 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:48:57,056 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:48:57,056 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand 34 states. [2018-07-24 10:48:57,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:57,252 INFO L93 Difference]: Finished difference Result 114 states and 114 transitions. [2018-07-24 10:48:57,253 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:48:57,253 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 104 [2018-07-24 10:48:57,253 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:57,254 INFO L225 Difference]: With dead ends: 114 [2018-07-24 10:48:57,254 INFO L226 Difference]: Without dead ends: 109 [2018-07-24 10:48:57,256 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:48:57,256 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-07-24 10:48:57,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 108. [2018-07-24 10:48:57,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-07-24 10:48:57,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 108 transitions. [2018-07-24 10:48:57,259 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 108 transitions. Word has length 104 [2018-07-24 10:48:57,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:57,260 INFO L471 AbstractCegarLoop]: Abstraction has 108 states and 108 transitions. [2018-07-24 10:48:57,260 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:48:57,260 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 108 transitions. [2018-07-24 10:48:57,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-07-24 10:48:57,261 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:57,261 INFO L353 BasicCegarLoop]: trace histogram [33, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:57,261 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:57,261 INFO L82 PathProgramCache]: Analyzing trace with hash 1678432143, now seen corresponding path program 32 times [2018-07-24 10:48:57,261 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:57,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:57,262 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:48:57,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:57,262 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:57,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:57,782 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:57,782 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:57,782 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:57,790 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:57,790 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:57,825 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:57,826 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:57,828 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:57,844 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:57,844 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:59,021 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:59,041 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:59,041 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:48:59,056 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:48:59,056 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:48:59,133 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:48:59,133 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:48:59,138 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:48:59,154 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:59,154 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:48:59,221 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:59,222 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:48:59,223 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 68 [2018-07-24 10:48:59,223 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:48:59,223 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:48:59,224 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:48:59,224 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:48:59,224 INFO L87 Difference]: Start difference. First operand 108 states and 108 transitions. Second operand 35 states. [2018-07-24 10:48:59,360 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:48:59,361 INFO L93 Difference]: Finished difference Result 117 states and 117 transitions. [2018-07-24 10:48:59,362 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:48:59,362 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 107 [2018-07-24 10:48:59,363 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:48:59,363 INFO L225 Difference]: With dead ends: 117 [2018-07-24 10:48:59,363 INFO L226 Difference]: Without dead ends: 112 [2018-07-24 10:48:59,364 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 461 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:48:59,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-07-24 10:48:59,366 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-07-24 10:48:59,366 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-07-24 10:48:59,367 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-07-24 10:48:59,367 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 111 transitions. Word has length 107 [2018-07-24 10:48:59,367 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:48:59,367 INFO L471 AbstractCegarLoop]: Abstraction has 111 states and 111 transitions. [2018-07-24 10:48:59,367 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:48:59,367 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-07-24 10:48:59,368 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-07-24 10:48:59,368 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:48:59,368 INFO L353 BasicCegarLoop]: trace histogram [34, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:48:59,368 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:48:59,369 INFO L82 PathProgramCache]: Analyzing trace with hash -398893846, now seen corresponding path program 33 times [2018-07-24 10:48:59,369 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:48:59,369 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:59,370 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:48:59,370 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:48:59,370 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:48:59,378 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:48:59,950 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:48:59,951 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:48:59,951 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:48:59,957 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:48:59,958 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:00,111 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-07-24 10:49:00,111 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:00,114 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:00,132 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:00,132 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:01,590 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:01,611 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:01,611 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:01,626 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:01,626 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:06,013 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-07-24 10:49:06,014 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:06,019 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:06,035 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,035 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:06,058 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,059 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:06,060 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 36] total 70 [2018-07-24 10:49:06,060 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:06,060 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:49:06,060 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:49:06,061 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:49:06,061 INFO L87 Difference]: Start difference. First operand 111 states and 111 transitions. Second operand 36 states. [2018-07-24 10:49:06,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:06,264 INFO L93 Difference]: Finished difference Result 120 states and 120 transitions. [2018-07-24 10:49:06,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-24 10:49:06,264 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 110 [2018-07-24 10:49:06,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:06,265 INFO L225 Difference]: With dead ends: 120 [2018-07-24 10:49:06,265 INFO L226 Difference]: Without dead ends: 115 [2018-07-24 10:49:06,266 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 474 GetRequests, 406 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:49:06,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-07-24 10:49:06,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 114. [2018-07-24 10:49:06,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-07-24 10:49:06,270 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 114 transitions. [2018-07-24 10:49:06,270 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 114 transitions. Word has length 110 [2018-07-24 10:49:06,270 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:06,270 INFO L471 AbstractCegarLoop]: Abstraction has 114 states and 114 transitions. [2018-07-24 10:49:06,271 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:49:06,271 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 114 transitions. [2018-07-24 10:49:06,271 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-07-24 10:49:06,271 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:06,271 INFO L353 BasicCegarLoop]: trace histogram [35, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:06,272 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:06,272 INFO L82 PathProgramCache]: Analyzing trace with hash 166335919, now seen corresponding path program 34 times [2018-07-24 10:49:06,272 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:06,272 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:06,273 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:06,273 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:06,273 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:06,281 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:07,007 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,007 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:07,008 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:07,014 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:07,014 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:07,053 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:07,053 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:07,056 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:07,076 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,076 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:08,739 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,759 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:08,759 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:08,773 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:08,773 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:08,857 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:08,857 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:08,861 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:08,879 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,879 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:08,928 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,929 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:08,930 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 72 [2018-07-24 10:49:08,930 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:08,930 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:49:08,930 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:49:08,931 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:49:08,931 INFO L87 Difference]: Start difference. First operand 114 states and 114 transitions. Second operand 37 states. [2018-07-24 10:49:09,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:09,107 INFO L93 Difference]: Finished difference Result 123 states and 123 transitions. [2018-07-24 10:49:09,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:49:09,108 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 113 [2018-07-24 10:49:09,108 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:09,109 INFO L225 Difference]: With dead ends: 123 [2018-07-24 10:49:09,109 INFO L226 Difference]: Without dead ends: 118 [2018-07-24 10:49:09,110 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:49:09,110 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-07-24 10:49:09,112 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 117. [2018-07-24 10:49:09,113 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-07-24 10:49:09,113 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-07-24 10:49:09,113 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 117 transitions. Word has length 113 [2018-07-24 10:49:09,114 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:09,114 INFO L471 AbstractCegarLoop]: Abstraction has 117 states and 117 transitions. [2018-07-24 10:49:09,114 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:49:09,114 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-07-24 10:49:09,115 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-07-24 10:49:09,115 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:09,115 INFO L353 BasicCegarLoop]: trace histogram [36, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:09,115 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:09,115 INFO L82 PathProgramCache]: Analyzing trace with hash -1640502582, now seen corresponding path program 35 times [2018-07-24 10:49:09,115 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:09,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:09,116 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:09,116 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:09,116 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:09,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:09,714 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,714 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:09,714 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:09,721 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:09,721 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:10,048 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-07-24 10:49:10,048 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:10,053 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:10,068 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:10,068 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:11,666 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:11,687 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:11,687 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:11,702 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:11,702 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:14,816 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-07-24 10:49:14,816 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:14,821 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:14,841 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:14,842 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:14,881 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:14,882 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:14,883 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 74 [2018-07-24 10:49:14,883 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:14,883 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:49:14,883 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:49:14,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:49:14,884 INFO L87 Difference]: Start difference. First operand 117 states and 117 transitions. Second operand 38 states. [2018-07-24 10:49:15,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:15,008 INFO L93 Difference]: Finished difference Result 126 states and 126 transitions. [2018-07-24 10:49:15,010 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:49:15,010 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 116 [2018-07-24 10:49:15,010 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:15,011 INFO L225 Difference]: With dead ends: 126 [2018-07-24 10:49:15,011 INFO L226 Difference]: Without dead ends: 121 [2018-07-24 10:49:15,012 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 428 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:49:15,012 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-07-24 10:49:15,014 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 120. [2018-07-24 10:49:15,014 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-07-24 10:49:15,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 120 transitions. [2018-07-24 10:49:15,014 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 120 transitions. Word has length 116 [2018-07-24 10:49:15,015 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:15,015 INFO L471 AbstractCegarLoop]: Abstraction has 120 states and 120 transitions. [2018-07-24 10:49:15,015 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:49:15,015 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 120 transitions. [2018-07-24 10:49:15,015 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:49:15,016 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:15,016 INFO L353 BasicCegarLoop]: trace histogram [37, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:15,016 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:15,016 INFO L82 PathProgramCache]: Analyzing trace with hash -341165105, now seen corresponding path program 36 times [2018-07-24 10:49:15,016 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:15,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:15,017 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:15,017 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:15,017 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:15,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:16,277 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,278 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:16,278 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:16,284 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:16,285 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:16,482 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-07-24 10:49:16,482 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:16,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:16,506 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:17,982 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:18,002 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:18,002 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:18,017 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:18,017 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:45,009 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-07-24 10:49:45,009 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:45,017 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:45,038 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:45,039 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:45,110 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:45,113 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:45,114 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 76 [2018-07-24 10:49:45,114 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:45,114 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:49:45,115 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:49:45,115 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:49:45,115 INFO L87 Difference]: Start difference. First operand 120 states and 120 transitions. Second operand 39 states. [2018-07-24 10:49:45,317 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:45,317 INFO L93 Difference]: Finished difference Result 129 states and 129 transitions. [2018-07-24 10:49:45,318 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:49:45,318 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 119 [2018-07-24 10:49:45,318 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:45,319 INFO L225 Difference]: With dead ends: 129 [2018-07-24 10:49:45,319 INFO L226 Difference]: Without dead ends: 124 [2018-07-24 10:49:45,320 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 439 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:49:45,320 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-07-24 10:49:45,321 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 123. [2018-07-24 10:49:45,322 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-07-24 10:49:45,322 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-07-24 10:49:45,322 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 123 transitions. Word has length 119 [2018-07-24 10:49:45,323 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:45,323 INFO L471 AbstractCegarLoop]: Abstraction has 123 states and 123 transitions. [2018-07-24 10:49:45,323 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:49:45,323 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-07-24 10:49:45,323 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-07-24 10:49:45,323 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:45,323 INFO L353 BasicCegarLoop]: trace histogram [38, 37, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:45,324 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:45,324 INFO L82 PathProgramCache]: Analyzing trace with hash 1976340650, now seen corresponding path program 37 times [2018-07-24 10:49:45,324 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:45,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:45,324 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:45,324 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:45,325 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:45,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:47,358 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:47,358 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:47,358 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:47,366 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:47,366 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:47,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:47,417 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:47,439 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:47,440 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:49,183 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:49,203 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:49,203 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:49,230 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:49,230 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:49,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:49,318 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:49,331 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:49,331 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:49,349 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:49,350 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:49,350 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 78 [2018-07-24 10:49:49,350 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:49,350 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:49:49,350 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:49:49,351 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:49:49,351 INFO L87 Difference]: Start difference. First operand 123 states and 123 transitions. Second operand 40 states. [2018-07-24 10:49:49,559 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:49,559 INFO L93 Difference]: Finished difference Result 132 states and 132 transitions. [2018-07-24 10:49:49,559 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 10:49:49,560 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 122 [2018-07-24 10:49:49,560 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:49,561 INFO L225 Difference]: With dead ends: 132 [2018-07-24 10:49:49,561 INFO L226 Difference]: Without dead ends: 127 [2018-07-24 10:49:49,561 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 526 GetRequests, 450 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:49:49,561 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-07-24 10:49:49,564 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 126. [2018-07-24 10:49:49,564 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-07-24 10:49:49,564 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 126 transitions. [2018-07-24 10:49:49,564 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 126 transitions. Word has length 122 [2018-07-24 10:49:49,565 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:49,565 INFO L471 AbstractCegarLoop]: Abstraction has 126 states and 126 transitions. [2018-07-24 10:49:49,565 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:49:49,565 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 126 transitions. [2018-07-24 10:49:49,566 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-07-24 10:49:49,566 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:49,566 INFO L353 BasicCegarLoop]: trace histogram [39, 38, 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:49,566 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:49,566 INFO L82 PathProgramCache]: Analyzing trace with hash 1191004655, now seen corresponding path program 38 times [2018-07-24 10:49:49,566 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:49,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:49,567 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:49,567 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:49,567 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:49,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:50,194 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:50,195 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:50,195 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:50,203 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:50,203 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:50,241 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:50,241 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:50,244 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:50,265 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:50,265 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:52,121 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:52,141 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:52,141 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:52,155 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:52,155 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:52,243 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:52,243 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:52,247 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:52,267 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:52,267 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:52,344 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:52,346 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:52,346 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 80 [2018-07-24 10:49:52,346 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:52,347 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:49:52,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:49:52,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:49:52,348 INFO L87 Difference]: Start difference. First operand 126 states and 126 transitions. Second operand 41 states. [2018-07-24 10:49:52,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:52,865 INFO L93 Difference]: Finished difference Result 135 states and 135 transitions. [2018-07-24 10:49:52,866 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:49:52,866 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 125 [2018-07-24 10:49:52,866 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:52,867 INFO L225 Difference]: With dead ends: 135 [2018-07-24 10:49:52,868 INFO L226 Difference]: Without dead ends: 130 [2018-07-24 10:49:52,868 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 539 GetRequests, 461 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:49:52,869 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-07-24 10:49:52,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 129. [2018-07-24 10:49:52,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-07-24 10:49:52,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-07-24 10:49:52,873 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 129 transitions. Word has length 125 [2018-07-24 10:49:52,874 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:52,874 INFO L471 AbstractCegarLoop]: Abstraction has 129 states and 129 transitions. [2018-07-24 10:49:52,874 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:49:52,874 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-07-24 10:49:52,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-07-24 10:49:52,875 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:52,875 INFO L353 BasicCegarLoop]: trace histogram [40, 39, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:52,875 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:52,875 INFO L82 PathProgramCache]: Analyzing trace with hash -66761078, now seen corresponding path program 39 times [2018-07-24 10:49:52,875 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:52,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:52,876 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:52,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:52,876 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:52,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:53,964 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:53,964 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:53,964 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:53,971 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:53,971 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:54,217 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-07-24 10:49:54,217 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:54,221 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:54,253 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:54,253 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:55,935 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:55,955 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:55,955 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:55,971 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:55,971 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:50:04,538 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-07-24 10:50:04,538 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:04,554 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:04,576 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:04,577 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:04,617 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:04,618 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:04,619 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42, 42, 42] total 82 [2018-07-24 10:50:04,619 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:04,619 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:50:04,620 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:50:04,620 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:50:04,620 INFO L87 Difference]: Start difference. First operand 129 states and 129 transitions. Second operand 42 states. [2018-07-24 10:50:04,834 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:04,834 INFO L93 Difference]: Finished difference Result 138 states and 138 transitions. [2018-07-24 10:50:04,834 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-07-24 10:50:04,835 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 128 [2018-07-24 10:50:04,835 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:04,836 INFO L225 Difference]: With dead ends: 138 [2018-07-24 10:50:04,836 INFO L226 Difference]: Without dead ends: 133 [2018-07-24 10:50:04,837 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 552 GetRequests, 472 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:50:04,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-07-24 10:50:04,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 132. [2018-07-24 10:50:04,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-07-24 10:50:04,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 132 transitions. [2018-07-24 10:50:04,841 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 132 transitions. Word has length 128 [2018-07-24 10:50:04,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:04,842 INFO L471 AbstractCegarLoop]: Abstraction has 132 states and 132 transitions. [2018-07-24 10:50:04,842 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:50:04,842 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 132 transitions. [2018-07-24 10:50:04,842 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-07-24 10:50:04,843 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:04,843 INFO L353 BasicCegarLoop]: trace histogram [41, 40, 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:04,843 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:04,843 INFO L82 PathProgramCache]: Analyzing trace with hash -871022577, now seen corresponding path program 40 times [2018-07-24 10:50:04,843 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:04,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:04,844 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:04,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:04,844 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:04,853 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:06,178 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:06,178 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:06,178 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:06,185 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:50:06,185 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:50:06,229 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:50:06,229 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:06,231 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:06,254 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:06,254 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:08,352 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:08,371 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:08,372 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:08,386 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:50:08,386 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:50:08,485 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:50:08,485 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:08,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:08,506 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:08,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:08,571 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:08,572 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:08,572 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 84 [2018-07-24 10:50:08,572 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:08,573 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:50:08,573 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:50:08,573 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:50:08,574 INFO L87 Difference]: Start difference. First operand 132 states and 132 transitions. Second operand 43 states. [2018-07-24 10:50:08,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:08,822 INFO L93 Difference]: Finished difference Result 141 states and 141 transitions. [2018-07-24 10:50:08,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:50:08,823 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 131 [2018-07-24 10:50:08,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:08,824 INFO L225 Difference]: With dead ends: 141 [2018-07-24 10:50:08,825 INFO L226 Difference]: Without dead ends: 136 [2018-07-24 10:50:08,825 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 565 GetRequests, 483 SyntacticMatches, 0 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:50:08,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-07-24 10:50:08,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 135. [2018-07-24 10:50:08,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-07-24 10:50:08,829 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-07-24 10:50:08,830 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 135 transitions. Word has length 131 [2018-07-24 10:50:08,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:08,830 INFO L471 AbstractCegarLoop]: Abstraction has 135 states and 135 transitions. [2018-07-24 10:50:08,830 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:50:08,830 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-07-24 10:50:08,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-07-24 10:50:08,831 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:08,831 INFO L353 BasicCegarLoop]: trace histogram [42, 41, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:08,831 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:08,832 INFO L82 PathProgramCache]: Analyzing trace with hash 997205098, now seen corresponding path program 41 times [2018-07-24 10:50:08,832 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:08,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:08,832 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:08,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:08,833 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:08,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:10,030 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:10,031 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:10,031 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:10,038 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:50:10,038 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:50:10,573 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-07-24 10:50:10,573 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:10,576 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:10,599 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:10,599 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:12,748 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:12,769 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:12,769 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:12,784 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:50:12,784 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:50:18,211 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-07-24 10:50:18,211 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:18,218 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:18,236 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:18,236 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:18,263 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:18,265 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:18,266 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 86 [2018-07-24 10:50:18,266 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:18,266 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:50:18,266 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:50:18,267 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:50:18,267 INFO L87 Difference]: Start difference. First operand 135 states and 135 transitions. Second operand 44 states. [2018-07-24 10:50:18,908 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:18,908 INFO L93 Difference]: Finished difference Result 144 states and 144 transitions. [2018-07-24 10:50:18,910 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-24 10:50:18,910 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 134 [2018-07-24 10:50:18,911 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:18,911 INFO L225 Difference]: With dead ends: 144 [2018-07-24 10:50:18,912 INFO L226 Difference]: Without dead ends: 139 [2018-07-24 10:50:18,912 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 578 GetRequests, 494 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:50:18,915 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-07-24 10:50:18,918 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 138. [2018-07-24 10:50:18,918 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-07-24 10:50:18,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 138 transitions. [2018-07-24 10:50:18,920 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 138 transitions. Word has length 134 [2018-07-24 10:50:18,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:18,920 INFO L471 AbstractCegarLoop]: Abstraction has 138 states and 138 transitions. [2018-07-24 10:50:18,921 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:50:18,921 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 138 transitions. [2018-07-24 10:50:18,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-07-24 10:50:18,922 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:18,922 INFO L353 BasicCegarLoop]: trace histogram [43, 42, 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:18,922 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:18,922 INFO L82 PathProgramCache]: Analyzing trace with hash -1113317841, now seen corresponding path program 42 times [2018-07-24 10:50:18,922 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:18,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:18,923 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:18,923 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:18,924 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:18,934 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:20,395 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:20,395 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:20,395 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:20,404 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:50:20,404 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:50:20,627 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-07-24 10:50:20,627 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:20,631 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:20,649 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:20,649 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:22,620 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:22,640 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:22,640 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:22,656 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:50:22,656 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:51:27,139 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-07-24 10:51:27,139 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:27,155 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:27,172 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:27,172 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:27,195 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:27,198 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:51:27,198 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 88 [2018-07-24 10:51:27,198 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:51:27,199 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:51:27,199 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:51:27,199 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:51:27,200 INFO L87 Difference]: Start difference. First operand 138 states and 138 transitions. Second operand 45 states. [2018-07-24 10:51:27,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:51:27,365 INFO L93 Difference]: Finished difference Result 147 states and 147 transitions. [2018-07-24 10:51:27,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-24 10:51:27,365 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 137 [2018-07-24 10:51:27,366 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:51:27,366 INFO L225 Difference]: With dead ends: 147 [2018-07-24 10:51:27,367 INFO L226 Difference]: Without dead ends: 142 [2018-07-24 10:51:27,367 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 505 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:51:27,368 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-07-24 10:51:27,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 141. [2018-07-24 10:51:27,372 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:51:27,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-07-24 10:51:27,373 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 141 transitions. Word has length 137 [2018-07-24 10:51:27,373 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:51:27,373 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 141 transitions. [2018-07-24 10:51:27,373 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:51:27,373 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-07-24 10:51:27,374 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-07-24 10:51:27,374 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:51:27,374 INFO L353 BasicCegarLoop]: trace histogram [44, 43, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:51:27,374 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:51:27,375 INFO L82 PathProgramCache]: Analyzing trace with hash -1675947446, now seen corresponding path program 43 times [2018-07-24 10:51:27,375 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:51:27,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:27,375 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:51:27,375 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:27,376 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:51:27,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:29,048 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:29,049 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:29,049 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:51:29,056 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:51:29,056 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:51:29,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:29,103 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:29,122 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:29,122 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:31,127 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:31,146 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:31,146 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:51:31,176 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:51:31,176 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:51:31,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:31,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:31,292 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:31,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:31,317 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:31,319 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:51:31,319 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 90 [2018-07-24 10:51:31,319 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:51:31,319 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-24 10:51:31,320 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-24 10:51:31,320 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:51:31,320 INFO L87 Difference]: Start difference. First operand 141 states and 141 transitions. Second operand 46 states. [2018-07-24 10:51:31,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:51:31,497 INFO L93 Difference]: Finished difference Result 150 states and 150 transitions. [2018-07-24 10:51:31,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-07-24 10:51:31,498 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 140 [2018-07-24 10:51:31,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:51:31,499 INFO L225 Difference]: With dead ends: 150 [2018-07-24 10:51:31,499 INFO L226 Difference]: Without dead ends: 145 [2018-07-24 10:51:31,499 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 604 GetRequests, 516 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:51:31,500 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-07-24 10:51:31,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 144. [2018-07-24 10:51:31,503 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-07-24 10:51:31,504 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 144 transitions. [2018-07-24 10:51:31,504 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 144 transitions. Word has length 140 [2018-07-24 10:51:31,504 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:51:31,504 INFO L471 AbstractCegarLoop]: Abstraction has 144 states and 144 transitions. [2018-07-24 10:51:31,504 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-24 10:51:31,504 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 144 transitions. [2018-07-24 10:51:31,505 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-07-24 10:51:31,505 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:51:31,505 INFO L353 BasicCegarLoop]: trace histogram [45, 44, 44, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:51:31,505 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:51:31,506 INFO L82 PathProgramCache]: Analyzing trace with hash 282846287, now seen corresponding path program 44 times [2018-07-24 10:51:31,506 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:51:31,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:31,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:51:31,506 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:31,507 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:51:31,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:32,344 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:32,344 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:32,344 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:51:32,354 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:51:32,354 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:51:32,401 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:51:32,401 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:32,403 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:32,422 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:32,422 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:34,594 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:34,614 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:34,614 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:51:34,629 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:51:34,629 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:51:34,726 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:51:34,727 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:34,731 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:34,751 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:34,752 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:34,778 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:34,779 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:51:34,780 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 92 [2018-07-24 10:51:34,780 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:51:34,780 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-24 10:51:34,780 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-24 10:51:34,781 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:51:34,781 INFO L87 Difference]: Start difference. First operand 144 states and 144 transitions. Second operand 47 states. [2018-07-24 10:51:34,940 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:51:34,940 INFO L93 Difference]: Finished difference Result 153 states and 153 transitions. [2018-07-24 10:51:34,941 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:51:34,941 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 143 [2018-07-24 10:51:34,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:51:34,942 INFO L225 Difference]: With dead ends: 153 [2018-07-24 10:51:34,942 INFO L226 Difference]: Without dead ends: 148 [2018-07-24 10:51:34,942 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 617 GetRequests, 527 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:51:34,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-07-24 10:51:34,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 147. [2018-07-24 10:51:34,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-07-24 10:51:34,946 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-07-24 10:51:34,946 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 147 transitions. Word has length 143 [2018-07-24 10:51:34,947 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:51:34,947 INFO L471 AbstractCegarLoop]: Abstraction has 147 states and 147 transitions. [2018-07-24 10:51:34,947 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-24 10:51:34,947 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-07-24 10:51:34,948 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-07-24 10:51:34,948 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:51:34,948 INFO L353 BasicCegarLoop]: trace histogram [46, 45, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:51:34,948 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:51:34,948 INFO L82 PathProgramCache]: Analyzing trace with hash -1013704662, now seen corresponding path program 45 times [2018-07-24 10:51:34,948 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:51:34,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:34,949 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:51:34,949 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:34,949 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:51:34,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:35,778 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:35,778 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:35,779 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:51:35,786 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:51:35,787 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:51:36,151 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-07-24 10:51:36,151 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:36,154 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:36,175 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:36,175 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:38,383 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:38,404 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:38,404 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:51:38,420 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:51:38,420 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:51:53,307 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-07-24 10:51:53,308 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:53,315 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:53,332 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:53,332 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:53,361 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:53,363 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:51:53,363 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48, 48, 48] total 94 [2018-07-24 10:51:53,363 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:51:53,363 INFO L450 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-07-24 10:51:53,364 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-07-24 10:51:53,364 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:51:53,364 INFO L87 Difference]: Start difference. First operand 147 states and 147 transitions. Second operand 48 states. [2018-07-24 10:51:53,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:51:53,622 INFO L93 Difference]: Finished difference Result 156 states and 156 transitions. [2018-07-24 10:51:53,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-07-24 10:51:53,622 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-07-24 10:51:53,622 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:51:53,623 INFO L225 Difference]: With dead ends: 156 [2018-07-24 10:51:53,623 INFO L226 Difference]: Without dead ends: 151 [2018-07-24 10:51:53,624 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 630 GetRequests, 538 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:51:53,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-07-24 10:51:53,627 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 150. [2018-07-24 10:51:53,627 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-07-24 10:51:53,628 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 150 transitions. [2018-07-24 10:51:53,628 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 150 transitions. Word has length 146 [2018-07-24 10:51:53,628 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:51:53,628 INFO L471 AbstractCegarLoop]: Abstraction has 150 states and 150 transitions. [2018-07-24 10:51:53,628 INFO L472 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-07-24 10:51:53,628 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 150 transitions. [2018-07-24 10:51:53,629 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-07-24 10:51:53,629 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:51:53,629 INFO L353 BasicCegarLoop]: trace histogram [47, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:51:53,630 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:51:53,630 INFO L82 PathProgramCache]: Analyzing trace with hash -1922133393, now seen corresponding path program 46 times [2018-07-24 10:51:53,630 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:51:53,630 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:53,631 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:51:53,631 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:53,631 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:51:53,641 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:54,587 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:54,587 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:54,587 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:51:54,596 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:51:54,596 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:51:54,645 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:51:54,645 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:54,647 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:54,668 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:54,668 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:56,979 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:56,999 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:56,999 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:51:57,013 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:51:57,014 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:51:57,125 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:51:57,125 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:57,131 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:57,152 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:57,152 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:51:57,173 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:57,174 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:51:57,174 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 96 [2018-07-24 10:51:57,175 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:51:57,175 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:51:57,175 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:51:57,175 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:51:57,176 INFO L87 Difference]: Start difference. First operand 150 states and 150 transitions. Second operand 49 states. [2018-07-24 10:51:57,333 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:51:57,333 INFO L93 Difference]: Finished difference Result 159 states and 159 transitions. [2018-07-24 10:51:57,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:51:57,334 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 149 [2018-07-24 10:51:57,334 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:51:57,335 INFO L225 Difference]: With dead ends: 159 [2018-07-24 10:51:57,335 INFO L226 Difference]: Without dead ends: 154 [2018-07-24 10:51:57,336 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 643 GetRequests, 549 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:51:57,336 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-07-24 10:51:57,339 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 153. [2018-07-24 10:51:57,339 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-07-24 10:51:57,340 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-07-24 10:51:57,340 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 153 transitions. Word has length 149 [2018-07-24 10:51:57,340 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:51:57,340 INFO L471 AbstractCegarLoop]: Abstraction has 153 states and 153 transitions. [2018-07-24 10:51:57,341 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-24 10:51:57,341 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-07-24 10:51:57,341 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-07-24 10:51:57,341 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:51:57,342 INFO L353 BasicCegarLoop]: trace histogram [48, 47, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:51:57,342 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:51:57,342 INFO L82 PathProgramCache]: Analyzing trace with hash 1961440778, now seen corresponding path program 47 times [2018-07-24 10:51:57,342 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:51:57,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:57,343 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:51:57,343 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:51:57,343 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:51:57,353 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:51:58,631 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:58,632 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:51:58,632 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:51:58,639 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:51:58,639 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:51:59,500 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-07-24 10:51:59,500 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:51:59,504 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:51:59,525 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:51:59,525 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:01,976 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:01,997 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:01,998 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:02,013 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:02,013 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:11,131 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-07-24 10:52:11,131 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:11,139 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:11,157 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:11,157 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:11,181 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:11,183 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:11,183 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 98 [2018-07-24 10:52:11,183 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:11,184 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-24 10:52:11,184 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-24 10:52:11,185 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:52:11,185 INFO L87 Difference]: Start difference. First operand 153 states and 153 transitions. Second operand 50 states. [2018-07-24 10:52:11,341 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:11,341 INFO L93 Difference]: Finished difference Result 162 states and 162 transitions. [2018-07-24 10:52:11,342 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-07-24 10:52:11,342 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 152 [2018-07-24 10:52:11,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:11,343 INFO L225 Difference]: With dead ends: 162 [2018-07-24 10:52:11,343 INFO L226 Difference]: Without dead ends: 157 [2018-07-24 10:52:11,344 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 560 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:52:11,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-07-24 10:52:11,347 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-07-24 10:52:11,347 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-07-24 10:52:11,348 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 156 transitions. [2018-07-24 10:52:11,348 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 156 transitions. Word has length 152 [2018-07-24 10:52:11,348 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:11,348 INFO L471 AbstractCegarLoop]: Abstraction has 156 states and 156 transitions. [2018-07-24 10:52:11,348 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-24 10:52:11,348 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 156 transitions. [2018-07-24 10:52:11,349 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-07-24 10:52:11,349 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:11,349 INFO L353 BasicCegarLoop]: trace histogram [49, 48, 48, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:11,349 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_false_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:11,349 INFO L82 PathProgramCache]: Analyzing trace with hash -309450609, now seen corresponding path program 48 times [2018-07-24 10:52:11,349 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:11,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:11,350 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:11,350 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:11,350 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:11,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:12,345 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:12,346 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:12,346 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:12,352 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:12,353 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:52:12,690 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-07-24 10:52:12,691 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:12,695 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:12,717 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:12,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-07-24 10:52:14,100 INFO L177 TraceCheckSpWp]: Timeout while computing interpolants [2018-07-24 10:52:14,301 WARN L512 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 96 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:14,301 WARN L540 AbstractCegarLoop]: Verification canceled [2018-07-24 10:52:14,307 WARN L202 ceAbstractionStarter]: Timeout [2018-07-24 10:52:14,307 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 10:52:14 BoogieIcfgContainer [2018-07-24 10:52:14,307 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 10:52:14,308 INFO L168 Benchmark]: Toolchain (without parser) took 259939.47 ms. Allocated memory was 1.5 GB in the beginning and 2.5 GB in the end (delta: 962.1 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -684.6 MB). Peak memory consumption was 277.5 MB. Max. memory is 7.1 GB. [2018-07-24 10:52:14,309 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:52:14,309 INFO L168 Benchmark]: CACSL2BoogieTranslator took 295.36 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:52:14,310 INFO L168 Benchmark]: Boogie Procedure Inliner took 26.36 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:52:14,310 INFO L168 Benchmark]: Boogie Preprocessor took 22.02 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:52:14,310 INFO L168 Benchmark]: RCFGBuilder took 301.69 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 751.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -794.3 MB). Peak memory consumption was 27.1 MB. Max. memory is 7.1 GB. [2018-07-24 10:52:14,311 INFO L168 Benchmark]: TraceAbstraction took 259289.10 ms. Allocated memory was 2.3 GB in the beginning and 2.5 GB in the end (delta: 210.8 MB). Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 99.1 MB). Peak memory consumption was 309.9 MB. Max. memory is 7.1 GB. [2018-07-24 10:52:14,313 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 295.36 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 26.36 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 22.02 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 301.69 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 751.3 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -794.3 MB). Peak memory consumption was 27.1 MB. Max. memory is 7.1 GB. * TraceAbstraction took 259289.10 ms. Allocated memory was 2.3 GB in the beginning and 2.5 GB in the end (delta: 210.8 MB). Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 99.1 MB). Peak memory consumption was 309.9 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 4]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 4). Cancelled while BasicCegarLoop was analyzing trace of length 156 with TraceHistMax 49, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 81 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 19 locations, 1 error locations. TIMEOUT Result, 259.2s OverallTime, 50 OverallIterations, 49 TraceHistogramMax, 8.1s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 547 SDtfs, 1176 SDslu, 8168 SDs, 0 SdLazy, 3322 SolverSat, 69 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 6.3s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 16784 GetRequests, 14433 SyntacticMatches, 0 SemanticMatches, 2351 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 74.9s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=156occurred in iteration=49, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 49 MinimizatonAttempts, 48 StatesRemovedByMinimization, 48 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.6s SsaConstructionTime, 163.7s SatisfiabilityAnalysisTime, 80.3s InterpolantComputationTime, 11724 NumberOfCodeBlocks, 11724 NumberOfCodeBlocksAsserted, 1311 NumberOfCheckSat, 19289 ConstructedInterpolants, 0 QuantifiedInterpolants, 5599801 SizeOfPredicates, 94 NumberOfNonLiveVariables, 17954 ConjunctsInSsa, 2444 ConjunctsInUnsatCore, 237 InterpolantComputations, 2 PerfectInterpolantSequences, 0/270720 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/array_false-unreach-call2_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_10-52-14-329.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/array_false-unreach-call2_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_10-52-14-329.csv Completed graceful shutdown