java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/array_true-unreach-call2_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:49:02,876 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:49:02,879 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:49:02,897 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:49:02,897 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:49:02,899 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:49:02,901 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:49:02,904 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:49:02,907 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:49:02,908 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:49:02,911 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:49:02,911 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:49:02,912 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:49:02,913 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:49:02,914 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:49:02,917 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:49:02,918 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:49:02,920 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:49:02,922 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:49:02,923 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:49:02,924 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:49:02,926 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:49:02,928 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:49:02,928 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:49:02,928 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:49:02,929 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:49:02,930 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:49:02,931 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:49:02,932 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:49:02,933 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:49:02,933 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:49:02,936 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:49:02,936 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:49:02,938 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:49:02,939 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:49:02,939 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:49:02,940 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:49:02,958 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:49:02,958 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:49:02,959 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:49:02,960 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:49:02,960 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:49:02,960 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:49:02,960 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:49:02,960 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:49:02,960 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:49:02,961 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:49:02,961 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:49:02,962 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:49:02,962 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:49:02,962 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:49:02,962 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:49:02,962 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:49:02,962 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:49:02,963 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:49:02,963 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:49:02,963 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:49:02,963 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:49:02,963 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:49:02,964 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:49:02,964 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:49:02,964 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:49:02,964 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:49:02,964 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:49:02,965 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:49:02,965 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:49:02,965 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:49:02,965 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:49:02,965 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:49:02,965 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:49:03,026 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:49:03,043 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:49:03,047 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:49:03,049 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:49:03,050 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:49:03,050 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/array_true-unreach-call2_true-termination.i [2018-07-24 10:49:03,396 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cdff6f5bc/b00e044323384aebb5974eb020518284/FLAGc6b927b0b [2018-07-24 10:49:03,550 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:49:03,551 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/array_true-unreach-call2_true-termination.i [2018-07-24 10:49:03,557 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cdff6f5bc/b00e044323384aebb5974eb020518284/FLAGc6b927b0b [2018-07-24 10:49:03,573 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/cdff6f5bc/b00e044323384aebb5974eb020518284 [2018-07-24 10:49:03,584 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:49:03,586 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:49:03,587 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:49:03,587 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:49:03,594 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:49:03,595 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,598 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@4ec4a681 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03, skipping insertion in model container [2018-07-24 10:49:03,598 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,762 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:49:03,802 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:49:03,818 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:49:03,823 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:49:03,836 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03 WrapperNode [2018-07-24 10:49:03,836 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:49:03,837 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:49:03,837 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:49:03,837 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:49:03,847 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,854 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,860 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:49:03,860 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:49:03,861 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:49:03,861 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:49:03,870 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,871 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,872 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,872 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,873 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,879 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,880 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... [2018-07-24 10:49:03,882 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:49:03,882 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:49:03,883 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:49:03,883 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:49:03,884 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:49:03,945 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:49:03,946 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assert [2018-07-24 10:49:03,946 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:49:03,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:49:03,946 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:49:03,946 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:49:03,946 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:49:03,947 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:49:04,186 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:49:04,187 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:49:04 BoogieIcfgContainer [2018-07-24 10:49:04,187 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:49:04,188 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:49:04,188 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:49:04,191 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:49:04,191 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:49:03" (1/3) ... [2018-07-24 10:49:04,192 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@61cfa74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:49:04, skipping insertion in model container [2018-07-24 10:49:04,192 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:49:03" (2/3) ... [2018-07-24 10:49:04,193 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@61cfa74 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:49:04, skipping insertion in model container [2018-07-24 10:49:04,193 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:49:04" (3/3) ... [2018-07-24 10:49:04,195 INFO L112 eAbstractionObserver]: Analyzing ICFG array_true-unreach-call2_true-termination.i [2018-07-24 10:49:04,205 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:49:04,213 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:49:04,274 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:49:04,275 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:49:04,276 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:49:04,276 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:49:04,276 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:49:04,276 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:49:04,276 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:49:04,276 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:49:04,276 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:49:04,292 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states. [2018-07-24 10:49:04,297 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:49:04,298 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:04,299 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:04,299 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:04,305 INFO L82 PathProgramCache]: Analyzing trace with hash 47309880, now seen corresponding path program 1 times [2018-07-24 10:49:04,307 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:04,362 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:04,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:04,363 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:04,363 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:04,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:04,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:04,419 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:49:04,420 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:49:04,420 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:49:04,425 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:49:04,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:49:04,441 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:49:04,444 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 2 states. [2018-07-24 10:49:04,464 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:04,464 INFO L93 Difference]: Finished difference Result 30 states and 33 transitions. [2018-07-24 10:49:04,464 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:49:04,466 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:49:04,467 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:04,475 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:49:04,476 INFO L226 Difference]: Without dead ends: 13 [2018-07-24 10:49:04,480 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:49:04,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-24 10:49:04,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-24 10:49:04,514 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-24 10:49:04,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-07-24 10:49:04,517 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 10 [2018-07-24 10:49:04,517 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:04,517 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-07-24 10:49:04,517 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:49:04,518 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-07-24 10:49:04,518 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:49:04,518 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:04,518 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:04,519 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:04,519 INFO L82 PathProgramCache]: Analyzing trace with hash 1197084163, now seen corresponding path program 1 times [2018-07-24 10:49:04,519 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:04,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:04,521 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:04,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:04,521 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:04,534 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:04,594 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:04,595 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:49:04,595 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:49:04,596 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:49:04,597 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:49:04,598 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:49:04,598 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:49:04,598 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 3 states. [2018-07-24 10:49:04,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:04,678 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-24 10:49:04,679 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:49:04,679 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:49:04,680 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:04,680 INFO L225 Difference]: With dead ends: 21 [2018-07-24 10:49:04,681 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:49:04,682 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:49:04,683 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:49:04,686 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2018-07-24 10:49:04,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-07-24 10:49:04,687 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-07-24 10:49:04,687 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2018-07-24 10:49:04,688 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:04,688 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-07-24 10:49:04,688 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:49:04,688 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-07-24 10:49:04,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:49:04,689 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:04,689 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:04,689 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:04,690 INFO L82 PathProgramCache]: Analyzing trace with hash 688816788, now seen corresponding path program 1 times [2018-07-24 10:49:04,690 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:04,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:04,691 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:04,691 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:04,692 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:04,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:04,777 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:04,777 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:04,778 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:04,794 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:04,794 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:04,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:04,819 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:04,843 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:04,844 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:05,134 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,160 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:05,160 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:05,178 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:05,178 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:05,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:05,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:05,217 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,218 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:05,258 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,260 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:05,260 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:49:05,261 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:05,261 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:49:05,261 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:49:05,262 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:49:05,262 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 4 states. [2018-07-24 10:49:05,315 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:05,316 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-07-24 10:49:05,317 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:49:05,317 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-07-24 10:49:05,317 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:05,318 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:49:05,318 INFO L226 Difference]: Without dead ends: 19 [2018-07-24 10:49:05,319 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:49:05,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-24 10:49:05,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-07-24 10:49:05,327 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:49:05,328 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-24 10:49:05,328 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2018-07-24 10:49:05,328 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:05,328 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-24 10:49:05,329 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:49:05,329 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-24 10:49:05,330 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:49:05,331 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:05,331 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:05,331 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:05,332 INFO L82 PathProgramCache]: Analyzing trace with hash -1344833437, now seen corresponding path program 2 times [2018-07-24 10:49:05,332 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:05,333 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:05,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:05,334 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:05,334 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:05,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:05,409 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,409 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:05,409 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:05,421 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:05,421 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:05,444 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:05,445 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:05,447 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:05,453 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,453 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:05,618 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,646 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:05,646 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:05,662 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:05,662 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:05,682 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:05,682 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:05,686 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:05,692 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,693 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:05,710 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:05,713 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:05,713 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:49:05,714 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:05,714 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:49:05,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:49:05,715 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:49:05,717 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 5 states. [2018-07-24 10:49:05,773 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:05,774 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-24 10:49:05,774 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:49:05,774 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-07-24 10:49:05,775 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:05,775 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:49:05,775 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:49:05,776 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:49:05,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:49:05,780 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2018-07-24 10:49:05,780 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-07-24 10:49:05,781 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-07-24 10:49:05,781 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2018-07-24 10:49:05,782 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:05,782 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-07-24 10:49:05,782 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:49:05,782 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-07-24 10:49:05,783 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:49:05,783 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:05,783 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:05,783 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:05,784 INFO L82 PathProgramCache]: Analyzing trace with hash -1010009036, now seen corresponding path program 3 times [2018-07-24 10:49:05,784 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:05,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:05,785 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:05,785 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:05,785 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:05,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:06,166 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,166 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:06,166 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:06,180 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:06,180 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:06,198 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:49:06,199 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:06,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:06,206 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,207 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:06,425 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,446 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:06,446 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:06,464 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:06,464 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:06,501 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:49:06,502 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:06,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:06,511 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,512 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:06,536 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,539 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:06,539 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:49:06,540 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:06,540 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:49:06,540 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:49:06,541 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:49:06,541 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 6 states. [2018-07-24 10:49:06,588 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:06,588 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-07-24 10:49:06,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:49:06,590 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-07-24 10:49:06,590 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:06,591 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:49:06,591 INFO L226 Difference]: Without dead ends: 25 [2018-07-24 10:49:06,592 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:49:06,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-07-24 10:49:06,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-07-24 10:49:06,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:49:06,597 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-24 10:49:06,597 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2018-07-24 10:49:06,597 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:06,598 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-24 10:49:06,598 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:49:06,598 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-24 10:49:06,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:49:06,601 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:06,602 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:06,602 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:06,602 INFO L82 PathProgramCache]: Analyzing trace with hash 829659843, now seen corresponding path program 4 times [2018-07-24 10:49:06,602 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:06,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:06,604 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:06,604 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:06,604 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:06,618 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:06,693 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,694 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:06,694 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:06,703 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:06,703 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:06,717 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:06,717 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:06,720 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:06,726 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:06,726 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:07,185 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,207 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:07,207 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:07,225 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:07,225 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:07,246 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:07,246 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:07,250 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:07,257 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,257 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:07,275 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,277 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:07,278 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:49:07,278 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:07,279 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:49:07,279 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:49:07,279 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:49:07,280 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 7 states. [2018-07-24 10:49:07,327 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:07,329 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-24 10:49:07,329 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:49:07,329 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-07-24 10:49:07,330 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:07,330 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:49:07,330 INFO L226 Difference]: Without dead ends: 28 [2018-07-24 10:49:07,331 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:49:07,331 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-24 10:49:07,334 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2018-07-24 10:49:07,335 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:49:07,336 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-07-24 10:49:07,336 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 23 [2018-07-24 10:49:07,336 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:07,336 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-07-24 10:49:07,336 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:49:07,337 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-07-24 10:49:07,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:49:07,338 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:07,338 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:07,338 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:07,338 INFO L82 PathProgramCache]: Analyzing trace with hash -1672430124, now seen corresponding path program 5 times [2018-07-24 10:49:07,338 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:07,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:07,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:07,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:07,340 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:07,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:07,433 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,434 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:07,434 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:07,448 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:07,448 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:07,489 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:49:07,489 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:07,491 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:07,505 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,505 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:07,690 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,711 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:07,711 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:07,728 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:07,728 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:07,769 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:49:07,770 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:07,773 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:07,780 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,780 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:07,798 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:07,800 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:07,800 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:49:07,801 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:07,801 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:49:07,801 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:49:07,802 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:49:07,802 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 8 states. [2018-07-24 10:49:07,865 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:07,865 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-07-24 10:49:07,867 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:49:07,868 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 26 [2018-07-24 10:49:07,868 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:07,869 INFO L225 Difference]: With dead ends: 36 [2018-07-24 10:49:07,869 INFO L226 Difference]: Without dead ends: 31 [2018-07-24 10:49:07,870 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 98 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:49:07,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-07-24 10:49:07,873 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-07-24 10:49:07,873 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:49:07,874 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-24 10:49:07,874 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 26 [2018-07-24 10:49:07,875 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:07,875 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-24 10:49:07,875 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:49:07,875 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-24 10:49:07,876 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:49:07,876 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:07,876 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:07,877 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:07,877 INFO L82 PathProgramCache]: Analyzing trace with hash 2017752355, now seen corresponding path program 6 times [2018-07-24 10:49:07,877 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:07,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:07,878 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:07,878 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:07,878 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:07,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:08,010 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,011 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:08,011 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:08,022 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:08,023 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:08,086 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:49:08,086 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:08,089 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:08,095 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,096 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:08,508 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,530 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:08,531 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:08,548 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:08,548 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:08,611 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:49:08,612 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:08,617 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:08,624 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,625 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:08,646 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,649 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:08,649 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:49:08,649 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:08,650 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:49:08,650 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:49:08,650 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:49:08,651 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 9 states. [2018-07-24 10:49:08,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:08,704 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-24 10:49:08,708 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:49:08,708 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-07-24 10:49:08,708 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:08,709 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:49:08,709 INFO L226 Difference]: Without dead ends: 34 [2018-07-24 10:49:08,710 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:49:08,710 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-24 10:49:08,713 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-07-24 10:49:08,714 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-07-24 10:49:08,714 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-07-24 10:49:08,715 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 29 [2018-07-24 10:49:08,715 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:08,715 INFO L471 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-07-24 10:49:08,715 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:49:08,715 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-07-24 10:49:08,716 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 10:49:08,716 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:08,716 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:08,717 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:08,717 INFO L82 PathProgramCache]: Analyzing trace with hash -2033891468, now seen corresponding path program 7 times [2018-07-24 10:49:08,717 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:08,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:08,718 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:08,718 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:08,718 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:08,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:08,847 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,847 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:08,848 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:08,857 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:08,857 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:08,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:08,884 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:08,892 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:08,892 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:09,082 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,103 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:09,103 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:09,121 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:09,121 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:09,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:09,148 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:09,156 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,156 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:09,169 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,170 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:09,171 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:49:09,171 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:09,171 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:49:09,171 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:49:09,172 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:49:09,172 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 10 states. [2018-07-24 10:49:09,235 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:09,235 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-07-24 10:49:09,238 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:49:09,238 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 32 [2018-07-24 10:49:09,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:09,239 INFO L225 Difference]: With dead ends: 42 [2018-07-24 10:49:09,239 INFO L226 Difference]: Without dead ends: 37 [2018-07-24 10:49:09,241 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:49:09,241 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-24 10:49:09,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2018-07-24 10:49:09,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:49:09,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-24 10:49:09,245 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 32 [2018-07-24 10:49:09,246 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:09,246 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-24 10:49:09,246 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:49:09,246 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-24 10:49:09,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:49:09,247 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:09,247 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:09,247 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:09,248 INFO L82 PathProgramCache]: Analyzing trace with hash 1205864323, now seen corresponding path program 8 times [2018-07-24 10:49:09,248 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:09,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:09,249 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:09,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:09,249 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:09,262 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:09,462 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,462 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:09,462 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:09,470 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:09,470 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:09,490 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:09,490 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:09,492 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:09,501 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,501 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:09,730 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,751 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:09,751 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:09,766 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:09,767 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:09,800 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:09,800 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:09,804 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:09,812 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,812 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:09,846 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:09,848 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:09,849 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:49:09,850 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:09,850 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:49:09,851 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:49:09,851 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:49:09,851 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 11 states. [2018-07-24 10:49:10,040 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:10,040 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-24 10:49:10,045 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:49:10,046 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 35 [2018-07-24 10:49:10,046 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:10,047 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:49:10,047 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:49:10,047 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:49:10,048 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:49:10,051 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2018-07-24 10:49:10,052 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:49:10,052 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-07-24 10:49:10,053 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 35 [2018-07-24 10:49:10,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:10,054 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-07-24 10:49:10,055 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:49:10,055 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-07-24 10:49:10,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-24 10:49:10,056 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:10,056 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:10,058 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:10,059 INFO L82 PathProgramCache]: Analyzing trace with hash 265558292, now seen corresponding path program 9 times [2018-07-24 10:49:10,059 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:10,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:10,060 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:10,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:10,060 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:10,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:10,190 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:10,190 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:10,190 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:10,198 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:10,198 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:10,238 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:49:10,238 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:10,241 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:10,249 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:10,250 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:10,468 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:10,489 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:10,489 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:10,506 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:10,506 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:10,791 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:49:10,791 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:10,795 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:10,803 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:10,804 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:10,857 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:10,860 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:10,860 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:49:10,860 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:10,861 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:49:10,861 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:49:10,861 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:49:10,862 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 12 states. [2018-07-24 10:49:10,939 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:10,939 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-07-24 10:49:10,940 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:49:10,940 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-07-24 10:49:10,941 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:10,941 INFO L225 Difference]: With dead ends: 48 [2018-07-24 10:49:10,942 INFO L226 Difference]: Without dead ends: 43 [2018-07-24 10:49:10,942 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:49:10,943 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-07-24 10:49:10,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-07-24 10:49:10,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:49:10,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-24 10:49:10,947 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 38 [2018-07-24 10:49:10,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:10,948 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-24 10:49:10,948 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:49:10,948 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-24 10:49:10,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:49:10,949 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:10,949 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:10,949 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:10,950 INFO L82 PathProgramCache]: Analyzing trace with hash -614706717, now seen corresponding path program 10 times [2018-07-24 10:49:10,950 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:10,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:10,951 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:10,951 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:10,951 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:10,960 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:11,218 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:11,219 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:11,219 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:11,233 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:11,233 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:11,277 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:11,278 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:11,280 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:11,289 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:11,289 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:11,952 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:11,974 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:11,974 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:11,990 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:49:11,990 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:49:12,022 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:49:12,023 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:12,026 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:12,036 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,036 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:12,096 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,099 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:12,100 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:49:12,100 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:12,101 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:49:12,101 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:49:12,101 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:49:12,102 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 13 states. [2018-07-24 10:49:12,364 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:12,364 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-24 10:49:12,365 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:49:12,365 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 41 [2018-07-24 10:49:12,365 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:12,366 INFO L225 Difference]: With dead ends: 51 [2018-07-24 10:49:12,366 INFO L226 Difference]: Without dead ends: 46 [2018-07-24 10:49:12,367 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:49:12,367 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-24 10:49:12,372 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2018-07-24 10:49:12,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-07-24 10:49:12,384 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-07-24 10:49:12,384 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 41 [2018-07-24 10:49:12,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:12,384 INFO L471 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-07-24 10:49:12,384 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:49:12,385 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-07-24 10:49:12,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:49:12,385 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:12,385 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:12,386 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:12,387 INFO L82 PathProgramCache]: Analyzing trace with hash 480719540, now seen corresponding path program 11 times [2018-07-24 10:49:12,387 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:12,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:12,388 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:12,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:12,388 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:12,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:12,628 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,628 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:12,629 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:12,637 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:12,637 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:12,665 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:49:12,665 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:12,667 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:12,675 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:12,676 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:13,116 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:13,137 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:13,137 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:13,152 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:49:13,152 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:13,309 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:49:13,309 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:13,312 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:13,320 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:13,320 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:13,375 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:13,377 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:13,377 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:49:13,377 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:13,377 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:49:13,378 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:49:13,378 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:49:13,381 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 14 states. [2018-07-24 10:49:13,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:13,469 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-07-24 10:49:13,470 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:49:13,470 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 44 [2018-07-24 10:49:13,470 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:13,471 INFO L225 Difference]: With dead ends: 54 [2018-07-24 10:49:13,471 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:49:13,472 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:49:13,473 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:49:13,477 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2018-07-24 10:49:13,477 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:49:13,478 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-07-24 10:49:13,478 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 44 [2018-07-24 10:49:13,478 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:13,478 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-07-24 10:49:13,479 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:49:13,479 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-07-24 10:49:13,479 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-24 10:49:13,480 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:13,480 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:13,480 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:13,480 INFO L82 PathProgramCache]: Analyzing trace with hash 1162826819, now seen corresponding path program 12 times [2018-07-24 10:49:13,480 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:13,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:13,481 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:13,481 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:13,481 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:13,490 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:13,636 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:13,636 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:13,637 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:13,645 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:13,645 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:13,690 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:49:13,691 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:13,692 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:13,700 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:13,700 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:13,993 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:14,014 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:14,014 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:14,029 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:49:14,029 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:49:14,631 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:49:14,631 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:14,635 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:14,643 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:14,644 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:14,695 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:14,697 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:14,697 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:49:14,697 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:14,697 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:49:14,698 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:49:14,698 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:49:14,699 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 15 states. [2018-07-24 10:49:14,784 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:14,784 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-07-24 10:49:14,784 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:49:14,784 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-07-24 10:49:14,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:14,785 INFO L225 Difference]: With dead ends: 57 [2018-07-24 10:49:14,785 INFO L226 Difference]: Without dead ends: 52 [2018-07-24 10:49:14,786 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:49:14,786 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-07-24 10:49:14,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-07-24 10:49:14,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-07-24 10:49:14,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-07-24 10:49:14,794 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 47 [2018-07-24 10:49:14,795 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:14,795 INFO L471 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-07-24 10:49:14,795 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:49:14,795 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-07-24 10:49:14,796 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-24 10:49:14,796 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:14,796 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:14,796 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:14,796 INFO L82 PathProgramCache]: Analyzing trace with hash -1964469164, now seen corresponding path program 13 times [2018-07-24 10:49:14,797 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:14,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:14,800 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:14,800 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:14,800 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:14,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:15,498 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:15,498 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:15,498 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:15,506 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:15,506 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:15,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:15,535 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:15,545 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:15,545 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:16,119 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,143 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:16,143 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:16,163 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:16,163 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:49:16,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:16,198 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:16,204 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,205 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:16,249 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,250 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:16,250 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:49:16,251 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:16,251 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:49:16,251 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:49:16,251 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:49:16,252 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 16 states. [2018-07-24 10:49:16,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:16,378 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-07-24 10:49:16,379 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:49:16,379 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 50 [2018-07-24 10:49:16,379 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:16,380 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:49:16,380 INFO L226 Difference]: Without dead ends: 55 [2018-07-24 10:49:16,381 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 186 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:49:16,382 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-07-24 10:49:16,385 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2018-07-24 10:49:16,385 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-24 10:49:16,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-07-24 10:49:16,386 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 50 [2018-07-24 10:49:16,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:16,387 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-07-24 10:49:16,387 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:49:16,387 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-07-24 10:49:16,388 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-07-24 10:49:16,388 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:16,388 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:16,388 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:16,388 INFO L82 PathProgramCache]: Analyzing trace with hash -808513885, now seen corresponding path program 14 times [2018-07-24 10:49:16,388 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:16,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:16,389 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:49:16,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:16,389 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:16,397 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:16,572 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,573 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:16,573 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:16,583 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:16,583 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:16,605 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:16,605 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:16,607 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:16,614 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,615 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:16,962 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:16,984 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:16,984 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:16,999 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:49:16,999 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:49:17,035 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:49:17,036 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:17,039 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:17,045 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:17,045 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:17,094 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:17,095 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:49:17,096 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:49:17,096 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:49:17,096 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:49:17,096 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:49:17,097 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:49:17,097 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 17 states. [2018-07-24 10:49:17,188 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:49:17,188 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-07-24 10:49:17,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:49:17,189 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 53 [2018-07-24 10:49:17,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:49:17,190 INFO L225 Difference]: With dead ends: 63 [2018-07-24 10:49:17,190 INFO L226 Difference]: Without dead ends: 58 [2018-07-24 10:49:17,191 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:49:17,191 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-07-24 10:49:17,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-07-24 10:49:17,194 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:49:17,195 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-07-24 10:49:17,195 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 53 [2018-07-24 10:49:17,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:49:17,196 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-07-24 10:49:17,196 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:49:17,196 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-07-24 10:49:17,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:49:17,197 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:49:17,197 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:49:17,197 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:49:17,197 INFO L82 PathProgramCache]: Analyzing trace with hash -792576524, now seen corresponding path program 15 times [2018-07-24 10:49:17,197 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:49:17,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:17,198 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:49:17,198 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:49:17,199 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:49:17,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:49:17,423 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:17,424 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:17,424 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:49:17,432 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:17,433 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:49:17,470 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:49:17,470 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:49:17,471 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:49:17,479 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:17,479 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:49:17,880 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:49:17,902 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:49:17,902 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:49:17,919 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:49:17,919 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:50:02,812 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:50:02,812 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:02,817 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:02,827 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:02,827 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:02,838 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:02,840 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:02,841 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:50:02,841 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:02,841 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:50:02,841 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:50:02,842 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:50:02,842 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 18 states. [2018-07-24 10:50:02,919 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:02,919 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-07-24 10:50:02,919 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:50:02,919 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-07-24 10:50:02,920 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:02,921 INFO L225 Difference]: With dead ends: 66 [2018-07-24 10:50:02,921 INFO L226 Difference]: Without dead ends: 61 [2018-07-24 10:50:02,922 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:50:02,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-07-24 10:50:02,926 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2018-07-24 10:50:02,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:50:02,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-07-24 10:50:02,927 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 56 [2018-07-24 10:50:02,928 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:02,928 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-07-24 10:50:02,928 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:50:02,928 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-07-24 10:50:02,929 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:50:02,929 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:02,929 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:02,929 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:02,930 INFO L82 PathProgramCache]: Analyzing trace with hash 1550942467, now seen corresponding path program 16 times [2018-07-24 10:50:02,930 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:02,930 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:02,931 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:02,931 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:02,931 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:02,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:04,358 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:04,358 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:04,359 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:04,366 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:50:04,366 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:50:04,388 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:50:04,389 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:04,390 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:04,400 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:04,400 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:04,982 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:05,002 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:05,002 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:05,017 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:50:05,017 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:50:05,057 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:50:05,057 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:05,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:05,070 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:05,071 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:05,127 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:05,129 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:05,129 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:50:05,129 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:05,129 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:50:05,130 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:50:05,130 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:50:05,131 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 19 states. [2018-07-24 10:50:05,197 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:05,197 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-07-24 10:50:05,203 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:50:05,204 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-07-24 10:50:05,204 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:05,204 INFO L225 Difference]: With dead ends: 69 [2018-07-24 10:50:05,204 INFO L226 Difference]: Without dead ends: 64 [2018-07-24 10:50:05,205 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:50:05,206 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-07-24 10:50:05,208 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2018-07-24 10:50:05,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:50:05,209 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-07-24 10:50:05,209 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 59 [2018-07-24 10:50:05,210 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:05,210 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-07-24 10:50:05,210 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:50:05,210 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-07-24 10:50:05,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-24 10:50:05,211 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:05,211 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:05,211 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:05,211 INFO L82 PathProgramCache]: Analyzing trace with hash -1663160428, now seen corresponding path program 17 times [2018-07-24 10:50:05,212 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:05,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:05,212 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:05,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:05,213 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:05,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:05,521 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:05,522 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:05,522 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:05,529 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:50:05,529 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:50:05,577 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:50:05,577 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:05,579 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:05,589 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:05,590 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:06,369 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:06,389 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:06,389 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:06,405 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:50:06,405 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:50:06,753 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:50:06,753 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:06,757 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:06,765 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:06,765 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:06,826 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:06,831 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:06,832 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:50:06,832 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:06,832 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:50:06,833 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:50:06,833 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:50:06,835 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 20 states. [2018-07-24 10:50:07,380 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:07,381 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-07-24 10:50:07,381 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:50:07,381 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 62 [2018-07-24 10:50:07,381 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:07,382 INFO L225 Difference]: With dead ends: 72 [2018-07-24 10:50:07,382 INFO L226 Difference]: Without dead ends: 67 [2018-07-24 10:50:07,383 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:50:07,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-24 10:50:07,386 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2018-07-24 10:50:07,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-24 10:50:07,386 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-07-24 10:50:07,386 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 62 [2018-07-24 10:50:07,386 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:07,386 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-07-24 10:50:07,387 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:50:07,387 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-07-24 10:50:07,387 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-07-24 10:50:07,387 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:07,387 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:07,387 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:07,388 INFO L82 PathProgramCache]: Analyzing trace with hash -1001608349, now seen corresponding path program 18 times [2018-07-24 10:50:07,388 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:07,388 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:07,389 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:07,389 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:07,389 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:07,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:08,145 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:08,145 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:08,145 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:08,153 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:50:08,153 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:50:08,209 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:50:08,209 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:08,211 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:08,222 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:08,222 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:08,873 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:08,893 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:08,893 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:08,909 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:50:08,910 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:50:46,389 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:50:46,390 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:46,395 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:46,403 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:46,403 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:46,419 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:46,421 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:46,422 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-07-24 10:50:46,422 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:46,422 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:50:46,423 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:50:46,424 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:50:46,424 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 21 states. [2018-07-24 10:50:46,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:46,524 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-07-24 10:50:46,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:50:46,524 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-07-24 10:50:46,525 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:46,525 INFO L225 Difference]: With dead ends: 75 [2018-07-24 10:50:46,525 INFO L226 Difference]: Without dead ends: 70 [2018-07-24 10:50:46,526 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:50:46,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-07-24 10:50:46,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-07-24 10:50:46,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:50:46,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-07-24 10:50:46,530 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 65 [2018-07-24 10:50:46,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:46,531 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-07-24 10:50:46,531 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:50:46,531 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-07-24 10:50:46,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-07-24 10:50:46,532 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:46,532 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:46,532 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:46,532 INFO L82 PathProgramCache]: Analyzing trace with hash 1986423092, now seen corresponding path program 19 times [2018-07-24 10:50:46,532 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:46,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:46,533 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:46,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:46,533 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:46,541 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:46,795 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:46,795 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:46,795 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:46,803 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:50:46,803 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:50:46,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:46,829 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:46,839 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:46,839 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:47,328 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:47,348 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:47,348 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:47,363 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:50:47,363 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:50:47,411 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:47,415 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:47,424 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:47,424 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:47,442 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:47,443 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:47,443 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-07-24 10:50:47,443 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:47,444 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:50:47,444 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:50:47,445 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:50:47,445 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 22 states. [2018-07-24 10:50:47,546 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:47,546 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-07-24 10:50:47,546 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:50:47,547 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2018-07-24 10:50:47,547 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:47,548 INFO L225 Difference]: With dead ends: 78 [2018-07-24 10:50:47,548 INFO L226 Difference]: Without dead ends: 73 [2018-07-24 10:50:47,549 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 252 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:50:47,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-07-24 10:50:47,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2018-07-24 10:50:47,553 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-24 10:50:47,554 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-07-24 10:50:47,554 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 68 [2018-07-24 10:50:47,554 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:47,554 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-07-24 10:50:47,554 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:50:47,554 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-07-24 10:50:47,555 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:50:47,555 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:47,555 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:47,555 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:47,555 INFO L82 PathProgramCache]: Analyzing trace with hash 938905027, now seen corresponding path program 20 times [2018-07-24 10:50:47,555 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:47,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:47,556 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:50:47,556 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:47,557 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:47,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:47,915 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:47,916 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:47,916 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:47,923 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:50:47,923 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:50:47,952 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:50:47,952 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:47,954 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:47,966 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:47,966 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:48,682 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:48,702 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:48,702 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:48,717 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:50:48,718 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:50:48,769 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:50:48,770 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:48,773 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:48,781 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:48,781 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:48,843 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:48,846 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:50:48,847 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-07-24 10:50:48,847 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:50:48,847 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:50:48,848 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:50:48,851 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:50:48,851 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 23 states. [2018-07-24 10:50:49,075 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:50:49,075 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-07-24 10:50:49,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:50:49,077 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 71 [2018-07-24 10:50:49,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:50:49,078 INFO L225 Difference]: With dead ends: 81 [2018-07-24 10:50:49,078 INFO L226 Difference]: Without dead ends: 76 [2018-07-24 10:50:49,078 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:50:49,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-07-24 10:50:49,081 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2018-07-24 10:50:49,081 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-24 10:50:49,081 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-07-24 10:50:49,082 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 71 [2018-07-24 10:50:49,082 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:50:49,082 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-07-24 10:50:49,082 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:50:49,082 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-07-24 10:50:49,083 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:50:49,083 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:50:49,083 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:50:49,083 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:50:49,083 INFO L82 PathProgramCache]: Analyzing trace with hash 1560603348, now seen corresponding path program 21 times [2018-07-24 10:50:49,083 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:50:49,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:49,084 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:50:49,084 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:50:49,084 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:50:49,092 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:50:49,468 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:49,469 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:49,469 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:50:49,478 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:50:49,478 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:50:49,540 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:50:49,540 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:50:49,542 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:50:49,552 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:49,552 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:50:50,128 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:50:50,149 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:50:50,149 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:50:50,166 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:50:50,166 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:46,521 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:52:46,521 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:46,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,534 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,534 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:46,552 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,556 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:46,556 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-07-24 10:52:46,556 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:46,556 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:52:46,557 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:52:46,557 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:52:46,558 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 24 states. [2018-07-24 10:52:46,637 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:46,637 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-07-24 10:52:46,638 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:52:46,638 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-07-24 10:52:46,638 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:46,639 INFO L225 Difference]: With dead ends: 84 [2018-07-24 10:52:46,639 INFO L226 Difference]: Without dead ends: 79 [2018-07-24 10:52:46,640 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 274 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:52:46,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-24 10:52:46,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2018-07-24 10:52:46,643 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-24 10:52:46,643 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-07-24 10:52:46,643 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 74 [2018-07-24 10:52:46,643 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:46,643 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-07-24 10:52:46,643 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:52:46,644 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-07-24 10:52:46,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 10:52:46,644 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:46,644 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:46,644 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:46,645 INFO L82 PathProgramCache]: Analyzing trace with hash -1618663389, now seen corresponding path program 22 times [2018-07-24 10:52:46,645 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:46,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,645 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:46,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,646 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:46,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:46,931 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,931 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:46,931 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:46,939 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:46,939 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:46,964 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:46,964 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:46,967 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,978 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,978 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:47,555 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,575 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:47,575 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:47,590 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:47,590 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:47,648 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:47,649 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:47,652 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:47,661 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,661 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:47,692 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,693 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:47,693 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-07-24 10:52:47,694 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:47,694 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:52:47,694 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:52:47,695 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:52:47,695 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 25 states. [2018-07-24 10:52:47,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:47,783 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-07-24 10:52:47,793 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:52:47,793 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 77 [2018-07-24 10:52:47,794 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:47,794 INFO L225 Difference]: With dead ends: 87 [2018-07-24 10:52:47,794 INFO L226 Difference]: Without dead ends: 82 [2018-07-24 10:52:47,796 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:52:47,796 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-07-24 10:52:47,798 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2018-07-24 10:52:47,798 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-07-24 10:52:47,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-07-24 10:52:47,798 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 77 [2018-07-24 10:52:47,799 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:47,799 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-07-24 10:52:47,799 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:52:47,799 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-07-24 10:52:47,801 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-07-24 10:52:47,801 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:47,802 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:47,802 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:47,802 INFO L82 PathProgramCache]: Analyzing trace with hash 1759753332, now seen corresponding path program 23 times [2018-07-24 10:52:47,802 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:47,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:47,803 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:47,803 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:47,803 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:47,814 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:48,096 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,096 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:48,096 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:48,103 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:48,103 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:48,197 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:52:48,197 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:48,200 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:48,209 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,209 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:48,867 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,887 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:48,887 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:48,902 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:48,902 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:49,712 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:52:49,712 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:49,716 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:49,727 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,727 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:49,737 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,739 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:49,739 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-07-24 10:52:49,739 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:49,739 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:52:49,740 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:52:49,740 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:52:49,741 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 26 states. [2018-07-24 10:52:49,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:49,823 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-07-24 10:52:49,824 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:52:49,824 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-07-24 10:52:49,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:49,825 INFO L225 Difference]: With dead ends: 90 [2018-07-24 10:52:49,825 INFO L226 Difference]: Without dead ends: 85 [2018-07-24 10:52:49,826 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:52:49,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-07-24 10:52:49,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2018-07-24 10:52:49,829 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-24 10:52:49,830 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-07-24 10:52:49,830 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 80 [2018-07-24 10:52:49,830 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:49,830 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-07-24 10:52:49,830 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:52:49,831 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-07-24 10:52:49,831 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-24 10:52:49,831 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:49,831 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:49,831 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_array_true_unreach_call__true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:49,832 INFO L82 PathProgramCache]: Analyzing trace with hash -91325821, now seen corresponding path program 24 times [2018-07-24 10:52:49,832 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:49,832 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:49,833 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:49,833 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:49,833 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:49,841 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:50,165 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,165 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:50,165 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:50,174 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:50,174 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:52:50,253 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:52:50,253 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:50,256 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:50,269 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:50,269 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:51,357 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:51,378 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:51,378 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:51,392 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:51,393 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown