java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-new/count_by_2_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:57:47,903 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:57:47,905 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:57:47,917 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:57:47,918 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:57:47,919 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:57:47,920 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:57:47,922 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:57:47,924 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:57:47,925 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:57:47,926 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:57:47,926 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:57:47,927 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:57:47,928 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:57:47,929 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:57:47,930 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:57:47,931 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:57:47,933 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:57:47,935 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:57:47,937 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:57:47,938 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:57:47,940 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:57:47,942 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:57:47,942 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:57:47,943 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:57:47,944 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:57:47,944 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:57:47,945 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:57:47,946 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:57:47,947 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:57:47,948 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:57:47,948 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:57:47,949 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:57:47,949 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:57:47,950 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:57:47,951 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:57:47,951 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:57:47,966 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:57:47,966 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:57:47,967 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:57:47,967 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:57:47,968 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:57:47,968 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:57:47,968 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:57:47,968 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:57:47,968 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:57:47,969 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:57:47,969 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:57:47,969 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:57:47,970 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:57:47,970 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:57:47,970 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:57:47,970 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:57:47,970 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:57:47,971 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:57:47,971 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:57:47,971 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:57:47,971 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:57:47,971 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:57:47,972 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:57:47,972 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:57:47,972 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:57:47,972 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:57:47,973 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:57:47,973 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:57:47,973 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:57:47,973 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:57:47,973 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:57:47,974 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:57:47,974 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:57:48,016 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:57:48,029 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:57:48,032 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:57:48,034 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:57:48,034 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:57:48,037 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-new/count_by_2_true-unreach-call_true-termination.i [2018-07-24 10:57:48,381 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/49c169615/626abef78df14f4ebf519c9183e81cce/FLAGf18addff8 [2018-07-24 10:57:48,510 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:57:48,511 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-new/count_by_2_true-unreach-call_true-termination.i [2018-07-24 10:57:48,516 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/49c169615/626abef78df14f4ebf519c9183e81cce/FLAGf18addff8 [2018-07-24 10:57:48,532 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/49c169615/626abef78df14f4ebf519c9183e81cce [2018-07-24 10:57:48,546 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:57:48,548 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:57:48,550 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:57:48,550 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:57:48,557 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:57:48,558 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,562 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@55bccd32 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48, skipping insertion in model container [2018-07-24 10:57:48,563 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,768 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:57:48,817 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:57:48,837 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:57:48,842 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:57:48,857 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48 WrapperNode [2018-07-24 10:57:48,857 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:57:48,858 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:57:48,858 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:57:48,859 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:57:48,869 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,875 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,882 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:57:48,882 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:57:48,882 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:57:48,883 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:57:48,894 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,894 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,895 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,895 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,897 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,904 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,906 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... [2018-07-24 10:57:48,908 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:57:48,908 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:57:48,909 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:57:48,909 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:57:48,910 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:57:48,984 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:57:48,984 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:57:48,984 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:57:48,985 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:57:48,985 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:57:48,985 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:57:48,985 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:57:48,986 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:57:49,249 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:57:49,250 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:57:49 BoogieIcfgContainer [2018-07-24 10:57:49,250 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:57:49,251 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:57:49,252 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:57:49,255 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:57:49,256 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:57:48" (1/3) ... [2018-07-24 10:57:49,257 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a940a5a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:57:49, skipping insertion in model container [2018-07-24 10:57:49,257 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:57:48" (2/3) ... [2018-07-24 10:57:49,257 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@1a940a5a and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:57:49, skipping insertion in model container [2018-07-24 10:57:49,258 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:57:49" (3/3) ... [2018-07-24 10:57:49,260 INFO L112 eAbstractionObserver]: Analyzing ICFG count_by_2_true-unreach-call_true-termination.i [2018-07-24 10:57:49,269 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:57:49,275 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:57:49,318 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:57:49,319 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:57:49,319 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:57:49,319 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:57:49,319 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:57:49,320 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:57:49,320 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:57:49,320 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:57:49,320 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:57:49,339 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states. [2018-07-24 10:57:49,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:57:49,345 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:49,346 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:49,347 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:49,351 INFO L82 PathProgramCache]: Analyzing trace with hash 888303788, now seen corresponding path program 1 times [2018-07-24 10:57:49,354 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:49,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,406 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:49,406 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,406 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:49,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:49,463 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:49,465 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:57:49,466 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:57:49,466 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:57:49,470 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:57:49,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:57:49,486 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:57:49,489 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 2 states. [2018-07-24 10:57:49,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:49,526 INFO L93 Difference]: Finished difference Result 32 states and 35 transitions. [2018-07-24 10:57:49,526 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:57:49,529 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:57:49,529 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:49,538 INFO L225 Difference]: With dead ends: 32 [2018-07-24 10:57:49,538 INFO L226 Difference]: Without dead ends: 13 [2018-07-24 10:57:49,542 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:57:49,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-24 10:57:49,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-24 10:57:49,581 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-24 10:57:49,581 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 13 transitions. [2018-07-24 10:57:49,584 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 13 transitions. Word has length 10 [2018-07-24 10:57:49,586 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:49,586 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 13 transitions. [2018-07-24 10:57:49,586 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:57:49,586 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 13 transitions. [2018-07-24 10:57:49,587 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:57:49,587 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:49,587 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:49,588 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:49,588 INFO L82 PathProgramCache]: Analyzing trace with hash 1497168015, now seen corresponding path program 1 times [2018-07-24 10:57:49,588 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:49,590 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,590 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:49,591 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,591 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:49,604 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:49,651 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:49,651 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:57:49,652 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:57:49,652 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:57:49,654 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:57:49,654 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:57:49,659 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:57:49,660 INFO L87 Difference]: Start difference. First operand 13 states and 13 transitions. Second operand 3 states. [2018-07-24 10:57:49,745 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:49,745 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-24 10:57:49,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:57:49,746 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:57:49,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:49,747 INFO L225 Difference]: With dead ends: 21 [2018-07-24 10:57:49,748 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:57:49,749 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:57:49,749 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:57:49,753 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 15. [2018-07-24 10:57:49,754 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 15 states. [2018-07-24 10:57:49,755 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15 states to 15 states and 15 transitions. [2018-07-24 10:57:49,755 INFO L78 Accepts]: Start accepts. Automaton has 15 states and 15 transitions. Word has length 11 [2018-07-24 10:57:49,755 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:49,756 INFO L471 AbstractCegarLoop]: Abstraction has 15 states and 15 transitions. [2018-07-24 10:57:49,756 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:57:49,756 INFO L276 IsEmpty]: Start isEmpty. Operand 15 states and 15 transitions. [2018-07-24 10:57:49,757 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:57:49,757 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:49,757 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:49,758 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:49,758 INFO L82 PathProgramCache]: Analyzing trace with hash 1742853384, now seen corresponding path program 1 times [2018-07-24 10:57:49,766 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:49,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:49,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,769 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:49,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:49,876 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:49,877 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:49,877 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:49,888 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:49,889 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:49,913 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:49,921 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:49,941 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:49,942 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,019 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,040 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:50,041 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:50,066 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:50,066 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:50,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:50,082 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:50,086 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,086 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,138 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,141 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:50,142 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:57:50,142 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:50,143 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:57:50,143 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:57:50,144 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:57:50,144 INFO L87 Difference]: Start difference. First operand 15 states and 15 transitions. Second operand 4 states. [2018-07-24 10:57:50,186 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:50,187 INFO L93 Difference]: Finished difference Result 24 states and 24 transitions. [2018-07-24 10:57:50,189 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:57:50,189 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-07-24 10:57:50,189 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:50,190 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:57:50,190 INFO L226 Difference]: Without dead ends: 19 [2018-07-24 10:57:50,191 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 58 GetRequests, 54 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:57:50,192 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-24 10:57:50,195 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-07-24 10:57:50,195 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:57:50,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-24 10:57:50,196 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 14 [2018-07-24 10:57:50,196 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:50,197 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-24 10:57:50,197 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:57:50,197 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-24 10:57:50,197 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:57:50,197 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:50,198 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:50,198 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:50,198 INFO L82 PathProgramCache]: Analyzing trace with hash -1963558417, now seen corresponding path program 2 times [2018-07-24 10:57:50,199 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:50,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:50,200 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:50,200 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:50,200 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:50,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:50,269 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,269 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:50,269 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:50,282 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:50,282 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:50,310 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:50,310 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:50,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:50,319 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,319 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,615 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,650 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:50,650 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:50,680 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:50,681 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:50,703 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:50,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:50,706 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:50,712 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,712 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:50,727 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,728 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:50,729 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:57:50,729 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:50,730 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:57:50,730 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:57:50,730 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:57:50,731 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 5 states. [2018-07-24 10:57:50,799 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:50,800 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-24 10:57:50,801 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:57:50,801 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-07-24 10:57:50,802 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:50,802 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:57:50,802 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:57:50,803 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 71 GetRequests, 65 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:57:50,803 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:57:50,807 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 21. [2018-07-24 10:57:50,807 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-07-24 10:57:50,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 21 transitions. [2018-07-24 10:57:50,808 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 21 transitions. Word has length 17 [2018-07-24 10:57:50,808 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:50,809 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 21 transitions. [2018-07-24 10:57:50,809 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:57:50,809 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 21 transitions. [2018-07-24 10:57:50,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:57:50,810 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:50,810 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:50,810 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:50,811 INFO L82 PathProgramCache]: Analyzing trace with hash -363309144, now seen corresponding path program 3 times [2018-07-24 10:57:50,811 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:50,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:50,812 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:50,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:50,812 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:50,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:50,915 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,915 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:50,915 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:50,930 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:50,930 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:50,946 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:57:50,946 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:50,948 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:50,955 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:50,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:51,171 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,191 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:51,191 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:51,208 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:51,208 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:51,229 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:57:51,229 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:51,233 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:51,242 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,242 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:51,293 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,296 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:51,297 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:57:51,297 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:51,297 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:57:51,297 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:57:51,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:57:51,304 INFO L87 Difference]: Start difference. First operand 21 states and 21 transitions. Second operand 6 states. [2018-07-24 10:57:51,340 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:51,340 INFO L93 Difference]: Finished difference Result 30 states and 30 transitions. [2018-07-24 10:57:51,341 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:57:51,342 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 20 [2018-07-24 10:57:51,342 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:51,343 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:57:51,343 INFO L226 Difference]: Without dead ends: 25 [2018-07-24 10:57:51,344 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 84 GetRequests, 76 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:57:51,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-07-24 10:57:51,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-07-24 10:57:51,348 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:57:51,349 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-24 10:57:51,349 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 20 [2018-07-24 10:57:51,349 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:51,350 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-24 10:57:51,350 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:57:51,350 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-24 10:57:51,351 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:57:51,351 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:51,351 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:51,351 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:51,352 INFO L82 PathProgramCache]: Analyzing trace with hash -1474202801, now seen corresponding path program 4 times [2018-07-24 10:57:51,352 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:51,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:51,353 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:51,353 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:51,353 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:51,360 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:51,446 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,446 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:51,447 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:51,455 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:51,456 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:51,463 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:51,464 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:51,466 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:51,474 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,474 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:51,860 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:51,895 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:51,926 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:51,926 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:51,947 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:51,947 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:51,951 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:51,957 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,958 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:51,985 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:51,989 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:51,989 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:57:51,989 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:51,990 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:57:51,990 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:57:51,990 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:57:51,991 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 7 states. [2018-07-24 10:57:52,049 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:52,050 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-24 10:57:52,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:57:52,052 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-07-24 10:57:52,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:52,053 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:57:52,054 INFO L226 Difference]: Without dead ends: 28 [2018-07-24 10:57:52,055 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 97 GetRequests, 87 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:57:52,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-24 10:57:52,058 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 27. [2018-07-24 10:57:52,059 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:57:52,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 27 transitions. [2018-07-24 10:57:52,060 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 27 transitions. Word has length 23 [2018-07-24 10:57:52,060 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:52,060 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 27 transitions. [2018-07-24 10:57:52,060 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:57:52,060 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 27 transitions. [2018-07-24 10:57:52,061 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:57:52,061 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:52,062 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:52,062 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:52,062 INFO L82 PathProgramCache]: Analyzing trace with hash 910844488, now seen corresponding path program 5 times [2018-07-24 10:57:52,062 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:52,063 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:52,063 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:52,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:52,064 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:52,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:52,171 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,172 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:52,172 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:52,180 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:52,180 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:52,193 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:57:52,193 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:52,195 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:52,202 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,203 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:52,335 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,356 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:52,356 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:52,372 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:52,373 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:52,400 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:57:52,400 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:52,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:52,410 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,411 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:52,433 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,434 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:52,435 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:57:52,435 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:52,436 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:57:52,436 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:57:52,437 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:57:52,437 INFO L87 Difference]: Start difference. First operand 27 states and 27 transitions. Second operand 8 states. [2018-07-24 10:57:52,509 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:52,510 INFO L93 Difference]: Finished difference Result 36 states and 36 transitions. [2018-07-24 10:57:52,511 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:57:52,511 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 26 [2018-07-24 10:57:52,511 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:52,512 INFO L225 Difference]: With dead ends: 36 [2018-07-24 10:57:52,512 INFO L226 Difference]: Without dead ends: 31 [2018-07-24 10:57:52,513 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 110 GetRequests, 98 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:57:52,513 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-07-24 10:57:52,516 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-07-24 10:57:52,517 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:57:52,517 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-24 10:57:52,518 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 26 [2018-07-24 10:57:52,518 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:52,518 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-24 10:57:52,518 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:57:52,518 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-24 10:57:52,519 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:57:52,519 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:52,519 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:52,520 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:52,520 INFO L82 PathProgramCache]: Analyzing trace with hash -2084313937, now seen corresponding path program 6 times [2018-07-24 10:57:52,520 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:52,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:52,521 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:52,521 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:52,521 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:52,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:52,632 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,632 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:52,632 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:52,643 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:52,644 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:52,677 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:57:52,677 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:52,679 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:52,687 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,687 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:52,968 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:52,997 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:52,997 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:53,012 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:53,013 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:53,047 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:57:53,048 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:53,051 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:53,058 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,059 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:53,077 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,079 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:53,080 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:57:53,080 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:53,080 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:57:53,080 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:57:53,081 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:57:53,081 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 9 states. [2018-07-24 10:57:53,127 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:53,127 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-24 10:57:53,130 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:57:53,130 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 29 [2018-07-24 10:57:53,131 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:53,131 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:57:53,131 INFO L226 Difference]: Without dead ends: 34 [2018-07-24 10:57:53,132 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 123 GetRequests, 109 SyntacticMatches, 0 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=120, Invalid=120, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:57:53,132 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-24 10:57:53,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 33. [2018-07-24 10:57:53,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-07-24 10:57:53,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 33 transitions. [2018-07-24 10:57:53,137 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 33 transitions. Word has length 29 [2018-07-24 10:57:53,138 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:53,138 INFO L471 AbstractCegarLoop]: Abstraction has 33 states and 33 transitions. [2018-07-24 10:57:53,138 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:57:53,138 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 33 transitions. [2018-07-24 10:57:53,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 10:57:53,139 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:53,139 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:53,139 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:53,140 INFO L82 PathProgramCache]: Analyzing trace with hash 1391588584, now seen corresponding path program 7 times [2018-07-24 10:57:53,140 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:53,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:53,141 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:53,141 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:53,141 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:53,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:53,257 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,257 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:53,257 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:53,265 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:53,266 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:53,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:53,275 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:53,284 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,284 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:53,502 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,526 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:53,527 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:53,543 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:53,543 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:53,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:53,563 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:53,571 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,571 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:53,640 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 0 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,646 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:53,646 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:57:53,647 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:53,647 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:57:53,647 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:57:53,648 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:57:53,648 INFO L87 Difference]: Start difference. First operand 33 states and 33 transitions. Second operand 10 states. [2018-07-24 10:57:53,800 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:53,800 INFO L93 Difference]: Finished difference Result 42 states and 42 transitions. [2018-07-24 10:57:53,804 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:57:53,805 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 32 [2018-07-24 10:57:53,805 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:53,806 INFO L225 Difference]: With dead ends: 42 [2018-07-24 10:57:53,806 INFO L226 Difference]: Without dead ends: 37 [2018-07-24 10:57:53,806 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 120 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:57:53,807 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-24 10:57:53,810 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 36. [2018-07-24 10:57:53,810 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:57:53,811 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-24 10:57:53,811 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 32 [2018-07-24 10:57:53,811 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:53,811 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-24 10:57:53,811 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:57:53,812 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-24 10:57:53,812 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:57:53,812 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:53,813 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:53,813 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:53,813 INFO L82 PathProgramCache]: Analyzing trace with hash 342085135, now seen corresponding path program 8 times [2018-07-24 10:57:53,813 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:53,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:53,814 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:53,814 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:53,814 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:53,822 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:53,943 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,943 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:53,944 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:53,951 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:53,951 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:53,961 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:53,961 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:53,964 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:53,973 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:53,973 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:54,224 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:54,245 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:54,245 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:54,261 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:54,261 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:54,280 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:54,280 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:54,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:54,292 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:54,292 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:54,314 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:54,316 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:54,316 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:57:54,316 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:54,317 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:57:54,317 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:57:54,318 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:57:54,318 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 11 states. [2018-07-24 10:57:54,414 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:54,414 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-24 10:57:54,415 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:57:54,415 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 35 [2018-07-24 10:57:54,415 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:54,416 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:57:54,416 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:57:54,417 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 149 GetRequests, 131 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:57:54,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:57:54,420 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 39. [2018-07-24 10:57:54,421 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:57:54,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 39 transitions. [2018-07-24 10:57:54,421 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 39 transitions. Word has length 35 [2018-07-24 10:57:54,422 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:54,422 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 39 transitions. [2018-07-24 10:57:54,422 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:57:54,422 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 39 transitions. [2018-07-24 10:57:54,423 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-24 10:57:54,423 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:54,423 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:54,424 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:54,424 INFO L82 PathProgramCache]: Analyzing trace with hash 1946750856, now seen corresponding path program 9 times [2018-07-24 10:57:54,424 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:54,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:54,425 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:54,425 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:54,425 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:54,433 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:54,625 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:54,626 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:54,626 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:54,640 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:54,640 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:54,658 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:57:54,659 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:54,660 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:54,670 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:54,670 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:54,902 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:54,923 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:54,923 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:54,940 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:54,941 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:54,988 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:57:54,988 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:54,991 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:54,999 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:55,000 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:55,063 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:55,065 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:55,065 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:57:55,065 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:55,066 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:57:55,066 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:57:55,067 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:57:55,067 INFO L87 Difference]: Start difference. First operand 39 states and 39 transitions. Second operand 12 states. [2018-07-24 10:57:55,109 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:55,109 INFO L93 Difference]: Finished difference Result 48 states and 48 transitions. [2018-07-24 10:57:55,110 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:57:55,110 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-07-24 10:57:55,111 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:55,112 INFO L225 Difference]: With dead ends: 48 [2018-07-24 10:57:55,112 INFO L226 Difference]: Without dead ends: 43 [2018-07-24 10:57:55,113 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 162 GetRequests, 142 SyntacticMatches, 0 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=231, Invalid=231, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:57:55,113 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43 states. [2018-07-24 10:57:55,117 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43 to 42. [2018-07-24 10:57:55,117 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:57:55,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-24 10:57:55,118 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 38 [2018-07-24 10:57:55,119 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:55,119 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-24 10:57:55,119 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:57:55,119 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-24 10:57:55,120 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:57:55,120 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:55,120 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:55,120 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:55,120 INFO L82 PathProgramCache]: Analyzing trace with hash -737726609, now seen corresponding path program 10 times [2018-07-24 10:57:55,121 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:55,121 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:55,121 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:55,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:55,122 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:55,128 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:55,293 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:55,293 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:55,293 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:55,301 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:55,301 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:55,336 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:55,337 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:55,339 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:55,348 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:55,348 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:56,030 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:56,050 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:56,051 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:56,066 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:56,066 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:56,088 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:56,088 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:56,091 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:56,100 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:56,101 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:56,161 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:56,164 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:56,165 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:57:56,165 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:56,165 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:57:56,166 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:57:56,166 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:57:56,167 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 13 states. [2018-07-24 10:57:56,278 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:56,278 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-24 10:57:56,278 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:57:56,279 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 41 [2018-07-24 10:57:56,279 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:56,280 INFO L225 Difference]: With dead ends: 51 [2018-07-24 10:57:56,280 INFO L226 Difference]: Without dead ends: 46 [2018-07-24 10:57:56,281 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 175 GetRequests, 153 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:57:56,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-24 10:57:56,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 45. [2018-07-24 10:57:56,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 45 states. [2018-07-24 10:57:56,286 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 45 states to 45 states and 45 transitions. [2018-07-24 10:57:56,286 INFO L78 Accepts]: Start accepts. Automaton has 45 states and 45 transitions. Word has length 41 [2018-07-24 10:57:56,286 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:56,286 INFO L471 AbstractCegarLoop]: Abstraction has 45 states and 45 transitions. [2018-07-24 10:57:56,287 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:57:56,287 INFO L276 IsEmpty]: Start isEmpty. Operand 45 states and 45 transitions. [2018-07-24 10:57:56,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:57:56,288 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:56,288 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:56,288 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:56,288 INFO L82 PathProgramCache]: Analyzing trace with hash -1714834904, now seen corresponding path program 11 times [2018-07-24 10:57:56,289 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:56,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:56,290 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:56,290 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:56,290 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:56,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:56,587 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:56,588 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:56,588 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:56,598 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:56,599 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:56,612 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:57:56,612 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:56,615 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:56,625 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:56,625 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:56,942 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:56,963 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:56,964 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:56,978 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:56,979 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:57,026 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:57:57,026 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:57,029 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:57,036 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,036 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:57,055 INFO L134 CoverageAnalysis]: Checked inductivity of 187 backedges. 0 proven. 187 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,056 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:57,057 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:57:57,057 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:57,057 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:57:57,057 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:57:57,058 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:57:57,058 INFO L87 Difference]: Start difference. First operand 45 states and 45 transitions. Second operand 14 states. [2018-07-24 10:57:57,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:57,154 INFO L93 Difference]: Finished difference Result 54 states and 54 transitions. [2018-07-24 10:57:57,154 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:57:57,154 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 44 [2018-07-24 10:57:57,155 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:57,156 INFO L225 Difference]: With dead ends: 54 [2018-07-24 10:57:57,156 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:57:57,157 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 188 GetRequests, 164 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:57:57,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:57:57,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 48. [2018-07-24 10:57:57,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:57:57,161 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-07-24 10:57:57,162 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 44 [2018-07-24 10:57:57,162 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:57,162 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-07-24 10:57:57,162 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:57:57,162 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-07-24 10:57:57,163 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-24 10:57:57,163 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:57,163 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:57,163 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:57,164 INFO L82 PathProgramCache]: Analyzing trace with hash 540281039, now seen corresponding path program 12 times [2018-07-24 10:57:57,164 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:57,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:57,165 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:57,165 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:57,165 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:57,171 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:57,324 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,324 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:57,324 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:57,331 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:57,331 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:57,345 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:57:57,345 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:57,346 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:57,356 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,356 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:57,649 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,670 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:57,671 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:57,686 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:57,686 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:57,752 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:57:57,752 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:57,755 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:57,765 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,766 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:57,821 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:57,822 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:57,822 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:57:57,822 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:57,823 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:57:57,823 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:57:57,824 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:57:57,824 INFO L87 Difference]: Start difference. First operand 48 states and 48 transitions. Second operand 15 states. [2018-07-24 10:57:57,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:57,892 INFO L93 Difference]: Finished difference Result 57 states and 57 transitions. [2018-07-24 10:57:57,893 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:57:57,893 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-07-24 10:57:57,893 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:57,894 INFO L225 Difference]: With dead ends: 57 [2018-07-24 10:57:57,894 INFO L226 Difference]: Without dead ends: 52 [2018-07-24 10:57:57,894 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 201 GetRequests, 175 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:57:57,894 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-07-24 10:57:57,899 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 51. [2018-07-24 10:57:57,899 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-07-24 10:57:57,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 51 transitions. [2018-07-24 10:57:57,900 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 51 transitions. Word has length 47 [2018-07-24 10:57:57,900 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:57,900 INFO L471 AbstractCegarLoop]: Abstraction has 51 states and 51 transitions. [2018-07-24 10:57:57,900 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:57:57,900 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 51 transitions. [2018-07-24 10:57:57,901 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-24 10:57:57,901 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:57,901 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:57,902 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:57,902 INFO L82 PathProgramCache]: Analyzing trace with hash 820894920, now seen corresponding path program 13 times [2018-07-24 10:57:57,902 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:57,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:57,903 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:57,903 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:57,903 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:57,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:58,283 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:58,283 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:58,283 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:58,291 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:58,291 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:58,315 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:58,317 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:58,326 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:58,327 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:59,003 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,023 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:59,023 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:59,038 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:59,038 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:59,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:59,060 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:59,068 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,068 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:59,088 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,089 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:59,089 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:57:59,090 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:59,090 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:57:59,090 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:57:59,091 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:57:59,091 INFO L87 Difference]: Start difference. First operand 51 states and 51 transitions. Second operand 16 states. [2018-07-24 10:57:59,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:59,137 INFO L93 Difference]: Finished difference Result 60 states and 60 transitions. [2018-07-24 10:57:59,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:57:59,138 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 50 [2018-07-24 10:57:59,138 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:59,139 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:57:59,139 INFO L226 Difference]: Without dead ends: 55 [2018-07-24 10:57:59,140 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 214 GetRequests, 186 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:57:59,140 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 55 states. [2018-07-24 10:57:59,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 55 to 54. [2018-07-24 10:57:59,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-24 10:57:59,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 54 transitions. [2018-07-24 10:57:59,145 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 54 transitions. Word has length 50 [2018-07-24 10:57:59,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:59,145 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 54 transitions. [2018-07-24 10:57:59,145 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:57:59,146 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 54 transitions. [2018-07-24 10:57:59,146 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-07-24 10:57:59,146 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:59,147 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:59,147 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:59,147 INFO L82 PathProgramCache]: Analyzing trace with hash -1712301521, now seen corresponding path program 14 times [2018-07-24 10:57:59,147 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:59,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:59,148 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:59,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:59,148 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:59,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:59,313 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,313 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:59,313 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:59,322 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:59,323 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:59,362 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:59,363 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:59,364 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:59,373 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,373 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:59,917 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,937 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:59,938 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:59,952 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:59,953 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:59,976 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:59,976 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:59,980 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:59,990 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:59,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:00,011 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:00,013 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:00,013 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:58:00,013 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:00,013 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:58:00,014 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:58:00,014 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:58:00,014 INFO L87 Difference]: Start difference. First operand 54 states and 54 transitions. Second operand 17 states. [2018-07-24 10:58:00,148 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:00,148 INFO L93 Difference]: Finished difference Result 63 states and 63 transitions. [2018-07-24 10:58:00,148 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:58:00,148 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 53 [2018-07-24 10:58:00,149 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:00,149 INFO L225 Difference]: With dead ends: 63 [2018-07-24 10:58:00,150 INFO L226 Difference]: Without dead ends: 58 [2018-07-24 10:58:00,151 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 227 GetRequests, 197 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:58:00,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-07-24 10:58:00,155 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-07-24 10:58:00,155 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:58:00,156 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 57 transitions. [2018-07-24 10:58:00,156 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 57 transitions. Word has length 53 [2018-07-24 10:58:00,156 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:00,156 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 57 transitions. [2018-07-24 10:58:00,156 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:58:00,156 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 57 transitions. [2018-07-24 10:58:00,157 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:58:00,157 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:00,157 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:00,158 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:00,158 INFO L82 PathProgramCache]: Analyzing trace with hash -1297117336, now seen corresponding path program 15 times [2018-07-24 10:58:00,158 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:00,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:00,159 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:00,159 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:00,159 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:00,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:00,371 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:00,371 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:00,371 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:00,382 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:00,383 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:00,403 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:58:00,403 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:00,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:00,412 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:00,413 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:00,812 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:00,834 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:00,834 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:00,849 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:00,850 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:00,932 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:58:00,932 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:00,935 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:00,943 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:00,943 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:00,967 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 0 proven. 345 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:00,968 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:00,968 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:58:00,969 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:00,969 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:58:00,969 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:58:00,970 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:58:00,970 INFO L87 Difference]: Start difference. First operand 57 states and 57 transitions. Second operand 18 states. [2018-07-24 10:58:01,053 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:01,053 INFO L93 Difference]: Finished difference Result 66 states and 66 transitions. [2018-07-24 10:58:01,054 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:58:01,054 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 56 [2018-07-24 10:58:01,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:01,055 INFO L225 Difference]: With dead ends: 66 [2018-07-24 10:58:01,056 INFO L226 Difference]: Without dead ends: 61 [2018-07-24 10:58:01,056 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 240 GetRequests, 208 SyntacticMatches, 0 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=561, Invalid=561, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:58:01,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 61 states. [2018-07-24 10:58:01,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 61 to 60. [2018-07-24 10:58:01,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:58:01,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 60 transitions. [2018-07-24 10:58:01,061 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 60 transitions. Word has length 56 [2018-07-24 10:58:01,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:01,062 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 60 transitions. [2018-07-24 10:58:01,062 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:58:01,062 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 60 transitions. [2018-07-24 10:58:01,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:58:01,063 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:01,063 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:01,063 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:01,063 INFO L82 PathProgramCache]: Analyzing trace with hash -2050874481, now seen corresponding path program 16 times [2018-07-24 10:58:01,064 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:01,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:01,065 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:01,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:01,065 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:01,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:01,770 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:01,771 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:01,771 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:01,778 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:01,779 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:01,793 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:01,793 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:01,795 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:01,807 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:01,808 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:02,534 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:02,554 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:02,554 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:02,574 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:02,574 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:02,602 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:02,603 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:02,605 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:02,612 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:02,612 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:02,674 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:02,676 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:02,676 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:58:02,676 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:02,677 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:58:02,677 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:58:02,677 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:58:02,680 INFO L87 Difference]: Start difference. First operand 60 states and 60 transitions. Second operand 19 states. [2018-07-24 10:58:02,809 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:02,810 INFO L93 Difference]: Finished difference Result 69 states and 69 transitions. [2018-07-24 10:58:02,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:58:02,813 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-07-24 10:58:02,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:02,814 INFO L225 Difference]: With dead ends: 69 [2018-07-24 10:58:02,814 INFO L226 Difference]: Without dead ends: 64 [2018-07-24 10:58:02,815 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 253 GetRequests, 219 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:58:02,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-07-24 10:58:02,818 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 63. [2018-07-24 10:58:02,818 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:58:02,819 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 63 transitions. [2018-07-24 10:58:02,819 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 63 transitions. Word has length 59 [2018-07-24 10:58:02,819 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:02,819 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 63 transitions. [2018-07-24 10:58:02,819 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:58:02,820 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 63 transitions. [2018-07-24 10:58:02,820 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-24 10:58:02,820 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:02,821 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:02,821 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:02,821 INFO L82 PathProgramCache]: Analyzing trace with hash 1154009608, now seen corresponding path program 17 times [2018-07-24 10:58:02,821 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:02,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:02,822 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:02,822 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:02,822 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:02,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:03,396 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:03,396 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:03,404 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:03,404 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:03,420 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:58:03,421 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:03,423 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:03,432 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:03,432 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:04,262 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:04,281 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:04,281 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:04,296 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:04,296 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:04,381 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:58:04,381 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:04,384 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:04,394 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:04,394 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:04,426 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:04,427 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:04,427 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:58:04,427 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:04,428 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:58:04,428 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:58:04,428 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:58:04,429 INFO L87 Difference]: Start difference. First operand 63 states and 63 transitions. Second operand 20 states. [2018-07-24 10:58:04,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:04,522 INFO L93 Difference]: Finished difference Result 72 states and 72 transitions. [2018-07-24 10:58:04,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:58:04,522 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 62 [2018-07-24 10:58:04,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:04,523 INFO L225 Difference]: With dead ends: 72 [2018-07-24 10:58:04,523 INFO L226 Difference]: Without dead ends: 67 [2018-07-24 10:58:04,524 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 266 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:58:04,524 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-24 10:58:04,526 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 66. [2018-07-24 10:58:04,526 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-24 10:58:04,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 66 transitions. [2018-07-24 10:58:04,527 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 66 transitions. Word has length 62 [2018-07-24 10:58:04,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:04,527 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 66 transitions. [2018-07-24 10:58:04,527 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:58:04,527 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 66 transitions. [2018-07-24 10:58:04,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-07-24 10:58:04,528 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:04,528 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:04,528 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:04,529 INFO L82 PathProgramCache]: Analyzing trace with hash 732914927, now seen corresponding path program 18 times [2018-07-24 10:58:04,529 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:04,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:04,530 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:04,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:04,530 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:04,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:05,289 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:05,290 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:05,290 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:05,302 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:05,302 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:05,319 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:58:05,320 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:05,321 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:05,330 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:05,330 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:05,843 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:05,865 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:05,865 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:05,881 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:05,881 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:05,985 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 19 check-sat command(s) [2018-07-24 10:58:05,985 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:05,988 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:05,997 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:05,997 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:06,007 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:06,009 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:06,009 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-07-24 10:58:06,009 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:06,009 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:58:06,010 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:58:06,010 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:58:06,010 INFO L87 Difference]: Start difference. First operand 66 states and 66 transitions. Second operand 21 states. [2018-07-24 10:58:06,088 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:06,088 INFO L93 Difference]: Finished difference Result 75 states and 75 transitions. [2018-07-24 10:58:06,088 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:58:06,089 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 65 [2018-07-24 10:58:06,089 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:06,090 INFO L225 Difference]: With dead ends: 75 [2018-07-24 10:58:06,090 INFO L226 Difference]: Without dead ends: 70 [2018-07-24 10:58:06,091 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 279 GetRequests, 241 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:58:06,091 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-07-24 10:58:06,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-07-24 10:58:06,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:58:06,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 69 transitions. [2018-07-24 10:58:06,096 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 69 transitions. Word has length 65 [2018-07-24 10:58:06,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:06,096 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 69 transitions. [2018-07-24 10:58:06,096 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:58:06,096 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 69 transitions. [2018-07-24 10:58:06,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-07-24 10:58:06,097 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:06,098 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:06,098 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:06,098 INFO L82 PathProgramCache]: Analyzing trace with hash 1500744872, now seen corresponding path program 19 times [2018-07-24 10:58:06,098 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:06,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:06,099 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:06,099 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:06,099 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:06,107 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:06,370 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:06,371 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:06,371 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:06,379 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:06,379 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:06,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:06,392 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:06,402 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:06,403 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:07,347 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:07,367 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:07,367 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:07,383 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:07,383 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:07,409 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:07,413 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:07,422 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:07,423 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:07,431 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 0 proven. 551 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:07,432 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:07,433 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-07-24 10:58:07,433 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:07,433 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:58:07,433 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:58:07,434 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:58:07,434 INFO L87 Difference]: Start difference. First operand 69 states and 69 transitions. Second operand 22 states. [2018-07-24 10:58:07,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:07,535 INFO L93 Difference]: Finished difference Result 78 states and 78 transitions. [2018-07-24 10:58:07,536 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:58:07,536 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 68 [2018-07-24 10:58:07,536 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:07,537 INFO L225 Difference]: With dead ends: 78 [2018-07-24 10:58:07,537 INFO L226 Difference]: Without dead ends: 73 [2018-07-24 10:58:07,538 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 292 GetRequests, 252 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:58:07,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 73 states. [2018-07-24 10:58:07,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 73 to 72. [2018-07-24 10:58:07,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-24 10:58:07,542 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 72 transitions. [2018-07-24 10:58:07,542 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 72 transitions. Word has length 68 [2018-07-24 10:58:07,542 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:07,542 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 72 transitions. [2018-07-24 10:58:07,543 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:58:07,543 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 72 transitions. [2018-07-24 10:58:07,543 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:58:07,543 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:07,544 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:07,544 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:07,544 INFO L82 PathProgramCache]: Analyzing trace with hash 926817871, now seen corresponding path program 20 times [2018-07-24 10:58:07,544 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:07,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:07,545 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:07,545 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:07,545 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:07,552 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:07,807 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:07,808 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:07,808 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:07,814 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:07,815 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:07,829 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:07,829 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:07,831 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:07,845 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:07,846 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:08,873 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:08,893 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:08,893 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:08,908 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:08,908 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:08,939 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:08,939 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:08,942 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:08,953 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:08,953 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:08,982 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:08,983 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:08,983 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-07-24 10:58:08,983 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:08,984 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:58:08,984 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:58:08,985 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:58:08,985 INFO L87 Difference]: Start difference. First operand 72 states and 72 transitions. Second operand 23 states. [2018-07-24 10:58:09,210 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:09,211 INFO L93 Difference]: Finished difference Result 81 states and 81 transitions. [2018-07-24 10:58:09,213 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:58:09,214 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 71 [2018-07-24 10:58:09,214 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:09,215 INFO L225 Difference]: With dead ends: 81 [2018-07-24 10:58:09,215 INFO L226 Difference]: Without dead ends: 76 [2018-07-24 10:58:09,216 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 305 GetRequests, 263 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:58:09,216 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-07-24 10:58:09,218 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 75. [2018-07-24 10:58:09,218 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-24 10:58:09,218 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 75 transitions. [2018-07-24 10:58:09,219 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 75 transitions. Word has length 71 [2018-07-24 10:58:09,219 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:09,219 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 75 transitions. [2018-07-24 10:58:09,219 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:58:09,219 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 75 transitions. [2018-07-24 10:58:09,220 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:58:09,220 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:09,220 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:09,220 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:09,220 INFO L82 PathProgramCache]: Analyzing trace with hash 1332336456, now seen corresponding path program 21 times [2018-07-24 10:58:09,221 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:09,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:09,221 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:09,221 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:09,222 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:09,227 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:09,516 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:09,516 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:09,516 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:09,525 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:09,525 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:09,547 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:58:09,547 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:09,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:09,559 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:09,559 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:10,130 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:10,150 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:10,150 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:10,165 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:10,165 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:10,289 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 22 check-sat command(s) [2018-07-24 10:58:10,289 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:10,292 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:10,301 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:10,301 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:10,321 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:10,323 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:10,323 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-07-24 10:58:10,323 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:10,323 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:58:10,324 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:58:10,324 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:58:10,325 INFO L87 Difference]: Start difference. First operand 75 states and 75 transitions. Second operand 24 states. [2018-07-24 10:58:10,426 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:10,427 INFO L93 Difference]: Finished difference Result 84 states and 84 transitions. [2018-07-24 10:58:10,427 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:58:10,427 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-07-24 10:58:10,427 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:10,428 INFO L225 Difference]: With dead ends: 84 [2018-07-24 10:58:10,428 INFO L226 Difference]: Without dead ends: 79 [2018-07-24 10:58:10,430 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 318 GetRequests, 274 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:58:10,430 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-24 10:58:10,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 78. [2018-07-24 10:58:10,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-24 10:58:10,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 78 transitions. [2018-07-24 10:58:10,433 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 78 transitions. Word has length 74 [2018-07-24 10:58:10,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:10,434 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 78 transitions. [2018-07-24 10:58:10,434 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:58:10,434 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 78 transitions. [2018-07-24 10:58:10,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 10:58:10,435 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:10,435 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:10,435 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:10,435 INFO L82 PathProgramCache]: Analyzing trace with hash 393498543, now seen corresponding path program 22 times [2018-07-24 10:58:10,435 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:10,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:10,436 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:10,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:10,437 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:10,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:10,700 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:10,701 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:10,701 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:10,707 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:10,708 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:10,723 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:10,723 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:10,725 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:10,733 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:10,733 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:11,338 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:11,358 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:11,358 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:11,373 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:11,373 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:11,409 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:11,409 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:11,412 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:11,421 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:11,422 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:11,460 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:11,462 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:11,462 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-07-24 10:58:11,462 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:11,462 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:58:11,463 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:58:11,463 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:58:11,464 INFO L87 Difference]: Start difference. First operand 78 states and 78 transitions. Second operand 25 states. [2018-07-24 10:58:11,537 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:11,537 INFO L93 Difference]: Finished difference Result 87 states and 87 transitions. [2018-07-24 10:58:11,540 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:58:11,541 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 77 [2018-07-24 10:58:11,541 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:11,542 INFO L225 Difference]: With dead ends: 87 [2018-07-24 10:58:11,542 INFO L226 Difference]: Without dead ends: 82 [2018-07-24 10:58:11,543 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 331 GetRequests, 285 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:58:11,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 82 states. [2018-07-24 10:58:11,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 82 to 81. [2018-07-24 10:58:11,548 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-07-24 10:58:11,548 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 81 transitions. [2018-07-24 10:58:11,548 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 81 transitions. Word has length 77 [2018-07-24 10:58:11,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:11,549 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 81 transitions. [2018-07-24 10:58:11,549 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:58:11,549 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 81 transitions. [2018-07-24 10:58:11,551 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-07-24 10:58:11,551 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:11,551 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:11,552 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:11,552 INFO L82 PathProgramCache]: Analyzing trace with hash 300263912, now seen corresponding path program 23 times [2018-07-24 10:58:11,552 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:11,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:11,553 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:11,553 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:11,553 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:11,564 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:11,873 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:11,873 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:11,873 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:11,880 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:11,881 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:11,901 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:58:11,901 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:11,903 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:11,916 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:11,916 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:12,549 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:12,569 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:12,569 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:12,585 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:12,585 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:12,704 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 24 check-sat command(s) [2018-07-24 10:58:12,704 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:12,707 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:12,716 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:12,716 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:12,737 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 0 proven. 805 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:12,738 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:12,738 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-07-24 10:58:12,738 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:12,738 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:58:12,739 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:58:12,739 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:58:12,740 INFO L87 Difference]: Start difference. First operand 81 states and 81 transitions. Second operand 26 states. [2018-07-24 10:58:12,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:12,845 INFO L93 Difference]: Finished difference Result 90 states and 90 transitions. [2018-07-24 10:58:12,846 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:58:12,846 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 80 [2018-07-24 10:58:12,846 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:12,847 INFO L225 Difference]: With dead ends: 90 [2018-07-24 10:58:12,847 INFO L226 Difference]: Without dead ends: 85 [2018-07-24 10:58:12,849 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 296 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:58:12,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 85 states. [2018-07-24 10:58:12,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 85 to 84. [2018-07-24 10:58:12,851 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-24 10:58:12,852 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 84 transitions. [2018-07-24 10:58:12,852 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 84 transitions. Word has length 80 [2018-07-24 10:58:12,852 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:12,852 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 84 transitions. [2018-07-24 10:58:12,853 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:58:12,853 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 84 transitions. [2018-07-24 10:58:12,853 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-24 10:58:12,853 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:12,854 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:12,854 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:12,854 INFO L82 PathProgramCache]: Analyzing trace with hash 1591212303, now seen corresponding path program 24 times [2018-07-24 10:58:12,854 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:12,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:12,855 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:12,855 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:12,855 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:12,861 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:13,454 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:13,454 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:13,455 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:13,462 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:13,462 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:13,487 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:58:13,488 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:13,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:13,502 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:13,503 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:14,306 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:14,327 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:14,327 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:14,342 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:14,342 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:14,490 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 25 check-sat command(s) [2018-07-24 10:58:14,490 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:14,493 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:14,503 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:14,503 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:14,522 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 0 proven. 876 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:14,523 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:14,523 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 52 [2018-07-24 10:58:14,523 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:14,524 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:58:14,524 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:58:14,525 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:58:14,525 INFO L87 Difference]: Start difference. First operand 84 states and 84 transitions. Second operand 27 states. [2018-07-24 10:58:14,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:14,610 INFO L93 Difference]: Finished difference Result 93 states and 93 transitions. [2018-07-24 10:58:14,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:58:14,611 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 83 [2018-07-24 10:58:14,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:14,612 INFO L225 Difference]: With dead ends: 93 [2018-07-24 10:58:14,612 INFO L226 Difference]: Without dead ends: 88 [2018-07-24 10:58:14,614 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 307 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:58:14,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-07-24 10:58:14,616 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 87. [2018-07-24 10:58:14,616 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-24 10:58:14,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 87 transitions. [2018-07-24 10:58:14,617 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 87 transitions. Word has length 83 [2018-07-24 10:58:14,617 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:14,617 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 87 transitions. [2018-07-24 10:58:14,617 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:58:14,617 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 87 transitions. [2018-07-24 10:58:14,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-07-24 10:58:14,618 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:14,618 INFO L353 BasicCegarLoop]: trace histogram [26, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:14,618 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:14,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1197407096, now seen corresponding path program 25 times [2018-07-24 10:58:14,618 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:14,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:14,619 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:14,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:14,619 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:14,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:15,016 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:15,016 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:15,016 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:15,024 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:15,024 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:15,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:15,040 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:15,053 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:15,053 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:15,877 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:15,896 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:15,897 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:15,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:15,912 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:15,944 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:15,948 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:15,958 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:15,958 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:16,001 INFO L134 CoverageAnalysis]: Checked inductivity of 950 backedges. 0 proven. 950 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:16,002 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:16,002 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 54 [2018-07-24 10:58:16,002 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:16,003 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:58:16,003 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:58:16,004 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:58:16,004 INFO L87 Difference]: Start difference. First operand 87 states and 87 transitions. Second operand 28 states. [2018-07-24 10:58:16,089 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:16,089 INFO L93 Difference]: Finished difference Result 96 states and 96 transitions. [2018-07-24 10:58:16,089 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:58:16,089 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 86 [2018-07-24 10:58:16,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:16,091 INFO L225 Difference]: With dead ends: 96 [2018-07-24 10:58:16,091 INFO L226 Difference]: Without dead ends: 91 [2018-07-24 10:58:16,092 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 370 GetRequests, 318 SyntacticMatches, 0 SemanticMatches, 52 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1431, Invalid=1431, Unknown=0, NotChecked=0, Total=2862 [2018-07-24 10:58:16,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-07-24 10:58:16,095 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-07-24 10:58:16,095 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-07-24 10:58:16,096 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 90 transitions. [2018-07-24 10:58:16,096 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 90 transitions. Word has length 86 [2018-07-24 10:58:16,096 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:16,096 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 90 transitions. [2018-07-24 10:58:16,096 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:58:16,096 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 90 transitions. [2018-07-24 10:58:16,097 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:58:16,097 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:16,097 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:16,097 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:16,097 INFO L82 PathProgramCache]: Analyzing trace with hash 594483823, now seen corresponding path program 26 times [2018-07-24 10:58:16,098 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:16,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:16,098 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:16,098 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:16,099 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:16,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:16,863 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:16,863 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:16,864 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:16,873 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:16,873 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:16,889 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:16,889 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:16,891 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:16,905 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:16,905 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:18,225 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:18,245 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:18,245 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:18,260 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:18,260 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:18,294 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:18,295 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:18,299 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:18,312 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:18,313 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:18,374 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 0 proven. 1027 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:18,378 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:18,379 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 56 [2018-07-24 10:58:18,379 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:18,379 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:58:18,379 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:58:18,380 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:58:18,381 INFO L87 Difference]: Start difference. First operand 90 states and 90 transitions. Second operand 29 states. [2018-07-24 10:58:18,521 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:18,521 INFO L93 Difference]: Finished difference Result 99 states and 99 transitions. [2018-07-24 10:58:18,522 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:58:18,523 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 89 [2018-07-24 10:58:18,523 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:18,523 INFO L225 Difference]: With dead ends: 99 [2018-07-24 10:58:18,523 INFO L226 Difference]: Without dead ends: 94 [2018-07-24 10:58:18,524 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 383 GetRequests, 329 SyntacticMatches, 0 SemanticMatches, 54 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1540, Invalid=1540, Unknown=0, NotChecked=0, Total=3080 [2018-07-24 10:58:18,525 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 94 states. [2018-07-24 10:58:18,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 94 to 93. [2018-07-24 10:58:18,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-07-24 10:58:18,527 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 93 transitions. [2018-07-24 10:58:18,527 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 93 transitions. Word has length 89 [2018-07-24 10:58:18,528 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:18,528 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 93 transitions. [2018-07-24 10:58:18,528 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:58:18,528 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 93 transitions. [2018-07-24 10:58:18,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-07-24 10:58:18,528 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:18,529 INFO L353 BasicCegarLoop]: trace histogram [28, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:18,529 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:18,529 INFO L82 PathProgramCache]: Analyzing trace with hash 668329768, now seen corresponding path program 27 times [2018-07-24 10:58:18,529 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:18,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:18,530 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:18,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:18,530 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:18,535 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:19,015 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:19,015 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:19,016 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:19,024 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:19,024 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:19,048 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-07-24 10:58:19,049 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:19,050 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:19,061 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:19,062 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:19,898 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:19,920 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:19,920 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:19,935 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:19,936 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:20,105 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 28 check-sat command(s) [2018-07-24 10:58:20,106 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:20,109 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:20,124 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:20,124 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:20,186 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 0 proven. 1107 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:20,187 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:20,188 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 30, 30, 30, 30] total 58 [2018-07-24 10:58:20,188 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:20,188 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:58:20,188 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:58:20,189 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:58:20,190 INFO L87 Difference]: Start difference. First operand 93 states and 93 transitions. Second operand 30 states. [2018-07-24 10:58:20,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:20,286 INFO L93 Difference]: Finished difference Result 102 states and 102 transitions. [2018-07-24 10:58:20,286 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-07-24 10:58:20,286 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 92 [2018-07-24 10:58:20,287 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:20,288 INFO L225 Difference]: With dead ends: 102 [2018-07-24 10:58:20,288 INFO L226 Difference]: Without dead ends: 97 [2018-07-24 10:58:20,289 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 396 GetRequests, 340 SyntacticMatches, 0 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=1653, Invalid=1653, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:58:20,289 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-07-24 10:58:20,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 96. [2018-07-24 10:58:20,292 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-07-24 10:58:20,292 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 96 transitions. [2018-07-24 10:58:20,292 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 96 transitions. Word has length 92 [2018-07-24 10:58:20,292 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:20,292 INFO L471 AbstractCegarLoop]: Abstraction has 96 states and 96 transitions. [2018-07-24 10:58:20,292 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:58:20,293 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 96 transitions. [2018-07-24 10:58:20,293 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-07-24 10:58:20,293 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:20,293 INFO L353 BasicCegarLoop]: trace histogram [29, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:20,293 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:20,293 INFO L82 PathProgramCache]: Analyzing trace with hash 1589621711, now seen corresponding path program 28 times [2018-07-24 10:58:20,293 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:20,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:20,294 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:20,294 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:20,294 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:20,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:21,847 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:21,848 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:21,848 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:21,857 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:21,857 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:21,873 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:21,874 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:21,876 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:21,890 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:21,891 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:22,902 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:22,922 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:22,922 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:22,938 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:22,938 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:22,977 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:22,977 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:22,980 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:22,991 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:22,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:23,063 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 0 proven. 1190 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:23,065 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:23,065 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 60 [2018-07-24 10:58:23,065 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:23,066 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:58:23,067 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:58:23,067 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:58:23,067 INFO L87 Difference]: Start difference. First operand 96 states and 96 transitions. Second operand 31 states. [2018-07-24 10:58:23,228 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:23,228 INFO L93 Difference]: Finished difference Result 105 states and 105 transitions. [2018-07-24 10:58:23,230 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:58:23,231 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 95 [2018-07-24 10:58:23,231 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:23,231 INFO L225 Difference]: With dead ends: 105 [2018-07-24 10:58:23,232 INFO L226 Difference]: Without dead ends: 100 [2018-07-24 10:58:23,233 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 351 SyntacticMatches, 0 SemanticMatches, 58 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1770, Invalid=1770, Unknown=0, NotChecked=0, Total=3540 [2018-07-24 10:58:23,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 100 states. [2018-07-24 10:58:23,237 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 100 to 99. [2018-07-24 10:58:23,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-24 10:58:23,238 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 99 transitions. [2018-07-24 10:58:23,238 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 99 transitions. Word has length 95 [2018-07-24 10:58:23,238 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:23,238 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 99 transitions. [2018-07-24 10:58:23,238 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:58:23,238 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 99 transitions. [2018-07-24 10:58:23,239 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-07-24 10:58:23,239 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:23,239 INFO L353 BasicCegarLoop]: trace histogram [30, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:23,239 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:23,240 INFO L82 PathProgramCache]: Analyzing trace with hash -1338093112, now seen corresponding path program 29 times [2018-07-24 10:58:23,240 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:23,240 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:23,241 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:23,241 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:23,241 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:23,247 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:23,904 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:23,904 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:23,905 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:23,923 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:23,923 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:23,947 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-07-24 10:58:23,947 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:23,950 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:23,967 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:23,967 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:25,832 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:25,852 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:25,852 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:25,869 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:25,869 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:26,056 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 30 check-sat command(s) [2018-07-24 10:58:26,056 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:26,060 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:26,074 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:26,074 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:26,102 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 0 proven. 1276 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:26,105 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:26,105 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 62 [2018-07-24 10:58:26,105 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:26,105 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:58:26,106 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:58:26,106 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:58:26,107 INFO L87 Difference]: Start difference. First operand 99 states and 99 transitions. Second operand 32 states. [2018-07-24 10:58:26,349 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:26,350 INFO L93 Difference]: Finished difference Result 108 states and 108 transitions. [2018-07-24 10:58:26,350 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:58:26,350 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 98 [2018-07-24 10:58:26,351 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:26,352 INFO L225 Difference]: With dead ends: 108 [2018-07-24 10:58:26,352 INFO L226 Difference]: Without dead ends: 103 [2018-07-24 10:58:26,353 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 422 GetRequests, 362 SyntacticMatches, 0 SemanticMatches, 60 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1891, Invalid=1891, Unknown=0, NotChecked=0, Total=3782 [2018-07-24 10:58:26,353 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103 states. [2018-07-24 10:58:26,356 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103 to 102. [2018-07-24 10:58:26,356 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:58:26,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 102 transitions. [2018-07-24 10:58:26,357 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 102 transitions. Word has length 98 [2018-07-24 10:58:26,357 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:26,357 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 102 transitions. [2018-07-24 10:58:26,357 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:58:26,357 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 102 transitions. [2018-07-24 10:58:26,358 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-07-24 10:58:26,358 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:26,358 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:26,358 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:26,359 INFO L82 PathProgramCache]: Analyzing trace with hash 1305462063, now seen corresponding path program 30 times [2018-07-24 10:58:26,359 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:26,359 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:26,360 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:26,360 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:26,360 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:26,366 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:26,961 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:26,962 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:26,962 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:26,969 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:26,970 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:26,997 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-07-24 10:58:26,997 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:27,000 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:27,013 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:27,013 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:28,031 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:28,051 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:28,051 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:28,067 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:28,067 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:28,263 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 31 check-sat command(s) [2018-07-24 10:58:28,263 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:28,267 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:28,282 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:28,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:28,320 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 0 proven. 1365 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:28,321 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:28,322 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 64 [2018-07-24 10:58:28,322 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:28,322 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:58:28,323 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:58:28,323 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:58:28,323 INFO L87 Difference]: Start difference. First operand 102 states and 102 transitions. Second operand 33 states. [2018-07-24 10:58:28,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:28,523 INFO L93 Difference]: Finished difference Result 111 states and 111 transitions. [2018-07-24 10:58:28,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:58:28,524 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 101 [2018-07-24 10:58:28,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:28,525 INFO L225 Difference]: With dead ends: 111 [2018-07-24 10:58:28,525 INFO L226 Difference]: Without dead ends: 106 [2018-07-24 10:58:28,526 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 435 GetRequests, 373 SyntacticMatches, 0 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=2016, Invalid=2016, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:58:28,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 106 states. [2018-07-24 10:58:28,529 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 106 to 105. [2018-07-24 10:58:28,530 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-07-24 10:58:28,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 105 transitions. [2018-07-24 10:58:28,530 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 105 transitions. Word has length 101 [2018-07-24 10:58:28,531 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:28,531 INFO L471 AbstractCegarLoop]: Abstraction has 105 states and 105 transitions. [2018-07-24 10:58:28,531 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:58:28,531 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 105 transitions. [2018-07-24 10:58:28,532 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-07-24 10:58:28,532 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:28,532 INFO L353 BasicCegarLoop]: trace histogram [32, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:28,532 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:28,532 INFO L82 PathProgramCache]: Analyzing trace with hash -1357626264, now seen corresponding path program 31 times [2018-07-24 10:58:28,532 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:28,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:28,533 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:28,533 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:28,533 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:28,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:29,789 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:29,789 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:29,789 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:29,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:29,799 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:29,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:29,817 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:29,831 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:29,832 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:31,108 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:31,128 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:31,128 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:31,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:31,143 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:31,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:31,184 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:31,200 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:31,201 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:31,268 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 0 proven. 1457 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:31,269 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:31,269 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 66 [2018-07-24 10:58:31,269 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:31,270 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:58:31,270 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:58:31,270 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:58:31,270 INFO L87 Difference]: Start difference. First operand 105 states and 105 transitions. Second operand 34 states. [2018-07-24 10:58:31,396 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:31,397 INFO L93 Difference]: Finished difference Result 114 states and 114 transitions. [2018-07-24 10:58:31,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:58:31,405 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 104 [2018-07-24 10:58:31,406 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:31,406 INFO L225 Difference]: With dead ends: 114 [2018-07-24 10:58:31,407 INFO L226 Difference]: Without dead ends: 109 [2018-07-24 10:58:31,407 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 384 SyntacticMatches, 0 SemanticMatches, 64 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2145, Invalid=2145, Unknown=0, NotChecked=0, Total=4290 [2018-07-24 10:58:31,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-07-24 10:58:31,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 108. [2018-07-24 10:58:31,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 108 states. [2018-07-24 10:58:31,411 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 108 states to 108 states and 108 transitions. [2018-07-24 10:58:31,411 INFO L78 Accepts]: Start accepts. Automaton has 108 states and 108 transitions. Word has length 104 [2018-07-24 10:58:31,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:31,411 INFO L471 AbstractCegarLoop]: Abstraction has 108 states and 108 transitions. [2018-07-24 10:58:31,411 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:58:31,411 INFO L276 IsEmpty]: Start isEmpty. Operand 108 states and 108 transitions. [2018-07-24 10:58:31,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 108 [2018-07-24 10:58:31,412 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:31,412 INFO L353 BasicCegarLoop]: trace histogram [33, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:31,412 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:31,413 INFO L82 PathProgramCache]: Analyzing trace with hash -786084209, now seen corresponding path program 32 times [2018-07-24 10:58:31,413 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:31,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:31,413 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:31,414 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:31,414 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:31,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:31,919 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:31,920 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:31,920 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:31,927 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:31,927 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:31,945 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:31,945 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:31,946 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:31,959 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:31,959 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:33,126 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:33,146 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:33,146 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:33,161 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:33,161 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:33,205 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:33,205 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:33,210 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:33,229 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:33,230 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:33,289 INFO L134 CoverageAnalysis]: Checked inductivity of 1552 backedges. 0 proven. 1552 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:33,290 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:33,291 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 68 [2018-07-24 10:58:33,291 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:33,291 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:58:33,292 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:58:33,292 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:58:33,293 INFO L87 Difference]: Start difference. First operand 108 states and 108 transitions. Second operand 35 states. [2018-07-24 10:58:33,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:33,619 INFO L93 Difference]: Finished difference Result 117 states and 117 transitions. [2018-07-24 10:58:33,619 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:58:33,619 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 107 [2018-07-24 10:58:33,620 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:33,621 INFO L225 Difference]: With dead ends: 117 [2018-07-24 10:58:33,621 INFO L226 Difference]: Without dead ends: 112 [2018-07-24 10:58:33,622 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 461 GetRequests, 395 SyntacticMatches, 0 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=2278, Invalid=2278, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 10:58:33,622 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-07-24 10:58:33,624 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-07-24 10:58:33,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-07-24 10:58:33,625 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 111 transitions. [2018-07-24 10:58:33,625 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 111 transitions. Word has length 107 [2018-07-24 10:58:33,625 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:33,625 INFO L471 AbstractCegarLoop]: Abstraction has 111 states and 111 transitions. [2018-07-24 10:58:33,625 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:58:33,625 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 111 transitions. [2018-07-24 10:58:33,626 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-07-24 10:58:33,626 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:33,626 INFO L353 BasicCegarLoop]: trace histogram [34, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:33,626 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:33,626 INFO L82 PathProgramCache]: Analyzing trace with hash 772914952, now seen corresponding path program 33 times [2018-07-24 10:58:33,626 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:33,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:33,627 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:33,627 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:33,627 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:33,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:34,398 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:34,399 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:34,399 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:34,407 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:34,407 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:34,436 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-07-24 10:58:34,437 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:34,438 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:34,454 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:34,454 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:35,813 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:35,834 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:35,834 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:35,850 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:35,850 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:36,078 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 34 check-sat command(s) [2018-07-24 10:58:36,078 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:36,082 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:36,094 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:36,095 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:36,114 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 0 proven. 1650 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:36,115 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:36,115 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 36, 36, 36, 36] total 70 [2018-07-24 10:58:36,115 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:36,116 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:58:36,116 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:58:36,116 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:58:36,116 INFO L87 Difference]: Start difference. First operand 111 states and 111 transitions. Second operand 36 states. [2018-07-24 10:58:36,330 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:36,330 INFO L93 Difference]: Finished difference Result 120 states and 120 transitions. [2018-07-24 10:58:36,330 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-24 10:58:36,331 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 110 [2018-07-24 10:58:36,331 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:36,332 INFO L225 Difference]: With dead ends: 120 [2018-07-24 10:58:36,332 INFO L226 Difference]: Without dead ends: 115 [2018-07-24 10:58:36,333 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 474 GetRequests, 406 SyntacticMatches, 0 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2415, Invalid=2415, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:58:36,333 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 115 states. [2018-07-24 10:58:36,336 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 115 to 114. [2018-07-24 10:58:36,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-07-24 10:58:36,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 114 transitions. [2018-07-24 10:58:36,337 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 114 transitions. Word has length 110 [2018-07-24 10:58:36,337 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:36,337 INFO L471 AbstractCegarLoop]: Abstraction has 114 states and 114 transitions. [2018-07-24 10:58:36,337 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:58:36,337 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 114 transitions. [2018-07-24 10:58:36,338 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-07-24 10:58:36,338 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:36,338 INFO L353 BasicCegarLoop]: trace histogram [35, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:36,339 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:36,339 INFO L82 PathProgramCache]: Analyzing trace with hash -859418641, now seen corresponding path program 34 times [2018-07-24 10:58:36,339 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:36,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:36,340 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:36,340 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:36,340 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:36,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:36,909 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:36,910 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:36,910 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:36,917 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:36,917 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:36,936 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:36,936 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:36,938 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:36,952 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:36,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:38,481 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:38,501 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:38,501 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:38,516 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:38,516 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:38,562 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:38,562 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:38,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:38,580 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:38,580 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:38,613 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 0 proven. 1751 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:38,616 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:38,617 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 72 [2018-07-24 10:58:38,617 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:38,617 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:58:38,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:58:38,618 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:58:38,619 INFO L87 Difference]: Start difference. First operand 114 states and 114 transitions. Second operand 37 states. [2018-07-24 10:58:38,786 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:38,786 INFO L93 Difference]: Finished difference Result 123 states and 123 transitions. [2018-07-24 10:58:38,787 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:58:38,788 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 113 [2018-07-24 10:58:38,788 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:38,789 INFO L225 Difference]: With dead ends: 123 [2018-07-24 10:58:38,789 INFO L226 Difference]: Without dead ends: 118 [2018-07-24 10:58:38,790 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 487 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 70 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=2556, Invalid=2556, Unknown=0, NotChecked=0, Total=5112 [2018-07-24 10:58:38,790 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 118 states. [2018-07-24 10:58:38,792 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 118 to 117. [2018-07-24 10:58:38,792 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-07-24 10:58:38,793 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 117 transitions. [2018-07-24 10:58:38,793 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 117 transitions. Word has length 113 [2018-07-24 10:58:38,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:38,794 INFO L471 AbstractCegarLoop]: Abstraction has 117 states and 117 transitions. [2018-07-24 10:58:38,794 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:58:38,794 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 117 transitions. [2018-07-24 10:58:38,794 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-07-24 10:58:38,795 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:38,795 INFO L353 BasicCegarLoop]: trace histogram [36, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:38,795 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:38,795 INFO L82 PathProgramCache]: Analyzing trace with hash -2089762392, now seen corresponding path program 35 times [2018-07-24 10:58:38,795 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:38,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:38,796 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:38,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:38,798 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:38,804 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:39,584 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:39,585 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:39,585 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:39,592 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:39,592 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:39,620 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-07-24 10:58:39,621 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:39,624 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:39,638 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:39,638 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:41,091 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:41,111 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:41,111 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:41,126 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:41,126 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:41,344 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 36 check-sat command(s) [2018-07-24 10:58:41,344 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:41,348 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:41,367 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:41,368 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:41,412 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 0 proven. 1855 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:41,413 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:41,414 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 74 [2018-07-24 10:58:41,414 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:41,414 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:58:41,414 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:58:41,415 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:58:41,415 INFO L87 Difference]: Start difference. First operand 117 states and 117 transitions. Second operand 38 states. [2018-07-24 10:58:41,528 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:41,528 INFO L93 Difference]: Finished difference Result 126 states and 126 transitions. [2018-07-24 10:58:41,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:58:41,529 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 116 [2018-07-24 10:58:41,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:41,530 INFO L225 Difference]: With dead ends: 126 [2018-07-24 10:58:41,530 INFO L226 Difference]: Without dead ends: 121 [2018-07-24 10:58:41,531 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 500 GetRequests, 428 SyntacticMatches, 0 SemanticMatches, 72 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2701, Invalid=2701, Unknown=0, NotChecked=0, Total=5402 [2018-07-24 10:58:41,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 121 states. [2018-07-24 10:58:41,533 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 121 to 120. [2018-07-24 10:58:41,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 120 states. [2018-07-24 10:58:41,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 120 states to 120 states and 120 transitions. [2018-07-24 10:58:41,534 INFO L78 Accepts]: Start accepts. Automaton has 120 states and 120 transitions. Word has length 116 [2018-07-24 10:58:41,534 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:41,534 INFO L471 AbstractCegarLoop]: Abstraction has 120 states and 120 transitions. [2018-07-24 10:58:41,534 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:58:41,534 INFO L276 IsEmpty]: Start isEmpty. Operand 120 states and 120 transitions. [2018-07-24 10:58:41,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 120 [2018-07-24 10:58:41,535 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:41,535 INFO L353 BasicCegarLoop]: trace histogram [37, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:41,535 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:41,535 INFO L82 PathProgramCache]: Analyzing trace with hash -2009544369, now seen corresponding path program 36 times [2018-07-24 10:58:41,536 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:41,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:41,536 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:41,536 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:41,536 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:41,542 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:42,246 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:42,246 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:42,246 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:42,253 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:42,253 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:42,284 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-07-24 10:58:42,284 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:42,287 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:42,301 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:42,302 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:43,800 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:43,820 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:43,820 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:43,835 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:58:43,835 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:58:44,094 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 37 check-sat command(s) [2018-07-24 10:58:44,094 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:44,098 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:44,119 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:44,119 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:44,199 INFO L134 CoverageAnalysis]: Checked inductivity of 1962 backedges. 0 proven. 1962 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:44,201 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:44,201 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 76 [2018-07-24 10:58:44,201 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:44,202 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:58:44,202 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:58:44,203 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:58:44,203 INFO L87 Difference]: Start difference. First operand 120 states and 120 transitions. Second operand 39 states. [2018-07-24 10:58:44,421 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:44,422 INFO L93 Difference]: Finished difference Result 129 states and 129 transitions. [2018-07-24 10:58:44,428 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:58:44,429 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 119 [2018-07-24 10:58:44,429 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:44,430 INFO L225 Difference]: With dead ends: 129 [2018-07-24 10:58:44,430 INFO L226 Difference]: Without dead ends: 124 [2018-07-24 10:58:44,430 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 439 SyntacticMatches, 0 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=2850, Invalid=2850, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:58:44,431 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 124 states. [2018-07-24 10:58:44,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 124 to 123. [2018-07-24 10:58:44,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 123 states. [2018-07-24 10:58:44,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 123 states to 123 states and 123 transitions. [2018-07-24 10:58:44,434 INFO L78 Accepts]: Start accepts. Automaton has 123 states and 123 transitions. Word has length 119 [2018-07-24 10:58:44,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:44,434 INFO L471 AbstractCegarLoop]: Abstraction has 123 states and 123 transitions. [2018-07-24 10:58:44,434 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:58:44,434 INFO L276 IsEmpty]: Start isEmpty. Operand 123 states and 123 transitions. [2018-07-24 10:58:44,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 123 [2018-07-24 10:58:44,435 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:44,435 INFO L353 BasicCegarLoop]: trace histogram [38, 37, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:44,435 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:44,436 INFO L82 PathProgramCache]: Analyzing trace with hash -236237752, now seen corresponding path program 37 times [2018-07-24 10:58:44,436 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:44,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:44,437 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:44,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:44,437 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:44,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:45,137 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:45,137 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:45,137 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:45,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:45,144 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:45,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:45,177 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:45,199 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:45,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:47,093 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:47,113 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:47,113 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:47,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:47,129 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:58:47,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:47,177 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:47,199 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:47,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:47,253 INFO L134 CoverageAnalysis]: Checked inductivity of 2072 backedges. 0 proven. 2072 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:47,254 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:47,254 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 78 [2018-07-24 10:58:47,254 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:47,254 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:58:47,255 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:58:47,255 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:58:47,256 INFO L87 Difference]: Start difference. First operand 123 states and 123 transitions. Second operand 40 states. [2018-07-24 10:58:47,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:47,399 INFO L93 Difference]: Finished difference Result 132 states and 132 transitions. [2018-07-24 10:58:47,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 10:58:47,400 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 122 [2018-07-24 10:58:47,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:47,401 INFO L225 Difference]: With dead ends: 132 [2018-07-24 10:58:47,401 INFO L226 Difference]: Without dead ends: 127 [2018-07-24 10:58:47,402 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 526 GetRequests, 450 SyntacticMatches, 0 SemanticMatches, 76 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=3003, Invalid=3003, Unknown=0, NotChecked=0, Total=6006 [2018-07-24 10:58:47,402 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-07-24 10:58:47,405 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 126. [2018-07-24 10:58:47,405 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 126 states. [2018-07-24 10:58:47,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126 states to 126 states and 126 transitions. [2018-07-24 10:58:47,406 INFO L78 Accepts]: Start accepts. Automaton has 126 states and 126 transitions. Word has length 122 [2018-07-24 10:58:47,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:47,406 INFO L471 AbstractCegarLoop]: Abstraction has 126 states and 126 transitions. [2018-07-24 10:58:47,406 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:58:47,406 INFO L276 IsEmpty]: Start isEmpty. Operand 126 states and 126 transitions. [2018-07-24 10:58:47,407 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 126 [2018-07-24 10:58:47,407 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:47,407 INFO L353 BasicCegarLoop]: trace histogram [39, 38, 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:47,407 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:47,408 INFO L82 PathProgramCache]: Analyzing trace with hash 243448495, now seen corresponding path program 38 times [2018-07-24 10:58:47,408 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:47,408 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:47,408 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:58:47,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:47,409 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:47,415 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:48,150 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:48,150 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:48,150 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:48,158 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:48,158 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:48,175 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:48,175 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:48,178 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:48,201 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:48,201 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:50,304 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:50,324 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:50,324 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:50,340 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:58:50,340 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:50,391 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:58:50,392 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:50,396 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:50,413 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:50,413 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:50,431 INFO L134 CoverageAnalysis]: Checked inductivity of 2185 backedges. 0 proven. 2185 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:50,432 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:50,433 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 80 [2018-07-24 10:58:50,433 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:50,433 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:58:50,433 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:58:50,434 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:58:50,434 INFO L87 Difference]: Start difference. First operand 126 states and 126 transitions. Second operand 41 states. [2018-07-24 10:58:50,597 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:50,598 INFO L93 Difference]: Finished difference Result 135 states and 135 transitions. [2018-07-24 10:58:50,599 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:58:50,599 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 125 [2018-07-24 10:58:50,600 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:50,600 INFO L225 Difference]: With dead ends: 135 [2018-07-24 10:58:50,600 INFO L226 Difference]: Without dead ends: 130 [2018-07-24 10:58:50,601 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 539 GetRequests, 461 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:58:50,601 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 130 states. [2018-07-24 10:58:50,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 130 to 129. [2018-07-24 10:58:50,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-07-24 10:58:50,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 129 transitions. [2018-07-24 10:58:50,605 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 129 transitions. Word has length 125 [2018-07-24 10:58:50,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:50,605 INFO L471 AbstractCegarLoop]: Abstraction has 129 states and 129 transitions. [2018-07-24 10:58:50,606 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:58:50,606 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 129 transitions. [2018-07-24 10:58:50,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 129 [2018-07-24 10:58:50,606 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:50,607 INFO L353 BasicCegarLoop]: trace histogram [40, 39, 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:50,607 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:50,607 INFO L82 PathProgramCache]: Analyzing trace with hash 1220239080, now seen corresponding path program 39 times [2018-07-24 10:58:50,607 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:50,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:50,608 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:50,608 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:50,608 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:50,614 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:51,281 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:51,282 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:51,282 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:51,289 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:51,289 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:51,334 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-07-24 10:58:51,334 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:51,336 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:51,352 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:51,352 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:53,082 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:53,104 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:53,104 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:53,120 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:58:53,120 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:58:53,413 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 40 check-sat command(s) [2018-07-24 10:58:53,413 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:53,417 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:53,440 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:53,440 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:53,482 INFO L134 CoverageAnalysis]: Checked inductivity of 2301 backedges. 0 proven. 2301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:53,483 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:53,483 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 42, 42, 42, 42] total 82 [2018-07-24 10:58:53,484 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:53,486 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:58:53,487 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:58:53,487 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:58:53,488 INFO L87 Difference]: Start difference. First operand 129 states and 129 transitions. Second operand 42 states. [2018-07-24 10:58:54,042 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:54,042 INFO L93 Difference]: Finished difference Result 138 states and 138 transitions. [2018-07-24 10:58:54,042 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-07-24 10:58:54,043 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 128 [2018-07-24 10:58:54,043 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:54,044 INFO L225 Difference]: With dead ends: 138 [2018-07-24 10:58:54,044 INFO L226 Difference]: Without dead ends: 133 [2018-07-24 10:58:54,045 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 552 GetRequests, 472 SyntacticMatches, 0 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=3321, Invalid=3321, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:58:54,045 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133 states. [2018-07-24 10:58:54,048 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133 to 132. [2018-07-24 10:58:54,048 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 132 states. [2018-07-24 10:58:54,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 132 states to 132 states and 132 transitions. [2018-07-24 10:58:54,049 INFO L78 Accepts]: Start accepts. Automaton has 132 states and 132 transitions. Word has length 128 [2018-07-24 10:58:54,050 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:54,050 INFO L471 AbstractCegarLoop]: Abstraction has 132 states and 132 transitions. [2018-07-24 10:58:54,050 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:58:54,050 INFO L276 IsEmpty]: Start isEmpty. Operand 132 states and 132 transitions. [2018-07-24 10:58:54,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 132 [2018-07-24 10:58:54,051 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:54,051 INFO L353 BasicCegarLoop]: trace histogram [41, 40, 40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:54,051 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:54,051 INFO L82 PathProgramCache]: Analyzing trace with hash -1909840881, now seen corresponding path program 40 times [2018-07-24 10:58:54,051 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:54,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:54,052 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:54,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:54,052 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:54,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:55,108 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:55,108 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:55,108 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:55,115 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:55,115 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:55,141 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:55,142 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:55,144 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:55,167 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:55,168 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:56,948 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:56,969 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:56,969 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:58:56,985 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:58:56,985 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:58:57,037 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:58:57,037 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:57,041 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:57,063 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:57,063 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:58:57,137 INFO L134 CoverageAnalysis]: Checked inductivity of 2420 backedges. 0 proven. 2420 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:57,138 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:58:57,139 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 84 [2018-07-24 10:58:57,139 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:58:57,140 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:58:57,140 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:58:57,141 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:58:57,141 INFO L87 Difference]: Start difference. First operand 132 states and 132 transitions. Second operand 43 states. [2018-07-24 10:58:57,586 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:58:57,586 INFO L93 Difference]: Finished difference Result 141 states and 141 transitions. [2018-07-24 10:58:57,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:58:57,586 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 131 [2018-07-24 10:58:57,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:58:57,591 INFO L225 Difference]: With dead ends: 141 [2018-07-24 10:58:57,591 INFO L226 Difference]: Without dead ends: 136 [2018-07-24 10:58:57,592 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 565 GetRequests, 483 SyntacticMatches, 0 SemanticMatches, 82 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=3486, Invalid=3486, Unknown=0, NotChecked=0, Total=6972 [2018-07-24 10:58:57,592 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 136 states. [2018-07-24 10:58:57,595 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 136 to 135. [2018-07-24 10:58:57,595 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 135 states. [2018-07-24 10:58:57,595 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 135 states to 135 states and 135 transitions. [2018-07-24 10:58:57,596 INFO L78 Accepts]: Start accepts. Automaton has 135 states and 135 transitions. Word has length 131 [2018-07-24 10:58:57,596 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:58:57,596 INFO L471 AbstractCegarLoop]: Abstraction has 135 states and 135 transitions. [2018-07-24 10:58:57,596 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:58:57,596 INFO L276 IsEmpty]: Start isEmpty. Operand 135 states and 135 transitions. [2018-07-24 10:58:57,597 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-07-24 10:58:57,597 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:58:57,597 INFO L353 BasicCegarLoop]: trace histogram [42, 41, 41, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:58:57,597 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:58:57,598 INFO L82 PathProgramCache]: Analyzing trace with hash -2086995576, now seen corresponding path program 41 times [2018-07-24 10:58:57,598 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:58:57,598 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:57,599 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:58:57,599 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:58:57,599 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:58:57,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:58:58,383 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:58,383 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:58:58,383 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:58:58,392 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:58:58,393 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:58:58,426 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-07-24 10:58:58,426 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:58:58,428 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:58:58,452 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:58:58,452 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:00,874 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:00,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:00,896 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:00,912 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:59:00,912 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:01,183 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 42 check-sat command(s) [2018-07-24 10:59:01,183 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:01,187 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:01,202 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:01,202 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:01,220 INFO L134 CoverageAnalysis]: Checked inductivity of 2542 backedges. 0 proven. 2542 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:01,221 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:01,221 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 86 [2018-07-24 10:59:01,221 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:01,222 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:59:01,222 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:59:01,222 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:59:01,223 INFO L87 Difference]: Start difference. First operand 135 states and 135 transitions. Second operand 44 states. [2018-07-24 10:59:01,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:01,874 INFO L93 Difference]: Finished difference Result 144 states and 144 transitions. [2018-07-24 10:59:01,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-24 10:59:01,876 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 134 [2018-07-24 10:59:01,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:01,877 INFO L225 Difference]: With dead ends: 144 [2018-07-24 10:59:01,878 INFO L226 Difference]: Without dead ends: 139 [2018-07-24 10:59:01,878 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 578 GetRequests, 494 SyntacticMatches, 0 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:59:01,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-07-24 10:59:01,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 138. [2018-07-24 10:59:01,882 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 138 states. [2018-07-24 10:59:01,883 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 138 states to 138 states and 138 transitions. [2018-07-24 10:59:01,883 INFO L78 Accepts]: Start accepts. Automaton has 138 states and 138 transitions. Word has length 134 [2018-07-24 10:59:01,884 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:01,884 INFO L471 AbstractCegarLoop]: Abstraction has 138 states and 138 transitions. [2018-07-24 10:59:01,884 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:59:01,884 INFO L276 IsEmpty]: Start isEmpty. Operand 138 states and 138 transitions. [2018-07-24 10:59:01,885 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 138 [2018-07-24 10:59:01,885 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:01,885 INFO L353 BasicCegarLoop]: trace histogram [43, 42, 42, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:01,885 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:01,886 INFO L82 PathProgramCache]: Analyzing trace with hash -1187707537, now seen corresponding path program 42 times [2018-07-24 10:59:01,886 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:01,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:01,887 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:01,887 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:01,887 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:01,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:02,775 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:02,775 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:02,775 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:02,784 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:59:02,784 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:59:02,822 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-07-24 10:59:02,822 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:02,824 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:02,842 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:02,843 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:05,020 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:05,041 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:05,041 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:05,056 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:59:05,057 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:59:05,387 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 43 check-sat command(s) [2018-07-24 10:59:05,388 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:05,392 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:05,410 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:05,410 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:05,434 INFO L134 CoverageAnalysis]: Checked inductivity of 2667 backedges. 0 proven. 2667 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:05,435 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:05,435 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 88 [2018-07-24 10:59:05,436 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:05,436 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:59:05,436 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:59:05,437 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:59:05,437 INFO L87 Difference]: Start difference. First operand 138 states and 138 transitions. Second operand 45 states. [2018-07-24 10:59:05,605 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:05,606 INFO L93 Difference]: Finished difference Result 147 states and 147 transitions. [2018-07-24 10:59:05,606 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-24 10:59:05,606 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 137 [2018-07-24 10:59:05,606 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:05,607 INFO L225 Difference]: With dead ends: 147 [2018-07-24 10:59:05,607 INFO L226 Difference]: Without dead ends: 142 [2018-07-24 10:59:05,608 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 591 GetRequests, 505 SyntacticMatches, 0 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=3828, Invalid=3828, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:59:05,608 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 142 states. [2018-07-24 10:59:05,610 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 142 to 141. [2018-07-24 10:59:05,611 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 141 states. [2018-07-24 10:59:05,611 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 141 states to 141 states and 141 transitions. [2018-07-24 10:59:05,611 INFO L78 Accepts]: Start accepts. Automaton has 141 states and 141 transitions. Word has length 137 [2018-07-24 10:59:05,612 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:05,612 INFO L471 AbstractCegarLoop]: Abstraction has 141 states and 141 transitions. [2018-07-24 10:59:05,612 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:59:05,612 INFO L276 IsEmpty]: Start isEmpty. Operand 141 states and 141 transitions. [2018-07-24 10:59:05,613 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 141 [2018-07-24 10:59:05,613 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:05,613 INFO L353 BasicCegarLoop]: trace histogram [44, 43, 43, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:05,613 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:05,613 INFO L82 PathProgramCache]: Analyzing trace with hash 1791237160, now seen corresponding path program 43 times [2018-07-24 10:59:05,613 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:05,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:05,614 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:05,614 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:05,614 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:05,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:06,637 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:06,638 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:06,638 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:06,646 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:59:06,646 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:59:06,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:06,670 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:06,705 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:06,705 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:08,762 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:08,782 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:08,782 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:08,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:59:08,798 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:59:08,846 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:08,850 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:08,869 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:08,869 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:08,896 INFO L134 CoverageAnalysis]: Checked inductivity of 2795 backedges. 0 proven. 2795 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (87)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:59:08,897 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:08,898 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 90 [2018-07-24 10:59:08,898 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:08,898 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-24 10:59:08,899 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-24 10:59:08,899 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:59:08,899 INFO L87 Difference]: Start difference. First operand 141 states and 141 transitions. Second operand 46 states. [2018-07-24 10:59:09,103 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:09,103 INFO L93 Difference]: Finished difference Result 150 states and 150 transitions. [2018-07-24 10:59:09,103 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-07-24 10:59:09,103 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 140 [2018-07-24 10:59:09,104 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:09,104 INFO L225 Difference]: With dead ends: 150 [2018-07-24 10:59:09,104 INFO L226 Difference]: Without dead ends: 145 [2018-07-24 10:59:09,105 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 604 GetRequests, 516 SyntacticMatches, 0 SemanticMatches, 88 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=4005, Invalid=4005, Unknown=0, NotChecked=0, Total=8010 [2018-07-24 10:59:09,106 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 145 states. [2018-07-24 10:59:09,108 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 145 to 144. [2018-07-24 10:59:09,108 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 144 states. [2018-07-24 10:59:09,108 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 144 states to 144 states and 144 transitions. [2018-07-24 10:59:09,108 INFO L78 Accepts]: Start accepts. Automaton has 144 states and 144 transitions. Word has length 140 [2018-07-24 10:59:09,109 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:09,109 INFO L471 AbstractCegarLoop]: Abstraction has 144 states and 144 transitions. [2018-07-24 10:59:09,109 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-24 10:59:09,109 INFO L276 IsEmpty]: Start isEmpty. Operand 144 states and 144 transitions. [2018-07-24 10:59:09,109 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 144 [2018-07-24 10:59:09,109 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:09,110 INFO L353 BasicCegarLoop]: trace histogram [45, 44, 44, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:09,110 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:09,110 INFO L82 PathProgramCache]: Analyzing trace with hash 623468239, now seen corresponding path program 44 times [2018-07-24 10:59:09,110 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:09,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:09,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:59:09,111 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:09,111 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:09,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:10,618 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:10,619 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:10,619 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:10,629 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:59:10,629 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:10,654 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:59:10,654 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:10,656 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:10,675 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:10,675 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:12,844 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:12,865 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:12,865 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:12,880 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:59:12,880 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:12,932 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:59:12,932 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:12,936 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:12,955 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:12,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:13,007 INFO L134 CoverageAnalysis]: Checked inductivity of 2926 backedges. 0 proven. 2926 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:13,008 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:13,009 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 92 [2018-07-24 10:59:13,009 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:13,009 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-24 10:59:13,009 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-24 10:59:13,010 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:59:13,010 INFO L87 Difference]: Start difference. First operand 144 states and 144 transitions. Second operand 47 states. [2018-07-24 10:59:13,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:13,671 INFO L93 Difference]: Finished difference Result 153 states and 153 transitions. [2018-07-24 10:59:13,671 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:59:13,671 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 143 [2018-07-24 10:59:13,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:13,672 INFO L225 Difference]: With dead ends: 153 [2018-07-24 10:59:13,673 INFO L226 Difference]: Without dead ends: 148 [2018-07-24 10:59:13,673 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 617 GetRequests, 527 SyntacticMatches, 0 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:59:13,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 148 states. [2018-07-24 10:59:13,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 148 to 147. [2018-07-24 10:59:13,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-07-24 10:59:13,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 147 transitions. [2018-07-24 10:59:13,677 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 147 transitions. Word has length 143 [2018-07-24 10:59:13,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:13,678 INFO L471 AbstractCegarLoop]: Abstraction has 147 states and 147 transitions. [2018-07-24 10:59:13,678 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-24 10:59:13,678 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 147 transitions. [2018-07-24 10:59:13,678 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-07-24 10:59:13,679 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:13,679 INFO L353 BasicCegarLoop]: trace histogram [46, 45, 45, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:13,679 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:13,679 INFO L82 PathProgramCache]: Analyzing trace with hash 854640328, now seen corresponding path program 45 times [2018-07-24 10:59:13,679 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:13,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:13,680 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:13,680 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:13,680 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:13,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:14,566 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:14,566 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:14,566 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:14,574 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:59:14,574 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:59:14,615 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-07-24 10:59:14,616 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:14,618 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:14,638 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:14,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:17,192 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:17,212 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:17,212 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:17,227 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:59:17,228 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:59:17,589 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 46 check-sat command(s) [2018-07-24 10:59:17,590 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:17,594 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:17,614 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:17,614 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:17,635 INFO L134 CoverageAnalysis]: Checked inductivity of 3060 backedges. 0 proven. 3060 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:17,636 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:17,637 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 48, 48, 48, 48] total 94 [2018-07-24 10:59:17,637 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:17,637 INFO L450 AbstractCegarLoop]: Interpolant automaton has 48 states [2018-07-24 10:59:17,637 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 48 interpolants. [2018-07-24 10:59:17,638 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:59:17,638 INFO L87 Difference]: Start difference. First operand 147 states and 147 transitions. Second operand 48 states. [2018-07-24 10:59:17,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:17,785 INFO L93 Difference]: Finished difference Result 156 states and 156 transitions. [2018-07-24 10:59:17,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 48 states. [2018-07-24 10:59:17,786 INFO L78 Accepts]: Start accepts. Automaton has 48 states. Word has length 146 [2018-07-24 10:59:17,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:17,787 INFO L225 Difference]: With dead ends: 156 [2018-07-24 10:59:17,787 INFO L226 Difference]: Without dead ends: 151 [2018-07-24 10:59:17,788 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 630 GetRequests, 538 SyntacticMatches, 0 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=4371, Invalid=4371, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:59:17,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 151 states. [2018-07-24 10:59:17,790 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 151 to 150. [2018-07-24 10:59:17,790 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 150 states. [2018-07-24 10:59:17,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 150 states to 150 states and 150 transitions. [2018-07-24 10:59:17,791 INFO L78 Accepts]: Start accepts. Automaton has 150 states and 150 transitions. Word has length 146 [2018-07-24 10:59:17,791 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:17,791 INFO L471 AbstractCegarLoop]: Abstraction has 150 states and 150 transitions. [2018-07-24 10:59:17,791 INFO L472 AbstractCegarLoop]: Interpolant automaton has 48 states. [2018-07-24 10:59:17,791 INFO L276 IsEmpty]: Start isEmpty. Operand 150 states and 150 transitions. [2018-07-24 10:59:17,792 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 150 [2018-07-24 10:59:17,792 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:17,792 INFO L353 BasicCegarLoop]: trace histogram [47, 46, 46, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:17,792 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:17,792 INFO L82 PathProgramCache]: Analyzing trace with hash -1425199057, now seen corresponding path program 46 times [2018-07-24 10:59:17,793 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:17,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:17,793 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:17,793 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:17,793 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:17,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:18,801 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:18,801 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:18,801 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:18,818 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:59:18,818 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:59:18,840 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:59:18,840 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:18,843 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:18,864 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:18,864 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:21,531 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:21,551 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:21,551 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:21,566 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:59:21,566 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:59:21,624 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:59:21,624 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:21,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:21,649 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:21,650 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:21,691 INFO L134 CoverageAnalysis]: Checked inductivity of 3197 backedges. 0 proven. 3197 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:21,692 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:21,692 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 96 [2018-07-24 10:59:21,692 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:21,692 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:59:21,693 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:59:21,693 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:59:21,693 INFO L87 Difference]: Start difference. First operand 150 states and 150 transitions. Second operand 49 states. [2018-07-24 10:59:21,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:21,839 INFO L93 Difference]: Finished difference Result 159 states and 159 transitions. [2018-07-24 10:59:21,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:59:21,839 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 149 [2018-07-24 10:59:21,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:21,841 INFO L225 Difference]: With dead ends: 159 [2018-07-24 10:59:21,841 INFO L226 Difference]: Without dead ends: 154 [2018-07-24 10:59:21,842 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 643 GetRequests, 549 SyntacticMatches, 0 SemanticMatches, 94 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.6s TimeCoverageRelationStatistics Valid=4560, Invalid=4560, Unknown=0, NotChecked=0, Total=9120 [2018-07-24 10:59:21,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 154 states. [2018-07-24 10:59:21,844 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 154 to 153. [2018-07-24 10:59:21,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 153 states. [2018-07-24 10:59:21,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 153 states to 153 states and 153 transitions. [2018-07-24 10:59:21,845 INFO L78 Accepts]: Start accepts. Automaton has 153 states and 153 transitions. Word has length 149 [2018-07-24 10:59:21,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:21,846 INFO L471 AbstractCegarLoop]: Abstraction has 153 states and 153 transitions. [2018-07-24 10:59:21,846 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-24 10:59:21,846 INFO L276 IsEmpty]: Start isEmpty. Operand 153 states and 153 transitions. [2018-07-24 10:59:21,847 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-07-24 10:59:21,847 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:21,847 INFO L353 BasicCegarLoop]: trace histogram [48, 47, 47, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:21,847 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:21,847 INFO L82 PathProgramCache]: Analyzing trace with hash 492501352, now seen corresponding path program 47 times [2018-07-24 10:59:21,847 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:21,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:21,848 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:21,848 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:21,848 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:21,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:22,790 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:22,791 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:22,791 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:22,798 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:59:22,798 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:22,836 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-07-24 10:59:22,836 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:22,839 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:22,860 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:22,860 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:25,463 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:25,483 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:25,483 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:25,499 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:59:25,499 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:25,846 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 48 check-sat command(s) [2018-07-24 10:59:25,846 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:25,850 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:25,872 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:25,873 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:25,904 INFO L134 CoverageAnalysis]: Checked inductivity of 3337 backedges. 0 proven. 3337 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:25,905 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:25,906 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 98 [2018-07-24 10:59:25,906 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:25,906 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-24 10:59:25,907 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-24 10:59:25,907 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:59:25,907 INFO L87 Difference]: Start difference. First operand 153 states and 153 transitions. Second operand 50 states. [2018-07-24 10:59:26,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:26,055 INFO L93 Difference]: Finished difference Result 162 states and 162 transitions. [2018-07-24 10:59:26,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-07-24 10:59:26,055 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 152 [2018-07-24 10:59:26,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:26,056 INFO L225 Difference]: With dead ends: 162 [2018-07-24 10:59:26,056 INFO L226 Difference]: Without dead ends: 157 [2018-07-24 10:59:26,058 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 656 GetRequests, 560 SyntacticMatches, 0 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:59:26,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-07-24 10:59:26,061 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 156. [2018-07-24 10:59:26,061 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 156 states. [2018-07-24 10:59:26,062 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 156 states to 156 states and 156 transitions. [2018-07-24 10:59:26,062 INFO L78 Accepts]: Start accepts. Automaton has 156 states and 156 transitions. Word has length 152 [2018-07-24 10:59:26,062 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:26,062 INFO L471 AbstractCegarLoop]: Abstraction has 156 states and 156 transitions. [2018-07-24 10:59:26,063 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-24 10:59:26,063 INFO L276 IsEmpty]: Start isEmpty. Operand 156 states and 156 transitions. [2018-07-24 10:59:26,063 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 156 [2018-07-24 10:59:26,064 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:26,064 INFO L353 BasicCegarLoop]: trace histogram [49, 48, 48, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:26,064 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:26,064 INFO L82 PathProgramCache]: Analyzing trace with hash -949585521, now seen corresponding path program 48 times [2018-07-24 10:59:26,064 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:26,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:26,065 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:26,065 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:26,065 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:26,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:27,093 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:27,093 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:27,093 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:27,101 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:59:27,101 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:59:27,147 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-07-24 10:59:27,147 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:27,149 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:27,171 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:27,171 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:29,660 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:29,681 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:29,682 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:29,703 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:59:29,703 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:59:30,115 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 49 check-sat command(s) [2018-07-24 10:59:30,115 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:30,119 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:30,140 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:30,140 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:30,170 INFO L134 CoverageAnalysis]: Checked inductivity of 3480 backedges. 0 proven. 3480 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:30,171 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:30,171 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 100 [2018-07-24 10:59:30,171 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:30,172 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:59:30,172 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:59:30,173 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2018-07-24 10:59:30,173 INFO L87 Difference]: Start difference. First operand 156 states and 156 transitions. Second operand 51 states. [2018-07-24 10:59:30,442 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:30,442 INFO L93 Difference]: Finished difference Result 165 states and 165 transitions. [2018-07-24 10:59:30,442 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:59:30,442 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 155 [2018-07-24 10:59:30,442 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:30,443 INFO L225 Difference]: With dead ends: 165 [2018-07-24 10:59:30,443 INFO L226 Difference]: Without dead ends: 160 [2018-07-24 10:59:30,444 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 669 GetRequests, 571 SyntacticMatches, 0 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=4950, Invalid=4950, Unknown=0, NotChecked=0, Total=9900 [2018-07-24 10:59:30,444 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-07-24 10:59:30,446 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 159. [2018-07-24 10:59:30,446 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-07-24 10:59:30,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 159 transitions. [2018-07-24 10:59:30,447 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 159 transitions. Word has length 155 [2018-07-24 10:59:30,447 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:30,447 INFO L471 AbstractCegarLoop]: Abstraction has 159 states and 159 transitions. [2018-07-24 10:59:30,447 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:59:30,447 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 159 transitions. [2018-07-24 10:59:30,448 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-07-24 10:59:30,448 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:30,448 INFO L353 BasicCegarLoop]: trace histogram [50, 49, 49, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:30,448 INFO L414 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:30,448 INFO L82 PathProgramCache]: Analyzing trace with hash 398242824, now seen corresponding path program 49 times [2018-07-24 10:59:30,448 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:30,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:30,449 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:30,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:30,449 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:30,457 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:31,502 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:31,502 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:31,503 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:31,509 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:59:31,509 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:59:31,537 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:31,539 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:31,562 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:31,562 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:34,157 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:34,177 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:34,177 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:34,192 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:59:34,193 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:59:34,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:34,252 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:34,276 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:34,276 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:34,354 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 0 proven. 3626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:34,356 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:34,356 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52, 52, 52] total 102 [2018-07-24 10:59:34,356 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:34,357 INFO L450 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-07-24 10:59:34,358 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-07-24 10:59:34,359 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:59:34,359 INFO L87 Difference]: Start difference. First operand 159 states and 159 transitions. Second operand 52 states. [2018-07-24 10:59:34,529 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:34,529 INFO L93 Difference]: Finished difference Result 168 states and 168 transitions. [2018-07-24 10:59:34,529 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-07-24 10:59:34,530 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 158 [2018-07-24 10:59:34,530 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:34,531 INFO L225 Difference]: With dead ends: 168 [2018-07-24 10:59:34,531 INFO L226 Difference]: Without dead ends: 163 [2018-07-24 10:59:34,532 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 682 GetRequests, 582 SyntacticMatches, 0 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:59:34,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 163 states. [2018-07-24 10:59:34,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 163 to 162. [2018-07-24 10:59:34,534 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-07-24 10:59:34,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 162 transitions. [2018-07-24 10:59:34,535 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 162 transitions. Word has length 158 [2018-07-24 10:59:34,535 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:34,536 INFO L471 AbstractCegarLoop]: Abstraction has 162 states and 162 transitions. [2018-07-24 10:59:34,536 INFO L472 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-07-24 10:59:34,536 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 162 transitions. [2018-07-24 10:59:34,537 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-07-24 10:59:34,537 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:34,537 INFO L353 BasicCegarLoop]: trace histogram [51, 50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:34,537 INFO L414 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:34,537 INFO L82 PathProgramCache]: Analyzing trace with hash -96781585, now seen corresponding path program 50 times [2018-07-24 10:59:34,537 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:34,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:34,538 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:59:34,538 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:34,538 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:34,547 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:37,618 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:37,619 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:37,619 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:37,625 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:59:37,626 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:37,675 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:59:37,676 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:37,679 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:37,711 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:37,711 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:40,661 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:40,682 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:40,682 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:40,698 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:59:40,698 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:40,759 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:59:40,759 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:40,763 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:40,787 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:40,787 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:40,819 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 0 proven. 3775 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:40,820 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:40,820 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53, 53, 53] total 104 [2018-07-24 10:59:40,820 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:40,821 INFO L450 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-07-24 10:59:40,821 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-07-24 10:59:40,821 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5356, Invalid=5356, Unknown=0, NotChecked=0, Total=10712 [2018-07-24 10:59:40,821 INFO L87 Difference]: Start difference. First operand 162 states and 162 transitions. Second operand 53 states. [2018-07-24 10:59:40,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:40,985 INFO L93 Difference]: Finished difference Result 171 states and 171 transitions. [2018-07-24 10:59:40,985 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-07-24 10:59:40,985 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 161 [2018-07-24 10:59:40,986 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:40,987 INFO L225 Difference]: With dead ends: 171 [2018-07-24 10:59:40,987 INFO L226 Difference]: Without dead ends: 166 [2018-07-24 10:59:40,987 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 695 GetRequests, 593 SyntacticMatches, 0 SemanticMatches, 102 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=5356, Invalid=5356, Unknown=0, NotChecked=0, Total=10712 [2018-07-24 10:59:40,988 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 166 states. [2018-07-24 10:59:40,990 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 166 to 165. [2018-07-24 10:59:40,991 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-07-24 10:59:40,991 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 165 transitions. [2018-07-24 10:59:40,991 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 165 transitions. Word has length 161 [2018-07-24 10:59:40,991 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:40,991 INFO L471 AbstractCegarLoop]: Abstraction has 165 states and 165 transitions. [2018-07-24 10:59:40,991 INFO L472 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-07-24 10:59:40,992 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 165 transitions. [2018-07-24 10:59:40,992 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-07-24 10:59:40,992 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:40,992 INFO L353 BasicCegarLoop]: trace histogram [52, 51, 51, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:40,992 INFO L414 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:40,993 INFO L82 PathProgramCache]: Analyzing trace with hash 1548744360, now seen corresponding path program 51 times [2018-07-24 10:59:40,993 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:40,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:40,993 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:40,993 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:40,994 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:41,002 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:42,451 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:42,451 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:42,451 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:42,458 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:59:42,459 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:59:42,508 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 52 check-sat command(s) [2018-07-24 10:59:42,508 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:42,510 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:42,533 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:42,533 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:45,339 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:45,359 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:45,360 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:45,375 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:59:45,375 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:59:45,823 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 52 check-sat command(s) [2018-07-24 10:59:45,823 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:45,828 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:45,855 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:45,856 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:45,908 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 0 proven. 3927 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:45,909 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:45,910 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [54, 54, 54, 54, 54] total 106 [2018-07-24 10:59:45,910 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:45,910 INFO L450 AbstractCegarLoop]: Interpolant automaton has 54 states [2018-07-24 10:59:45,910 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 54 interpolants. [2018-07-24 10:59:45,911 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5565, Invalid=5565, Unknown=0, NotChecked=0, Total=11130 [2018-07-24 10:59:45,911 INFO L87 Difference]: Start difference. First operand 165 states and 165 transitions. Second operand 54 states. [2018-07-24 10:59:46,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:46,090 INFO L93 Difference]: Finished difference Result 174 states and 174 transitions. [2018-07-24 10:59:46,090 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 54 states. [2018-07-24 10:59:46,090 INFO L78 Accepts]: Start accepts. Automaton has 54 states. Word has length 164 [2018-07-24 10:59:46,090 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:46,091 INFO L225 Difference]: With dead ends: 174 [2018-07-24 10:59:46,091 INFO L226 Difference]: Without dead ends: 169 [2018-07-24 10:59:46,092 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 708 GetRequests, 604 SyntacticMatches, 0 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=5565, Invalid=5565, Unknown=0, NotChecked=0, Total=11130 [2018-07-24 10:59:46,093 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-07-24 10:59:46,094 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 168. [2018-07-24 10:59:46,094 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 168 states. [2018-07-24 10:59:46,095 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 168 states to 168 states and 168 transitions. [2018-07-24 10:59:46,095 INFO L78 Accepts]: Start accepts. Automaton has 168 states and 168 transitions. Word has length 164 [2018-07-24 10:59:46,095 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:46,095 INFO L471 AbstractCegarLoop]: Abstraction has 168 states and 168 transitions. [2018-07-24 10:59:46,095 INFO L472 AbstractCegarLoop]: Interpolant automaton has 54 states. [2018-07-24 10:59:46,095 INFO L276 IsEmpty]: Start isEmpty. Operand 168 states and 168 transitions. [2018-07-24 10:59:46,096 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 168 [2018-07-24 10:59:46,096 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:46,096 INFO L353 BasicCegarLoop]: trace histogram [53, 52, 52, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:46,096 INFO L414 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:46,096 INFO L82 PathProgramCache]: Analyzing trace with hash 655455311, now seen corresponding path program 52 times [2018-07-24 10:59:46,096 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:46,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:46,097 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:46,097 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:46,097 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:46,105 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:47,202 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:47,202 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:47,202 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:47,209 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:59:47,210 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:59:47,236 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:59:47,237 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:47,241 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:47,273 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:47,274 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:50,275 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:50,296 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:50,296 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:50,311 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:59:50,311 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:59:50,379 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:59:50,379 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:50,383 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:50,410 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:50,410 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:50,448 INFO L134 CoverageAnalysis]: Checked inductivity of 4082 backedges. 0 proven. 4082 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:50,449 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:50,450 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 55] total 108 [2018-07-24 10:59:50,450 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:50,450 INFO L450 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-07-24 10:59:50,450 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-07-24 10:59:50,451 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5778, Invalid=5778, Unknown=0, NotChecked=0, Total=11556 [2018-07-24 10:59:50,451 INFO L87 Difference]: Start difference. First operand 168 states and 168 transitions. Second operand 55 states. [2018-07-24 10:59:50,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:50,722 INFO L93 Difference]: Finished difference Result 177 states and 177 transitions. [2018-07-24 10:59:50,722 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:59:50,722 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 167 [2018-07-24 10:59:50,723 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:50,723 INFO L225 Difference]: With dead ends: 177 [2018-07-24 10:59:50,723 INFO L226 Difference]: Without dead ends: 172 [2018-07-24 10:59:50,724 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 721 GetRequests, 615 SyntacticMatches, 0 SemanticMatches, 106 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 4.0s TimeCoverageRelationStatistics Valid=5778, Invalid=5778, Unknown=0, NotChecked=0, Total=11556 [2018-07-24 10:59:50,725 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-07-24 10:59:50,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 171. [2018-07-24 10:59:50,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-07-24 10:59:50,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 171 transitions. [2018-07-24 10:59:50,728 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 171 transitions. Word has length 167 [2018-07-24 10:59:50,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:50,728 INFO L471 AbstractCegarLoop]: Abstraction has 171 states and 171 transitions. [2018-07-24 10:59:50,728 INFO L472 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-07-24 10:59:50,728 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 171 transitions. [2018-07-24 10:59:50,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-07-24 10:59:50,729 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:50,729 INFO L353 BasicCegarLoop]: trace histogram [54, 53, 53, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:50,729 INFO L414 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:50,729 INFO L82 PathProgramCache]: Analyzing trace with hash 298762568, now seen corresponding path program 53 times [2018-07-24 10:59:50,729 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:50,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:50,730 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:50,730 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:50,730 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:50,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:52,979 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:52,979 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:52,979 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:52,987 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:59:52,988 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:53,035 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 54 check-sat command(s) [2018-07-24 10:59:53,035 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:53,038 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:53,064 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:53,065 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:56,378 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:56,398 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:56,398 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:59:56,413 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:59:56,413 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:59:56,830 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 54 check-sat command(s) [2018-07-24 10:59:56,831 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:56,835 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:56,861 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:56,861 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:59:56,895 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 0 proven. 4240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:56,897 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:59:56,897 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [56, 56, 56, 56, 56] total 110 [2018-07-24 10:59:56,897 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:59:56,898 INFO L450 AbstractCegarLoop]: Interpolant automaton has 56 states [2018-07-24 10:59:56,899 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 56 interpolants. [2018-07-24 10:59:56,900 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5995, Invalid=5995, Unknown=0, NotChecked=0, Total=11990 [2018-07-24 10:59:56,900 INFO L87 Difference]: Start difference. First operand 171 states and 171 transitions. Second operand 56 states. [2018-07-24 10:59:57,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:59:57,115 INFO L93 Difference]: Finished difference Result 180 states and 180 transitions. [2018-07-24 10:59:57,115 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 56 states. [2018-07-24 10:59:57,115 INFO L78 Accepts]: Start accepts. Automaton has 56 states. Word has length 170 [2018-07-24 10:59:57,115 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:59:57,116 INFO L225 Difference]: With dead ends: 180 [2018-07-24 10:59:57,116 INFO L226 Difference]: Without dead ends: 175 [2018-07-24 10:59:57,117 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 734 GetRequests, 626 SyntacticMatches, 0 SemanticMatches, 108 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=5995, Invalid=5995, Unknown=0, NotChecked=0, Total=11990 [2018-07-24 10:59:57,117 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 175 states. [2018-07-24 10:59:57,119 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 175 to 174. [2018-07-24 10:59:57,120 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-07-24 10:59:57,120 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 174 transitions. [2018-07-24 10:59:57,120 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 174 transitions. Word has length 170 [2018-07-24 10:59:57,120 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:59:57,120 INFO L471 AbstractCegarLoop]: Abstraction has 174 states and 174 transitions. [2018-07-24 10:59:57,120 INFO L472 AbstractCegarLoop]: Interpolant automaton has 56 states. [2018-07-24 10:59:57,120 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 174 transitions. [2018-07-24 10:59:57,121 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-07-24 10:59:57,121 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:59:57,121 INFO L353 BasicCegarLoop]: trace histogram [55, 54, 54, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:59:57,121 INFO L414 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:59:57,121 INFO L82 PathProgramCache]: Analyzing trace with hash -185653841, now seen corresponding path program 54 times [2018-07-24 10:59:57,122 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:59:57,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:57,122 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:59:57,122 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:59:57,122 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:59:57,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:59:59,676 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:59,676 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:59:59,676 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:59:59,684 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:59:59,684 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:59:59,735 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-07-24 10:59:59,735 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:59:59,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:59:59,764 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:59:59,764 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:03,231 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:03,251 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:03,251 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:03,267 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 11:00:03,267 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 11:00:03,770 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-07-24 11:00:03,770 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:03,775 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:03,801 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:03,801 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:03,835 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 0 proven. 4401 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:03,837 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:03,837 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57, 57, 57] total 112 [2018-07-24 11:00:03,837 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:03,838 INFO L450 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-07-24 11:00:03,838 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-07-24 11:00:03,838 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6216, Invalid=6216, Unknown=0, NotChecked=0, Total=12432 [2018-07-24 11:00:03,838 INFO L87 Difference]: Start difference. First operand 174 states and 174 transitions. Second operand 57 states. [2018-07-24 11:00:04,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:04,044 INFO L93 Difference]: Finished difference Result 183 states and 183 transitions. [2018-07-24 11:00:04,044 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-07-24 11:00:04,044 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 173 [2018-07-24 11:00:04,044 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:04,045 INFO L225 Difference]: With dead ends: 183 [2018-07-24 11:00:04,046 INFO L226 Difference]: Without dead ends: 178 [2018-07-24 11:00:04,046 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 747 GetRequests, 637 SyntacticMatches, 0 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=6216, Invalid=6216, Unknown=0, NotChecked=0, Total=12432 [2018-07-24 11:00:04,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 178 states. [2018-07-24 11:00:04,050 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 178 to 177. [2018-07-24 11:00:04,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-07-24 11:00:04,051 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 177 transitions. [2018-07-24 11:00:04,051 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 177 transitions. Word has length 173 [2018-07-24 11:00:04,051 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:04,051 INFO L471 AbstractCegarLoop]: Abstraction has 177 states and 177 transitions. [2018-07-24 11:00:04,051 INFO L472 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-07-24 11:00:04,051 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 177 transitions. [2018-07-24 11:00:04,052 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-07-24 11:00:04,052 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:04,052 INFO L353 BasicCegarLoop]: trace histogram [56, 55, 55, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:04,052 INFO L414 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:04,052 INFO L82 PathProgramCache]: Analyzing trace with hash -344779800, now seen corresponding path program 55 times [2018-07-24 11:00:04,052 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:04,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:04,053 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:04,053 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:04,053 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:04,063 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:06,868 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:06,868 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:06,868 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:06,877 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:00:06,877 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 11:00:06,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:06,906 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:06,934 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:06,934 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:10,171 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:10,192 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:10,192 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:10,207 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:00:10,207 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 11:00:10,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:10,271 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:10,299 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:10,299 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:10,338 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 0 proven. 4565 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:10,339 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:10,339 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [58, 58, 58, 58, 58] total 114 [2018-07-24 11:00:10,339 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:10,340 INFO L450 AbstractCegarLoop]: Interpolant automaton has 58 states [2018-07-24 11:00:10,340 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 58 interpolants. [2018-07-24 11:00:10,341 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6441, Invalid=6441, Unknown=0, NotChecked=0, Total=12882 [2018-07-24 11:00:10,341 INFO L87 Difference]: Start difference. First operand 177 states and 177 transitions. Second operand 58 states. [2018-07-24 11:00:10,562 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:10,562 INFO L93 Difference]: Finished difference Result 186 states and 186 transitions. [2018-07-24 11:00:10,562 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 58 states. [2018-07-24 11:00:10,562 INFO L78 Accepts]: Start accepts. Automaton has 58 states. Word has length 176 [2018-07-24 11:00:10,563 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:10,564 INFO L225 Difference]: With dead ends: 186 [2018-07-24 11:00:10,564 INFO L226 Difference]: Without dead ends: 181 [2018-07-24 11:00:10,565 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 760 GetRequests, 648 SyntacticMatches, 0 SemanticMatches, 112 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=6441, Invalid=6441, Unknown=0, NotChecked=0, Total=12882 [2018-07-24 11:00:10,565 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 181 states. [2018-07-24 11:00:10,568 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 181 to 180. [2018-07-24 11:00:10,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-07-24 11:00:10,569 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 180 transitions. [2018-07-24 11:00:10,569 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 180 transitions. Word has length 176 [2018-07-24 11:00:10,569 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:10,569 INFO L471 AbstractCegarLoop]: Abstraction has 180 states and 180 transitions. [2018-07-24 11:00:10,569 INFO L472 AbstractCegarLoop]: Interpolant automaton has 58 states. [2018-07-24 11:00:10,569 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 180 transitions. [2018-07-24 11:00:10,570 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2018-07-24 11:00:10,570 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:10,570 INFO L353 BasicCegarLoop]: trace histogram [57, 56, 56, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:10,571 INFO L414 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:10,571 INFO L82 PathProgramCache]: Analyzing trace with hash 777670415, now seen corresponding path program 56 times [2018-07-24 11:00:10,571 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:10,571 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:10,572 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:00:10,572 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:10,572 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:10,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:12,698 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:12,699 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:12,699 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:12,707 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 11:00:12,707 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:00:12,735 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 11:00:12,736 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:12,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:12,766 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:12,766 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:16,139 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:16,161 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:16,161 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:16,175 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 11:00:16,176 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:00:16,241 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 11:00:16,241 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:16,246 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:16,282 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:16,282 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:16,378 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 0 proven. 4732 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:16,379 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:16,380 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 59, 59] total 116 [2018-07-24 11:00:16,380 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:16,380 INFO L450 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-07-24 11:00:16,381 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-07-24 11:00:16,381 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6670, Invalid=6670, Unknown=0, NotChecked=0, Total=13340 [2018-07-24 11:00:16,381 INFO L87 Difference]: Start difference. First operand 180 states and 180 transitions. Second operand 59 states. [2018-07-24 11:00:16,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:16,610 INFO L93 Difference]: Finished difference Result 189 states and 189 transitions. [2018-07-24 11:00:16,610 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-24 11:00:16,611 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 179 [2018-07-24 11:00:16,611 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:16,612 INFO L225 Difference]: With dead ends: 189 [2018-07-24 11:00:16,612 INFO L226 Difference]: Without dead ends: 184 [2018-07-24 11:00:16,613 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 773 GetRequests, 659 SyntacticMatches, 0 SemanticMatches, 114 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=6670, Invalid=6670, Unknown=0, NotChecked=0, Total=13340 [2018-07-24 11:00:16,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 184 states. [2018-07-24 11:00:16,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 184 to 183. [2018-07-24 11:00:16,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-07-24 11:00:16,617 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 183 transitions. [2018-07-24 11:00:16,618 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 183 transitions. Word has length 179 [2018-07-24 11:00:16,618 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:16,618 INFO L471 AbstractCegarLoop]: Abstraction has 183 states and 183 transitions. [2018-07-24 11:00:16,618 INFO L472 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-07-24 11:00:16,618 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 183 transitions. [2018-07-24 11:00:16,619 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-07-24 11:00:16,619 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:16,619 INFO L353 BasicCegarLoop]: trace histogram [58, 57, 57, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:16,619 INFO L414 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:16,620 INFO L82 PathProgramCache]: Analyzing trace with hash -923341176, now seen corresponding path program 57 times [2018-07-24 11:00:16,620 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:16,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:16,620 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:16,620 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:16,621 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:16,631 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:18,087 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:18,087 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:18,087 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:18,094 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 11:00:18,094 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 11:00:18,149 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 58 check-sat command(s) [2018-07-24 11:00:18,149 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:18,151 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:18,180 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:18,180 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:22,016 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:22,045 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:22,045 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:22,061 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 11:00:22,061 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 11:00:22,592 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 58 check-sat command(s) [2018-07-24 11:00:22,592 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:22,596 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:22,625 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:22,625 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:22,666 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 0 proven. 4902 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:22,667 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:22,668 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [60, 60, 60, 60, 60] total 118 [2018-07-24 11:00:22,668 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:22,668 INFO L450 AbstractCegarLoop]: Interpolant automaton has 60 states [2018-07-24 11:00:22,668 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 60 interpolants. [2018-07-24 11:00:22,669 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=6903, Invalid=6903, Unknown=0, NotChecked=0, Total=13806 [2018-07-24 11:00:22,669 INFO L87 Difference]: Start difference. First operand 183 states and 183 transitions. Second operand 60 states. [2018-07-24 11:00:22,904 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:22,904 INFO L93 Difference]: Finished difference Result 192 states and 192 transitions. [2018-07-24 11:00:22,904 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 60 states. [2018-07-24 11:00:22,904 INFO L78 Accepts]: Start accepts. Automaton has 60 states. Word has length 182 [2018-07-24 11:00:22,904 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:22,905 INFO L225 Difference]: With dead ends: 192 [2018-07-24 11:00:22,905 INFO L226 Difference]: Without dead ends: 187 [2018-07-24 11:00:22,906 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 786 GetRequests, 670 SyntacticMatches, 0 SemanticMatches, 116 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.2s TimeCoverageRelationStatistics Valid=6903, Invalid=6903, Unknown=0, NotChecked=0, Total=13806 [2018-07-24 11:00:22,906 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-07-24 11:00:22,909 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 186. [2018-07-24 11:00:22,909 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-07-24 11:00:22,909 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 186 transitions. [2018-07-24 11:00:22,910 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 186 transitions. Word has length 182 [2018-07-24 11:00:22,910 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:22,910 INFO L471 AbstractCegarLoop]: Abstraction has 186 states and 186 transitions. [2018-07-24 11:00:22,910 INFO L472 AbstractCegarLoop]: Interpolant automaton has 60 states. [2018-07-24 11:00:22,910 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 186 transitions. [2018-07-24 11:00:22,911 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-07-24 11:00:22,911 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:22,911 INFO L353 BasicCegarLoop]: trace histogram [59, 58, 58, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:22,912 INFO L414 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:22,912 INFO L82 PathProgramCache]: Analyzing trace with hash 559476847, now seen corresponding path program 58 times [2018-07-24 11:00:22,912 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:22,912 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:22,913 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:22,913 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:22,913 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:22,924 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:24,215 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:24,216 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:24,216 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:24,223 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 11:00:24,223 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 11:00:24,249 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 11:00:24,249 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:24,251 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:24,282 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:24,282 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:28,132 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:28,154 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:28,154 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:28,169 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 11:00:28,169 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 11:00:28,244 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 11:00:28,244 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:28,248 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:28,275 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:28,276 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:28,313 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 0 proven. 5075 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:28,314 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:28,315 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61, 61, 61] total 120 [2018-07-24 11:00:28,315 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:28,315 INFO L450 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-07-24 11:00:28,316 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-07-24 11:00:28,316 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7140, Invalid=7140, Unknown=0, NotChecked=0, Total=14280 [2018-07-24 11:00:28,316 INFO L87 Difference]: Start difference. First operand 186 states and 186 transitions. Second operand 61 states. [2018-07-24 11:00:28,572 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:28,572 INFO L93 Difference]: Finished difference Result 195 states and 195 transitions. [2018-07-24 11:00:28,573 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-07-24 11:00:28,573 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 185 [2018-07-24 11:00:28,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:28,575 INFO L225 Difference]: With dead ends: 195 [2018-07-24 11:00:28,575 INFO L226 Difference]: Without dead ends: 190 [2018-07-24 11:00:28,576 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 799 GetRequests, 681 SyntacticMatches, 0 SemanticMatches, 118 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.0s TimeCoverageRelationStatistics Valid=7140, Invalid=7140, Unknown=0, NotChecked=0, Total=14280 [2018-07-24 11:00:28,577 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190 states. [2018-07-24 11:00:28,579 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190 to 189. [2018-07-24 11:00:28,580 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-07-24 11:00:28,593 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 189 transitions. [2018-07-24 11:00:28,594 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 189 transitions. Word has length 185 [2018-07-24 11:00:28,594 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:28,594 INFO L471 AbstractCegarLoop]: Abstraction has 189 states and 189 transitions. [2018-07-24 11:00:28,594 INFO L472 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-07-24 11:00:28,594 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 189 transitions. [2018-07-24 11:00:28,595 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 189 [2018-07-24 11:00:28,596 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:28,596 INFO L353 BasicCegarLoop]: trace histogram [60, 59, 59, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:28,596 INFO L414 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:28,596 INFO L82 PathProgramCache]: Analyzing trace with hash 1452560680, now seen corresponding path program 59 times [2018-07-24 11:00:28,596 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:28,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:28,597 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:28,597 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:28,597 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:28,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:29,975 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:29,975 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:29,975 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:29,983 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 11:00:29,983 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:00:30,040 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-07-24 11:00:30,040 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:30,043 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:30,074 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:30,075 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:34,153 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:34,173 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:34,174 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:34,188 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 11:00:34,189 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:00:34,687 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 60 check-sat command(s) [2018-07-24 11:00:34,687 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:34,691 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:34,719 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:34,719 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:34,755 INFO L134 CoverageAnalysis]: Checked inductivity of 5251 backedges. 0 proven. 5251 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:34,757 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:34,757 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [62, 62, 62, 62, 62] total 122 [2018-07-24 11:00:34,757 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:34,757 INFO L450 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-07-24 11:00:34,758 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-07-24 11:00:34,759 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7381, Invalid=7381, Unknown=0, NotChecked=0, Total=14762 [2018-07-24 11:00:34,759 INFO L87 Difference]: Start difference. First operand 189 states and 189 transitions. Second operand 62 states. [2018-07-24 11:00:35,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:35,003 INFO L93 Difference]: Finished difference Result 198 states and 198 transitions. [2018-07-24 11:00:35,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-07-24 11:00:35,004 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 188 [2018-07-24 11:00:35,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:35,005 INFO L225 Difference]: With dead ends: 198 [2018-07-24 11:00:35,005 INFO L226 Difference]: Without dead ends: 193 [2018-07-24 11:00:35,006 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 812 GetRequests, 692 SyntacticMatches, 0 SemanticMatches, 120 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=7381, Invalid=7381, Unknown=0, NotChecked=0, Total=14762 [2018-07-24 11:00:35,006 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-07-24 11:00:35,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 192. [2018-07-24 11:00:35,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-07-24 11:00:35,008 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 192 transitions. [2018-07-24 11:00:35,008 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 192 transitions. Word has length 188 [2018-07-24 11:00:35,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:35,009 INFO L471 AbstractCegarLoop]: Abstraction has 192 states and 192 transitions. [2018-07-24 11:00:35,009 INFO L472 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-07-24 11:00:35,009 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 192 transitions. [2018-07-24 11:00:35,009 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-07-24 11:00:35,010 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:35,010 INFO L353 BasicCegarLoop]: trace histogram [61, 60, 60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:35,010 INFO L414 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:35,010 INFO L82 PathProgramCache]: Analyzing trace with hash -9369137, now seen corresponding path program 60 times [2018-07-24 11:00:35,010 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:35,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:35,011 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:35,011 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:35,011 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:35,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:36,413 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:36,413 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:36,413 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:36,422 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 11:00:36,422 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 11:00:36,484 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-07-24 11:00:36,484 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:36,487 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:36,520 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:36,520 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:40,625 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:40,645 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:40,645 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:40,660 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 11:00:40,660 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 11:00:41,231 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-07-24 11:00:41,231 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:41,235 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:41,266 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:41,267 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:41,309 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 0 proven. 5430 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:41,310 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:41,311 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63, 63, 63, 63] total 124 [2018-07-24 11:00:41,311 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:41,311 INFO L450 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-07-24 11:00:41,312 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-07-24 11:00:41,312 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7626, Invalid=7626, Unknown=0, NotChecked=0, Total=15252 [2018-07-24 11:00:41,312 INFO L87 Difference]: Start difference. First operand 192 states and 192 transitions. Second operand 63 states. [2018-07-24 11:00:41,578 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:41,578 INFO L93 Difference]: Finished difference Result 201 states and 201 transitions. [2018-07-24 11:00:41,578 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-07-24 11:00:41,578 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 191 [2018-07-24 11:00:41,578 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:41,579 INFO L225 Difference]: With dead ends: 201 [2018-07-24 11:00:41,579 INFO L226 Difference]: Without dead ends: 196 [2018-07-24 11:00:41,580 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 825 GetRequests, 703 SyntacticMatches, 0 SemanticMatches, 122 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.4s TimeCoverageRelationStatistics Valid=7626, Invalid=7626, Unknown=0, NotChecked=0, Total=15252 [2018-07-24 11:00:41,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 196 states. [2018-07-24 11:00:41,582 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 196 to 195. [2018-07-24 11:00:41,583 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-07-24 11:00:41,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 195 transitions. [2018-07-24 11:00:41,583 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 195 transitions. Word has length 191 [2018-07-24 11:00:41,583 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:41,583 INFO L471 AbstractCegarLoop]: Abstraction has 195 states and 195 transitions. [2018-07-24 11:00:41,584 INFO L472 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-07-24 11:00:41,584 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 195 transitions. [2018-07-24 11:00:41,584 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-07-24 11:00:41,585 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:41,585 INFO L353 BasicCegarLoop]: trace histogram [62, 61, 61, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:41,585 INFO L414 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:41,585 INFO L82 PathProgramCache]: Analyzing trace with hash -1392165944, now seen corresponding path program 61 times [2018-07-24 11:00:41,585 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:41,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:41,586 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:41,586 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:41,586 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:41,598 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:43,927 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:43,927 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:43,927 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:43,934 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:00:43,935 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 11:00:43,967 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:43,969 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:44,002 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:44,002 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:48,319 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:48,340 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:48,340 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:48,355 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:00:48,355 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 11:00:48,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:48,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:48,455 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:48,456 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:48,493 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 0 proven. 5612 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:48,494 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:48,495 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [64, 64, 64, 64, 64] total 126 [2018-07-24 11:00:48,495 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:48,495 INFO L450 AbstractCegarLoop]: Interpolant automaton has 64 states [2018-07-24 11:00:48,496 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 64 interpolants. [2018-07-24 11:00:48,496 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7875, Invalid=7875, Unknown=0, NotChecked=0, Total=15750 [2018-07-24 11:00:48,496 INFO L87 Difference]: Start difference. First operand 195 states and 195 transitions. Second operand 64 states. [2018-07-24 11:00:48,776 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:48,777 INFO L93 Difference]: Finished difference Result 204 states and 204 transitions. [2018-07-24 11:00:48,777 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 64 states. [2018-07-24 11:00:48,777 INFO L78 Accepts]: Start accepts. Automaton has 64 states. Word has length 194 [2018-07-24 11:00:48,778 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:48,778 INFO L225 Difference]: With dead ends: 204 [2018-07-24 11:00:48,778 INFO L226 Difference]: Without dead ends: 199 [2018-07-24 11:00:48,779 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 838 GetRequests, 714 SyntacticMatches, 0 SemanticMatches, 124 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=7875, Invalid=7875, Unknown=0, NotChecked=0, Total=15750 [2018-07-24 11:00:48,779 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-07-24 11:00:48,782 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 198. [2018-07-24 11:00:48,782 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-07-24 11:00:48,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 198 transitions. [2018-07-24 11:00:48,783 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 198 transitions. Word has length 194 [2018-07-24 11:00:48,783 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:48,783 INFO L471 AbstractCegarLoop]: Abstraction has 198 states and 198 transitions. [2018-07-24 11:00:48,783 INFO L472 AbstractCegarLoop]: Interpolant automaton has 64 states. [2018-07-24 11:00:48,783 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 198 transitions. [2018-07-24 11:00:48,784 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-07-24 11:00:48,784 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:48,784 INFO L353 BasicCegarLoop]: trace histogram [63, 62, 62, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:48,785 INFO L414 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:48,785 INFO L82 PathProgramCache]: Analyzing trace with hash 1034459951, now seen corresponding path program 62 times [2018-07-24 11:00:48,785 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:48,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:48,786 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:00:48,786 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:48,786 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:48,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:50,308 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:50,308 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:50,308 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:50,315 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 11:00:50,315 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:00:50,348 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 11:00:50,348 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:50,350 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:50,383 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:50,384 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:54,896 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:54,916 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:54,916 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:00:54,933 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 11:00:54,933 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:00:55,007 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 11:00:55,007 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:55,012 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:55,046 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:55,046 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:00:55,088 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 0 proven. 5797 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:55,089 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:00:55,089 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65, 65, 65, 65] total 128 [2018-07-24 11:00:55,089 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:00:55,090 INFO L450 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-07-24 11:00:55,090 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-07-24 11:00:55,091 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8128, Invalid=8128, Unknown=0, NotChecked=0, Total=16256 [2018-07-24 11:00:55,091 INFO L87 Difference]: Start difference. First operand 198 states and 198 transitions. Second operand 65 states. [2018-07-24 11:00:55,399 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:00:55,400 INFO L93 Difference]: Finished difference Result 207 states and 207 transitions. [2018-07-24 11:00:55,400 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-07-24 11:00:55,400 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 197 [2018-07-24 11:00:55,400 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:00:55,401 INFO L225 Difference]: With dead ends: 207 [2018-07-24 11:00:55,402 INFO L226 Difference]: Without dead ends: 202 [2018-07-24 11:00:55,402 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 851 GetRequests, 725 SyntacticMatches, 0 SemanticMatches, 126 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 5.9s TimeCoverageRelationStatistics Valid=8128, Invalid=8128, Unknown=0, NotChecked=0, Total=16256 [2018-07-24 11:00:55,403 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 202 states. [2018-07-24 11:00:55,406 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 202 to 201. [2018-07-24 11:00:55,406 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-07-24 11:00:55,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 201 transitions. [2018-07-24 11:00:55,407 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 201 transitions. Word has length 197 [2018-07-24 11:00:55,407 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:00:55,407 INFO L471 AbstractCegarLoop]: Abstraction has 201 states and 201 transitions. [2018-07-24 11:00:55,407 INFO L472 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-07-24 11:00:55,407 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 201 transitions. [2018-07-24 11:00:55,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-07-24 11:00:55,409 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:00:55,409 INFO L353 BasicCegarLoop]: trace histogram [64, 63, 63, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:00:55,409 INFO L414 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:00:55,409 INFO L82 PathProgramCache]: Analyzing trace with hash -243028376, now seen corresponding path program 63 times [2018-07-24 11:00:55,409 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:00:55,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:55,410 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:00:55,410 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:00:55,410 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:00:55,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:00:59,166 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:59,166 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:00:59,166 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:00:59,174 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 11:00:59,174 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 11:00:59,361 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 64 check-sat command(s) [2018-07-24 11:00:59,361 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:00:59,363 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:00:59,397 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:00:59,397 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:03,909 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:03,930 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:03,930 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:01:03,959 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 11:01:03,959 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 11:01:04,576 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 64 check-sat command(s) [2018-07-24 11:01:04,577 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:04,581 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:04,612 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:04,612 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:04,646 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 0 proven. 5985 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:04,648 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:01:04,648 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [66, 66, 66, 66, 66] total 130 [2018-07-24 11:01:04,648 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:01:04,648 INFO L450 AbstractCegarLoop]: Interpolant automaton has 66 states [2018-07-24 11:01:04,649 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 66 interpolants. [2018-07-24 11:01:04,649 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8385, Invalid=8385, Unknown=0, NotChecked=0, Total=16770 [2018-07-24 11:01:04,649 INFO L87 Difference]: Start difference. First operand 201 states and 201 transitions. Second operand 66 states. [2018-07-24 11:01:04,932 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:01:04,933 INFO L93 Difference]: Finished difference Result 210 states and 210 transitions. [2018-07-24 11:01:04,933 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 66 states. [2018-07-24 11:01:04,933 INFO L78 Accepts]: Start accepts. Automaton has 66 states. Word has length 200 [2018-07-24 11:01:04,933 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:01:04,934 INFO L225 Difference]: With dead ends: 210 [2018-07-24 11:01:04,934 INFO L226 Difference]: Without dead ends: 205 [2018-07-24 11:01:04,935 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 864 GetRequests, 736 SyntacticMatches, 0 SemanticMatches, 128 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 8.1s TimeCoverageRelationStatistics Valid=8385, Invalid=8385, Unknown=0, NotChecked=0, Total=16770 [2018-07-24 11:01:04,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 205 states. [2018-07-24 11:01:04,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 205 to 204. [2018-07-24 11:01:04,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-07-24 11:01:04,938 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 204 transitions. [2018-07-24 11:01:04,938 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 204 transitions. Word has length 200 [2018-07-24 11:01:04,938 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:01:04,939 INFO L471 AbstractCegarLoop]: Abstraction has 204 states and 204 transitions. [2018-07-24 11:01:04,939 INFO L472 AbstractCegarLoop]: Interpolant automaton has 66 states. [2018-07-24 11:01:04,939 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 204 transitions. [2018-07-24 11:01:04,939 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-07-24 11:01:04,940 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:01:04,940 INFO L353 BasicCegarLoop]: trace histogram [65, 64, 64, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:01:04,940 INFO L414 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:01:04,940 INFO L82 PathProgramCache]: Analyzing trace with hash -192568177, now seen corresponding path program 64 times [2018-07-24 11:01:04,940 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:01:04,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:04,941 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:01:04,941 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:04,941 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:01:04,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:06,472 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:06,473 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:06,473 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:01:06,482 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 11:01:06,482 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 11:01:06,515 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 11:01:06,516 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:06,518 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:06,568 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:06,568 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:11,261 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:11,282 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:11,282 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:01:11,298 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 11:01:11,298 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 11:01:11,381 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 11:01:11,381 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:11,386 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:11,418 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:11,418 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:11,473 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 0 proven. 6176 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:11,475 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:01:11,475 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67, 67, 67, 67] total 132 [2018-07-24 11:01:11,476 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:01:11,476 INFO L450 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-07-24 11:01:11,477 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-07-24 11:01:11,477 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8646, Invalid=8646, Unknown=0, NotChecked=0, Total=17292 [2018-07-24 11:01:11,477 INFO L87 Difference]: Start difference. First operand 204 states and 204 transitions. Second operand 67 states. [2018-07-24 11:01:11,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:01:11,757 INFO L93 Difference]: Finished difference Result 213 states and 213 transitions. [2018-07-24 11:01:11,757 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-07-24 11:01:11,757 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 203 [2018-07-24 11:01:11,758 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:01:11,759 INFO L225 Difference]: With dead ends: 213 [2018-07-24 11:01:11,759 INFO L226 Difference]: Without dead ends: 208 [2018-07-24 11:01:11,760 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 877 GetRequests, 747 SyntacticMatches, 0 SemanticMatches, 130 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 6.1s TimeCoverageRelationStatistics Valid=8646, Invalid=8646, Unknown=0, NotChecked=0, Total=17292 [2018-07-24 11:01:11,760 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 208 states. [2018-07-24 11:01:11,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 208 to 207. [2018-07-24 11:01:11,763 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-07-24 11:01:11,764 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 207 transitions. [2018-07-24 11:01:11,764 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 207 transitions. Word has length 203 [2018-07-24 11:01:11,764 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:01:11,764 INFO L471 AbstractCegarLoop]: Abstraction has 207 states and 207 transitions. [2018-07-24 11:01:11,764 INFO L472 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-07-24 11:01:11,764 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 207 transitions. [2018-07-24 11:01:11,765 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-07-24 11:01:11,765 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:01:11,765 INFO L353 BasicCegarLoop]: trace histogram [66, 65, 65, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:01:11,765 INFO L414 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:01:11,765 INFO L82 PathProgramCache]: Analyzing trace with hash -171333368, now seen corresponding path program 65 times [2018-07-24 11:01:11,765 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:01:11,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:11,766 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:01:11,766 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:11,766 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:01:11,775 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:13,611 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:13,612 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:13,612 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:01:13,620 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 11:01:13,621 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:01:13,682 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 66 check-sat command(s) [2018-07-24 11:01:13,682 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:13,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:13,721 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:13,722 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:18,592 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:18,613 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:18,613 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:01:18,630 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 11:01:18,631 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:01:19,259 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 66 check-sat command(s) [2018-07-24 11:01:19,260 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:19,266 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:19,315 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:19,315 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:19,359 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 0 proven. 6370 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:19,360 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:01:19,361 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [68, 68, 68, 68, 68] total 134 [2018-07-24 11:01:19,361 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:01:19,361 INFO L450 AbstractCegarLoop]: Interpolant automaton has 68 states [2018-07-24 11:01:19,362 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 68 interpolants. [2018-07-24 11:01:19,362 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8911, Invalid=8911, Unknown=0, NotChecked=0, Total=17822 [2018-07-24 11:01:19,363 INFO L87 Difference]: Start difference. First operand 207 states and 207 transitions. Second operand 68 states. [2018-07-24 11:01:19,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:01:19,598 INFO L93 Difference]: Finished difference Result 216 states and 216 transitions. [2018-07-24 11:01:19,598 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 68 states. [2018-07-24 11:01:19,599 INFO L78 Accepts]: Start accepts. Automaton has 68 states. Word has length 206 [2018-07-24 11:01:19,599 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:01:19,600 INFO L225 Difference]: With dead ends: 216 [2018-07-24 11:01:19,600 INFO L226 Difference]: Without dead ends: 211 [2018-07-24 11:01:19,601 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 890 GetRequests, 758 SyntacticMatches, 0 SemanticMatches, 132 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 6.5s TimeCoverageRelationStatistics Valid=8911, Invalid=8911, Unknown=0, NotChecked=0, Total=17822 [2018-07-24 11:01:19,602 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 211 states. [2018-07-24 11:01:19,604 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 211 to 210. [2018-07-24 11:01:19,604 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 210 states. [2018-07-24 11:01:19,605 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 210 states to 210 states and 210 transitions. [2018-07-24 11:01:19,605 INFO L78 Accepts]: Start accepts. Automaton has 210 states and 210 transitions. Word has length 206 [2018-07-24 11:01:19,605 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:01:19,605 INFO L471 AbstractCegarLoop]: Abstraction has 210 states and 210 transitions. [2018-07-24 11:01:19,605 INFO L472 AbstractCegarLoop]: Interpolant automaton has 68 states. [2018-07-24 11:01:19,605 INFO L276 IsEmpty]: Start isEmpty. Operand 210 states and 210 transitions. [2018-07-24 11:01:19,606 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 210 [2018-07-24 11:01:19,606 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:01:19,606 INFO L353 BasicCegarLoop]: trace histogram [67, 66, 66, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:01:19,606 INFO L414 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:01:19,606 INFO L82 PathProgramCache]: Analyzing trace with hash 1074669039, now seen corresponding path program 66 times [2018-07-24 11:01:19,607 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:01:19,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:19,607 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:01:19,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:19,608 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:01:19,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:21,384 INFO L134 CoverageAnalysis]: Checked inductivity of 6567 backedges. 0 proven. 6567 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:21,384 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:21,384 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:01:21,391 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 11:01:21,391 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 11:01:21,455 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 67 check-sat command(s) [2018-07-24 11:01:21,455 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:21,458 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:21,496 INFO L134 CoverageAnalysis]: Checked inductivity of 6567 backedges. 0 proven. 6567 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:21,496 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:26,542 INFO L134 CoverageAnalysis]: Checked inductivity of 6567 backedges. 0 proven. 6567 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:26,562 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:26,562 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:01:26,577 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 11:01:26,577 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 11:01:27,249 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 67 check-sat command(s) [2018-07-24 11:01:27,250 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:27,254 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:27,291 INFO L134 CoverageAnalysis]: Checked inductivity of 6567 backedges. 0 proven. 6567 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:27,291 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:27,350 INFO L134 CoverageAnalysis]: Checked inductivity of 6567 backedges. 0 proven. 6567 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:27,352 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:01:27,352 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69, 69, 69, 69] total 136 [2018-07-24 11:01:27,352 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:01:27,352 INFO L450 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-07-24 11:01:27,353 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-07-24 11:01:27,353 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9180, Invalid=9180, Unknown=0, NotChecked=0, Total=18360 [2018-07-24 11:01:27,353 INFO L87 Difference]: Start difference. First operand 210 states and 210 transitions. Second operand 69 states. [2018-07-24 11:01:27,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:01:27,653 INFO L93 Difference]: Finished difference Result 219 states and 219 transitions. [2018-07-24 11:01:27,653 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-07-24 11:01:27,653 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 209 [2018-07-24 11:01:27,654 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:01:27,655 INFO L225 Difference]: With dead ends: 219 [2018-07-24 11:01:27,655 INFO L226 Difference]: Without dead ends: 214 [2018-07-24 11:01:27,655 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 903 GetRequests, 769 SyntacticMatches, 0 SemanticMatches, 134 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 6.7s TimeCoverageRelationStatistics Valid=9180, Invalid=9180, Unknown=0, NotChecked=0, Total=18360 [2018-07-24 11:01:27,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2018-07-24 11:01:27,658 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 213. [2018-07-24 11:01:27,658 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-07-24 11:01:27,659 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 213 transitions. [2018-07-24 11:01:27,659 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 213 transitions. Word has length 209 [2018-07-24 11:01:27,659 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:01:27,659 INFO L471 AbstractCegarLoop]: Abstraction has 213 states and 213 transitions. [2018-07-24 11:01:27,659 INFO L472 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-07-24 11:01:27,659 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 213 transitions. [2018-07-24 11:01:27,660 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-07-24 11:01:27,661 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:01:27,661 INFO L353 BasicCegarLoop]: trace histogram [68, 67, 67, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:01:27,661 INFO L414 AbstractCegarLoop]: === Iteration 69 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:01:27,661 INFO L82 PathProgramCache]: Analyzing trace with hash -669963352, now seen corresponding path program 67 times [2018-07-24 11:01:27,661 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:01:27,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:27,662 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 11:01:27,662 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:27,662 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:01:27,677 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:29,739 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 0 proven. 6767 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:29,739 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:29,739 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:01:29,747 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:01:29,747 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 11:01:29,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:29,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:29,834 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 0 proven. 6767 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:29,835 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:34,994 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 0 proven. 6767 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:35,015 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:35,015 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 11:01:35,031 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:01:35,031 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 11:01:35,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:35,106 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:35,143 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 0 proven. 6767 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:35,144 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 11:01:35,186 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 0 proven. 6767 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:35,187 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 11:01:35,188 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [70, 70, 70, 70, 70] total 138 [2018-07-24 11:01:35,188 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 11:01:35,188 INFO L450 AbstractCegarLoop]: Interpolant automaton has 70 states [2018-07-24 11:01:35,189 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 70 interpolants. [2018-07-24 11:01:35,189 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=9453, Invalid=9453, Unknown=0, NotChecked=0, Total=18906 [2018-07-24 11:01:35,189 INFO L87 Difference]: Start difference. First operand 213 states and 213 transitions. Second operand 70 states. [2018-07-24 11:01:35,437 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 11:01:35,438 INFO L93 Difference]: Finished difference Result 222 states and 222 transitions. [2018-07-24 11:01:35,438 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 70 states. [2018-07-24 11:01:35,438 INFO L78 Accepts]: Start accepts. Automaton has 70 states. Word has length 212 [2018-07-24 11:01:35,439 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 11:01:35,440 INFO L225 Difference]: With dead ends: 222 [2018-07-24 11:01:35,440 INFO L226 Difference]: Without dead ends: 217 [2018-07-24 11:01:35,441 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 916 GetRequests, 780 SyntacticMatches, 0 SemanticMatches, 136 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 7.1s TimeCoverageRelationStatistics Valid=9453, Invalid=9453, Unknown=0, NotChecked=0, Total=18906 [2018-07-24 11:01:35,441 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-07-24 11:01:35,445 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 216. [2018-07-24 11:01:35,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-07-24 11:01:35,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 216 transitions. [2018-07-24 11:01:35,446 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 216 transitions. Word has length 212 [2018-07-24 11:01:35,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 11:01:35,446 INFO L471 AbstractCegarLoop]: Abstraction has 216 states and 216 transitions. [2018-07-24 11:01:35,446 INFO L472 AbstractCegarLoop]: Interpolant automaton has 70 states. [2018-07-24 11:01:35,446 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 216 transitions. [2018-07-24 11:01:35,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-07-24 11:01:35,447 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 11:01:35,447 INFO L353 BasicCegarLoop]: trace histogram [69, 68, 68, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 11:01:35,448 INFO L414 AbstractCegarLoop]: === Iteration 70 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_new_count_by___true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 11:01:35,448 INFO L82 PathProgramCache]: Analyzing trace with hash -1614274737, now seen corresponding path program 68 times [2018-07-24 11:01:35,448 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 11:01:35,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:35,449 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 11:01:35,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 11:01:35,449 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 11:01:35,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 11:01:37,334 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 0 proven. 6970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:37,334 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 11:01:37,334 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:01:37,341 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 11:01:37,341 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 11:01:37,376 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 11:01:37,376 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 11:01:37,379 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 11:01:37,416 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 0 proven. 6970 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 11:01:37,416 INFO L316 TraceCheckSpWp]: Computing backward predicates... Received shutdown request... [2018-07-24 11:01:40,903 INFO L177 TraceCheckSpWp]: Timeout while computing interpolants [2018-07-24 11:01:41,104 WARN L512 AbstractCegarLoop]: Destroyed unattended storables created during the last iteration: 136 z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 11:01:41,105 WARN L540 AbstractCegarLoop]: Verification canceled [2018-07-24 11:01:41,110 WARN L202 ceAbstractionStarter]: Timeout [2018-07-24 11:01:41,110 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 11:01:41 BoogieIcfgContainer [2018-07-24 11:01:41,110 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 11:01:41,111 INFO L168 Benchmark]: Toolchain (without parser) took 232564.64 ms. Allocated memory was 1.5 GB in the beginning and 2.2 GB in the end (delta: 637.5 MB). Free memory was 1.4 GB in the beginning and 2.1 GB in the end (delta: -673.5 MB). Peak memory consumption was 536.1 MB. Max. memory is 7.1 GB. [2018-07-24 11:01:41,112 INFO L168 Benchmark]: CDTParser took 0.31 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 11:01:41,112 INFO L168 Benchmark]: CACSL2BoogieTranslator took 307.88 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 11:01:41,113 INFO L168 Benchmark]: Boogie Procedure Inliner took 23.66 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 11:01:41,113 INFO L168 Benchmark]: Boogie Preprocessor took 25.81 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 11:01:41,113 INFO L168 Benchmark]: RCFGBuilder took 342.07 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 739.8 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -782.0 MB). Peak memory consumption was 26.9 MB. Max. memory is 7.1 GB. [2018-07-24 11:01:41,113 INFO L168 Benchmark]: TraceAbstraction took 231858.76 ms. Allocated memory was 2.3 GB in the beginning and 2.2 GB in the end (delta: -102.2 MB). Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 98.0 MB). Peak memory consumption was 567.7 MB. Max. memory is 7.1 GB. [2018-07-24 11:01:41,115 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.31 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 307.88 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 23.66 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 25.81 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 342.07 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 739.8 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -782.0 MB). Peak memory consumption was 26.9 MB. Max. memory is 7.1 GB. * TraceAbstraction took 231858.76 ms. Allocated memory was 2.3 GB in the beginning and 2.2 GB in the end (delta: -102.2 MB). Free memory was 2.2 GB in the beginning and 2.1 GB in the end (delta: 98.0 MB). Peak memory consumption was 567.7 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was analyzing trace of length 216 with TraceHistMax 69, while TraceCheckSpWp was constructing backward predicates, while PredicateComparison was comparing new predicate (quantifier-free) to 119 known predicates. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 20 locations, 1 error locations. TIMEOUT Result, 231.8s OverallTime, 70 OverallIterations, 69 TraceHistogramMax, 12.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 768 SDtfs, 2346 SDslu, 12146 SDs, 0 SdLazy, 6053 SolverSat, 125 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 9.2s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 32634 GetRequests, 27943 SyntacticMatches, 0 SemanticMatches, 4691 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 186.2s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=216occurred in iteration=69, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.2s AutomataMinimizationTime, 69 MinimizatonAttempts, 68 StatesRemovedByMinimization, 68 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 0.3s SsaConstructionTime, 12.7s SatisfiabilityAnalysisTime, 195.2s InterpolantComputationTime, 22734 NumberOfCodeBlocks, 22734 NumberOfCodeBlocksAsserted, 2535 NumberOfCheckSat, 37539 ConstructedInterpolants, 0 QuantifiedInterpolants, 15389451 SizeOfPredicates, 134 NumberOfNonLiveVariables, 21306 ConjunctsInSsa, 4824 ConjunctsInUnsatCore, 337 InterpolantComputations, 2 PerfectInterpolantSequences, 0/774520 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/count_by_2_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_11-01-41-124.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/count_by_2_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_11-01-41-124.csv Completed graceful shutdown