java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-invgen/down_true-unreach-call_true-termination.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:53:54,139 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:53:54,141 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:53:54,158 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:53:54,158 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:53:54,160 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:53:54,162 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:53:54,164 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:53:54,167 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:53:54,168 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:53:54,176 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:53:54,176 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:53:54,177 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:53:54,178 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:53:54,181 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:53:54,182 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:53:54,183 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:53:54,186 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:53:54,189 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:53:54,190 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:53:54,191 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:53:54,192 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:53:54,194 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:53:54,195 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:53:54,195 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:53:54,195 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:53:54,196 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:53:54,197 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:53:54,198 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:53:54,199 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:53:54,199 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:53:54,199 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:53:54,200 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:53:54,200 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:53:54,201 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:53:54,201 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:53:54,202 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:53:54,219 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:53:54,220 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:53:54,220 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:53:54,221 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:53:54,221 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:53:54,221 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:53:54,221 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:53:54,221 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:53:54,222 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:53:54,222 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:53:54,222 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:53:54,222 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:53:54,223 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:53:54,223 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:53:54,223 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:53:54,223 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:53:54,223 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:53:54,224 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:53:54,224 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:53:54,224 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:53:54,224 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:53:54,224 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:53:54,225 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:53:54,225 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:53:54,225 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:53:54,225 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:53:54,225 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:53:54,226 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:53:54,226 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:53:54,226 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:53:54,226 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:53:54,226 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:53:54,227 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:53:54,280 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:53:54,295 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:53:54,301 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:53:54,302 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:53:54,303 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:53:54,304 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-invgen/down_true-unreach-call_true-termination.i [2018-07-24 10:53:54,662 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b961a9a8b/4138ad675b72452bab5c87cacdbbb44b/FLAGb721c55b5 [2018-07-24 10:53:54,804 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:53:54,804 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-invgen/down_true-unreach-call_true-termination.i [2018-07-24 10:53:54,811 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b961a9a8b/4138ad675b72452bab5c87cacdbbb44b/FLAGb721c55b5 [2018-07-24 10:53:54,833 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/b961a9a8b/4138ad675b72452bab5c87cacdbbb44b [2018-07-24 10:53:54,845 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:53:54,847 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:53:54,849 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:53:54,849 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:53:54,857 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:53:54,858 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:53:54" (1/1) ... [2018-07-24 10:53:54,861 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@37778f3c and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:54, skipping insertion in model container [2018-07-24 10:53:54,861 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:53:54" (1/1) ... [2018-07-24 10:53:55,035 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:53:55,066 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:53:55,081 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:53:55,086 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:53:55,096 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55 WrapperNode [2018-07-24 10:53:55,096 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:53:55,097 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:53:55,097 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:53:55,097 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:53:55,107 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,113 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,119 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:53:55,119 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:53:55,119 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:53:55,119 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:53:55,128 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,129 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,130 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,130 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,132 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,137 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,138 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... [2018-07-24 10:53:55,139 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:53:55,139 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:53:55,140 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:53:55,140 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:53:55,141 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:53:55,197 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:53:55,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:53:55,198 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:53:55,198 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assert [2018-07-24 10:53:55,198 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:53:55,198 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:53:55,199 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:53:55,199 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:53:55,469 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:53:55,470 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:53:55 BoogieIcfgContainer [2018-07-24 10:53:55,470 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:53:55,471 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:53:55,471 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:53:55,475 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:53:55,475 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:53:54" (1/3) ... [2018-07-24 10:53:55,476 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@51c7facf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:53:55, skipping insertion in model container [2018-07-24 10:53:55,476 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:53:55" (2/3) ... [2018-07-24 10:53:55,477 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@51c7facf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:53:55, skipping insertion in model container [2018-07-24 10:53:55,477 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:53:55" (3/3) ... [2018-07-24 10:53:55,479 INFO L112 eAbstractionObserver]: Analyzing ICFG down_true-unreach-call_true-termination.i [2018-07-24 10:53:55,501 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:53:55,509 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:53:55,557 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:53:55,558 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:53:55,558 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:53:55,558 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:53:55,558 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:53:55,558 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:53:55,558 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:53:55,558 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:53:55,559 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:53:55,574 INFO L276 IsEmpty]: Start isEmpty. Operand 23 states. [2018-07-24 10:53:55,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-07-24 10:53:55,579 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:55,580 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:55,580 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:55,586 INFO L82 PathProgramCache]: Analyzing trace with hash 910151092, now seen corresponding path program 1 times [2018-07-24 10:53:55,589 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:55,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:55,643 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:55,643 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:55,644 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:55,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:55,699 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:55,701 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:53:55,701 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:53:55,702 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:53:55,706 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:53:55,721 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:53:55,721 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:53:55,723 INFO L87 Difference]: Start difference. First operand 23 states. Second operand 2 states. [2018-07-24 10:53:55,742 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:55,742 INFO L93 Difference]: Finished difference Result 39 states and 46 transitions. [2018-07-24 10:53:55,743 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:53:55,744 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 13 [2018-07-24 10:53:55,744 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:55,753 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:53:55,753 INFO L226 Difference]: Without dead ends: 18 [2018-07-24 10:53:55,756 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:53:55,773 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-07-24 10:53:55,789 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-07-24 10:53:55,791 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:53:55,792 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2018-07-24 10:53:55,794 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 19 transitions. Word has length 13 [2018-07-24 10:53:55,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:55,794 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 19 transitions. [2018-07-24 10:53:55,794 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:53:55,795 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 19 transitions. [2018-07-24 10:53:55,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:53:55,795 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:55,796 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:55,796 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:55,796 INFO L82 PathProgramCache]: Analyzing trace with hash -1578698797, now seen corresponding path program 1 times [2018-07-24 10:53:55,796 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:55,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:55,798 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:55,798 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:55,798 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:55,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:56,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,020 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:53:56,021 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2018-07-24 10:53:56,021 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:53:56,024 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:53:56,025 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:53:56,026 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2018-07-24 10:53:56,026 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. Second operand 5 states. [2018-07-24 10:53:56,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:56,133 INFO L93 Difference]: Finished difference Result 33 states and 35 transitions. [2018-07-24 10:53:56,133 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:53:56,133 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 14 [2018-07-24 10:53:56,134 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:56,134 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:53:56,135 INFO L226 Difference]: Without dead ends: 20 [2018-07-24 10:53:56,136 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=17, Invalid=25, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:53:56,136 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-07-24 10:53:56,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-07-24 10:53:56,140 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-07-24 10:53:56,141 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 21 transitions. [2018-07-24 10:53:56,141 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 21 transitions. Word has length 14 [2018-07-24 10:53:56,142 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:56,142 INFO L471 AbstractCegarLoop]: Abstraction has 20 states and 21 transitions. [2018-07-24 10:53:56,142 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:53:56,142 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 21 transitions. [2018-07-24 10:53:56,143 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 17 [2018-07-24 10:53:56,143 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:56,143 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:56,143 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:56,144 INFO L82 PathProgramCache]: Analyzing trace with hash -1516611795, now seen corresponding path program 1 times [2018-07-24 10:53:56,144 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:56,145 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:56,145 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:56,146 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:56,146 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:56,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:56,270 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,271 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:53:56,271 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [6] imperfect sequences [] total 6 [2018-07-24 10:53:56,271 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:53:56,272 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:53:56,272 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:53:56,272 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=10, Invalid=20, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:53:56,273 INFO L87 Difference]: Start difference. First operand 20 states and 21 transitions. Second operand 6 states. [2018-07-24 10:53:56,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:56,459 INFO L93 Difference]: Finished difference Result 34 states and 36 transitions. [2018-07-24 10:53:56,463 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:53:56,463 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 16 [2018-07-24 10:53:56,463 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:56,466 INFO L225 Difference]: With dead ends: 34 [2018-07-24 10:53:56,466 INFO L226 Difference]: Without dead ends: 32 [2018-07-24 10:53:56,467 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 7 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:53:56,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-07-24 10:53:56,483 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 27. [2018-07-24 10:53:56,484 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:53:56,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2018-07-24 10:53:56,485 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 28 transitions. Word has length 16 [2018-07-24 10:53:56,485 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:56,488 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 28 transitions. [2018-07-24 10:53:56,488 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:53:56,488 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 28 transitions. [2018-07-24 10:53:56,489 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 25 [2018-07-24 10:53:56,489 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:56,489 INFO L353 BasicCegarLoop]: trace histogram [2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:56,491 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:56,491 INFO L82 PathProgramCache]: Analyzing trace with hash 894011864, now seen corresponding path program 1 times [2018-07-24 10:53:56,491 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:56,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:56,493 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:56,493 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:56,493 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:56,520 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:56,709 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,709 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:56,710 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:56,727 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:56,727 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:56,756 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:56,764 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:56,788 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,788 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:56,872 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:56,895 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:56,911 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:56,911 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:56,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:56,935 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:56,943 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,944 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:57,042 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 5 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:57,044 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:57,045 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 7 [2018-07-24 10:53:57,045 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:57,045 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:53:57,046 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:53:57,046 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=29, Unknown=0, NotChecked=0, Total=42 [2018-07-24 10:53:57,046 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. Second operand 7 states. [2018-07-24 10:53:57,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:57,288 INFO L93 Difference]: Finished difference Result 46 states and 49 transitions. [2018-07-24 10:53:57,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:53:57,288 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 24 [2018-07-24 10:53:57,289 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:57,293 INFO L225 Difference]: With dead ends: 46 [2018-07-24 10:53:57,293 INFO L226 Difference]: Without dead ends: 29 [2018-07-24 10:53:57,295 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 104 GetRequests, 88 SyntacticMatches, 8 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=31, Invalid=59, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:53:57,295 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 29 states. [2018-07-24 10:53:57,303 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 29 to 29. [2018-07-24 10:53:57,303 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 29 states. [2018-07-24 10:53:57,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 29 states to 29 states and 30 transitions. [2018-07-24 10:53:57,304 INFO L78 Accepts]: Start accepts. Automaton has 29 states and 30 transitions. Word has length 24 [2018-07-24 10:53:57,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:57,305 INFO L471 AbstractCegarLoop]: Abstraction has 29 states and 30 transitions. [2018-07-24 10:53:57,305 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:53:57,305 INFO L276 IsEmpty]: Start isEmpty. Operand 29 states and 30 transitions. [2018-07-24 10:53:57,306 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:53:57,306 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:57,308 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:57,308 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:57,308 INFO L82 PathProgramCache]: Analyzing trace with hash -1409744718, now seen corresponding path program 2 times [2018-07-24 10:53:57,309 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:57,311 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:57,311 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:57,312 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:57,312 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:57,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:57,456 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 7 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:57,457 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:57,457 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:57,470 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:57,470 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:57,486 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:57,487 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:57,489 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:57,567 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:57,567 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:57,917 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:57,939 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:57,939 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:57,954 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:57,955 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:57,978 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:57,978 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:57,982 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:57,990 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:57,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:58,104 INFO L134 CoverageAnalysis]: Checked inductivity of 11 backedges. 8 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:58,106 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:58,106 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 7, 7, 7] total 10 [2018-07-24 10:53:58,106 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:58,107 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:53:58,107 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:53:58,107 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=68, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:53:58,108 INFO L87 Difference]: Start difference. First operand 29 states and 30 transitions. Second operand 10 states. [2018-07-24 10:53:58,234 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:58,234 INFO L93 Difference]: Finished difference Result 39 states and 40 transitions. [2018-07-24 10:53:58,235 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:53:58,235 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 26 [2018-07-24 10:53:58,235 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:58,236 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:53:58,236 INFO L226 Difference]: Without dead ends: 37 [2018-07-24 10:53:58,237 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 115 GetRequests, 93 SyntacticMatches, 12 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=35, Invalid=97, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:53:58,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37 states. [2018-07-24 10:53:58,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37 to 37. [2018-07-24 10:53:58,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 37 states. [2018-07-24 10:53:58,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37 states to 37 states and 38 transitions. [2018-07-24 10:53:58,245 INFO L78 Accepts]: Start accepts. Automaton has 37 states and 38 transitions. Word has length 26 [2018-07-24 10:53:58,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:58,246 INFO L471 AbstractCegarLoop]: Abstraction has 37 states and 38 transitions. [2018-07-24 10:53:58,246 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:53:58,246 INFO L276 IsEmpty]: Start isEmpty. Operand 37 states and 38 transitions. [2018-07-24 10:53:58,246 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 35 [2018-07-24 10:53:58,247 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:58,247 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:58,247 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:58,247 INFO L82 PathProgramCache]: Analyzing trace with hash 847044189, now seen corresponding path program 3 times [2018-07-24 10:53:58,247 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:58,248 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:58,249 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:58,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:58,249 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:58,265 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:58,371 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:58,371 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:58,371 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:58,389 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:58,390 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:58,413 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:53:58,414 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:58,418 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:58,428 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:58,428 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:58,534 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:58,554 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:58,555 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:58,571 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:58,572 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:58,605 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:53:58,605 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:58,609 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:58,618 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:58,618 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:58,773 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 6 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:58,775 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:58,775 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 9 [2018-07-24 10:53:58,775 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:58,776 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:53:58,776 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:53:58,776 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=51, Unknown=0, NotChecked=0, Total=72 [2018-07-24 10:53:58,777 INFO L87 Difference]: Start difference. First operand 37 states and 38 transitions. Second operand 9 states. [2018-07-24 10:53:58,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:58,971 INFO L93 Difference]: Finished difference Result 60 states and 64 transitions. [2018-07-24 10:53:58,972 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:53:58,972 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 34 [2018-07-24 10:53:58,972 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:58,973 INFO L225 Difference]: With dead ends: 60 [2018-07-24 10:53:58,973 INFO L226 Difference]: Without dead ends: 39 [2018-07-24 10:53:58,974 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 124 SyntacticMatches, 12 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 35 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=49, Invalid=107, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:53:58,974 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-07-24 10:53:58,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-07-24 10:53:58,980 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:53:58,981 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 40 transitions. [2018-07-24 10:53:58,981 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 40 transitions. Word has length 34 [2018-07-24 10:53:58,981 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:58,981 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 40 transitions. [2018-07-24 10:53:58,981 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:53:58,982 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 40 transitions. [2018-07-24 10:53:58,983 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 37 [2018-07-24 10:53:58,983 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:58,983 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:58,983 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:58,983 INFO L82 PathProgramCache]: Analyzing trace with hash -1886319433, now seen corresponding path program 4 times [2018-07-24 10:53:58,984 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:58,984 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:58,985 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:58,985 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:58,985 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:58,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:59,253 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 15 proven. 14 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-07-24 10:53:59,254 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:59,254 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:59,263 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:59,263 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:59,280 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:59,280 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:59,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:59,335 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:59,335 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:59,403 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:59,423 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:59,423 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:59,439 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:59,439 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:59,473 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:59,473 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:59,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:59,487 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:59,487 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:59,586 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 16 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 10:53:59,589 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:59,589 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 8, 8, 8, 8] total 11 [2018-07-24 10:53:59,589 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:59,590 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:53:59,590 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:53:59,590 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=83, Unknown=0, NotChecked=0, Total=110 [2018-07-24 10:53:59,591 INFO L87 Difference]: Start difference. First operand 39 states and 40 transitions. Second operand 11 states. [2018-07-24 10:53:59,732 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:59,732 INFO L93 Difference]: Finished difference Result 49 states and 50 transitions. [2018-07-24 10:53:59,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:53:59,733 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 36 [2018-07-24 10:53:59,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:59,735 INFO L225 Difference]: With dead ends: 49 [2018-07-24 10:53:59,735 INFO L226 Difference]: Without dead ends: 47 [2018-07-24 10:53:59,735 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 157 GetRequests, 130 SyntacticMatches, 16 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 59 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:53:59,736 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 47 states. [2018-07-24 10:53:59,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 47 to 47. [2018-07-24 10:53:59,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 47 states. [2018-07-24 10:53:59,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 47 states to 47 states and 48 transitions. [2018-07-24 10:53:59,742 INFO L78 Accepts]: Start accepts. Automaton has 47 states and 48 transitions. Word has length 36 [2018-07-24 10:53:59,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:59,743 INFO L471 AbstractCegarLoop]: Abstraction has 47 states and 48 transitions. [2018-07-24 10:53:59,743 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:53:59,743 INFO L276 IsEmpty]: Start isEmpty. Operand 47 states and 48 transitions. [2018-07-24 10:53:59,744 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 10:53:59,744 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:59,744 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:59,745 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:59,745 INFO L82 PathProgramCache]: Analyzing trace with hash 413078882, now seen corresponding path program 5 times [2018-07-24 10:53:59,745 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:59,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:59,746 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:59,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:59,746 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:59,758 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:59,913 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:53:59,913 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:59,913 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:59,921 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:59,921 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:59,937 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-07-24 10:53:59,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:59,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:59,951 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:53:59,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:00,057 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:00,077 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:00,077 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:00,094 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:00,094 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:00,136 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 4 check-sat command(s) [2018-07-24 10:54:00,136 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:00,140 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:00,150 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:00,151 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:00,254 INFO L134 CoverageAnalysis]: Checked inductivity of 51 backedges. 27 proven. 12 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:00,263 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:00,263 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 11 [2018-07-24 10:54:00,263 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:00,264 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:54:00,264 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:54:00,264 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=31, Invalid=79, Unknown=0, NotChecked=0, Total=110 [2018-07-24 10:54:00,265 INFO L87 Difference]: Start difference. First operand 47 states and 48 transitions. Second operand 11 states. [2018-07-24 10:54:00,477 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:00,477 INFO L93 Difference]: Finished difference Result 74 states and 79 transitions. [2018-07-24 10:54:00,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:00,480 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 44 [2018-07-24 10:54:00,481 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:00,481 INFO L225 Difference]: With dead ends: 74 [2018-07-24 10:54:00,482 INFO L226 Difference]: Without dead ends: 49 [2018-07-24 10:54:00,482 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 190 GetRequests, 160 SyntacticMatches, 16 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 69 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=71, Invalid=169, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:54:00,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49 states. [2018-07-24 10:54:00,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49 to 49. [2018-07-24 10:54:00,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 49 states. [2018-07-24 10:54:00,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 49 states to 49 states and 50 transitions. [2018-07-24 10:54:00,490 INFO L78 Accepts]: Start accepts. Automaton has 49 states and 50 transitions. Word has length 44 [2018-07-24 10:54:00,490 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:00,490 INFO L471 AbstractCegarLoop]: Abstraction has 49 states and 50 transitions. [2018-07-24 10:54:00,491 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:54:00,491 INFO L276 IsEmpty]: Start isEmpty. Operand 49 states and 50 transitions. [2018-07-24 10:54:00,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 47 [2018-07-24 10:54:00,492 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:00,492 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:00,493 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:00,493 INFO L82 PathProgramCache]: Analyzing trace with hash -1657234628, now seen corresponding path program 6 times [2018-07-24 10:54:00,493 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:00,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:00,494 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:00,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:00,494 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:00,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:00,623 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 25 proven. 28 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 10:54:00,624 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:00,624 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:00,631 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:00,631 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:00,686 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:00,687 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:00,690 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:00,777 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:00,777 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:00,854 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:00,874 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:00,874 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:00,891 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:00,891 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:00,941 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 5 check-sat command(s) [2018-07-24 10:54:00,941 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:00,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:00,955 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:00,956 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:01,040 INFO L134 CoverageAnalysis]: Checked inductivity of 59 backedges. 26 proven. 21 refuted. 0 times theorem prover too weak. 12 trivial. 0 not checked. [2018-07-24 10:54:01,042 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:01,042 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 9, 9, 9, 9] total 12 [2018-07-24 10:54:01,042 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:01,043 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:54:01,043 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:54:01,044 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:54:01,044 INFO L87 Difference]: Start difference. First operand 49 states and 50 transitions. Second operand 12 states. [2018-07-24 10:54:01,307 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:01,308 INFO L93 Difference]: Finished difference Result 59 states and 60 transitions. [2018-07-24 10:54:01,308 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:54:01,308 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 46 [2018-07-24 10:54:01,308 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:01,309 INFO L225 Difference]: With dead ends: 59 [2018-07-24 10:54:01,309 INFO L226 Difference]: Without dead ends: 57 [2018-07-24 10:54:01,310 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 167 SyntacticMatches, 20 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 84 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=46, Invalid=136, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:54:01,310 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 57 states. [2018-07-24 10:54:01,316 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 57 to 57. [2018-07-24 10:54:01,316 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:54:01,316 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 58 transitions. [2018-07-24 10:54:01,317 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 58 transitions. Word has length 46 [2018-07-24 10:54:01,317 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:01,317 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 58 transitions. [2018-07-24 10:54:01,317 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:54:01,318 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 58 transitions. [2018-07-24 10:54:01,318 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 55 [2018-07-24 10:54:01,319 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:01,319 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:01,319 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:01,319 INFO L82 PathProgramCache]: Analyzing trace with hash -1939452185, now seen corresponding path program 7 times [2018-07-24 10:54:01,319 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:01,320 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:01,320 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:01,321 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:01,321 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:01,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:01,479 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:01,479 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:01,479 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:01,486 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:01,487 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:01,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:01,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:01,522 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:01,522 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:02,133 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:02,154 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:02,154 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:02,170 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:02,170 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:02,209 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:02,213 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:02,224 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:02,225 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:02,656 INFO L134 CoverageAnalysis]: Checked inductivity of 88 backedges. 44 proven. 20 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:02,658 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:02,658 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 13 [2018-07-24 10:54:02,658 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:02,659 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:54:02,659 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:54:02,659 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=43, Invalid=113, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:02,659 INFO L87 Difference]: Start difference. First operand 57 states and 58 transitions. Second operand 13 states. [2018-07-24 10:54:02,936 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:02,936 INFO L93 Difference]: Finished difference Result 88 states and 94 transitions. [2018-07-24 10:54:02,937 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:54:02,937 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 54 [2018-07-24 10:54:02,937 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:02,938 INFO L225 Difference]: With dead ends: 88 [2018-07-24 10:54:02,938 INFO L226 Difference]: Without dead ends: 59 [2018-07-24 10:54:02,939 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 233 GetRequests, 196 SyntacticMatches, 20 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 114 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=97, Invalid=245, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:54:02,940 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 59 states. [2018-07-24 10:54:02,946 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 59 to 59. [2018-07-24 10:54:02,946 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 59 states. [2018-07-24 10:54:02,947 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 59 states to 59 states and 60 transitions. [2018-07-24 10:54:02,948 INFO L78 Accepts]: Start accepts. Automaton has 59 states and 60 transitions. Word has length 54 [2018-07-24 10:54:02,948 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:02,948 INFO L471 AbstractCegarLoop]: Abstraction has 59 states and 60 transitions. [2018-07-24 10:54:02,948 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:54:02,948 INFO L276 IsEmpty]: Start isEmpty. Operand 59 states and 60 transitions. [2018-07-24 10:54:02,949 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:54:02,949 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:02,950 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:02,950 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:02,950 INFO L82 PathProgramCache]: Analyzing trace with hash -2124559295, now seen corresponding path program 8 times [2018-07-24 10:54:02,953 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:02,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:02,954 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:02,954 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:02,955 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:02,972 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:03,281 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 37 proven. 46 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:54:03,282 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:03,282 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:03,293 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:03,293 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:03,328 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:03,328 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:03,331 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:03,492 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:03,492 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:03,620 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:03,641 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:03,641 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:03,657 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:03,657 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:03,698 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:03,698 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:03,701 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:03,711 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:03,712 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:04,034 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 36 refuted. 0 times theorem prover too weak. 24 trivial. 0 not checked. [2018-07-24 10:54:04,035 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:04,035 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 10, 10, 10, 10] total 13 [2018-07-24 10:54:04,035 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:04,036 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:54:04,036 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:54:04,036 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=40, Invalid=116, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:54:04,036 INFO L87 Difference]: Start difference. First operand 59 states and 60 transitions. Second operand 13 states. [2018-07-24 10:54:04,157 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:04,157 INFO L93 Difference]: Finished difference Result 69 states and 70 transitions. [2018-07-24 10:54:04,157 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:54:04,157 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 56 [2018-07-24 10:54:04,158 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:04,158 INFO L225 Difference]: With dead ends: 69 [2018-07-24 10:54:04,158 INFO L226 Difference]: Without dead ends: 67 [2018-07-24 10:54:04,159 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 241 GetRequests, 204 SyntacticMatches, 24 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 113 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=53, Invalid=157, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:04,159 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67 states. [2018-07-24 10:54:04,164 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67 to 67. [2018-07-24 10:54:04,165 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 67 states. [2018-07-24 10:54:04,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67 states to 67 states and 68 transitions. [2018-07-24 10:54:04,166 INFO L78 Accepts]: Start accepts. Automaton has 67 states and 68 transitions. Word has length 56 [2018-07-24 10:54:04,166 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:04,166 INFO L471 AbstractCegarLoop]: Abstraction has 67 states and 68 transitions. [2018-07-24 10:54:04,166 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:54:04,166 INFO L276 IsEmpty]: Start isEmpty. Operand 67 states and 68 transitions. [2018-07-24 10:54:04,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 65 [2018-07-24 10:54:04,167 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:04,167 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:04,168 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:04,168 INFO L82 PathProgramCache]: Analyzing trace with hash 2048961260, now seen corresponding path program 9 times [2018-07-24 10:54:04,168 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:04,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:04,169 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:04,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:04,169 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:04,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:04,380 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:04,380 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:04,380 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:04,387 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:04,387 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:04,413 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:54:04,413 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:04,415 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:04,424 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:04,424 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:04,604 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:04,624 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:04,625 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:04,641 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:04,641 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:04,705 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:54:04,705 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:04,709 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:04,720 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:04,720 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:04,854 INFO L134 CoverageAnalysis]: Checked inductivity of 135 backedges. 65 proven. 30 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:04,855 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:04,856 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 15 [2018-07-24 10:54:04,856 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:04,856 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:54:04,857 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:54:04,857 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:04,857 INFO L87 Difference]: Start difference. First operand 67 states and 68 transitions. Second operand 15 states. [2018-07-24 10:54:05,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:05,227 INFO L93 Difference]: Finished difference Result 102 states and 109 transitions. [2018-07-24 10:54:05,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:54:05,227 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 64 [2018-07-24 10:54:05,228 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:05,229 INFO L225 Difference]: With dead ends: 102 [2018-07-24 10:54:05,229 INFO L226 Difference]: Without dead ends: 69 [2018-07-24 10:54:05,231 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 276 GetRequests, 232 SyntacticMatches, 24 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 170 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=127, Invalid=335, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:54:05,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69 states. [2018-07-24 10:54:05,238 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69 to 69. [2018-07-24 10:54:05,238 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:54:05,239 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 70 transitions. [2018-07-24 10:54:05,239 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 70 transitions. Word has length 64 [2018-07-24 10:54:05,240 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:05,240 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 70 transitions. [2018-07-24 10:54:05,240 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:54:05,240 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 70 transitions. [2018-07-24 10:54:05,241 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 67 [2018-07-24 10:54:05,241 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:05,241 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:05,242 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:05,242 INFO L82 PathProgramCache]: Analyzing trace with hash -368656442, now seen corresponding path program 10 times [2018-07-24 10:54:05,242 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:05,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:05,243 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:05,243 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:05,243 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:05,268 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:05,416 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 51 proven. 68 refuted. 0 times theorem prover too weak. 28 trivial. 0 not checked. [2018-07-24 10:54:05,416 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:05,416 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:05,425 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:05,425 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:05,447 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:05,447 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:05,449 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:05,508 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:05,508 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:05,588 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:05,608 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:05,609 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:05,626 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:05,626 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:05,680 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:05,680 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:05,683 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:05,693 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:05,694 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:05,938 INFO L134 CoverageAnalysis]: Checked inductivity of 147 backedges. 52 proven. 55 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:54:05,940 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:05,940 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 14 [2018-07-24 10:54:05,940 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:05,941 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:54:05,941 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:54:05,941 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=134, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:54:05,942 INFO L87 Difference]: Start difference. First operand 69 states and 70 transitions. Second operand 14 states. [2018-07-24 10:54:06,094 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:06,095 INFO L93 Difference]: Finished difference Result 79 states and 80 transitions. [2018-07-24 10:54:06,099 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:54:06,100 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 66 [2018-07-24 10:54:06,100 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:06,101 INFO L225 Difference]: With dead ends: 79 [2018-07-24 10:54:06,101 INFO L226 Difference]: Without dead ends: 77 [2018-07-24 10:54:06,101 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 241 SyntacticMatches, 28 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 146 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=61, Invalid=179, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:54:06,102 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 77 states. [2018-07-24 10:54:06,106 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 77 to 77. [2018-07-24 10:54:06,106 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 77 states. [2018-07-24 10:54:06,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77 states to 77 states and 78 transitions. [2018-07-24 10:54:06,107 INFO L78 Accepts]: Start accepts. Automaton has 77 states and 78 transitions. Word has length 66 [2018-07-24 10:54:06,108 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:06,108 INFO L471 AbstractCegarLoop]: Abstraction has 77 states and 78 transitions. [2018-07-24 10:54:06,108 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:54:06,108 INFO L276 IsEmpty]: Start isEmpty. Operand 77 states and 78 transitions. [2018-07-24 10:54:06,111 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:54:06,111 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:06,111 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:06,111 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:06,111 INFO L82 PathProgramCache]: Analyzing trace with hash -1212921487, now seen corresponding path program 11 times [2018-07-24 10:54:06,112 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:06,112 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:06,112 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:06,113 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:06,113 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:06,123 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:06,298 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:06,298 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:06,298 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:06,305 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:06,306 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:06,331 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:54:06,332 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:06,334 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:06,344 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:06,344 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:06,480 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:06,500 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:06,500 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:06,515 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:06,515 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:06,601 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 7 check-sat command(s) [2018-07-24 10:54:06,601 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:06,605 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:06,615 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:06,615 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:06,773 INFO L134 CoverageAnalysis]: Checked inductivity of 192 backedges. 90 proven. 42 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:06,775 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:06,775 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 17 [2018-07-24 10:54:06,775 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:06,775 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:54:06,776 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:54:06,776 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=73, Invalid=199, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:54:06,776 INFO L87 Difference]: Start difference. First operand 77 states and 78 transitions. Second operand 17 states. [2018-07-24 10:54:07,217 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:07,217 INFO L93 Difference]: Finished difference Result 116 states and 124 transitions. [2018-07-24 10:54:07,217 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:07,217 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 74 [2018-07-24 10:54:07,218 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:07,218 INFO L225 Difference]: With dead ends: 116 [2018-07-24 10:54:07,218 INFO L226 Difference]: Without dead ends: 79 [2018-07-24 10:54:07,219 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 319 GetRequests, 268 SyntacticMatches, 28 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 237 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=161, Invalid=439, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:54:07,220 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 79 states. [2018-07-24 10:54:07,229 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 79 to 79. [2018-07-24 10:54:07,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 79 states. [2018-07-24 10:54:07,233 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 79 states to 79 states and 80 transitions. [2018-07-24 10:54:07,234 INFO L78 Accepts]: Start accepts. Automaton has 79 states and 80 transitions. Word has length 74 [2018-07-24 10:54:07,234 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:07,234 INFO L471 AbstractCegarLoop]: Abstraction has 79 states and 80 transitions. [2018-07-24 10:54:07,234 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:54:07,234 INFO L276 IsEmpty]: Start isEmpty. Operand 79 states and 80 transitions. [2018-07-24 10:54:07,235 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 77 [2018-07-24 10:54:07,235 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:07,236 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:07,236 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:07,236 INFO L82 PathProgramCache]: Analyzing trace with hash -1462659637, now seen corresponding path program 12 times [2018-07-24 10:54:07,236 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:07,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:07,238 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:07,239 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:07,239 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:07,249 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:07,406 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 67 proven. 94 refuted. 0 times theorem prover too weak. 45 trivial. 0 not checked. [2018-07-24 10:54:07,406 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:07,406 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:07,413 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:07,413 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:07,444 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:54:07,445 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:07,446 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:07,509 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:07,510 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:07,827 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:07,847 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:07,847 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:07,862 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:07,863 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:07,951 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 8 check-sat command(s) [2018-07-24 10:54:07,951 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:07,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:07,962 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:07,963 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:08,148 INFO L134 CoverageAnalysis]: Checked inductivity of 206 backedges. 68 proven. 78 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 10:54:08,149 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:08,150 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 12, 12, 12, 12] total 15 [2018-07-24 10:54:08,150 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:08,150 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:54:08,150 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:54:08,151 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=57, Invalid=153, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:54:08,151 INFO L87 Difference]: Start difference. First operand 79 states and 80 transitions. Second operand 15 states. [2018-07-24 10:54:08,351 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:08,351 INFO L93 Difference]: Finished difference Result 89 states and 90 transitions. [2018-07-24 10:54:08,353 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:54:08,354 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 76 [2018-07-24 10:54:08,354 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:08,355 INFO L225 Difference]: With dead ends: 89 [2018-07-24 10:54:08,355 INFO L226 Difference]: Without dead ends: 87 [2018-07-24 10:54:08,356 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 325 GetRequests, 278 SyntacticMatches, 32 SemanticMatches, 15 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 183 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=70, Invalid=202, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:54:08,356 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 87 states. [2018-07-24 10:54:08,362 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 87 to 87. [2018-07-24 10:54:08,362 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 87 states. [2018-07-24 10:54:08,363 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 87 states to 87 states and 88 transitions. [2018-07-24 10:54:08,363 INFO L78 Accepts]: Start accepts. Automaton has 87 states and 88 transitions. Word has length 76 [2018-07-24 10:54:08,363 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:08,363 INFO L471 AbstractCegarLoop]: Abstraction has 87 states and 88 transitions. [2018-07-24 10:54:08,364 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:54:08,364 INFO L276 IsEmpty]: Start isEmpty. Operand 87 states and 88 transitions. [2018-07-24 10:54:08,365 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 85 [2018-07-24 10:54:08,365 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:08,365 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:08,365 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:08,365 INFO L82 PathProgramCache]: Analyzing trace with hash 647973494, now seen corresponding path program 13 times [2018-07-24 10:54:08,365 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:08,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:08,366 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:08,366 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:08,367 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:08,375 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:08,584 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:08,584 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:08,584 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:08,593 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:08,593 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:08,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:08,623 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:08,640 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:08,640 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:08,863 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:08,883 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:08,883 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:08,898 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:08,898 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:08,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:08,957 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:08,967 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:08,967 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:09,120 INFO L134 CoverageAnalysis]: Checked inductivity of 259 backedges. 119 proven. 56 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:09,122 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:09,122 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 19 [2018-07-24 10:54:09,122 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:09,123 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:54:09,123 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:54:09,123 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:54:09,123 INFO L87 Difference]: Start difference. First operand 87 states and 88 transitions. Second operand 19 states. [2018-07-24 10:54:09,424 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:09,424 INFO L93 Difference]: Finished difference Result 130 states and 139 transitions. [2018-07-24 10:54:09,425 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:54:09,425 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 84 [2018-07-24 10:54:09,425 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:09,427 INFO L225 Difference]: With dead ends: 130 [2018-07-24 10:54:09,427 INFO L226 Difference]: Without dead ends: 89 [2018-07-24 10:54:09,428 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 362 GetRequests, 304 SyntacticMatches, 32 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 315 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=199, Invalid=557, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:54:09,428 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89 states. [2018-07-24 10:54:09,433 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89 to 89. [2018-07-24 10:54:09,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 89 states. [2018-07-24 10:54:09,433 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89 states to 89 states and 90 transitions. [2018-07-24 10:54:09,434 INFO L78 Accepts]: Start accepts. Automaton has 89 states and 90 transitions. Word has length 84 [2018-07-24 10:54:09,434 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:09,434 INFO L471 AbstractCegarLoop]: Abstraction has 89 states and 90 transitions. [2018-07-24 10:54:09,434 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:54:09,434 INFO L276 IsEmpty]: Start isEmpty. Operand 89 states and 90 transitions. [2018-07-24 10:54:09,435 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 87 [2018-07-24 10:54:09,435 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:09,435 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 8, 8, 8, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:09,435 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:09,436 INFO L82 PathProgramCache]: Analyzing trace with hash 1425305168, now seen corresponding path program 14 times [2018-07-24 10:54:09,436 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:09,436 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:09,436 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:09,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:09,437 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:09,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:09,604 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 85 proven. 124 refuted. 0 times theorem prover too weak. 66 trivial. 0 not checked. [2018-07-24 10:54:09,604 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:09,605 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:09,613 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:09,613 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:09,653 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:09,654 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:09,656 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:09,714 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:09,714 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:09,892 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:09,912 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:09,912 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:09,928 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:09,928 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:09,987 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:09,987 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:09,991 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:10,002 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:10,002 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:10,153 INFO L134 CoverageAnalysis]: Checked inductivity of 275 backedges. 86 proven. 105 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:54:10,154 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:10,155 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 13, 13, 13] total 16 [2018-07-24 10:54:10,155 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:10,155 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:54:10,155 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:54:10,155 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=67, Invalid=173, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:54:10,155 INFO L87 Difference]: Start difference. First operand 89 states and 90 transitions. Second operand 16 states. [2018-07-24 10:54:10,335 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:10,335 INFO L93 Difference]: Finished difference Result 99 states and 100 transitions. [2018-07-24 10:54:10,335 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:54:10,336 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 86 [2018-07-24 10:54:10,336 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:10,337 INFO L225 Difference]: With dead ends: 99 [2018-07-24 10:54:10,337 INFO L226 Difference]: Without dead ends: 97 [2018-07-24 10:54:10,338 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 367 GetRequests, 315 SyntacticMatches, 36 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 224 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=80, Invalid=226, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:54:10,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97 states. [2018-07-24 10:54:10,343 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97 to 97. [2018-07-24 10:54:10,343 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 97 states. [2018-07-24 10:54:10,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97 states to 97 states and 98 transitions. [2018-07-24 10:54:10,344 INFO L78 Accepts]: Start accepts. Automaton has 97 states and 98 transitions. Word has length 86 [2018-07-24 10:54:10,344 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:10,344 INFO L471 AbstractCegarLoop]: Abstraction has 97 states and 98 transitions. [2018-07-24 10:54:10,344 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:54:10,344 INFO L276 IsEmpty]: Start isEmpty. Operand 97 states and 98 transitions. [2018-07-24 10:54:10,345 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 95 [2018-07-24 10:54:10,345 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:10,346 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:10,346 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:10,346 INFO L82 PathProgramCache]: Analyzing trace with hash 1442303483, now seen corresponding path program 15 times [2018-07-24 10:54:10,346 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:10,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:10,347 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:10,347 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:10,347 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:10,355 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:10,746 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:10,746 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:10,746 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:10,754 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:10,755 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:10,791 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:54:10,791 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:10,794 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:10,805 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:10,805 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:10,942 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:10,962 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:10,962 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:10,976 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:10,977 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:11,090 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:54:11,090 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:11,096 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:11,109 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:11,109 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:11,383 INFO L134 CoverageAnalysis]: Checked inductivity of 336 backedges. 152 proven. 72 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:11,384 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:11,385 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 21 [2018-07-24 10:54:11,385 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:11,385 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:54:11,385 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:54:11,386 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=111, Invalid=309, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:54:11,386 INFO L87 Difference]: Start difference. First operand 97 states and 98 transitions. Second operand 21 states. [2018-07-24 10:54:11,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:11,681 INFO L93 Difference]: Finished difference Result 144 states and 154 transitions. [2018-07-24 10:54:11,682 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:54:11,682 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 94 [2018-07-24 10:54:11,682 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:11,683 INFO L225 Difference]: With dead ends: 144 [2018-07-24 10:54:11,683 INFO L226 Difference]: Without dead ends: 99 [2018-07-24 10:54:11,684 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 405 GetRequests, 340 SyntacticMatches, 36 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 404 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=241, Invalid=689, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:54:11,684 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-07-24 10:54:11,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-07-24 10:54:11,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-24 10:54:11,691 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 100 transitions. [2018-07-24 10:54:11,691 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 100 transitions. Word has length 94 [2018-07-24 10:54:11,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:11,691 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 100 transitions. [2018-07-24 10:54:11,691 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:54:11,692 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 100 transitions. [2018-07-24 10:54:11,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 97 [2018-07-24 10:54:11,693 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:11,693 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 9, 9, 9, 9, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:11,693 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:11,693 INFO L82 PathProgramCache]: Analyzing trace with hash 1832741205, now seen corresponding path program 16 times [2018-07-24 10:54:11,693 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:11,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:11,694 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:11,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:11,694 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:11,703 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:12,475 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 105 proven. 158 refuted. 0 times theorem prover too weak. 91 trivial. 0 not checked. [2018-07-24 10:54:12,476 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:12,476 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:12,483 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:12,483 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:12,515 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:12,515 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:12,517 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:12,559 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:12,559 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:12,786 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:12,805 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:12,805 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:12,821 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:12,822 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:12,895 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:12,895 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:12,899 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:12,912 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:12,913 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:13,115 INFO L134 CoverageAnalysis]: Checked inductivity of 354 backedges. 106 proven. 136 refuted. 0 times theorem prover too weak. 112 trivial. 0 not checked. [2018-07-24 10:54:13,117 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:13,117 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 14, 14, 14, 14] total 17 [2018-07-24 10:54:13,117 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:13,117 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:54:13,118 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:54:13,118 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=194, Unknown=0, NotChecked=0, Total=272 [2018-07-24 10:54:13,118 INFO L87 Difference]: Start difference. First operand 99 states and 100 transitions. Second operand 17 states. [2018-07-24 10:54:13,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:13,296 INFO L93 Difference]: Finished difference Result 109 states and 110 transitions. [2018-07-24 10:54:13,297 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:54:13,297 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 96 [2018-07-24 10:54:13,297 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:13,298 INFO L225 Difference]: With dead ends: 109 [2018-07-24 10:54:13,299 INFO L226 Difference]: Without dead ends: 107 [2018-07-24 10:54:13,299 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 409 GetRequests, 352 SyntacticMatches, 40 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 269 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=91, Invalid=251, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:54:13,299 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107 states. [2018-07-24 10:54:13,304 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107 to 107. [2018-07-24 10:54:13,304 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 107 states. [2018-07-24 10:54:13,305 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 107 states to 107 states and 108 transitions. [2018-07-24 10:54:13,305 INFO L78 Accepts]: Start accepts. Automaton has 107 states and 108 transitions. Word has length 96 [2018-07-24 10:54:13,305 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:13,306 INFO L471 AbstractCegarLoop]: Abstraction has 107 states and 108 transitions. [2018-07-24 10:54:13,306 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:54:13,306 INFO L276 IsEmpty]: Start isEmpty. Operand 107 states and 108 transitions. [2018-07-24 10:54:13,307 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-07-24 10:54:13,307 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:13,307 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:13,307 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:13,307 INFO L82 PathProgramCache]: Analyzing trace with hash -1536429056, now seen corresponding path program 17 times [2018-07-24 10:54:13,307 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:13,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:13,308 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:13,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:13,308 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:13,317 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:13,580 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:13,580 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:13,580 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:13,589 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:13,589 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:13,625 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:54:13,626 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:13,628 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:13,646 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:13,646 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:13,870 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:13,889 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:13,889 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:13,904 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:13,905 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:14,037 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:54:14,037 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:14,041 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:14,057 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:14,057 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:14,756 INFO L134 CoverageAnalysis]: Checked inductivity of 423 backedges. 189 proven. 90 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (35)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:54:14,761 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:14,761 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 23 [2018-07-24 10:54:14,761 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:14,761 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:54:14,762 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:54:14,762 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=133, Invalid=373, Unknown=0, NotChecked=0, Total=506 [2018-07-24 10:54:14,762 INFO L87 Difference]: Start difference. First operand 107 states and 108 transitions. Second operand 23 states. [2018-07-24 10:54:15,180 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:15,180 INFO L93 Difference]: Finished difference Result 158 states and 169 transitions. [2018-07-24 10:54:15,181 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:54:15,181 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 104 [2018-07-24 10:54:15,182 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:15,183 INFO L225 Difference]: With dead ends: 158 [2018-07-24 10:54:15,183 INFO L226 Difference]: Without dead ends: 109 [2018-07-24 10:54:15,184 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 448 GetRequests, 376 SyntacticMatches, 40 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 504 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=287, Invalid=835, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:15,184 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 109 states. [2018-07-24 10:54:15,189 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 109 to 109. [2018-07-24 10:54:15,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 109 states. [2018-07-24 10:54:15,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 109 states to 109 states and 110 transitions. [2018-07-24 10:54:15,190 INFO L78 Accepts]: Start accepts. Automaton has 109 states and 110 transitions. Word has length 104 [2018-07-24 10:54:15,191 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:15,191 INFO L471 AbstractCegarLoop]: Abstraction has 109 states and 110 transitions. [2018-07-24 10:54:15,191 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:54:15,191 INFO L276 IsEmpty]: Start isEmpty. Operand 109 states and 110 transitions. [2018-07-24 10:54:15,192 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-07-24 10:54:15,192 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:15,192 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 10, 10, 10, 9, 9, 9, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:15,192 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:15,192 INFO L82 PathProgramCache]: Analyzing trace with hash -99440934, now seen corresponding path program 18 times [2018-07-24 10:54:15,193 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:15,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:15,193 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:15,193 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:15,194 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:15,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:16,133 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 127 proven. 196 refuted. 0 times theorem prover too weak. 120 trivial. 0 not checked. [2018-07-24 10:54:16,133 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:16,133 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:16,140 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:16,140 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:16,176 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:54:16,176 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:16,179 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:16,224 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:16,224 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:16,523 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:16,544 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:16,544 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:16,559 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:16,559 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:16,706 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 11 check-sat command(s) [2018-07-24 10:54:16,707 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:16,712 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:16,728 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:16,728 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:17,559 INFO L134 CoverageAnalysis]: Checked inductivity of 443 backedges. 128 proven. 171 refuted. 0 times theorem prover too weak. 144 trivial. 0 not checked. [2018-07-24 10:54:17,561 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:17,561 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 15, 15, 15, 15] total 18 [2018-07-24 10:54:17,561 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:17,561 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:54:17,562 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:54:17,562 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=90, Invalid=216, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:54:17,562 INFO L87 Difference]: Start difference. First operand 109 states and 110 transitions. Second operand 18 states. [2018-07-24 10:54:17,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:17,785 INFO L93 Difference]: Finished difference Result 119 states and 120 transitions. [2018-07-24 10:54:17,785 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:17,785 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 106 [2018-07-24 10:54:17,785 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:17,787 INFO L225 Difference]: With dead ends: 119 [2018-07-24 10:54:17,787 INFO L226 Difference]: Without dead ends: 117 [2018-07-24 10:54:17,788 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 451 GetRequests, 389 SyntacticMatches, 44 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 318 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=103, Invalid=277, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:54:17,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-07-24 10:54:17,793 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-07-24 10:54:17,793 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-07-24 10:54:17,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 118 transitions. [2018-07-24 10:54:17,794 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 118 transitions. Word has length 106 [2018-07-24 10:54:17,794 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:17,794 INFO L471 AbstractCegarLoop]: Abstraction has 117 states and 118 transitions. [2018-07-24 10:54:17,794 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:54:17,795 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 118 transitions. [2018-07-24 10:54:17,795 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 115 [2018-07-24 10:54:17,795 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:17,795 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 11, 11, 11, 10, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:17,796 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:17,796 INFO L82 PathProgramCache]: Analyzing trace with hash -499000187, now seen corresponding path program 19 times [2018-07-24 10:54:17,796 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:17,796 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:17,797 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:17,797 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:17,797 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:17,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:18,237 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:18,237 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:18,237 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:18,245 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:18,245 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:18,278 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:18,281 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:18,298 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:18,298 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:18,558 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:18,579 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:18,579 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:18,594 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:18,594 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:18,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:18,668 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:18,684 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:18,684 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:19,437 INFO L134 CoverageAnalysis]: Checked inductivity of 520 backedges. 230 proven. 110 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:19,439 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:19,439 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 25 [2018-07-24 10:54:19,439 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:19,439 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:54:19,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:54:19,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=157, Invalid=443, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:54:19,440 INFO L87 Difference]: Start difference. First operand 117 states and 118 transitions. Second operand 25 states. [2018-07-24 10:54:19,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:19,707 INFO L93 Difference]: Finished difference Result 172 states and 184 transitions. [2018-07-24 10:54:19,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:54:19,709 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 114 [2018-07-24 10:54:19,710 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:19,711 INFO L225 Difference]: With dead ends: 172 [2018-07-24 10:54:19,711 INFO L226 Difference]: Without dead ends: 119 [2018-07-24 10:54:19,712 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 491 GetRequests, 412 SyntacticMatches, 44 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 615 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=337, Invalid=995, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:54:19,712 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119 states. [2018-07-24 10:54:19,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119 to 119. [2018-07-24 10:54:19,718 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 119 states. [2018-07-24 10:54:19,718 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 119 states to 119 states and 120 transitions. [2018-07-24 10:54:19,718 INFO L78 Accepts]: Start accepts. Automaton has 119 states and 120 transitions. Word has length 114 [2018-07-24 10:54:19,719 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:19,719 INFO L471 AbstractCegarLoop]: Abstraction has 119 states and 120 transitions. [2018-07-24 10:54:19,719 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:54:19,719 INFO L276 IsEmpty]: Start isEmpty. Operand 119 states and 120 transitions. [2018-07-24 10:54:19,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-07-24 10:54:19,719 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:19,720 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 11, 11, 11, 11, 10, 10, 10, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:19,720 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:19,720 INFO L82 PathProgramCache]: Analyzing trace with hash -1351465249, now seen corresponding path program 20 times [2018-07-24 10:54:19,720 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:19,720 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:19,720 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:19,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:19,721 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:19,729 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:19,916 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 151 proven. 238 refuted. 0 times theorem prover too weak. 153 trivial. 0 not checked. [2018-07-24 10:54:19,916 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:19,916 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:19,924 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:19,924 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:19,960 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:19,960 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:19,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:20,138 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:20,138 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:20,294 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:20,314 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:20,314 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:20,330 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:20,330 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:20,410 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:20,411 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:20,428 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:20,450 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:20,450 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:21,095 INFO L134 CoverageAnalysis]: Checked inductivity of 542 backedges. 152 proven. 210 refuted. 0 times theorem prover too weak. 180 trivial. 0 not checked. [2018-07-24 10:54:21,096 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:21,097 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 16, 16, 16, 16] total 19 [2018-07-24 10:54:21,097 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:21,097 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:54:21,097 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:54:21,098 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=103, Invalid=239, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:54:21,098 INFO L87 Difference]: Start difference. First operand 119 states and 120 transitions. Second operand 19 states. [2018-07-24 10:54:21,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:21,334 INFO L93 Difference]: Finished difference Result 129 states and 130 transitions. [2018-07-24 10:54:21,334 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:54:21,335 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 116 [2018-07-24 10:54:21,335 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:21,336 INFO L225 Difference]: With dead ends: 129 [2018-07-24 10:54:21,336 INFO L226 Difference]: Without dead ends: 127 [2018-07-24 10:54:21,337 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 493 GetRequests, 426 SyntacticMatches, 48 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 371 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=116, Invalid=304, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:54:21,338 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127 states. [2018-07-24 10:54:21,342 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127 to 127. [2018-07-24 10:54:21,342 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 127 states. [2018-07-24 10:54:21,342 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 127 states to 127 states and 128 transitions. [2018-07-24 10:54:21,343 INFO L78 Accepts]: Start accepts. Automaton has 127 states and 128 transitions. Word has length 116 [2018-07-24 10:54:21,343 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:21,343 INFO L471 AbstractCegarLoop]: Abstraction has 127 states and 128 transitions. [2018-07-24 10:54:21,343 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:54:21,343 INFO L276 IsEmpty]: Start isEmpty. Operand 127 states and 128 transitions. [2018-07-24 10:54:21,344 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 125 [2018-07-24 10:54:21,344 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:21,344 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:21,344 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:21,344 INFO L82 PathProgramCache]: Analyzing trace with hash 1935124362, now seen corresponding path program 21 times [2018-07-24 10:54:21,344 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:21,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:21,345 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:21,345 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:21,345 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:21,356 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:21,939 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:21,939 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:21,939 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:21,947 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:21,947 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:22,140 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 10:54:22,141 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:22,144 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:22,166 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:22,166 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:23,742 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:23,761 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:23,762 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:23,777 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:23,777 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:23,962 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 10:54:23,963 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:23,968 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:23,986 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:23,986 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:24,247 INFO L134 CoverageAnalysis]: Checked inductivity of 627 backedges. 275 proven. 132 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:24,248 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:24,248 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 27, 27, 27, 27] total 27 [2018-07-24 10:54:24,248 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:24,249 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:54:24,249 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:54:24,249 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=183, Invalid=519, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:54:24,250 INFO L87 Difference]: Start difference. First operand 127 states and 128 transitions. Second operand 27 states. [2018-07-24 10:54:24,801 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:24,802 INFO L93 Difference]: Finished difference Result 186 states and 199 transitions. [2018-07-24 10:54:24,810 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:54:24,810 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 124 [2018-07-24 10:54:24,811 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:24,812 INFO L225 Difference]: With dead ends: 186 [2018-07-24 10:54:24,812 INFO L226 Difference]: Without dead ends: 129 [2018-07-24 10:54:24,814 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 534 GetRequests, 448 SyntacticMatches, 48 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 737 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=391, Invalid=1169, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:54:24,815 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 129 states. [2018-07-24 10:54:24,821 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 129 to 129. [2018-07-24 10:54:24,821 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 129 states. [2018-07-24 10:54:24,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129 states to 129 states and 130 transitions. [2018-07-24 10:54:24,822 INFO L78 Accepts]: Start accepts. Automaton has 129 states and 130 transitions. Word has length 124 [2018-07-24 10:54:24,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:24,822 INFO L471 AbstractCegarLoop]: Abstraction has 129 states and 130 transitions. [2018-07-24 10:54:24,822 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:54:24,822 INFO L276 IsEmpty]: Start isEmpty. Operand 129 states and 130 transitions. [2018-07-24 10:54:24,823 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 127 [2018-07-24 10:54:24,823 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:24,823 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 12, 12, 12, 11, 11, 11, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:24,824 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:24,824 INFO L82 PathProgramCache]: Analyzing trace with hash -1896715932, now seen corresponding path program 22 times [2018-07-24 10:54:24,824 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:24,824 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:24,825 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:24,825 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:24,825 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:24,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:25,169 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 177 proven. 284 refuted. 0 times theorem prover too weak. 190 trivial. 0 not checked. [2018-07-24 10:54:25,169 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:25,169 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:25,177 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:25,178 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:25,217 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:25,217 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:25,219 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:25,293 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:25,293 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:25,462 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:25,482 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:25,482 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:25,496 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:25,497 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:25,597 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:25,597 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:25,602 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:25,619 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:25,619 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:25,879 INFO L134 CoverageAnalysis]: Checked inductivity of 651 backedges. 178 proven. 253 refuted. 0 times theorem prover too weak. 220 trivial. 0 not checked. [2018-07-24 10:54:25,880 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:25,881 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 17, 17, 17, 17] total 20 [2018-07-24 10:54:25,881 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:25,881 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:54:25,882 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:54:25,882 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=117, Invalid=263, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:54:25,882 INFO L87 Difference]: Start difference. First operand 129 states and 130 transitions. Second operand 20 states. [2018-07-24 10:54:26,076 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:26,076 INFO L93 Difference]: Finished difference Result 139 states and 140 transitions. [2018-07-24 10:54:26,077 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:54:26,077 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 126 [2018-07-24 10:54:26,077 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:26,079 INFO L225 Difference]: With dead ends: 139 [2018-07-24 10:54:26,079 INFO L226 Difference]: Without dead ends: 137 [2018-07-24 10:54:26,080 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 535 GetRequests, 463 SyntacticMatches, 52 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 428 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=130, Invalid=332, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:54:26,080 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 137 states. [2018-07-24 10:54:26,086 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 137 to 137. [2018-07-24 10:54:26,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 137 states. [2018-07-24 10:54:26,087 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 137 states to 137 states and 138 transitions. [2018-07-24 10:54:26,087 INFO L78 Accepts]: Start accepts. Automaton has 137 states and 138 transitions. Word has length 126 [2018-07-24 10:54:26,087 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:26,087 INFO L471 AbstractCegarLoop]: Abstraction has 137 states and 138 transitions. [2018-07-24 10:54:26,087 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:54:26,087 INFO L276 IsEmpty]: Start isEmpty. Operand 137 states and 138 transitions. [2018-07-24 10:54:26,088 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 135 [2018-07-24 10:54:26,088 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:26,088 INFO L353 BasicCegarLoop]: trace histogram [13, 13, 13, 13, 13, 12, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:26,089 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:26,089 INFO L82 PathProgramCache]: Analyzing trace with hash -249334513, now seen corresponding path program 23 times [2018-07-24 10:54:26,089 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:26,089 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:26,090 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:26,090 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:26,090 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:26,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:26,424 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:26,424 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:26,424 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:26,431 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:26,431 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:26,492 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-07-24 10:54:26,492 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:26,496 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:26,521 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:26,521 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:26,825 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:26,844 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:26,845 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:26,859 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:26,860 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:27,082 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 13 check-sat command(s) [2018-07-24 10:54:27,082 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:27,087 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:27,108 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:27,108 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:27,491 INFO L134 CoverageAnalysis]: Checked inductivity of 744 backedges. 324 proven. 156 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:27,492 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:27,493 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 29 [2018-07-24 10:54:27,493 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:27,493 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:54:27,493 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:54:27,494 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=211, Invalid=601, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:54:27,494 INFO L87 Difference]: Start difference. First operand 137 states and 138 transitions. Second operand 29 states. [2018-07-24 10:54:27,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:27,970 INFO L93 Difference]: Finished difference Result 200 states and 214 transitions. [2018-07-24 10:54:27,970 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:54:27,970 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 134 [2018-07-24 10:54:27,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:27,971 INFO L225 Difference]: With dead ends: 200 [2018-07-24 10:54:27,971 INFO L226 Difference]: Without dead ends: 139 [2018-07-24 10:54:27,972 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 577 GetRequests, 484 SyntacticMatches, 52 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 870 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=449, Invalid=1357, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:54:27,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 139 states. [2018-07-24 10:54:27,979 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 139 to 139. [2018-07-24 10:54:27,979 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 139 states. [2018-07-24 10:54:27,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 139 states to 139 states and 140 transitions. [2018-07-24 10:54:27,980 INFO L78 Accepts]: Start accepts. Automaton has 139 states and 140 transitions. Word has length 134 [2018-07-24 10:54:27,980 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:27,980 INFO L471 AbstractCegarLoop]: Abstraction has 139 states and 140 transitions. [2018-07-24 10:54:27,980 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:54:27,980 INFO L276 IsEmpty]: Start isEmpty. Operand 139 states and 140 transitions. [2018-07-24 10:54:27,981 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-07-24 10:54:27,981 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:27,982 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 13, 13, 13, 13, 12, 12, 12, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:27,982 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:27,982 INFO L82 PathProgramCache]: Analyzing trace with hash 163655273, now seen corresponding path program 24 times [2018-07-24 10:54:27,982 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:27,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:27,983 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:27,983 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:27,983 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:27,992 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:28,431 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 205 proven. 334 refuted. 0 times theorem prover too weak. 231 trivial. 0 not checked. [2018-07-24 10:54:28,431 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:28,432 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:28,438 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:28,439 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:28,490 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-07-24 10:54:28,490 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:28,494 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:28,615 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:28,615 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:28,801 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:28,821 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:28,821 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:28,837 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:28,838 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:29,057 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 14 check-sat command(s) [2018-07-24 10:54:29,057 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:29,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:29,077 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:29,078 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:29,296 INFO L134 CoverageAnalysis]: Checked inductivity of 770 backedges. 206 proven. 300 refuted. 0 times theorem prover too weak. 264 trivial. 0 not checked. [2018-07-24 10:54:29,297 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:29,298 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 18, 18, 18, 18] total 21 [2018-07-24 10:54:29,298 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:29,298 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:54:29,298 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:54:29,298 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=132, Invalid=288, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:54:29,299 INFO L87 Difference]: Start difference. First operand 139 states and 140 transitions. Second operand 21 states. [2018-07-24 10:54:29,711 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:29,712 INFO L93 Difference]: Finished difference Result 149 states and 150 transitions. [2018-07-24 10:54:29,712 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:54:29,712 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 136 [2018-07-24 10:54:29,713 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:29,714 INFO L225 Difference]: With dead ends: 149 [2018-07-24 10:54:29,714 INFO L226 Difference]: Without dead ends: 147 [2018-07-24 10:54:29,715 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 577 GetRequests, 500 SyntacticMatches, 56 SemanticMatches, 21 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 489 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=145, Invalid=361, Unknown=0, NotChecked=0, Total=506 [2018-07-24 10:54:29,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147 states. [2018-07-24 10:54:29,722 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147 to 147. [2018-07-24 10:54:29,722 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 147 states. [2018-07-24 10:54:29,723 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 147 states to 147 states and 148 transitions. [2018-07-24 10:54:29,723 INFO L78 Accepts]: Start accepts. Automaton has 147 states and 148 transitions. Word has length 136 [2018-07-24 10:54:29,723 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:29,723 INFO L471 AbstractCegarLoop]: Abstraction has 147 states and 148 transitions. [2018-07-24 10:54:29,723 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:54:29,724 INFO L276 IsEmpty]: Start isEmpty. Operand 147 states and 148 transitions. [2018-07-24 10:54:29,724 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 145 [2018-07-24 10:54:29,724 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:29,725 INFO L353 BasicCegarLoop]: trace histogram [14, 14, 14, 14, 14, 13, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:29,725 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:29,725 INFO L82 PathProgramCache]: Analyzing trace with hash 1286825236, now seen corresponding path program 25 times [2018-07-24 10:54:29,725 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:29,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:29,726 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:29,726 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:29,726 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:29,735 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:30,210 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:30,210 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:30,210 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:30,217 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:30,217 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:30,264 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:30,268 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:30,290 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:30,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:30,669 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:30,689 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:30,689 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:30,705 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:30,705 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:30,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:30,800 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:30,817 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:30,817 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:31,347 INFO L134 CoverageAnalysis]: Checked inductivity of 871 backedges. 377 proven. 182 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:31,348 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:31,349 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 31 [2018-07-24 10:54:31,349 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:31,349 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:54:31,349 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:54:31,350 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=241, Invalid=689, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:54:31,350 INFO L87 Difference]: Start difference. First operand 147 states and 148 transitions. Second operand 31 states. [2018-07-24 10:54:32,237 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:32,237 INFO L93 Difference]: Finished difference Result 214 states and 229 transitions. [2018-07-24 10:54:32,237 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:54:32,238 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 144 [2018-07-24 10:54:32,238 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:32,239 INFO L225 Difference]: With dead ends: 214 [2018-07-24 10:54:32,239 INFO L226 Difference]: Without dead ends: 149 [2018-07-24 10:54:32,240 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 620 GetRequests, 520 SyntacticMatches, 56 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1014 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=511, Invalid=1559, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:54:32,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 149 states. [2018-07-24 10:54:32,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 149 to 149. [2018-07-24 10:54:32,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 149 states. [2018-07-24 10:54:32,248 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 149 states to 149 states and 150 transitions. [2018-07-24 10:54:32,249 INFO L78 Accepts]: Start accepts. Automaton has 149 states and 150 transitions. Word has length 144 [2018-07-24 10:54:32,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:32,249 INFO L471 AbstractCegarLoop]: Abstraction has 149 states and 150 transitions. [2018-07-24 10:54:32,249 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:54:32,249 INFO L276 IsEmpty]: Start isEmpty. Operand 149 states and 150 transitions. [2018-07-24 10:54:32,250 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 147 [2018-07-24 10:54:32,250 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:32,250 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 14, 14, 14, 13, 13, 13, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:32,250 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:32,251 INFO L82 PathProgramCache]: Analyzing trace with hash -1566263826, now seen corresponding path program 26 times [2018-07-24 10:54:32,251 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:32,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:32,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:32,252 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:32,252 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:32,260 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:32,476 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 235 proven. 388 refuted. 0 times theorem prover too weak. 276 trivial. 0 not checked. [2018-07-24 10:54:32,476 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:32,477 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:32,486 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:32,486 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:32,528 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:32,528 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:32,530 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:32,592 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:32,593 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:32,813 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:32,834 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:32,834 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:32,849 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:32,849 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:32,954 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:32,955 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:32,963 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:32,990 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:32,990 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:33,605 INFO L134 CoverageAnalysis]: Checked inductivity of 899 backedges. 236 proven. 351 refuted. 0 times theorem prover too weak. 312 trivial. 0 not checked. [2018-07-24 10:54:33,606 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:33,606 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 19, 19, 19, 19] total 22 [2018-07-24 10:54:33,606 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:33,607 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:54:33,607 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:54:33,607 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=148, Invalid=314, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:54:33,607 INFO L87 Difference]: Start difference. First operand 149 states and 150 transitions. Second operand 22 states. [2018-07-24 10:54:33,914 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:33,915 INFO L93 Difference]: Finished difference Result 159 states and 160 transitions. [2018-07-24 10:54:33,915 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:54:33,915 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 146 [2018-07-24 10:54:33,916 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:33,917 INFO L225 Difference]: With dead ends: 159 [2018-07-24 10:54:33,917 INFO L226 Difference]: Without dead ends: 157 [2018-07-24 10:54:33,918 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 619 GetRequests, 537 SyntacticMatches, 60 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 554 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=161, Invalid=391, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:54:33,918 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157 states. [2018-07-24 10:54:33,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157 to 157. [2018-07-24 10:54:33,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 157 states. [2018-07-24 10:54:33,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157 states to 157 states and 158 transitions. [2018-07-24 10:54:33,926 INFO L78 Accepts]: Start accepts. Automaton has 157 states and 158 transitions. Word has length 146 [2018-07-24 10:54:33,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:33,926 INFO L471 AbstractCegarLoop]: Abstraction has 157 states and 158 transitions. [2018-07-24 10:54:33,926 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:54:33,926 INFO L276 IsEmpty]: Start isEmpty. Operand 157 states and 158 transitions. [2018-07-24 10:54:33,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 155 [2018-07-24 10:54:33,927 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:33,927 INFO L353 BasicCegarLoop]: trace histogram [15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:33,928 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:33,928 INFO L82 PathProgramCache]: Analyzing trace with hash 1890424729, now seen corresponding path program 27 times [2018-07-24 10:54:33,928 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:33,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:33,929 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:33,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:33,929 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:33,937 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:34,346 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:34,347 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:34,347 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:34,354 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:34,354 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:34,418 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-07-24 10:54:34,418 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:34,422 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:34,447 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:34,447 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:34,822 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:34,842 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:34,843 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:34,858 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:34,858 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:35,114 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-07-24 10:54:35,115 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:35,120 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:35,138 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:35,138 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:35,513 INFO L134 CoverageAnalysis]: Checked inductivity of 1008 backedges. 434 proven. 210 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:35,515 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:35,515 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 33 [2018-07-24 10:54:35,515 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:35,515 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:54:35,516 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:54:35,516 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=273, Invalid=783, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:54:35,516 INFO L87 Difference]: Start difference. First operand 157 states and 158 transitions. Second operand 33 states. [2018-07-24 10:54:36,585 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:36,585 INFO L93 Difference]: Finished difference Result 228 states and 244 transitions. [2018-07-24 10:54:36,586 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:54:36,586 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 154 [2018-07-24 10:54:36,587 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:36,587 INFO L225 Difference]: With dead ends: 228 [2018-07-24 10:54:36,588 INFO L226 Difference]: Without dead ends: 159 [2018-07-24 10:54:36,589 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 663 GetRequests, 556 SyntacticMatches, 60 SemanticMatches, 47 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1169 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=577, Invalid=1775, Unknown=0, NotChecked=0, Total=2352 [2018-07-24 10:54:36,589 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 159 states. [2018-07-24 10:54:36,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 159 to 159. [2018-07-24 10:54:36,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-07-24 10:54:36,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 160 transitions. [2018-07-24 10:54:36,599 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 160 transitions. Word has length 154 [2018-07-24 10:54:36,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:36,599 INFO L471 AbstractCegarLoop]: Abstraction has 159 states and 160 transitions. [2018-07-24 10:54:36,600 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:54:36,600 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 160 transitions. [2018-07-24 10:54:36,601 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 157 [2018-07-24 10:54:36,601 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:36,601 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 15, 15, 15, 15, 14, 14, 14, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:36,601 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:36,601 INFO L82 PathProgramCache]: Analyzing trace with hash 268115955, now seen corresponding path program 28 times [2018-07-24 10:54:36,602 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:36,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:36,602 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:36,603 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:36,603 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:36,613 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:36,977 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 267 proven. 446 refuted. 0 times theorem prover too weak. 325 trivial. 0 not checked. [2018-07-24 10:54:36,978 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:36,978 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:36,985 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:36,985 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:37,030 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:37,030 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:37,033 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:37,100 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:37,100 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:37,464 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:37,483 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:37,483 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:37,498 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:37,499 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:37,615 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:37,615 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:37,620 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:37,639 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:37,639 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:37,903 INFO L134 CoverageAnalysis]: Checked inductivity of 1038 backedges. 268 proven. 406 refuted. 0 times theorem prover too weak. 364 trivial. 0 not checked. [2018-07-24 10:54:37,905 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:37,905 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 20, 20, 20, 20] total 23 [2018-07-24 10:54:37,905 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:37,905 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:54:37,905 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:54:37,906 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=165, Invalid=341, Unknown=0, NotChecked=0, Total=506 [2018-07-24 10:54:37,906 INFO L87 Difference]: Start difference. First operand 159 states and 160 transitions. Second operand 23 states. [2018-07-24 10:54:38,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:38,593 INFO L93 Difference]: Finished difference Result 169 states and 170 transitions. [2018-07-24 10:54:38,594 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:54:38,594 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 156 [2018-07-24 10:54:38,595 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:38,596 INFO L225 Difference]: With dead ends: 169 [2018-07-24 10:54:38,596 INFO L226 Difference]: Without dead ends: 167 [2018-07-24 10:54:38,596 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 661 GetRequests, 574 SyntacticMatches, 64 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 623 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=178, Invalid=422, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:54:38,597 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 167 states. [2018-07-24 10:54:38,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 167 to 167. [2018-07-24 10:54:38,603 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 167 states. [2018-07-24 10:54:38,604 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 167 states to 167 states and 168 transitions. [2018-07-24 10:54:38,604 INFO L78 Accepts]: Start accepts. Automaton has 167 states and 168 transitions. Word has length 156 [2018-07-24 10:54:38,604 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:38,604 INFO L471 AbstractCegarLoop]: Abstraction has 167 states and 168 transitions. [2018-07-24 10:54:38,605 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:54:38,605 INFO L276 IsEmpty]: Start isEmpty. Operand 167 states and 168 transitions. [2018-07-24 10:54:38,605 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-07-24 10:54:38,606 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:38,606 INFO L353 BasicCegarLoop]: trace histogram [16, 16, 16, 16, 16, 15, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:38,606 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:38,606 INFO L82 PathProgramCache]: Analyzing trace with hash 1666198686, now seen corresponding path program 29 times [2018-07-24 10:54:38,606 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:38,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:38,607 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:38,607 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:38,607 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:38,617 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:39,013 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:39,013 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:39,013 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:39,021 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:39,021 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:39,080 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2018-07-24 10:54:39,080 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:39,084 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:39,111 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:39,112 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:39,490 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:39,519 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:39,520 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:39,548 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:39,548 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:39,848 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 16 check-sat command(s) [2018-07-24 10:54:39,848 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:39,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:39,877 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:39,877 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:40,235 INFO L134 CoverageAnalysis]: Checked inductivity of 1155 backedges. 495 proven. 240 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:40,236 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:40,236 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 35 [2018-07-24 10:54:40,237 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:40,237 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:54:40,237 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:54:40,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=307, Invalid=883, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:54:40,238 INFO L87 Difference]: Start difference. First operand 167 states and 168 transitions. Second operand 35 states. [2018-07-24 10:54:41,191 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:41,192 INFO L93 Difference]: Finished difference Result 242 states and 259 transitions. [2018-07-24 10:54:41,192 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:54:41,192 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 164 [2018-07-24 10:54:41,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:41,193 INFO L225 Difference]: With dead ends: 242 [2018-07-24 10:54:41,194 INFO L226 Difference]: Without dead ends: 169 [2018-07-24 10:54:41,195 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 706 GetRequests, 592 SyntacticMatches, 64 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1335 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=647, Invalid=2005, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:54:41,195 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 169 states. [2018-07-24 10:54:41,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 169 to 169. [2018-07-24 10:54:41,205 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 169 states. [2018-07-24 10:54:41,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 169 states to 169 states and 170 transitions. [2018-07-24 10:54:41,206 INFO L78 Accepts]: Start accepts. Automaton has 169 states and 170 transitions. Word has length 164 [2018-07-24 10:54:41,206 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:41,206 INFO L471 AbstractCegarLoop]: Abstraction has 169 states and 170 transitions. [2018-07-24 10:54:41,206 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:54:41,206 INFO L276 IsEmpty]: Start isEmpty. Operand 169 states and 170 transitions. [2018-07-24 10:54:41,211 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 167 [2018-07-24 10:54:41,211 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:41,211 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 16, 16, 16, 15, 15, 15, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:41,211 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:41,211 INFO L82 PathProgramCache]: Analyzing trace with hash -574976904, now seen corresponding path program 30 times [2018-07-24 10:54:41,211 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:41,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:41,212 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:41,212 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:41,213 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:41,223 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:41,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 301 proven. 508 refuted. 0 times theorem prover too weak. 378 trivial. 0 not checked. [2018-07-24 10:54:41,780 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:41,780 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:41,786 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:41,786 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:41,847 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-07-24 10:54:41,848 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:41,852 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:42,145 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:42,145 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:42,446 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:42,465 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:42,465 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:42,481 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:42,481 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:42,771 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 17 check-sat command(s) [2018-07-24 10:54:42,771 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:42,783 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:42,811 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:42,812 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:44,891 INFO L134 CoverageAnalysis]: Checked inductivity of 1187 backedges. 302 proven. 465 refuted. 0 times theorem prover too weak. 420 trivial. 0 not checked. [2018-07-24 10:54:44,893 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:44,893 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 21, 21, 21, 21] total 24 [2018-07-24 10:54:44,893 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:44,894 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:54:44,894 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:54:44,894 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=183, Invalid=369, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:54:44,895 INFO L87 Difference]: Start difference. First operand 169 states and 170 transitions. Second operand 24 states. [2018-07-24 10:54:45,115 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:45,116 INFO L93 Difference]: Finished difference Result 179 states and 180 transitions. [2018-07-24 10:54:45,116 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:54:45,116 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 166 [2018-07-24 10:54:45,117 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:45,118 INFO L225 Difference]: With dead ends: 179 [2018-07-24 10:54:45,119 INFO L226 Difference]: Without dead ends: 177 [2018-07-24 10:54:45,120 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 703 GetRequests, 611 SyntacticMatches, 68 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 696 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=196, Invalid=454, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:45,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-07-24 10:54:45,128 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-07-24 10:54:45,128 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-07-24 10:54:45,129 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 178 transitions. [2018-07-24 10:54:45,129 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 178 transitions. Word has length 166 [2018-07-24 10:54:45,132 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:45,133 INFO L471 AbstractCegarLoop]: Abstraction has 177 states and 178 transitions. [2018-07-24 10:54:45,133 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:54:45,133 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 178 transitions. [2018-07-24 10:54:45,134 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 175 [2018-07-24 10:54:45,134 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:45,134 INFO L353 BasicCegarLoop]: trace histogram [17, 17, 17, 17, 17, 16, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:45,134 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:45,135 INFO L82 PathProgramCache]: Analyzing trace with hash -395230173, now seen corresponding path program 31 times [2018-07-24 10:54:45,135 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:45,135 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,136 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:45,136 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:45,136 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:45,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:45,955 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:45,956 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:45,956 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:45,963 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:45,963 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:46,013 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:46,017 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:46,039 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:46,039 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:46,477 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:46,497 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:46,497 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:46,512 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:46,512 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:46,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:46,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:46,656 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:46,656 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:47,206 INFO L134 CoverageAnalysis]: Checked inductivity of 1312 backedges. 560 proven. 272 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:47,208 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:47,208 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 37 [2018-07-24 10:54:47,208 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:47,209 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:54:47,209 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:54:47,209 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=343, Invalid=989, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:54:47,209 INFO L87 Difference]: Start difference. First operand 177 states and 178 transitions. Second operand 37 states. [2018-07-24 10:54:49,008 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:49,008 INFO L93 Difference]: Finished difference Result 256 states and 274 transitions. [2018-07-24 10:54:49,016 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:54:49,016 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 174 [2018-07-24 10:54:49,017 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:49,018 INFO L225 Difference]: With dead ends: 256 [2018-07-24 10:54:49,018 INFO L226 Difference]: Without dead ends: 179 [2018-07-24 10:54:49,020 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 749 GetRequests, 628 SyntacticMatches, 68 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1512 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=721, Invalid=2249, Unknown=0, NotChecked=0, Total=2970 [2018-07-24 10:54:49,020 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 179 states. [2018-07-24 10:54:49,029 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 179 to 179. [2018-07-24 10:54:49,030 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 179 states. [2018-07-24 10:54:49,030 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 179 states to 179 states and 180 transitions. [2018-07-24 10:54:49,031 INFO L78 Accepts]: Start accepts. Automaton has 179 states and 180 transitions. Word has length 174 [2018-07-24 10:54:49,031 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:49,031 INFO L471 AbstractCegarLoop]: Abstraction has 179 states and 180 transitions. [2018-07-24 10:54:49,031 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:54:49,031 INFO L276 IsEmpty]: Start isEmpty. Operand 179 states and 180 transitions. [2018-07-24 10:54:49,032 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-07-24 10:54:49,032 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:49,033 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 17, 17, 17, 17, 16, 16, 16, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:49,033 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:49,033 INFO L82 PathProgramCache]: Analyzing trace with hash -1888412803, now seen corresponding path program 32 times [2018-07-24 10:54:49,033 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:49,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:49,034 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:49,034 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:49,034 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:49,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:50,153 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 337 proven. 574 refuted. 0 times theorem prover too weak. 435 trivial. 0 not checked. [2018-07-24 10:54:50,153 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:50,153 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:50,161 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:50,161 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:50,209 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:50,210 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:50,212 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:50,304 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:50,304 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:50,653 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:50,672 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:50,673 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:50,688 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:50,688 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:50,805 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:50,805 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:50,811 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:50,833 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:50,834 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:51,148 INFO L134 CoverageAnalysis]: Checked inductivity of 1346 backedges. 338 proven. 528 refuted. 0 times theorem prover too weak. 480 trivial. 0 not checked. [2018-07-24 10:54:51,149 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:51,149 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 22, 22, 22, 22] total 25 [2018-07-24 10:54:51,149 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:51,150 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:54:51,150 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:54:51,151 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=202, Invalid=398, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:54:51,151 INFO L87 Difference]: Start difference. First operand 179 states and 180 transitions. Second operand 25 states. [2018-07-24 10:54:52,604 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:52,604 INFO L93 Difference]: Finished difference Result 189 states and 190 transitions. [2018-07-24 10:54:52,605 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 24 states. [2018-07-24 10:54:52,605 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 176 [2018-07-24 10:54:52,605 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:52,607 INFO L225 Difference]: With dead ends: 189 [2018-07-24 10:54:52,607 INFO L226 Difference]: Without dead ends: 187 [2018-07-24 10:54:52,607 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 745 GetRequests, 648 SyntacticMatches, 72 SemanticMatches, 25 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 773 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=215, Invalid=487, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:54:52,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 187 states. [2018-07-24 10:54:52,615 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 187 to 187. [2018-07-24 10:54:52,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 187 states. [2018-07-24 10:54:52,616 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 187 states to 187 states and 188 transitions. [2018-07-24 10:54:52,616 INFO L78 Accepts]: Start accepts. Automaton has 187 states and 188 transitions. Word has length 176 [2018-07-24 10:54:52,616 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:52,617 INFO L471 AbstractCegarLoop]: Abstraction has 187 states and 188 transitions. [2018-07-24 10:54:52,617 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:54:52,617 INFO L276 IsEmpty]: Start isEmpty. Operand 187 states and 188 transitions. [2018-07-24 10:54:52,618 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 185 [2018-07-24 10:54:52,618 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:52,618 INFO L353 BasicCegarLoop]: trace histogram [18, 18, 18, 18, 18, 17, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:52,618 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:52,618 INFO L82 PathProgramCache]: Analyzing trace with hash -1551958488, now seen corresponding path program 33 times [2018-07-24 10:54:52,619 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:52,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:52,619 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:52,619 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:52,619 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:52,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:53,224 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:53,225 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:53,225 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:53,232 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:53,233 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:53,298 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-07-24 10:54:53,299 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:53,302 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:53,332 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:53,333 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,077 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:54,098 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:54,098 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:54,113 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:54,113 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:54,469 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 18 check-sat command(s) [2018-07-24 10:54:54,469 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:54,475 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:54,499 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:54,500 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,986 INFO L134 CoverageAnalysis]: Checked inductivity of 1479 backedges. 629 proven. 306 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:54,988 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:54,988 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 39 [2018-07-24 10:54:54,988 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:54,989 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:54:54,989 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:54:54,989 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=381, Invalid=1101, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:54:54,990 INFO L87 Difference]: Start difference. First operand 187 states and 188 transitions. Second operand 39 states. [2018-07-24 10:54:56,057 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:56,057 INFO L93 Difference]: Finished difference Result 270 states and 289 transitions. [2018-07-24 10:54:56,057 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:54:56,057 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 184 [2018-07-24 10:54:56,058 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:56,059 INFO L225 Difference]: With dead ends: 270 [2018-07-24 10:54:56,059 INFO L226 Difference]: Without dead ends: 189 [2018-07-24 10:54:56,060 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 792 GetRequests, 664 SyntacticMatches, 72 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1700 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=799, Invalid=2507, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:54:56,060 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-07-24 10:54:56,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2018-07-24 10:54:56,068 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-07-24 10:54:56,068 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 190 transitions. [2018-07-24 10:54:56,069 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 190 transitions. Word has length 184 [2018-07-24 10:54:56,069 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:56,069 INFO L471 AbstractCegarLoop]: Abstraction has 189 states and 190 transitions. [2018-07-24 10:54:56,069 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:54:56,069 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 190 transitions. [2018-07-24 10:54:56,070 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 187 [2018-07-24 10:54:56,070 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:56,070 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 18, 18, 18, 17, 17, 17, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:56,071 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:56,071 INFO L82 PathProgramCache]: Analyzing trace with hash 1111813378, now seen corresponding path program 34 times [2018-07-24 10:54:56,071 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:56,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:56,072 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:56,072 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:56,072 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:56,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:56,403 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 375 proven. 644 refuted. 0 times theorem prover too weak. 496 trivial. 0 not checked. [2018-07-24 10:54:56,403 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:56,403 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:56,411 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:56,411 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:56,469 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:56,469 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:56,472 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:56,544 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:56,545 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:56,864 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:56,885 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:56,885 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:56,900 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:56,900 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:57,038 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:57,038 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:57,045 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:57,075 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:57,075 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:57,920 INFO L134 CoverageAnalysis]: Checked inductivity of 1515 backedges. 376 proven. 595 refuted. 0 times theorem prover too weak. 544 trivial. 0 not checked. [2018-07-24 10:54:57,922 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:57,922 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 23, 23, 23, 23] total 26 [2018-07-24 10:54:57,922 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:57,922 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:54:57,922 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:54:57,923 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=428, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:54:57,923 INFO L87 Difference]: Start difference. First operand 189 states and 190 transitions. Second operand 26 states. [2018-07-24 10:54:58,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:58,169 INFO L93 Difference]: Finished difference Result 199 states and 200 transitions. [2018-07-24 10:54:58,170 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:54:58,170 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 186 [2018-07-24 10:54:58,171 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:58,172 INFO L225 Difference]: With dead ends: 199 [2018-07-24 10:54:58,172 INFO L226 Difference]: Without dead ends: 197 [2018-07-24 10:54:58,172 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 787 GetRequests, 685 SyntacticMatches, 76 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 854 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=235, Invalid=521, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:54:58,173 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 197 states. [2018-07-24 10:54:58,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 197 to 197. [2018-07-24 10:54:58,179 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 197 states. [2018-07-24 10:54:58,179 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 197 states to 197 states and 198 transitions. [2018-07-24 10:54:58,179 INFO L78 Accepts]: Start accepts. Automaton has 197 states and 198 transitions. Word has length 186 [2018-07-24 10:54:58,180 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:58,180 INFO L471 AbstractCegarLoop]: Abstraction has 197 states and 198 transitions. [2018-07-24 10:54:58,180 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:54:58,180 INFO L276 IsEmpty]: Start isEmpty. Operand 197 states and 198 transitions. [2018-07-24 10:54:58,181 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-07-24 10:54:58,181 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:58,181 INFO L353 BasicCegarLoop]: trace histogram [19, 19, 19, 19, 19, 18, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:58,181 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:58,182 INFO L82 PathProgramCache]: Analyzing trace with hash -1182827859, now seen corresponding path program 35 times [2018-07-24 10:54:58,182 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:58,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:58,182 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:58,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:58,182 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:58,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:59,157 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:54:59,157 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:59,157 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:59,164 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:59,164 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:59,232 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-07-24 10:54:59,233 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:59,236 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:59,268 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:54:59,268 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:59,742 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:54:59,763 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:59,763 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:59,778 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:59,779 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:00,163 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 19 check-sat command(s) [2018-07-24 10:55:00,163 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:00,170 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:00,221 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:00,221 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:00,698 INFO L134 CoverageAnalysis]: Checked inductivity of 1656 backedges. 702 proven. 342 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:00,699 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:00,699 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 41 [2018-07-24 10:55:00,699 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:00,700 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:55:00,700 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:55:00,700 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=421, Invalid=1219, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:55:00,701 INFO L87 Difference]: Start difference. First operand 197 states and 198 transitions. Second operand 41 states. [2018-07-24 10:55:01,825 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:01,825 INFO L93 Difference]: Finished difference Result 284 states and 304 transitions. [2018-07-24 10:55:01,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:55:01,826 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 194 [2018-07-24 10:55:01,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:01,827 INFO L225 Difference]: With dead ends: 284 [2018-07-24 10:55:01,827 INFO L226 Difference]: Without dead ends: 199 [2018-07-24 10:55:01,828 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 835 GetRequests, 700 SyntacticMatches, 76 SemanticMatches, 59 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1899 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=881, Invalid=2779, Unknown=0, NotChecked=0, Total=3660 [2018-07-24 10:55:01,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 199 states. [2018-07-24 10:55:01,836 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 199 to 199. [2018-07-24 10:55:01,836 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 199 states. [2018-07-24 10:55:01,837 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 199 states to 199 states and 200 transitions. [2018-07-24 10:55:01,837 INFO L78 Accepts]: Start accepts. Automaton has 199 states and 200 transitions. Word has length 194 [2018-07-24 10:55:01,837 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:01,837 INFO L471 AbstractCegarLoop]: Abstraction has 199 states and 200 transitions. [2018-07-24 10:55:01,837 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:55:01,838 INFO L276 IsEmpty]: Start isEmpty. Operand 199 states and 200 transitions. [2018-07-24 10:55:01,838 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 197 [2018-07-24 10:55:01,839 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:01,839 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 19, 19, 19, 19, 18, 18, 18, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:01,839 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:01,839 INFO L82 PathProgramCache]: Analyzing trace with hash -822861561, now seen corresponding path program 36 times [2018-07-24 10:55:01,839 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:01,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:01,840 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:01,840 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:01,840 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:01,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:02,151 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 415 proven. 718 refuted. 0 times theorem prover too weak. 561 trivial. 0 not checked. [2018-07-24 10:55:02,151 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:02,151 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:02,158 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:02,158 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:02,230 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:55:02,230 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:02,234 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:02,306 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:02,307 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:02,678 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:02,698 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:02,698 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:02,712 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:02,712 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:03,108 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:55:03,108 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:03,116 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:03,142 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:03,142 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:03,513 INFO L134 CoverageAnalysis]: Checked inductivity of 1694 backedges. 416 proven. 666 refuted. 0 times theorem prover too weak. 612 trivial. 0 not checked. [2018-07-24 10:55:03,515 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:03,515 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 24, 24, 24, 24] total 27 [2018-07-24 10:55:03,515 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:03,516 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:55:03,516 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:55:03,517 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=243, Invalid=459, Unknown=0, NotChecked=0, Total=702 [2018-07-24 10:55:03,517 INFO L87 Difference]: Start difference. First operand 199 states and 200 transitions. Second operand 27 states. [2018-07-24 10:55:03,795 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:03,795 INFO L93 Difference]: Finished difference Result 209 states and 210 transitions. [2018-07-24 10:55:03,796 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:55:03,796 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 196 [2018-07-24 10:55:03,796 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:03,797 INFO L225 Difference]: With dead ends: 209 [2018-07-24 10:55:03,797 INFO L226 Difference]: Without dead ends: 207 [2018-07-24 10:55:03,797 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 829 GetRequests, 722 SyntacticMatches, 80 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 939 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=256, Invalid=556, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:55:03,798 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-07-24 10:55:03,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-07-24 10:55:03,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-07-24 10:55:03,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 208 transitions. [2018-07-24 10:55:03,807 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 208 transitions. Word has length 196 [2018-07-24 10:55:03,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:03,807 INFO L471 AbstractCegarLoop]: Abstraction has 207 states and 208 transitions. [2018-07-24 10:55:03,808 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:55:03,808 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 208 transitions. [2018-07-24 10:55:03,810 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 205 [2018-07-24 10:55:03,810 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:03,810 INFO L353 BasicCegarLoop]: trace histogram [20, 20, 20, 20, 20, 19, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:03,810 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:03,811 INFO L82 PathProgramCache]: Analyzing trace with hash -216999502, now seen corresponding path program 37 times [2018-07-24 10:55:03,811 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:03,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:03,811 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:03,812 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:03,812 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:03,823 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:04,842 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:04,843 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:04,843 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:04,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:04,871 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:04,931 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:04,934 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:04,963 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:04,964 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:05,511 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:05,531 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:05,531 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:05,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:05,548 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:05,675 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:05,682 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:05,709 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:05,709 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:06,233 INFO L134 CoverageAnalysis]: Checked inductivity of 1843 backedges. 779 proven. 380 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:06,235 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:06,235 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 43 [2018-07-24 10:55:06,235 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:06,235 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:55:06,236 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:55:06,236 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=463, Invalid=1343, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:55:06,236 INFO L87 Difference]: Start difference. First operand 207 states and 208 transitions. Second operand 43 states. [2018-07-24 10:55:07,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:07,054 INFO L93 Difference]: Finished difference Result 298 states and 319 transitions. [2018-07-24 10:55:07,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:55:07,055 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 204 [2018-07-24 10:55:07,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:07,056 INFO L225 Difference]: With dead ends: 298 [2018-07-24 10:55:07,056 INFO L226 Difference]: Without dead ends: 209 [2018-07-24 10:55:07,057 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 878 GetRequests, 736 SyntacticMatches, 80 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2109 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=967, Invalid=3065, Unknown=0, NotChecked=0, Total=4032 [2018-07-24 10:55:07,057 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 209 states. [2018-07-24 10:55:07,065 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 209 to 209. [2018-07-24 10:55:07,065 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 209 states. [2018-07-24 10:55:07,066 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209 states to 209 states and 210 transitions. [2018-07-24 10:55:07,066 INFO L78 Accepts]: Start accepts. Automaton has 209 states and 210 transitions. Word has length 204 [2018-07-24 10:55:07,066 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:07,066 INFO L471 AbstractCegarLoop]: Abstraction has 209 states and 210 transitions. [2018-07-24 10:55:07,066 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:55:07,066 INFO L276 IsEmpty]: Start isEmpty. Operand 209 states and 210 transitions. [2018-07-24 10:55:07,067 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-07-24 10:55:07,067 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:07,067 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 20, 20, 20, 19, 19, 19, 19, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:07,067 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:07,068 INFO L82 PathProgramCache]: Analyzing trace with hash 1809110924, now seen corresponding path program 38 times [2018-07-24 10:55:07,068 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:07,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:07,068 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:07,068 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:07,069 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:07,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:07,463 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 457 proven. 796 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-07-24 10:55:07,464 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:07,464 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:07,472 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:07,472 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:07,531 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:07,531 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:07,534 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:07,610 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:07,610 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:08,101 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:08,121 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:08,122 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:08,136 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:08,136 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:08,275 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:08,275 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:08,282 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:08,311 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:08,311 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:08,808 INFO L134 CoverageAnalysis]: Checked inductivity of 1883 backedges. 458 proven. 741 refuted. 0 times theorem prover too weak. 684 trivial. 0 not checked. [2018-07-24 10:55:08,810 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:08,810 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 25, 25, 25, 25] total 28 [2018-07-24 10:55:08,810 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:08,810 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:55:08,811 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:55:08,811 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=265, Invalid=491, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:55:08,811 INFO L87 Difference]: Start difference. First operand 209 states and 210 transitions. Second operand 28 states. [2018-07-24 10:55:09,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:09,288 INFO L93 Difference]: Finished difference Result 219 states and 220 transitions. [2018-07-24 10:55:09,288 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:55:09,288 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 206 [2018-07-24 10:55:09,288 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:09,289 INFO L225 Difference]: With dead ends: 219 [2018-07-24 10:55:09,289 INFO L226 Difference]: Without dead ends: 217 [2018-07-24 10:55:09,290 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 871 GetRequests, 759 SyntacticMatches, 84 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1028 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=278, Invalid=592, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:09,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 217 states. [2018-07-24 10:55:09,299 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 217 to 217. [2018-07-24 10:55:09,299 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 217 states. [2018-07-24 10:55:09,300 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 217 states to 217 states and 218 transitions. [2018-07-24 10:55:09,300 INFO L78 Accepts]: Start accepts. Automaton has 217 states and 218 transitions. Word has length 206 [2018-07-24 10:55:09,300 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:09,300 INFO L471 AbstractCegarLoop]: Abstraction has 217 states and 218 transitions. [2018-07-24 10:55:09,300 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:55:09,300 INFO L276 IsEmpty]: Start isEmpty. Operand 217 states and 218 transitions. [2018-07-24 10:55:09,302 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 215 [2018-07-24 10:55:09,302 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:09,302 INFO L353 BasicCegarLoop]: trace histogram [21, 21, 21, 21, 21, 20, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:09,302 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:09,302 INFO L82 PathProgramCache]: Analyzing trace with hash 1583954743, now seen corresponding path program 39 times [2018-07-24 10:55:09,303 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:09,305 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:09,306 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:09,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:09,306 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:09,316 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:11,894 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:11,894 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:11,894 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:11,901 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:11,901 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:11,981 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-07-24 10:55:11,981 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:11,986 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:12,016 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:12,016 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:12,638 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:12,659 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:12,660 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:12,675 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:12,676 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:13,126 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 21 check-sat command(s) [2018-07-24 10:55:13,126 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:13,132 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:13,162 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:13,162 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:13,761 INFO L134 CoverageAnalysis]: Checked inductivity of 2040 backedges. 860 proven. 420 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:13,763 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:13,763 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 45 [2018-07-24 10:55:13,763 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:13,764 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:55:13,764 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:55:13,764 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=507, Invalid=1473, Unknown=0, NotChecked=0, Total=1980 [2018-07-24 10:55:13,765 INFO L87 Difference]: Start difference. First operand 217 states and 218 transitions. Second operand 45 states. [2018-07-24 10:55:14,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:14,988 INFO L93 Difference]: Finished difference Result 312 states and 334 transitions. [2018-07-24 10:55:14,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-24 10:55:14,988 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 214 [2018-07-24 10:55:14,988 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:14,989 INFO L225 Difference]: With dead ends: 312 [2018-07-24 10:55:14,989 INFO L226 Difference]: Without dead ends: 219 [2018-07-24 10:55:14,990 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 921 GetRequests, 772 SyntacticMatches, 84 SemanticMatches, 65 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2330 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=1057, Invalid=3365, Unknown=0, NotChecked=0, Total=4422 [2018-07-24 10:55:14,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-07-24 10:55:15,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 219. [2018-07-24 10:55:15,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2018-07-24 10:55:15,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 220 transitions. [2018-07-24 10:55:15,001 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 220 transitions. Word has length 214 [2018-07-24 10:55:15,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:15,001 INFO L471 AbstractCegarLoop]: Abstraction has 219 states and 220 transitions. [2018-07-24 10:55:15,001 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:55:15,002 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 220 transitions. [2018-07-24 10:55:15,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 217 [2018-07-24 10:55:15,003 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:15,003 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 21, 21, 21, 21, 20, 20, 20, 20, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:15,003 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:15,003 INFO L82 PathProgramCache]: Analyzing trace with hash -824889199, now seen corresponding path program 40 times [2018-07-24 10:55:15,004 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:15,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,004 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:15,005 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,005 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:15,016 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,930 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 501 proven. 878 refuted. 0 times theorem prover too weak. 703 trivial. 0 not checked. [2018-07-24 10:55:15,930 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,930 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:15,937 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:15,937 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:16,002 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:16,002 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:16,006 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,106 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:16,106 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,530 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:16,550 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:16,550 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:16,565 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:16,565 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:16,726 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:16,726 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:16,733 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,764 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:16,764 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:17,204 INFO L134 CoverageAnalysis]: Checked inductivity of 2082 backedges. 502 proven. 820 refuted. 0 times theorem prover too weak. 760 trivial. 0 not checked. [2018-07-24 10:55:17,205 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:17,205 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26, 26, 26, 26] total 29 [2018-07-24 10:55:17,205 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:17,206 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:55:17,206 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:55:17,206 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=288, Invalid=524, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:55:17,207 INFO L87 Difference]: Start difference. First operand 219 states and 220 transitions. Second operand 29 states. [2018-07-24 10:55:17,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:17,497 INFO L93 Difference]: Finished difference Result 229 states and 230 transitions. [2018-07-24 10:55:17,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:55:17,498 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 216 [2018-07-24 10:55:17,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:17,500 INFO L225 Difference]: With dead ends: 229 [2018-07-24 10:55:17,500 INFO L226 Difference]: Without dead ends: 227 [2018-07-24 10:55:17,500 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 913 GetRequests, 796 SyntacticMatches, 88 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1121 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=301, Invalid=629, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:55:17,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 227 states. [2018-07-24 10:55:17,507 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 227 to 227. [2018-07-24 10:55:17,507 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 227 states. [2018-07-24 10:55:17,508 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 227 states to 227 states and 228 transitions. [2018-07-24 10:55:17,508 INFO L78 Accepts]: Start accepts. Automaton has 227 states and 228 transitions. Word has length 216 [2018-07-24 10:55:17,508 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:17,508 INFO L471 AbstractCegarLoop]: Abstraction has 227 states and 228 transitions. [2018-07-24 10:55:17,509 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:55:17,509 INFO L276 IsEmpty]: Start isEmpty. Operand 227 states and 228 transitions. [2018-07-24 10:55:17,509 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-07-24 10:55:17,510 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:17,510 INFO L353 BasicCegarLoop]: trace histogram [22, 22, 22, 22, 22, 21, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:17,510 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:17,510 INFO L82 PathProgramCache]: Analyzing trace with hash 1901510460, now seen corresponding path program 41 times [2018-07-24 10:55:17,510 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:17,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,511 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:17,511 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,511 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:17,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:18,446 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:18,446 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:18,447 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:18,455 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:18,456 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:18,537 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2018-07-24 10:55:18,537 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:18,541 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:18,576 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:18,576 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:19,420 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:19,440 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:19,440 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:19,456 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:19,456 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:19,938 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 22 check-sat command(s) [2018-07-24 10:55:19,938 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:19,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:19,978 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:19,978 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:20,746 INFO L134 CoverageAnalysis]: Checked inductivity of 2247 backedges. 945 proven. 462 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:20,747 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:20,748 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 47 [2018-07-24 10:55:20,748 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:20,748 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-24 10:55:20,748 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-24 10:55:20,749 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=553, Invalid=1609, Unknown=0, NotChecked=0, Total=2162 [2018-07-24 10:55:20,749 INFO L87 Difference]: Start difference. First operand 227 states and 228 transitions. Second operand 47 states. [2018-07-24 10:55:21,982 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:21,982 INFO L93 Difference]: Finished difference Result 326 states and 349 transitions. [2018-07-24 10:55:21,982 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:55:21,982 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 224 [2018-07-24 10:55:21,983 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:21,983 INFO L225 Difference]: With dead ends: 326 [2018-07-24 10:55:21,984 INFO L226 Difference]: Without dead ends: 229 [2018-07-24 10:55:21,984 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 964 GetRequests, 808 SyntacticMatches, 88 SemanticMatches, 68 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2562 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1151, Invalid=3679, Unknown=0, NotChecked=0, Total=4830 [2018-07-24 10:55:21,985 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 229 states. [2018-07-24 10:55:21,994 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 229 to 229. [2018-07-24 10:55:21,995 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 229 states. [2018-07-24 10:55:21,995 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229 states to 229 states and 230 transitions. [2018-07-24 10:55:21,995 INFO L78 Accepts]: Start accepts. Automaton has 229 states and 230 transitions. Word has length 224 [2018-07-24 10:55:21,996 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:21,996 INFO L471 AbstractCegarLoop]: Abstraction has 229 states and 230 transitions. [2018-07-24 10:55:21,996 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-24 10:55:21,996 INFO L276 IsEmpty]: Start isEmpty. Operand 229 states and 230 transitions. [2018-07-24 10:55:21,997 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 227 [2018-07-24 10:55:21,997 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:21,997 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 22, 22, 22, 21, 21, 21, 21, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:21,998 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:21,998 INFO L82 PathProgramCache]: Analyzing trace with hash -814003178, now seen corresponding path program 42 times [2018-07-24 10:55:21,998 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:21,998 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:21,999 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:21,999 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:21,999 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:22,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:23,108 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 547 proven. 964 refuted. 0 times theorem prover too weak. 780 trivial. 0 not checked. [2018-07-24 10:55:23,108 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:23,108 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:23,117 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:23,117 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:23,201 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 23 check-sat command(s) [2018-07-24 10:55:23,201 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:23,205 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:23,283 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:23,283 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,763 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:23,783 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:23,783 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:23,798 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:23,798 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:24,305 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 23 check-sat command(s) [2018-07-24 10:55:24,305 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:24,313 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:24,352 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:24,352 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:25,107 INFO L134 CoverageAnalysis]: Checked inductivity of 2291 backedges. 548 proven. 903 refuted. 0 times theorem prover too weak. 840 trivial. 0 not checked. [2018-07-24 10:55:25,108 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:25,109 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 27, 27, 27, 27] total 30 [2018-07-24 10:55:25,109 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:25,109 INFO L450 AbstractCegarLoop]: Interpolant automaton has 30 states [2018-07-24 10:55:25,109 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 30 interpolants. [2018-07-24 10:55:25,109 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=312, Invalid=558, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:25,110 INFO L87 Difference]: Start difference. First operand 229 states and 230 transitions. Second operand 30 states. [2018-07-24 10:55:25,452 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:25,452 INFO L93 Difference]: Finished difference Result 239 states and 240 transitions. [2018-07-24 10:55:25,453 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:55:25,453 INFO L78 Accepts]: Start accepts. Automaton has 30 states. Word has length 226 [2018-07-24 10:55:25,453 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:25,455 INFO L225 Difference]: With dead ends: 239 [2018-07-24 10:55:25,455 INFO L226 Difference]: Without dead ends: 237 [2018-07-24 10:55:25,455 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 955 GetRequests, 833 SyntacticMatches, 92 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1218 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=325, Invalid=667, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:55:25,456 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-07-24 10:55:25,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 237. [2018-07-24 10:55:25,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-07-24 10:55:25,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 238 transitions. [2018-07-24 10:55:25,465 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 238 transitions. Word has length 226 [2018-07-24 10:55:25,466 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:25,466 INFO L471 AbstractCegarLoop]: Abstraction has 237 states and 238 transitions. [2018-07-24 10:55:25,466 INFO L472 AbstractCegarLoop]: Interpolant automaton has 30 states. [2018-07-24 10:55:25,466 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 238 transitions. [2018-07-24 10:55:25,467 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 235 [2018-07-24 10:55:25,467 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:25,468 INFO L353 BasicCegarLoop]: trace histogram [23, 23, 23, 23, 23, 22, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:25,468 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:25,468 INFO L82 PathProgramCache]: Analyzing trace with hash -1421900351, now seen corresponding path program 43 times [2018-07-24 10:55:25,468 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:25,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:25,469 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:25,469 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:25,469 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:25,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:26,330 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:26,330 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:26,330 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:26,337 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:26,337 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:26,403 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:26,407 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:26,486 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:26,486 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:27,620 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:27,639 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:27,639 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:27,655 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:27,656 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:27,800 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:27,806 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:27,837 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:27,837 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:28,490 INFO L134 CoverageAnalysis]: Checked inductivity of 2464 backedges. 1034 proven. 506 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:28,491 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:28,491 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 49 [2018-07-24 10:55:28,492 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:28,492 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:55:28,492 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:55:28,492 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=601, Invalid=1751, Unknown=0, NotChecked=0, Total=2352 [2018-07-24 10:55:28,493 INFO L87 Difference]: Start difference. First operand 237 states and 238 transitions. Second operand 49 states. [2018-07-24 10:55:29,905 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:29,905 INFO L93 Difference]: Finished difference Result 340 states and 364 transitions. [2018-07-24 10:55:29,911 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:55:29,911 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 234 [2018-07-24 10:55:29,912 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:29,913 INFO L225 Difference]: With dead ends: 340 [2018-07-24 10:55:29,913 INFO L226 Difference]: Without dead ends: 239 [2018-07-24 10:55:29,914 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1007 GetRequests, 844 SyntacticMatches, 92 SemanticMatches, 71 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2805 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1249, Invalid=4007, Unknown=0, NotChecked=0, Total=5256 [2018-07-24 10:55:29,914 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 239 states. [2018-07-24 10:55:29,925 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 239 to 239. [2018-07-24 10:55:29,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 239 states. [2018-07-24 10:55:29,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 239 states to 239 states and 240 transitions. [2018-07-24 10:55:29,926 INFO L78 Accepts]: Start accepts. Automaton has 239 states and 240 transitions. Word has length 234 [2018-07-24 10:55:29,926 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:29,926 INFO L471 AbstractCegarLoop]: Abstraction has 239 states and 240 transitions. [2018-07-24 10:55:29,926 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-24 10:55:29,927 INFO L276 IsEmpty]: Start isEmpty. Operand 239 states and 240 transitions. [2018-07-24 10:55:29,928 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2018-07-24 10:55:29,928 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:29,928 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 23, 23, 23, 23, 22, 22, 22, 22, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:29,928 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:29,929 INFO L82 PathProgramCache]: Analyzing trace with hash -1998239205, now seen corresponding path program 44 times [2018-07-24 10:55:29,929 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:29,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:29,929 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:29,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:29,930 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:29,941 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:30,484 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 595 proven. 1054 refuted. 0 times theorem prover too weak. 861 trivial. 0 not checked. [2018-07-24 10:55:30,485 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:30,485 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:30,493 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:30,493 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:30,561 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:30,561 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:30,564 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:30,652 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:30,652 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:31,349 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:31,369 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:31,369 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:31,383 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:31,384 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:31,539 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:31,539 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:31,548 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:31,630 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:31,630 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:32,140 INFO L134 CoverageAnalysis]: Checked inductivity of 2510 backedges. 596 proven. 990 refuted. 0 times theorem prover too weak. 924 trivial. 0 not checked. [2018-07-24 10:55:32,141 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:32,141 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 28, 28, 28, 28] total 31 [2018-07-24 10:55:32,141 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:32,142 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:55:32,142 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:55:32,142 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=337, Invalid=593, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:55:32,143 INFO L87 Difference]: Start difference. First operand 239 states and 240 transitions. Second operand 31 states. [2018-07-24 10:55:32,475 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:32,476 INFO L93 Difference]: Finished difference Result 249 states and 250 transitions. [2018-07-24 10:55:32,476 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 30 states. [2018-07-24 10:55:32,476 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 236 [2018-07-24 10:55:32,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:32,479 INFO L225 Difference]: With dead ends: 249 [2018-07-24 10:55:32,479 INFO L226 Difference]: Without dead ends: 247 [2018-07-24 10:55:32,480 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 997 GetRequests, 870 SyntacticMatches, 96 SemanticMatches, 31 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1319 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=350, Invalid=706, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:55:32,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 247 states. [2018-07-24 10:55:32,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 247 to 247. [2018-07-24 10:55:32,489 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 247 states. [2018-07-24 10:55:32,490 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 247 states to 247 states and 248 transitions. [2018-07-24 10:55:32,490 INFO L78 Accepts]: Start accepts. Automaton has 247 states and 248 transitions. Word has length 236 [2018-07-24 10:55:32,491 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:32,491 INFO L471 AbstractCegarLoop]: Abstraction has 247 states and 248 transitions. [2018-07-24 10:55:32,491 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:55:32,491 INFO L276 IsEmpty]: Start isEmpty. Operand 247 states and 248 transitions. [2018-07-24 10:55:32,492 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 245 [2018-07-24 10:55:32,492 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:32,492 INFO L353 BasicCegarLoop]: trace histogram [24, 24, 24, 24, 24, 23, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:32,493 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:32,493 INFO L82 PathProgramCache]: Analyzing trace with hash -1222529338, now seen corresponding path program 45 times [2018-07-24 10:55:32,493 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:32,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:32,494 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:32,494 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:32,494 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:32,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:33,337 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:33,337 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:33,337 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:33,346 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:33,346 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:33,432 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-07-24 10:55:33,433 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:33,437 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:33,475 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:33,475 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:34,203 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:34,224 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:34,224 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:34,239 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:34,239 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:34,821 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 24 check-sat command(s) [2018-07-24 10:55:34,821 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:34,829 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:34,868 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:34,869 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:35,649 INFO L134 CoverageAnalysis]: Checked inductivity of 2691 backedges. 1127 proven. 552 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:35,651 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:35,651 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 51 [2018-07-24 10:55:35,651 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:35,652 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:55:35,652 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:55:35,652 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=651, Invalid=1899, Unknown=0, NotChecked=0, Total=2550 [2018-07-24 10:55:35,653 INFO L87 Difference]: Start difference. First operand 247 states and 248 transitions. Second operand 51 states. [2018-07-24 10:55:36,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:36,698 INFO L93 Difference]: Finished difference Result 354 states and 379 transitions. [2018-07-24 10:55:36,698 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:55:36,698 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 244 [2018-07-24 10:55:36,698 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:36,699 INFO L225 Difference]: With dead ends: 354 [2018-07-24 10:55:36,699 INFO L226 Difference]: Without dead ends: 249 [2018-07-24 10:55:36,700 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1050 GetRequests, 880 SyntacticMatches, 96 SemanticMatches, 74 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3059 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1351, Invalid=4349, Unknown=0, NotChecked=0, Total=5700 [2018-07-24 10:55:36,701 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249 states. [2018-07-24 10:55:36,711 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249 to 249. [2018-07-24 10:55:36,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 249 states. [2018-07-24 10:55:36,712 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 249 states to 249 states and 250 transitions. [2018-07-24 10:55:36,713 INFO L78 Accepts]: Start accepts. Automaton has 249 states and 250 transitions. Word has length 244 [2018-07-24 10:55:36,713 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:36,713 INFO L471 AbstractCegarLoop]: Abstraction has 249 states and 250 transitions. [2018-07-24 10:55:36,713 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:55:36,713 INFO L276 IsEmpty]: Start isEmpty. Operand 249 states and 250 transitions. [2018-07-24 10:55:36,714 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 247 [2018-07-24 10:55:36,714 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:36,715 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 24, 24, 24, 23, 23, 23, 23, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:36,715 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:36,715 INFO L82 PathProgramCache]: Analyzing trace with hash -70694240, now seen corresponding path program 46 times [2018-07-24 10:55:36,715 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:36,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:36,716 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:36,716 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:36,716 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:36,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:37,322 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 645 proven. 1148 refuted. 0 times theorem prover too weak. 946 trivial. 0 not checked. [2018-07-24 10:55:37,322 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:37,322 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:37,330 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:37,331 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:37,400 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:37,401 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:37,404 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:37,493 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:37,493 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:38,025 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:38,045 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:38,045 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:38,060 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:38,060 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:38,244 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:38,244 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:38,252 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:38,290 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:38,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:38,881 INFO L134 CoverageAnalysis]: Checked inductivity of 2739 backedges. 646 proven. 1081 refuted. 0 times theorem prover too weak. 1012 trivial. 0 not checked. [2018-07-24 10:55:38,882 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:38,882 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 29, 29, 29, 29] total 32 [2018-07-24 10:55:38,883 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:38,883 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:55:38,883 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:55:38,884 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=363, Invalid=629, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:55:38,884 INFO L87 Difference]: Start difference. First operand 249 states and 250 transitions. Second operand 32 states. [2018-07-24 10:55:39,258 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:39,258 INFO L93 Difference]: Finished difference Result 259 states and 260 transitions. [2018-07-24 10:55:39,259 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:55:39,259 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 246 [2018-07-24 10:55:39,259 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:39,261 INFO L225 Difference]: With dead ends: 259 [2018-07-24 10:55:39,261 INFO L226 Difference]: Without dead ends: 257 [2018-07-24 10:55:39,262 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1039 GetRequests, 907 SyntacticMatches, 100 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1424 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=376, Invalid=746, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:55:39,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 257 states. [2018-07-24 10:55:39,272 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 257 to 257. [2018-07-24 10:55:39,272 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 257 states. [2018-07-24 10:55:39,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 257 states to 257 states and 258 transitions. [2018-07-24 10:55:39,273 INFO L78 Accepts]: Start accepts. Automaton has 257 states and 258 transitions. Word has length 246 [2018-07-24 10:55:39,273 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:39,273 INFO L471 AbstractCegarLoop]: Abstraction has 257 states and 258 transitions. [2018-07-24 10:55:39,274 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:55:39,274 INFO L276 IsEmpty]: Start isEmpty. Operand 257 states and 258 transitions. [2018-07-24 10:55:39,275 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-07-24 10:55:39,275 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:39,275 INFO L353 BasicCegarLoop]: trace histogram [25, 25, 25, 25, 25, 24, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:39,275 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:39,276 INFO L82 PathProgramCache]: Analyzing trace with hash 227760715, now seen corresponding path program 47 times [2018-07-24 10:55:39,276 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:39,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:39,276 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:39,276 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:39,277 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:39,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:40,628 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:40,628 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:40,628 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:40,649 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:40,649 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:40,751 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-07-24 10:55:40,752 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:40,757 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:40,797 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:40,797 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:41,604 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:41,624 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:41,624 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:41,639 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:41,639 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:42,256 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 25 check-sat command(s) [2018-07-24 10:55:42,256 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:42,270 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:42,310 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:42,310 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:43,124 INFO L134 CoverageAnalysis]: Checked inductivity of 2928 backedges. 1224 proven. 600 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:43,126 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:43,126 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [53, 53, 53, 53, 53] total 53 [2018-07-24 10:55:43,126 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:43,127 INFO L450 AbstractCegarLoop]: Interpolant automaton has 53 states [2018-07-24 10:55:43,127 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 53 interpolants. [2018-07-24 10:55:43,127 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=2053, Unknown=0, NotChecked=0, Total=2756 [2018-07-24 10:55:43,127 INFO L87 Difference]: Start difference. First operand 257 states and 258 transitions. Second operand 53 states. [2018-07-24 10:55:44,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:44,422 INFO L93 Difference]: Finished difference Result 368 states and 394 transitions. [2018-07-24 10:55:44,423 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 53 states. [2018-07-24 10:55:44,423 INFO L78 Accepts]: Start accepts. Automaton has 53 states. Word has length 254 [2018-07-24 10:55:44,423 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:44,424 INFO L225 Difference]: With dead ends: 368 [2018-07-24 10:55:44,424 INFO L226 Difference]: Without dead ends: 259 [2018-07-24 10:55:44,425 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1093 GetRequests, 916 SyntacticMatches, 100 SemanticMatches, 77 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3324 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1457, Invalid=4705, Unknown=0, NotChecked=0, Total=6162 [2018-07-24 10:55:44,425 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 259 states. [2018-07-24 10:55:44,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 259 to 259. [2018-07-24 10:55:44,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-07-24 10:55:44,436 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 260 transitions. [2018-07-24 10:55:44,436 INFO L78 Accepts]: Start accepts. Automaton has 259 states and 260 transitions. Word has length 254 [2018-07-24 10:55:44,436 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:44,436 INFO L471 AbstractCegarLoop]: Abstraction has 259 states and 260 transitions. [2018-07-24 10:55:44,437 INFO L472 AbstractCegarLoop]: Interpolant automaton has 53 states. [2018-07-24 10:55:44,437 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 260 transitions. [2018-07-24 10:55:44,438 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 257 [2018-07-24 10:55:44,438 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:44,438 INFO L353 BasicCegarLoop]: trace histogram [26, 25, 25, 25, 25, 25, 24, 24, 24, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:44,439 INFO L414 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:44,439 INFO L82 PathProgramCache]: Analyzing trace with hash 813002149, now seen corresponding path program 48 times [2018-07-24 10:55:44,439 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:44,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:44,440 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:44,440 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:44,440 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:44,452 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:45,090 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 697 proven. 1246 refuted. 0 times theorem prover too weak. 1035 trivial. 0 not checked. [2018-07-24 10:55:45,090 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:45,090 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:45,097 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:45,097 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:45,203 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-07-24 10:55:45,204 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:45,208 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:45,308 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:45,308 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,879 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:45,899 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:45,899 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:45,913 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:45,913 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:46,546 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 26 check-sat command(s) [2018-07-24 10:55:46,547 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:46,555 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:46,596 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:46,596 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:47,169 INFO L134 CoverageAnalysis]: Checked inductivity of 2978 backedges. 698 proven. 1176 refuted. 0 times theorem prover too weak. 1104 trivial. 0 not checked. [2018-07-24 10:55:47,171 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:47,171 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 30, 30, 30, 30] total 33 [2018-07-24 10:55:47,171 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:47,172 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:55:47,172 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:55:47,172 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=390, Invalid=666, Unknown=0, NotChecked=0, Total=1056 [2018-07-24 10:55:47,172 INFO L87 Difference]: Start difference. First operand 259 states and 260 transitions. Second operand 33 states. [2018-07-24 10:55:47,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:47,557 INFO L93 Difference]: Finished difference Result 269 states and 270 transitions. [2018-07-24 10:55:47,557 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:55:47,557 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 256 [2018-07-24 10:55:47,558 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:47,559 INFO L225 Difference]: With dead ends: 269 [2018-07-24 10:55:47,560 INFO L226 Difference]: Without dead ends: 267 [2018-07-24 10:55:47,560 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1081 GetRequests, 944 SyntacticMatches, 104 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1533 ImplicationChecksByTransitivity, 1.6s TimeCoverageRelationStatistics Valid=403, Invalid=787, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:55:47,560 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 267 states. [2018-07-24 10:55:47,571 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 267 to 267. [2018-07-24 10:55:47,571 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 267 states. [2018-07-24 10:55:47,571 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 267 states to 267 states and 268 transitions. [2018-07-24 10:55:47,572 INFO L78 Accepts]: Start accepts. Automaton has 267 states and 268 transitions. Word has length 256 [2018-07-24 10:55:47,572 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:47,572 INFO L471 AbstractCegarLoop]: Abstraction has 267 states and 268 transitions. [2018-07-24 10:55:47,572 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:55:47,572 INFO L276 IsEmpty]: Start isEmpty. Operand 267 states and 268 transitions. [2018-07-24 10:55:47,574 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 265 [2018-07-24 10:55:47,574 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:47,574 INFO L353 BasicCegarLoop]: trace histogram [26, 26, 26, 26, 26, 25, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:47,574 INFO L414 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:47,574 INFO L82 PathProgramCache]: Analyzing trace with hash 381855824, now seen corresponding path program 49 times [2018-07-24 10:55:47,575 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:47,575 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:47,575 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:47,575 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:47,575 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:47,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:48,517 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:48,518 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:48,518 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:48,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:48,524 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:48,601 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:48,605 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:48,646 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:48,646 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:49,525 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:49,545 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:49,545 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:49,560 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:49,560 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:49,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:49,727 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:49,770 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:49,770 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:50,994 INFO L134 CoverageAnalysis]: Checked inductivity of 3175 backedges. 1325 proven. 650 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:50,995 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:50,996 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 55] total 55 [2018-07-24 10:55:50,996 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:50,996 INFO L450 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-07-24 10:55:50,996 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-07-24 10:55:50,997 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=757, Invalid=2213, Unknown=0, NotChecked=0, Total=2970 [2018-07-24 10:55:50,998 INFO L87 Difference]: Start difference. First operand 267 states and 268 transitions. Second operand 55 states. [2018-07-24 10:55:51,923 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:51,923 INFO L93 Difference]: Finished difference Result 382 states and 409 transitions. [2018-07-24 10:55:51,923 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:55:51,923 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 264 [2018-07-24 10:55:51,924 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:51,925 INFO L225 Difference]: With dead ends: 382 [2018-07-24 10:55:51,925 INFO L226 Difference]: Without dead ends: 269 [2018-07-24 10:55:51,926 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1136 GetRequests, 952 SyntacticMatches, 104 SemanticMatches, 80 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3600 ImplicationChecksByTransitivity, 3.4s TimeCoverageRelationStatistics Valid=1567, Invalid=5075, Unknown=0, NotChecked=0, Total=6642 [2018-07-24 10:55:51,926 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 269 states. [2018-07-24 10:55:51,935 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 269 to 269. [2018-07-24 10:55:51,936 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 269 states. [2018-07-24 10:55:51,936 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 269 states to 269 states and 270 transitions. [2018-07-24 10:55:51,936 INFO L78 Accepts]: Start accepts. Automaton has 269 states and 270 transitions. Word has length 264 [2018-07-24 10:55:51,937 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:51,937 INFO L471 AbstractCegarLoop]: Abstraction has 269 states and 270 transitions. [2018-07-24 10:55:51,937 INFO L472 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-07-24 10:55:51,937 INFO L276 IsEmpty]: Start isEmpty. Operand 269 states and 270 transitions. [2018-07-24 10:55:51,938 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 267 [2018-07-24 10:55:51,938 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:51,938 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 26, 26, 26, 26, 25, 25, 25, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:51,939 INFO L414 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:51,939 INFO L82 PathProgramCache]: Analyzing trace with hash -657468630, now seen corresponding path program 50 times [2018-07-24 10:55:51,939 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:51,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:51,940 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:51,940 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:51,940 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:51,953 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:52,409 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 751 proven. 1348 refuted. 0 times theorem prover too weak. 1128 trivial. 0 not checked. [2018-07-24 10:55:52,409 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:52,409 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:52,416 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:52,416 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:52,496 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:52,496 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:52,500 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:52,598 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:52,598 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:53,240 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:53,259 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:53,260 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:53,276 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:53,276 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:53,453 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:53,454 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:53,462 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:53,506 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:53,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:54,123 INFO L134 CoverageAnalysis]: Checked inductivity of 3227 backedges. 752 proven. 1275 refuted. 0 times theorem prover too weak. 1200 trivial. 0 not checked. [2018-07-24 10:55:54,125 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:54,125 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 31, 31, 31, 31] total 34 [2018-07-24 10:55:54,126 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:54,126 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:55:54,126 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:55:54,127 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=418, Invalid=704, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:55:54,127 INFO L87 Difference]: Start difference. First operand 269 states and 270 transitions. Second operand 34 states. [2018-07-24 10:55:54,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:54,498 INFO L93 Difference]: Finished difference Result 279 states and 280 transitions. [2018-07-24 10:55:54,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:55:54,498 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 266 [2018-07-24 10:55:54,499 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:54,500 INFO L225 Difference]: With dead ends: 279 [2018-07-24 10:55:54,500 INFO L226 Difference]: Without dead ends: 277 [2018-07-24 10:55:54,501 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1123 GetRequests, 981 SyntacticMatches, 108 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1646 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=431, Invalid=829, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:54,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 277 states. [2018-07-24 10:55:54,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 277 to 277. [2018-07-24 10:55:54,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 277 states. [2018-07-24 10:55:54,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 277 states to 277 states and 278 transitions. [2018-07-24 10:55:54,512 INFO L78 Accepts]: Start accepts. Automaton has 277 states and 278 transitions. Word has length 266 [2018-07-24 10:55:54,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:54,513 INFO L471 AbstractCegarLoop]: Abstraction has 277 states and 278 transitions. [2018-07-24 10:55:54,513 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:55:54,513 INFO L276 IsEmpty]: Start isEmpty. Operand 277 states and 278 transitions. [2018-07-24 10:55:54,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 275 [2018-07-24 10:55:54,514 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:54,515 INFO L353 BasicCegarLoop]: trace histogram [27, 27, 27, 27, 27, 26, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:54,515 INFO L414 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:54,515 INFO L82 PathProgramCache]: Analyzing trace with hash -864700203, now seen corresponding path program 51 times [2018-07-24 10:55:54,515 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:54,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:54,516 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:54,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:54,516 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:54,528 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:55,822 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:55:55,822 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:55,822 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:55,829 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:55,829 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:55,944 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-07-24 10:55:55,944 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:55,949 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:55,995 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:55:55,995 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:56,962 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:55:56,983 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:56,983 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:56,999 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:56,999 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:57,714 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 27 check-sat command(s) [2018-07-24 10:55:57,714 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:57,722 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:57,768 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:55:57,768 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:58,675 INFO L134 CoverageAnalysis]: Checked inductivity of 3432 backedges. 1430 proven. 702 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:55:58,677 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:58,677 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [57, 57, 57, 57, 57] total 57 [2018-07-24 10:55:58,677 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:58,678 INFO L450 AbstractCegarLoop]: Interpolant automaton has 57 states [2018-07-24 10:55:58,678 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 57 interpolants. [2018-07-24 10:55:58,678 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=813, Invalid=2379, Unknown=0, NotChecked=0, Total=3192 [2018-07-24 10:55:58,678 INFO L87 Difference]: Start difference. First operand 277 states and 278 transitions. Second operand 57 states. [2018-07-24 10:55:59,832 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:59,832 INFO L93 Difference]: Finished difference Result 396 states and 424 transitions. [2018-07-24 10:55:59,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 57 states. [2018-07-24 10:55:59,833 INFO L78 Accepts]: Start accepts. Automaton has 57 states. Word has length 274 [2018-07-24 10:55:59,833 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:59,834 INFO L225 Difference]: With dead ends: 396 [2018-07-24 10:55:59,834 INFO L226 Difference]: Without dead ends: 279 [2018-07-24 10:55:59,835 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1179 GetRequests, 988 SyntacticMatches, 108 SemanticMatches, 83 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3887 ImplicationChecksByTransitivity, 3.5s TimeCoverageRelationStatistics Valid=1681, Invalid=5459, Unknown=0, NotChecked=0, Total=7140 [2018-07-24 10:55:59,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 279 states. [2018-07-24 10:55:59,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 279 to 279. [2018-07-24 10:55:59,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 279 states. [2018-07-24 10:55:59,845 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 279 states to 279 states and 280 transitions. [2018-07-24 10:55:59,846 INFO L78 Accepts]: Start accepts. Automaton has 279 states and 280 transitions. Word has length 274 [2018-07-24 10:55:59,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:59,846 INFO L471 AbstractCegarLoop]: Abstraction has 279 states and 280 transitions. [2018-07-24 10:55:59,846 INFO L472 AbstractCegarLoop]: Interpolant automaton has 57 states. [2018-07-24 10:55:59,846 INFO L276 IsEmpty]: Start isEmpty. Operand 279 states and 280 transitions. [2018-07-24 10:55:59,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 277 [2018-07-24 10:55:59,848 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:59,848 INFO L353 BasicCegarLoop]: trace histogram [28, 27, 27, 27, 27, 27, 26, 26, 26, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:59,848 INFO L414 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:59,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1918278447, now seen corresponding path program 52 times [2018-07-24 10:55:59,849 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:59,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:59,849 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:59,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:59,850 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:59,866 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:00,695 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 807 proven. 1454 refuted. 0 times theorem prover too weak. 1225 trivial. 0 not checked. [2018-07-24 10:56:00,695 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:00,695 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:00,706 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:00,706 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:00,791 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:00,791 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:00,796 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:00,924 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:56:00,924 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:01,587 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:56:01,608 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:01,608 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:01,624 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:01,624 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:01,835 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:01,836 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:01,845 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:01,892 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:56:01,892 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:02,572 INFO L134 CoverageAnalysis]: Checked inductivity of 3486 backedges. 808 proven. 1378 refuted. 0 times theorem prover too weak. 1300 trivial. 0 not checked. [2018-07-24 10:56:02,574 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:02,574 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 32, 32, 32, 32] total 35 [2018-07-24 10:56:02,574 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:02,575 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:56:02,575 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:56:02,575 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=447, Invalid=743, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:56:02,575 INFO L87 Difference]: Start difference. First operand 279 states and 280 transitions. Second operand 35 states. [2018-07-24 10:56:03,037 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:03,038 INFO L93 Difference]: Finished difference Result 289 states and 290 transitions. [2018-07-24 10:56:03,038 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:56:03,038 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 276 [2018-07-24 10:56:03,039 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:03,041 INFO L225 Difference]: With dead ends: 289 [2018-07-24 10:56:03,041 INFO L226 Difference]: Without dead ends: 287 [2018-07-24 10:56:03,041 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1165 GetRequests, 1018 SyntacticMatches, 112 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1763 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=460, Invalid=872, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:56:03,041 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 287 states. [2018-07-24 10:56:03,053 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 287 to 287. [2018-07-24 10:56:03,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 287 states. [2018-07-24 10:56:03,054 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 287 states to 287 states and 288 transitions. [2018-07-24 10:56:03,054 INFO L78 Accepts]: Start accepts. Automaton has 287 states and 288 transitions. Word has length 276 [2018-07-24 10:56:03,054 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:03,054 INFO L471 AbstractCegarLoop]: Abstraction has 287 states and 288 transitions. [2018-07-24 10:56:03,054 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:56:03,054 INFO L276 IsEmpty]: Start isEmpty. Operand 287 states and 288 transitions. [2018-07-24 10:56:03,056 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 285 [2018-07-24 10:56:03,056 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:03,056 INFO L353 BasicCegarLoop]: trace histogram [28, 28, 28, 28, 28, 27, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:03,056 INFO L414 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:03,057 INFO L82 PathProgramCache]: Analyzing trace with hash -603280422, now seen corresponding path program 53 times [2018-07-24 10:56:03,057 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:03,057 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:03,057 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:03,058 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:03,058 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:03,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:04,092 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:04,092 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:04,092 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:04,100 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:04,100 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:04,212 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-07-24 10:56:04,212 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:04,217 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:04,279 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:04,280 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:05,221 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:05,242 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:05,242 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:05,257 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:05,257 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:06,012 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-07-24 10:56:06,012 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:06,026 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:06,074 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:06,075 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:07,029 INFO L134 CoverageAnalysis]: Checked inductivity of 3699 backedges. 1539 proven. 756 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:07,030 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:07,031 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [59, 59, 59, 59, 59] total 59 [2018-07-24 10:56:07,031 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:07,031 INFO L450 AbstractCegarLoop]: Interpolant automaton has 59 states [2018-07-24 10:56:07,031 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 59 interpolants. [2018-07-24 10:56:07,032 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=871, Invalid=2551, Unknown=0, NotChecked=0, Total=3422 [2018-07-24 10:56:07,032 INFO L87 Difference]: Start difference. First operand 287 states and 288 transitions. Second operand 59 states. [2018-07-24 10:56:08,603 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:08,604 INFO L93 Difference]: Finished difference Result 410 states and 439 transitions. [2018-07-24 10:56:08,604 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 59 states. [2018-07-24 10:56:08,604 INFO L78 Accepts]: Start accepts. Automaton has 59 states. Word has length 284 [2018-07-24 10:56:08,604 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:08,605 INFO L225 Difference]: With dead ends: 410 [2018-07-24 10:56:08,605 INFO L226 Difference]: Without dead ends: 289 [2018-07-24 10:56:08,606 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1222 GetRequests, 1024 SyntacticMatches, 112 SemanticMatches, 86 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4185 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1799, Invalid=5857, Unknown=0, NotChecked=0, Total=7656 [2018-07-24 10:56:08,607 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 289 states. [2018-07-24 10:56:08,619 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 289 to 289. [2018-07-24 10:56:08,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 289 states. [2018-07-24 10:56:08,620 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 289 states to 289 states and 290 transitions. [2018-07-24 10:56:08,620 INFO L78 Accepts]: Start accepts. Automaton has 289 states and 290 transitions. Word has length 284 [2018-07-24 10:56:08,620 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:08,620 INFO L471 AbstractCegarLoop]: Abstraction has 289 states and 290 transitions. [2018-07-24 10:56:08,620 INFO L472 AbstractCegarLoop]: Interpolant automaton has 59 states. [2018-07-24 10:56:08,621 INFO L276 IsEmpty]: Start isEmpty. Operand 289 states and 290 transitions. [2018-07-24 10:56:08,640 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 287 [2018-07-24 10:56:08,641 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:08,641 INFO L353 BasicCegarLoop]: trace histogram [29, 28, 28, 28, 28, 28, 27, 27, 27, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:08,641 INFO L414 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:08,643 INFO L82 PathProgramCache]: Analyzing trace with hash -400562764, now seen corresponding path program 54 times [2018-07-24 10:56:08,643 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:08,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:08,644 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:08,644 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:08,644 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:08,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:09,206 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 865 proven. 1564 refuted. 0 times theorem prover too weak. 1326 trivial. 0 not checked. [2018-07-24 10:56:09,207 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:09,207 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:09,215 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:09,215 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:09,328 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-07-24 10:56:09,329 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:09,333 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:09,443 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:09,443 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:10,157 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:10,177 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:10,178 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:10,192 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:10,192 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:11,004 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-07-24 10:56:11,004 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:11,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:11,060 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:11,060 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:11,803 INFO L134 CoverageAnalysis]: Checked inductivity of 3755 backedges. 866 proven. 1485 refuted. 0 times theorem prover too weak. 1404 trivial. 0 not checked. [2018-07-24 10:56:11,805 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:11,805 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 33, 33, 33, 33] total 36 [2018-07-24 10:56:11,806 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:11,806 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:56:11,806 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:56:11,806 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=477, Invalid=783, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:56:11,807 INFO L87 Difference]: Start difference. First operand 289 states and 290 transitions. Second operand 36 states. [2018-07-24 10:56:12,176 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:12,176 INFO L93 Difference]: Finished difference Result 299 states and 300 transitions. [2018-07-24 10:56:12,177 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:56:12,177 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 286 [2018-07-24 10:56:12,177 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:12,179 INFO L225 Difference]: With dead ends: 299 [2018-07-24 10:56:12,179 INFO L226 Difference]: Without dead ends: 297 [2018-07-24 10:56:12,180 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1207 GetRequests, 1055 SyntacticMatches, 116 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1884 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=490, Invalid=916, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:56:12,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 297 states. [2018-07-24 10:56:12,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 297 to 297. [2018-07-24 10:56:12,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 297 states. [2018-07-24 10:56:12,191 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 297 states to 297 states and 298 transitions. [2018-07-24 10:56:12,192 INFO L78 Accepts]: Start accepts. Automaton has 297 states and 298 transitions. Word has length 286 [2018-07-24 10:56:12,192 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:12,192 INFO L471 AbstractCegarLoop]: Abstraction has 297 states and 298 transitions. [2018-07-24 10:56:12,192 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:56:12,192 INFO L276 IsEmpty]: Start isEmpty. Operand 297 states and 298 transitions. [2018-07-24 10:56:12,194 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 295 [2018-07-24 10:56:12,194 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:12,194 INFO L353 BasicCegarLoop]: trace histogram [29, 29, 29, 29, 29, 28, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:12,194 INFO L414 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:12,195 INFO L82 PathProgramCache]: Analyzing trace with hash 1215799647, now seen corresponding path program 55 times [2018-07-24 10:56:12,195 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:12,195 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:12,195 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:12,195 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:12,196 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:12,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:13,481 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:13,482 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:13,482 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:13,490 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:13,490 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:13,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:13,575 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:13,627 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:13,627 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:14,646 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:14,667 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:14,667 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 111 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:14,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:14,682 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:14,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:14,871 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:14,916 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:14,916 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:16,279 INFO L134 CoverageAnalysis]: Checked inductivity of 3976 backedges. 1652 proven. 812 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:16,280 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:16,281 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [61, 61, 61, 61, 61] total 61 [2018-07-24 10:56:16,281 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:16,281 INFO L450 AbstractCegarLoop]: Interpolant automaton has 61 states [2018-07-24 10:56:16,281 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 61 interpolants. [2018-07-24 10:56:16,282 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=931, Invalid=2729, Unknown=0, NotChecked=0, Total=3660 [2018-07-24 10:56:16,282 INFO L87 Difference]: Start difference. First operand 297 states and 298 transitions. Second operand 61 states. [2018-07-24 10:56:17,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:17,945 INFO L93 Difference]: Finished difference Result 424 states and 454 transitions. [2018-07-24 10:56:17,945 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 61 states. [2018-07-24 10:56:17,945 INFO L78 Accepts]: Start accepts. Automaton has 61 states. Word has length 294 [2018-07-24 10:56:17,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:17,946 INFO L225 Difference]: With dead ends: 424 [2018-07-24 10:56:17,946 INFO L226 Difference]: Without dead ends: 299 [2018-07-24 10:56:17,947 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1265 GetRequests, 1060 SyntacticMatches, 116 SemanticMatches, 89 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4494 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=1921, Invalid=6269, Unknown=0, NotChecked=0, Total=8190 [2018-07-24 10:56:17,947 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 299 states. [2018-07-24 10:56:17,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 299 to 299. [2018-07-24 10:56:17,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 299 states. [2018-07-24 10:56:17,959 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 299 states to 299 states and 300 transitions. [2018-07-24 10:56:17,959 INFO L78 Accepts]: Start accepts. Automaton has 299 states and 300 transitions. Word has length 294 [2018-07-24 10:56:17,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:17,959 INFO L471 AbstractCegarLoop]: Abstraction has 299 states and 300 transitions. [2018-07-24 10:56:17,959 INFO L472 AbstractCegarLoop]: Interpolant automaton has 61 states. [2018-07-24 10:56:17,959 INFO L276 IsEmpty]: Start isEmpty. Operand 299 states and 300 transitions. [2018-07-24 10:56:17,961 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 297 [2018-07-24 10:56:17,961 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:17,961 INFO L353 BasicCegarLoop]: trace histogram [30, 29, 29, 29, 29, 29, 28, 28, 28, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:17,962 INFO L414 AbstractCegarLoop]: === Iteration 59 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:17,962 INFO L82 PathProgramCache]: Analyzing trace with hash -1260793159, now seen corresponding path program 56 times [2018-07-24 10:56:17,962 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:17,962 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:17,963 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:17,963 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:17,963 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:17,977 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:18,540 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 925 proven. 1678 refuted. 0 times theorem prover too weak. 1431 trivial. 0 not checked. [2018-07-24 10:56:18,540 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:18,541 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 112 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:18,548 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:18,549 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:18,635 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:18,635 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:18,638 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:18,748 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:18,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:19,526 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:19,547 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:19,547 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 113 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:19,562 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:19,562 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:19,756 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:19,756 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:19,764 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:19,815 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:19,816 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:20,568 INFO L134 CoverageAnalysis]: Checked inductivity of 4034 backedges. 926 proven. 1596 refuted. 0 times theorem prover too weak. 1512 trivial. 0 not checked. [2018-07-24 10:56:20,569 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:20,570 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 34, 34, 34, 34] total 37 [2018-07-24 10:56:20,570 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:20,570 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:56:20,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:56:20,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=508, Invalid=824, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:56:20,571 INFO L87 Difference]: Start difference. First operand 299 states and 300 transitions. Second operand 37 states. [2018-07-24 10:56:21,137 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:21,138 INFO L93 Difference]: Finished difference Result 309 states and 310 transitions. [2018-07-24 10:56:21,138 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-24 10:56:21,138 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 296 [2018-07-24 10:56:21,139 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:21,140 INFO L225 Difference]: With dead ends: 309 [2018-07-24 10:56:21,140 INFO L226 Difference]: Without dead ends: 307 [2018-07-24 10:56:21,141 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1249 GetRequests, 1092 SyntacticMatches, 120 SemanticMatches, 37 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2009 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=521, Invalid=961, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:56:21,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 307 states. [2018-07-24 10:56:21,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 307 to 307. [2018-07-24 10:56:21,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 307 states. [2018-07-24 10:56:21,151 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 307 states to 307 states and 308 transitions. [2018-07-24 10:56:21,151 INFO L78 Accepts]: Start accepts. Automaton has 307 states and 308 transitions. Word has length 296 [2018-07-24 10:56:21,152 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:21,152 INFO L471 AbstractCegarLoop]: Abstraction has 307 states and 308 transitions. [2018-07-24 10:56:21,152 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:56:21,152 INFO L276 IsEmpty]: Start isEmpty. Operand 307 states and 308 transitions. [2018-07-24 10:56:21,153 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 305 [2018-07-24 10:56:21,154 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:21,154 INFO L353 BasicCegarLoop]: trace histogram [30, 30, 30, 30, 30, 29, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:21,154 INFO L414 AbstractCegarLoop]: === Iteration 60 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:21,154 INFO L82 PathProgramCache]: Analyzing trace with hash -1941259932, now seen corresponding path program 57 times [2018-07-24 10:56:21,154 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:21,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:21,155 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:21,155 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:21,155 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:21,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:22,389 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:22,389 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:22,389 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 114 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:22,396 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:22,396 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:22,515 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-07-24 10:56:22,515 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:22,520 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:22,575 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:22,576 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:23,686 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:23,707 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:23,707 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 115 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:23,721 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:23,721 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:24,610 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 30 check-sat command(s) [2018-07-24 10:56:24,610 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:24,619 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:24,674 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:24,674 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:25,917 INFO L134 CoverageAnalysis]: Checked inductivity of 4263 backedges. 1769 proven. 870 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:25,919 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:25,919 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [63, 63, 63, 63, 63] total 63 [2018-07-24 10:56:25,919 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:25,919 INFO L450 AbstractCegarLoop]: Interpolant automaton has 63 states [2018-07-24 10:56:25,920 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 63 interpolants. [2018-07-24 10:56:25,920 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=993, Invalid=2913, Unknown=0, NotChecked=0, Total=3906 [2018-07-24 10:56:25,920 INFO L87 Difference]: Start difference. First operand 307 states and 308 transitions. Second operand 63 states. [2018-07-24 10:56:27,785 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:27,786 INFO L93 Difference]: Finished difference Result 438 states and 469 transitions. [2018-07-24 10:56:27,786 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 63 states. [2018-07-24 10:56:27,786 INFO L78 Accepts]: Start accepts. Automaton has 63 states. Word has length 304 [2018-07-24 10:56:27,786 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:27,787 INFO L225 Difference]: With dead ends: 438 [2018-07-24 10:56:27,787 INFO L226 Difference]: Without dead ends: 309 [2018-07-24 10:56:27,788 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1308 GetRequests, 1096 SyntacticMatches, 120 SemanticMatches, 92 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4814 ImplicationChecksByTransitivity, 4.1s TimeCoverageRelationStatistics Valid=2047, Invalid=6695, Unknown=0, NotChecked=0, Total=8742 [2018-07-24 10:56:27,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 309 states. [2018-07-24 10:56:27,806 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 309 to 309. [2018-07-24 10:56:27,806 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 309 states. [2018-07-24 10:56:27,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 309 states to 309 states and 310 transitions. [2018-07-24 10:56:27,807 INFO L78 Accepts]: Start accepts. Automaton has 309 states and 310 transitions. Word has length 304 [2018-07-24 10:56:27,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:27,807 INFO L471 AbstractCegarLoop]: Abstraction has 309 states and 310 transitions. [2018-07-24 10:56:27,807 INFO L472 AbstractCegarLoop]: Interpolant automaton has 63 states. [2018-07-24 10:56:27,807 INFO L276 IsEmpty]: Start isEmpty. Operand 309 states and 310 transitions. [2018-07-24 10:56:27,809 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 307 [2018-07-24 10:56:27,809 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:27,809 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 30, 30, 30, 30, 29, 29, 29, 29, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:27,809 INFO L414 AbstractCegarLoop]: === Iteration 61 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:27,810 INFO L82 PathProgramCache]: Analyzing trace with hash -2067103170, now seen corresponding path program 58 times [2018-07-24 10:56:27,810 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:27,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:27,810 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:27,811 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:27,811 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:27,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:28,442 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 987 proven. 1796 refuted. 0 times theorem prover too weak. 1540 trivial. 0 not checked. [2018-07-24 10:56:28,442 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:28,442 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 116 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:28,450 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:28,450 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:28,544 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:28,544 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:28,548 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:28,665 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:28,665 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:29,516 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:29,536 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:29,536 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 117 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:29,551 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:29,551 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:29,790 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:29,790 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:29,804 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:29,856 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:29,856 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:30,719 INFO L134 CoverageAnalysis]: Checked inductivity of 4323 backedges. 988 proven. 1711 refuted. 0 times theorem prover too weak. 1624 trivial. 0 not checked. [2018-07-24 10:56:30,720 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:30,721 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 35, 35, 35, 35] total 38 [2018-07-24 10:56:30,721 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:30,721 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:56:30,721 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:56:30,722 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=540, Invalid=866, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:56:30,722 INFO L87 Difference]: Start difference. First operand 309 states and 310 transitions. Second operand 38 states. [2018-07-24 10:56:31,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:31,271 INFO L93 Difference]: Finished difference Result 319 states and 320 transitions. [2018-07-24 10:56:31,271 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:56:31,271 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 306 [2018-07-24 10:56:31,272 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:31,273 INFO L225 Difference]: With dead ends: 319 [2018-07-24 10:56:31,273 INFO L226 Difference]: Without dead ends: 317 [2018-07-24 10:56:31,274 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1291 GetRequests, 1129 SyntacticMatches, 124 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2138 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=553, Invalid=1007, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:56:31,274 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 317 states. [2018-07-24 10:56:31,282 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 317 to 317. [2018-07-24 10:56:31,282 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 317 states. [2018-07-24 10:56:31,283 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 317 states to 317 states and 318 transitions. [2018-07-24 10:56:31,283 INFO L78 Accepts]: Start accepts. Automaton has 317 states and 318 transitions. Word has length 306 [2018-07-24 10:56:31,283 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:31,283 INFO L471 AbstractCegarLoop]: Abstraction has 317 states and 318 transitions. [2018-07-24 10:56:31,283 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:56:31,283 INFO L276 IsEmpty]: Start isEmpty. Operand 317 states and 318 transitions. [2018-07-24 10:56:31,285 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2018-07-24 10:56:31,285 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:31,285 INFO L353 BasicCegarLoop]: trace histogram [31, 31, 31, 31, 31, 30, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:31,285 INFO L414 AbstractCegarLoop]: === Iteration 62 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:31,286 INFO L82 PathProgramCache]: Analyzing trace with hash 1001001961, now seen corresponding path program 59 times [2018-07-24 10:56:31,286 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:31,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:31,286 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:31,286 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:31,287 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:31,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:32,600 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:32,601 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:32,601 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 118 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:32,608 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:32,609 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:32,739 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2018-07-24 10:56:32,739 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:32,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:32,832 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:32,832 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:34,166 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:34,186 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:34,186 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 119 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:34,200 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:34,201 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:35,112 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 31 check-sat command(s) [2018-07-24 10:56:35,113 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:35,121 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:35,198 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:35,198 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:36,724 INFO L134 CoverageAnalysis]: Checked inductivity of 4560 backedges. 1890 proven. 930 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:36,726 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:36,726 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [65, 65, 65, 65, 65] total 65 [2018-07-24 10:56:36,726 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:36,726 INFO L450 AbstractCegarLoop]: Interpolant automaton has 65 states [2018-07-24 10:56:36,727 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 65 interpolants. [2018-07-24 10:56:36,727 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1057, Invalid=3103, Unknown=0, NotChecked=0, Total=4160 [2018-07-24 10:56:36,727 INFO L87 Difference]: Start difference. First operand 317 states and 318 transitions. Second operand 65 states. [2018-07-24 10:56:38,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:38,590 INFO L93 Difference]: Finished difference Result 452 states and 484 transitions. [2018-07-24 10:56:38,590 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 65 states. [2018-07-24 10:56:38,590 INFO L78 Accepts]: Start accepts. Automaton has 65 states. Word has length 314 [2018-07-24 10:56:38,591 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:38,592 INFO L225 Difference]: With dead ends: 452 [2018-07-24 10:56:38,592 INFO L226 Difference]: Without dead ends: 319 [2018-07-24 10:56:38,593 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1351 GetRequests, 1132 SyntacticMatches, 124 SemanticMatches, 95 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5145 ImplicationChecksByTransitivity, 4.6s TimeCoverageRelationStatistics Valid=2177, Invalid=7135, Unknown=0, NotChecked=0, Total=9312 [2018-07-24 10:56:38,593 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 319 states. [2018-07-24 10:56:38,605 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 319 to 319. [2018-07-24 10:56:38,605 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 319 states. [2018-07-24 10:56:38,606 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 319 states to 319 states and 320 transitions. [2018-07-24 10:56:38,606 INFO L78 Accepts]: Start accepts. Automaton has 319 states and 320 transitions. Word has length 314 [2018-07-24 10:56:38,606 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:38,606 INFO L471 AbstractCegarLoop]: Abstraction has 319 states and 320 transitions. [2018-07-24 10:56:38,606 INFO L472 AbstractCegarLoop]: Interpolant automaton has 65 states. [2018-07-24 10:56:38,607 INFO L276 IsEmpty]: Start isEmpty. Operand 319 states and 320 transitions. [2018-07-24 10:56:38,608 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 317 [2018-07-24 10:56:38,608 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:38,609 INFO L353 BasicCegarLoop]: trace histogram [32, 31, 31, 31, 31, 31, 30, 30, 30, 30, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:38,609 INFO L414 AbstractCegarLoop]: === Iteration 63 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:38,609 INFO L82 PathProgramCache]: Analyzing trace with hash 1473254467, now seen corresponding path program 60 times [2018-07-24 10:56:38,609 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:38,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:38,610 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:38,610 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:38,610 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:38,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:39,294 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1051 proven. 1918 refuted. 0 times theorem prover too weak. 1653 trivial. 0 not checked. [2018-07-24 10:56:39,295 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:39,295 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 120 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:39,301 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:39,301 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:39,563 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 32 check-sat command(s) [2018-07-24 10:56:39,564 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:39,567 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:39,681 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:39,681 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:40,525 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:40,545 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:40,545 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 121 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:40,559 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:40,560 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:41,483 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 32 check-sat command(s) [2018-07-24 10:56:41,483 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:41,494 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:41,553 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:41,553 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:42,491 INFO L134 CoverageAnalysis]: Checked inductivity of 4622 backedges. 1052 proven. 1830 refuted. 0 times theorem prover too weak. 1740 trivial. 0 not checked. [2018-07-24 10:56:42,492 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:42,493 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 36, 36, 36, 36] total 39 [2018-07-24 10:56:42,493 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:42,494 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:56:42,494 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:56:42,494 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=909, Unknown=0, NotChecked=0, Total=1482 [2018-07-24 10:56:42,495 INFO L87 Difference]: Start difference. First operand 319 states and 320 transitions. Second operand 39 states. [2018-07-24 10:56:42,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:42,988 INFO L93 Difference]: Finished difference Result 329 states and 330 transitions. [2018-07-24 10:56:42,988 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:56:42,988 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 316 [2018-07-24 10:56:42,989 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:42,990 INFO L225 Difference]: With dead ends: 329 [2018-07-24 10:56:42,990 INFO L226 Difference]: Without dead ends: 327 [2018-07-24 10:56:42,991 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1333 GetRequests, 1166 SyntacticMatches, 128 SemanticMatches, 39 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2271 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=586, Invalid=1054, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:56:42,991 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 327 states. [2018-07-24 10:56:42,999 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 327 to 327. [2018-07-24 10:56:43,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 327 states. [2018-07-24 10:56:43,000 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 327 states to 327 states and 328 transitions. [2018-07-24 10:56:43,000 INFO L78 Accepts]: Start accepts. Automaton has 327 states and 328 transitions. Word has length 316 [2018-07-24 10:56:43,000 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:43,001 INFO L471 AbstractCegarLoop]: Abstraction has 327 states and 328 transitions. [2018-07-24 10:56:43,001 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:56:43,001 INFO L276 IsEmpty]: Start isEmpty. Operand 327 states and 328 transitions. [2018-07-24 10:56:43,002 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 325 [2018-07-24 10:56:43,002 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:43,002 INFO L353 BasicCegarLoop]: trace histogram [32, 32, 32, 32, 32, 31, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:43,002 INFO L414 AbstractCegarLoop]: === Iteration 64 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:43,002 INFO L82 PathProgramCache]: Analyzing trace with hash 643027182, now seen corresponding path program 61 times [2018-07-24 10:56:43,003 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:43,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:43,003 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:43,003 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:43,003 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:43,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:44,520 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:44,520 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:44,520 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 122 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:44,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:44,528 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:44,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:44,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:44,688 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:44,689 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:45,932 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:45,952 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:45,953 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 123 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:45,969 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:45,969 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:46,173 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:46,182 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:46,244 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:46,244 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:47,762 INFO L134 CoverageAnalysis]: Checked inductivity of 4867 backedges. 2015 proven. 992 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:47,764 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:47,764 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [67, 67, 67, 67, 67] total 67 [2018-07-24 10:56:47,764 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:47,765 INFO L450 AbstractCegarLoop]: Interpolant automaton has 67 states [2018-07-24 10:56:47,766 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 67 interpolants. [2018-07-24 10:56:47,766 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1123, Invalid=3299, Unknown=0, NotChecked=0, Total=4422 [2018-07-24 10:56:47,767 INFO L87 Difference]: Start difference. First operand 327 states and 328 transitions. Second operand 67 states. [2018-07-24 10:56:49,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:49,849 INFO L93 Difference]: Finished difference Result 466 states and 499 transitions. [2018-07-24 10:56:49,849 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 67 states. [2018-07-24 10:56:49,850 INFO L78 Accepts]: Start accepts. Automaton has 67 states. Word has length 324 [2018-07-24 10:56:49,850 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:49,851 INFO L225 Difference]: With dead ends: 466 [2018-07-24 10:56:49,851 INFO L226 Difference]: Without dead ends: 329 [2018-07-24 10:56:49,852 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1394 GetRequests, 1168 SyntacticMatches, 128 SemanticMatches, 98 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5487 ImplicationChecksByTransitivity, 4.8s TimeCoverageRelationStatistics Valid=2311, Invalid=7589, Unknown=0, NotChecked=0, Total=9900 [2018-07-24 10:56:49,852 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 329 states. [2018-07-24 10:56:49,865 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 329 to 329. [2018-07-24 10:56:49,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 329 states. [2018-07-24 10:56:49,866 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 329 states to 329 states and 330 transitions. [2018-07-24 10:56:49,866 INFO L78 Accepts]: Start accepts. Automaton has 329 states and 330 transitions. Word has length 324 [2018-07-24 10:56:49,867 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:49,867 INFO L471 AbstractCegarLoop]: Abstraction has 329 states and 330 transitions. [2018-07-24 10:56:49,867 INFO L472 AbstractCegarLoop]: Interpolant automaton has 67 states. [2018-07-24 10:56:49,867 INFO L276 IsEmpty]: Start isEmpty. Operand 329 states and 330 transitions. [2018-07-24 10:56:49,869 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 327 [2018-07-24 10:56:49,869 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:49,869 INFO L353 BasicCegarLoop]: trace histogram [33, 32, 32, 32, 32, 32, 31, 31, 31, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:49,869 INFO L414 AbstractCegarLoop]: === Iteration 65 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:49,870 INFO L82 PathProgramCache]: Analyzing trace with hash 593537224, now seen corresponding path program 62 times [2018-07-24 10:56:49,871 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:49,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:49,871 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:49,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:49,872 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:49,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:50,618 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1117 proven. 2044 refuted. 0 times theorem prover too weak. 1770 trivial. 0 not checked. [2018-07-24 10:56:50,619 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:50,619 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 124 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:50,628 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:50,628 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:50,725 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:50,726 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:50,730 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:51,088 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:51,088 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:52,168 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:52,188 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:52,189 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 125 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:52,203 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:52,203 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:52,418 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:52,418 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:52,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:52,481 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:52,481 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:53,397 INFO L134 CoverageAnalysis]: Checked inductivity of 4931 backedges. 1118 proven. 1953 refuted. 0 times theorem prover too weak. 1860 trivial. 0 not checked. [2018-07-24 10:56:53,399 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:53,399 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 37, 37, 37, 37] total 40 [2018-07-24 10:56:53,399 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:53,400 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:56:53,400 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:56:53,400 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=607, Invalid=953, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:56:53,400 INFO L87 Difference]: Start difference. First operand 329 states and 330 transitions. Second operand 40 states. [2018-07-24 10:56:53,851 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:53,852 INFO L93 Difference]: Finished difference Result 339 states and 340 transitions. [2018-07-24 10:56:53,852 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:56:53,852 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 326 [2018-07-24 10:56:53,853 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:53,855 INFO L225 Difference]: With dead ends: 339 [2018-07-24 10:56:53,855 INFO L226 Difference]: Without dead ends: 337 [2018-07-24 10:56:53,855 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1375 GetRequests, 1203 SyntacticMatches, 132 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2408 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=620, Invalid=1102, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:56:53,855 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 337 states. [2018-07-24 10:56:53,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 337 to 337. [2018-07-24 10:56:53,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 337 states. [2018-07-24 10:56:53,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 337 states to 337 states and 338 transitions. [2018-07-24 10:56:53,868 INFO L78 Accepts]: Start accepts. Automaton has 337 states and 338 transitions. Word has length 326 [2018-07-24 10:56:53,868 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:53,868 INFO L471 AbstractCegarLoop]: Abstraction has 337 states and 338 transitions. [2018-07-24 10:56:53,869 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:56:53,869 INFO L276 IsEmpty]: Start isEmpty. Operand 337 states and 338 transitions. [2018-07-24 10:56:53,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 335 [2018-07-24 10:56:53,870 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:53,870 INFO L353 BasicCegarLoop]: trace histogram [33, 33, 33, 33, 33, 32, 32, 32, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:53,871 INFO L414 AbstractCegarLoop]: === Iteration 66 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:53,871 INFO L82 PathProgramCache]: Analyzing trace with hash -107081613, now seen corresponding path program 63 times [2018-07-24 10:56:53,871 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:53,871 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:53,871 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:53,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:53,872 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:53,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:55,651 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:56:55,651 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:55,651 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 126 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:55,660 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:55,661 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:55,791 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-07-24 10:56:55,791 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:55,796 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:55,861 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:56:55,861 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:57,515 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:56:57,536 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:57,536 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 127 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:57,550 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:57,550 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:58,565 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 33 check-sat command(s) [2018-07-24 10:56:58,566 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:58,576 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:58,637 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:56:58,637 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:59,996 INFO L134 CoverageAnalysis]: Checked inductivity of 5184 backedges. 2144 proven. 1056 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:56:59,997 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:59,998 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [69, 69, 69, 69, 69] total 69 [2018-07-24 10:56:59,998 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:59,998 INFO L450 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-07-24 10:56:59,999 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-07-24 10:56:59,999 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1191, Invalid=3501, Unknown=0, NotChecked=0, Total=4692 [2018-07-24 10:57:00,000 INFO L87 Difference]: Start difference. First operand 337 states and 338 transitions. Second operand 69 states. [2018-07-24 10:57:02,538 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:02,539 INFO L93 Difference]: Finished difference Result 480 states and 514 transitions. [2018-07-24 10:57:02,539 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-07-24 10:57:02,539 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 334 [2018-07-24 10:57:02,540 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:02,541 INFO L225 Difference]: With dead ends: 480 [2018-07-24 10:57:02,541 INFO L226 Difference]: Without dead ends: 339 [2018-07-24 10:57:02,543 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1437 GetRequests, 1204 SyntacticMatches, 132 SemanticMatches, 101 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5840 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=2449, Invalid=8057, Unknown=0, NotChecked=0, Total=10506 [2018-07-24 10:57:02,543 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 339 states. [2018-07-24 10:57:02,556 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 339 to 339. [2018-07-24 10:57:02,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 339 states. [2018-07-24 10:57:02,556 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 339 states to 339 states and 340 transitions. [2018-07-24 10:57:02,557 INFO L78 Accepts]: Start accepts. Automaton has 339 states and 340 transitions. Word has length 334 [2018-07-24 10:57:02,557 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:02,557 INFO L471 AbstractCegarLoop]: Abstraction has 339 states and 340 transitions. [2018-07-24 10:57:02,557 INFO L472 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-07-24 10:57:02,557 INFO L276 IsEmpty]: Start isEmpty. Operand 339 states and 340 transitions. [2018-07-24 10:57:02,559 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 337 [2018-07-24 10:57:02,559 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:02,559 INFO L353 BasicCegarLoop]: trace histogram [34, 33, 33, 33, 33, 33, 32, 32, 32, 32, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:02,559 INFO L414 AbstractCegarLoop]: === Iteration 67 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:02,559 INFO L82 PathProgramCache]: Analyzing trace with hash -192258099, now seen corresponding path program 64 times [2018-07-24 10:57:02,559 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:02,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:02,560 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:02,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:02,560 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:02,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:03,226 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1185 proven. 2174 refuted. 0 times theorem prover too weak. 1891 trivial. 0 not checked. [2018-07-24 10:57:03,226 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:03,226 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 128 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:03,234 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:03,234 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:03,337 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:03,337 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:03,342 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:03,474 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:57:03,475 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:04,440 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:57:04,460 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:04,460 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 129 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:04,475 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:04,476 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:04,739 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:04,739 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:04,748 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:04,821 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:57:04,821 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:05,752 INFO L134 CoverageAnalysis]: Checked inductivity of 5250 backedges. 1186 proven. 2080 refuted. 0 times theorem prover too weak. 1984 trivial. 0 not checked. [2018-07-24 10:57:05,754 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:05,754 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 38, 38, 38, 38] total 41 [2018-07-24 10:57:05,754 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:05,755 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:57:05,755 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:57:05,755 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=642, Invalid=998, Unknown=0, NotChecked=0, Total=1640 [2018-07-24 10:57:05,755 INFO L87 Difference]: Start difference. First operand 339 states and 340 transitions. Second operand 41 states. [2018-07-24 10:57:06,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:06,294 INFO L93 Difference]: Finished difference Result 349 states and 350 transitions. [2018-07-24 10:57:06,294 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 10:57:06,295 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 336 [2018-07-24 10:57:06,295 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:06,297 INFO L225 Difference]: With dead ends: 349 [2018-07-24 10:57:06,297 INFO L226 Difference]: Without dead ends: 347 [2018-07-24 10:57:06,298 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1417 GetRequests, 1240 SyntacticMatches, 136 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2549 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=655, Invalid=1151, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:57:06,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 347 states. [2018-07-24 10:57:06,312 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 347 to 347. [2018-07-24 10:57:06,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 347 states. [2018-07-24 10:57:06,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 347 states to 347 states and 348 transitions. [2018-07-24 10:57:06,313 INFO L78 Accepts]: Start accepts. Automaton has 347 states and 348 transitions. Word has length 336 [2018-07-24 10:57:06,313 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:06,314 INFO L471 AbstractCegarLoop]: Abstraction has 347 states and 348 transitions. [2018-07-24 10:57:06,314 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:57:06,314 INFO L276 IsEmpty]: Start isEmpty. Operand 347 states and 348 transitions. [2018-07-24 10:57:06,316 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 345 [2018-07-24 10:57:06,316 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:06,316 INFO L353 BasicCegarLoop]: trace histogram [34, 34, 34, 34, 34, 33, 33, 33, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:06,316 INFO L414 AbstractCegarLoop]: === Iteration 68 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:06,316 INFO L82 PathProgramCache]: Analyzing trace with hash 1651962488, now seen corresponding path program 65 times [2018-07-24 10:57:06,317 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:06,317 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:06,317 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:06,317 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:06,317 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:06,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:08,218 INFO L134 CoverageAnalysis]: Checked inductivity of 5511 backedges. 2277 proven. 1122 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:08,218 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:08,219 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 130 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:08,227 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:08,227 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:08,371 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 34 check-sat command(s) [2018-07-24 10:57:08,371 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:08,375 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:08,443 INFO L134 CoverageAnalysis]: Checked inductivity of 5511 backedges. 2277 proven. 1122 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:08,443 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:09,815 INFO L134 CoverageAnalysis]: Checked inductivity of 5511 backedges. 2277 proven. 1122 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:09,836 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:09,836 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 131 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:09,852 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:09,852 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:10,926 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 34 check-sat command(s) [2018-07-24 10:57:10,927 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:10,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:11,009 INFO L134 CoverageAnalysis]: Checked inductivity of 5511 backedges. 2277 proven. 1122 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:11,009 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:12,694 INFO L134 CoverageAnalysis]: Checked inductivity of 5511 backedges. 2277 proven. 1122 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:12,696 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:12,696 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [71, 71, 71, 71, 71] total 71 [2018-07-24 10:57:12,697 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:12,697 INFO L450 AbstractCegarLoop]: Interpolant automaton has 71 states [2018-07-24 10:57:12,697 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 71 interpolants. [2018-07-24 10:57:12,698 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1261, Invalid=3709, Unknown=0, NotChecked=0, Total=4970 [2018-07-24 10:57:12,698 INFO L87 Difference]: Start difference. First operand 347 states and 348 transitions. Second operand 71 states. [2018-07-24 10:57:15,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:15,028 INFO L93 Difference]: Finished difference Result 494 states and 529 transitions. [2018-07-24 10:57:15,028 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 71 states. [2018-07-24 10:57:15,029 INFO L78 Accepts]: Start accepts. Automaton has 71 states. Word has length 344 [2018-07-24 10:57:15,029 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:15,030 INFO L225 Difference]: With dead ends: 494 [2018-07-24 10:57:15,030 INFO L226 Difference]: Without dead ends: 349 [2018-07-24 10:57:15,031 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1480 GetRequests, 1240 SyntacticMatches, 136 SemanticMatches, 104 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6204 ImplicationChecksByTransitivity, 5.5s TimeCoverageRelationStatistics Valid=2591, Invalid=8539, Unknown=0, NotChecked=0, Total=11130 [2018-07-24 10:57:15,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 349 states. [2018-07-24 10:57:15,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 349 to 349. [2018-07-24 10:57:15,044 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 349 states. [2018-07-24 10:57:15,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 349 states to 349 states and 350 transitions. [2018-07-24 10:57:15,045 INFO L78 Accepts]: Start accepts. Automaton has 349 states and 350 transitions. Word has length 344 [2018-07-24 10:57:15,045 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:15,045 INFO L471 AbstractCegarLoop]: Abstraction has 349 states and 350 transitions. [2018-07-24 10:57:15,045 INFO L472 AbstractCegarLoop]: Interpolant automaton has 71 states. [2018-07-24 10:57:15,045 INFO L276 IsEmpty]: Start isEmpty. Operand 349 states and 350 transitions. [2018-07-24 10:57:15,046 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 347 [2018-07-24 10:57:15,047 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:15,047 INFO L353 BasicCegarLoop]: trace histogram [35, 34, 34, 34, 34, 34, 33, 33, 33, 33, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:15,047 INFO L414 AbstractCegarLoop]: === Iteration 69 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:15,047 INFO L82 PathProgramCache]: Analyzing trace with hash -1846322862, now seen corresponding path program 66 times [2018-07-24 10:57:15,047 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:15,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:15,048 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:15,048 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:15,048 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:15,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:15,779 INFO L134 CoverageAnalysis]: Checked inductivity of 5579 backedges. 1255 proven. 2308 refuted. 0 times theorem prover too weak. 2016 trivial. 0 not checked. [2018-07-24 10:57:15,779 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:15,780 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 132 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:15,790 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:15,790 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:15,936 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-07-24 10:57:15,936 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:15,940 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:16,069 INFO L134 CoverageAnalysis]: Checked inductivity of 5579 backedges. 1256 proven. 2211 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:16,069 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:17,452 INFO L134 CoverageAnalysis]: Checked inductivity of 5579 backedges. 1256 proven. 2211 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:17,473 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:17,473 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 133 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:17,488 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:17,488 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:18,620 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-07-24 10:57:18,620 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:18,631 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:18,711 INFO L134 CoverageAnalysis]: Checked inductivity of 5579 backedges. 1256 proven. 2211 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:18,712 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:19,734 INFO L134 CoverageAnalysis]: Checked inductivity of 5579 backedges. 1256 proven. 2211 refuted. 0 times theorem prover too weak. 2112 trivial. 0 not checked. [2018-07-24 10:57:19,736 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:19,736 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 39, 39, 39, 39] total 42 [2018-07-24 10:57:19,736 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:19,737 INFO L450 AbstractCegarLoop]: Interpolant automaton has 42 states [2018-07-24 10:57:19,737 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 42 interpolants. [2018-07-24 10:57:19,737 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=678, Invalid=1044, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:57:19,737 INFO L87 Difference]: Start difference. First operand 349 states and 350 transitions. Second operand 42 states. [2018-07-24 10:57:20,163 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:20,163 INFO L93 Difference]: Finished difference Result 359 states and 360 transitions. [2018-07-24 10:57:20,164 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:57:20,164 INFO L78 Accepts]: Start accepts. Automaton has 42 states. Word has length 346 [2018-07-24 10:57:20,165 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:20,166 INFO L225 Difference]: With dead ends: 359 [2018-07-24 10:57:20,166 INFO L226 Difference]: Without dead ends: 357 [2018-07-24 10:57:20,167 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1459 GetRequests, 1277 SyntacticMatches, 140 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2694 ImplicationChecksByTransitivity, 2.8s TimeCoverageRelationStatistics Valid=691, Invalid=1201, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:57:20,167 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357 states. [2018-07-24 10:57:20,177 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357 to 357. [2018-07-24 10:57:20,177 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 357 states. [2018-07-24 10:57:20,178 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 357 states to 357 states and 358 transitions. [2018-07-24 10:57:20,178 INFO L78 Accepts]: Start accepts. Automaton has 357 states and 358 transitions. Word has length 346 [2018-07-24 10:57:20,178 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:20,178 INFO L471 AbstractCegarLoop]: Abstraction has 357 states and 358 transitions. [2018-07-24 10:57:20,178 INFO L472 AbstractCegarLoop]: Interpolant automaton has 42 states. [2018-07-24 10:57:20,178 INFO L276 IsEmpty]: Start isEmpty. Operand 357 states and 358 transitions. [2018-07-24 10:57:20,180 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 355 [2018-07-24 10:57:20,180 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:20,181 INFO L353 BasicCegarLoop]: trace histogram [35, 35, 35, 35, 35, 34, 34, 34, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:20,181 INFO L414 AbstractCegarLoop]: === Iteration 70 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:20,181 INFO L82 PathProgramCache]: Analyzing trace with hash -1352362243, now seen corresponding path program 67 times [2018-07-24 10:57:20,181 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:20,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:20,182 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:20,182 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:20,182 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:20,196 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:21,799 INFO L134 CoverageAnalysis]: Checked inductivity of 5848 backedges. 2414 proven. 1190 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:21,800 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:21,800 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 134 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:21,807 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:21,807 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:21,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:21,914 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:21,986 INFO L134 CoverageAnalysis]: Checked inductivity of 5848 backedges. 2414 proven. 1190 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:21,986 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:23,685 INFO L134 CoverageAnalysis]: Checked inductivity of 5848 backedges. 2414 proven. 1190 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:23,707 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:23,707 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 135 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:23,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:23,721 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:23,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:23,957 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:24,029 INFO L134 CoverageAnalysis]: Checked inductivity of 5848 backedges. 2414 proven. 1190 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:24,029 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:25,566 INFO L134 CoverageAnalysis]: Checked inductivity of 5848 backedges. 2414 proven. 1190 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:25,567 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:25,568 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [73, 73, 73, 73, 73] total 73 [2018-07-24 10:57:25,568 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:25,568 INFO L450 AbstractCegarLoop]: Interpolant automaton has 73 states [2018-07-24 10:57:25,569 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 73 interpolants. [2018-07-24 10:57:25,569 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1333, Invalid=3923, Unknown=0, NotChecked=0, Total=5256 [2018-07-24 10:57:25,569 INFO L87 Difference]: Start difference. First operand 357 states and 358 transitions. Second operand 73 states. [2018-07-24 10:57:28,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:28,264 INFO L93 Difference]: Finished difference Result 508 states and 544 transitions. [2018-07-24 10:57:28,264 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 73 states. [2018-07-24 10:57:28,264 INFO L78 Accepts]: Start accepts. Automaton has 73 states. Word has length 354 [2018-07-24 10:57:28,264 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:28,265 INFO L225 Difference]: With dead ends: 508 [2018-07-24 10:57:28,265 INFO L226 Difference]: Without dead ends: 359 [2018-07-24 10:57:28,266 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1523 GetRequests, 1276 SyntacticMatches, 140 SemanticMatches, 107 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6579 ImplicationChecksByTransitivity, 5.6s TimeCoverageRelationStatistics Valid=2737, Invalid=9035, Unknown=0, NotChecked=0, Total=11772 [2018-07-24 10:57:28,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 359 states. [2018-07-24 10:57:28,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 359 to 359. [2018-07-24 10:57:28,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 359 states. [2018-07-24 10:57:28,279 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 359 states to 359 states and 360 transitions. [2018-07-24 10:57:28,279 INFO L78 Accepts]: Start accepts. Automaton has 359 states and 360 transitions. Word has length 354 [2018-07-24 10:57:28,279 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:28,279 INFO L471 AbstractCegarLoop]: Abstraction has 359 states and 360 transitions. [2018-07-24 10:57:28,279 INFO L472 AbstractCegarLoop]: Interpolant automaton has 73 states. [2018-07-24 10:57:28,279 INFO L276 IsEmpty]: Start isEmpty. Operand 359 states and 360 transitions. [2018-07-24 10:57:28,281 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 357 [2018-07-24 10:57:28,281 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:28,281 INFO L353 BasicCegarLoop]: trace histogram [36, 35, 35, 35, 35, 35, 34, 34, 34, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:28,281 INFO L414 AbstractCegarLoop]: === Iteration 71 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:28,281 INFO L82 PathProgramCache]: Analyzing trace with hash -1646676649, now seen corresponding path program 68 times [2018-07-24 10:57:28,281 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:28,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:28,282 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:28,282 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:28,282 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:28,297 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:28,997 INFO L134 CoverageAnalysis]: Checked inductivity of 5918 backedges. 1327 proven. 2446 refuted. 0 times theorem prover too weak. 2145 trivial. 0 not checked. [2018-07-24 10:57:28,997 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:28,997 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 136 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:29,005 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:29,005 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:29,113 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:29,113 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:29,118 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:29,254 INFO L134 CoverageAnalysis]: Checked inductivity of 5918 backedges. 1328 proven. 2346 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:29,254 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:30,351 INFO L134 CoverageAnalysis]: Checked inductivity of 5918 backedges. 1328 proven. 2346 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:30,371 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:30,372 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 137 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:30,387 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:30,387 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:30,623 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:30,624 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:30,639 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:30,708 INFO L134 CoverageAnalysis]: Checked inductivity of 5918 backedges. 1328 proven. 2346 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:30,708 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:31,823 INFO L134 CoverageAnalysis]: Checked inductivity of 5918 backedges. 1328 proven. 2346 refuted. 0 times theorem prover too weak. 2244 trivial. 0 not checked. [2018-07-24 10:57:31,824 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:31,825 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 40, 40, 40, 40] total 43 [2018-07-24 10:57:31,825 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:31,825 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:57:31,826 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:57:31,826 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=715, Invalid=1091, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 10:57:31,826 INFO L87 Difference]: Start difference. First operand 359 states and 360 transitions. Second operand 43 states. [2018-07-24 10:57:32,457 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:32,458 INFO L93 Difference]: Finished difference Result 369 states and 370 transitions. [2018-07-24 10:57:32,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 42 states. [2018-07-24 10:57:32,458 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 356 [2018-07-24 10:57:32,458 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:32,459 INFO L225 Difference]: With dead ends: 369 [2018-07-24 10:57:32,460 INFO L226 Difference]: Without dead ends: 367 [2018-07-24 10:57:32,460 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1501 GetRequests, 1314 SyntacticMatches, 144 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2843 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=728, Invalid=1252, Unknown=0, NotChecked=0, Total=1980 [2018-07-24 10:57:32,460 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 367 states. [2018-07-24 10:57:32,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 367 to 367. [2018-07-24 10:57:32,470 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 367 states. [2018-07-24 10:57:32,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 367 states to 367 states and 368 transitions. [2018-07-24 10:57:32,471 INFO L78 Accepts]: Start accepts. Automaton has 367 states and 368 transitions. Word has length 356 [2018-07-24 10:57:32,471 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:32,471 INFO L471 AbstractCegarLoop]: Abstraction has 367 states and 368 transitions. [2018-07-24 10:57:32,471 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:57:32,471 INFO L276 IsEmpty]: Start isEmpty. Operand 367 states and 368 transitions. [2018-07-24 10:57:32,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 365 [2018-07-24 10:57:32,473 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:32,473 INFO L353 BasicCegarLoop]: trace histogram [36, 36, 36, 36, 36, 35, 35, 35, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:32,473 INFO L414 AbstractCegarLoop]: === Iteration 72 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:32,473 INFO L82 PathProgramCache]: Analyzing trace with hash -226157054, now seen corresponding path program 69 times [2018-07-24 10:57:32,473 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:32,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:32,474 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:32,474 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:32,474 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:32,489 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:34,235 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2555 proven. 1260 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:34,235 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:34,235 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 138 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:34,245 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:34,245 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:34,397 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2018-07-24 10:57:34,397 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:34,402 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:34,478 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2555 proven. 1260 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:34,478 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:36,008 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2555 proven. 1260 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:36,028 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:36,029 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 139 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:36,045 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:36,045 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:37,259 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 36 check-sat command(s) [2018-07-24 10:57:37,260 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:37,270 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:37,345 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2555 proven. 1260 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:37,345 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:39,184 INFO L134 CoverageAnalysis]: Checked inductivity of 6195 backedges. 2555 proven. 1260 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:39,186 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:39,186 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [75, 75, 75, 75, 75] total 75 [2018-07-24 10:57:39,186 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:39,187 INFO L450 AbstractCegarLoop]: Interpolant automaton has 75 states [2018-07-24 10:57:39,187 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 75 interpolants. [2018-07-24 10:57:39,188 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1407, Invalid=4143, Unknown=0, NotChecked=0, Total=5550 [2018-07-24 10:57:39,188 INFO L87 Difference]: Start difference. First operand 367 states and 368 transitions. Second operand 75 states. [2018-07-24 10:57:41,224 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:41,224 INFO L93 Difference]: Finished difference Result 522 states and 559 transitions. [2018-07-24 10:57:41,224 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 75 states. [2018-07-24 10:57:41,224 INFO L78 Accepts]: Start accepts. Automaton has 75 states. Word has length 364 [2018-07-24 10:57:41,225 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:41,226 INFO L225 Difference]: With dead ends: 522 [2018-07-24 10:57:41,226 INFO L226 Difference]: Without dead ends: 369 [2018-07-24 10:57:41,228 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1566 GetRequests, 1312 SyntacticMatches, 144 SemanticMatches, 110 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6965 ImplicationChecksByTransitivity, 5.8s TimeCoverageRelationStatistics Valid=2887, Invalid=9545, Unknown=0, NotChecked=0, Total=12432 [2018-07-24 10:57:41,228 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 369 states. [2018-07-24 10:57:41,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 369 to 369. [2018-07-24 10:57:41,244 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 369 states. [2018-07-24 10:57:41,245 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 369 states to 369 states and 370 transitions. [2018-07-24 10:57:41,245 INFO L78 Accepts]: Start accepts. Automaton has 369 states and 370 transitions. Word has length 364 [2018-07-24 10:57:41,245 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:41,245 INFO L471 AbstractCegarLoop]: Abstraction has 369 states and 370 transitions. [2018-07-24 10:57:41,246 INFO L472 AbstractCegarLoop]: Interpolant automaton has 75 states. [2018-07-24 10:57:41,246 INFO L276 IsEmpty]: Start isEmpty. Operand 369 states and 370 transitions. [2018-07-24 10:57:41,248 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 367 [2018-07-24 10:57:41,248 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:41,248 INFO L353 BasicCegarLoop]: trace histogram [37, 36, 36, 36, 36, 36, 35, 35, 35, 35, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:41,248 INFO L414 AbstractCegarLoop]: === Iteration 73 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:41,249 INFO L82 PathProgramCache]: Analyzing trace with hash 940807132, now seen corresponding path program 70 times [2018-07-24 10:57:41,249 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:41,250 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:41,250 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:41,251 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:41,251 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:41,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:42,025 INFO L134 CoverageAnalysis]: Checked inductivity of 6267 backedges. 1401 proven. 2588 refuted. 0 times theorem prover too weak. 2278 trivial. 0 not checked. [2018-07-24 10:57:42,026 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:42,026 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 140 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:42,033 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:42,033 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:42,150 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:42,151 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:42,156 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:42,290 INFO L134 CoverageAnalysis]: Checked inductivity of 6267 backedges. 1402 proven. 2485 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:42,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:43,790 INFO L134 CoverageAnalysis]: Checked inductivity of 6267 backedges. 1402 proven. 2485 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:43,811 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:43,811 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 141 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:43,826 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:43,826 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:44,123 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:44,123 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:44,135 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:44,223 INFO L134 CoverageAnalysis]: Checked inductivity of 6267 backedges. 1402 proven. 2485 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:44,223 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:45,431 INFO L134 CoverageAnalysis]: Checked inductivity of 6267 backedges. 1402 proven. 2485 refuted. 0 times theorem prover too weak. 2380 trivial. 0 not checked. [2018-07-24 10:57:45,433 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:45,433 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 41, 41, 41, 41] total 44 [2018-07-24 10:57:45,433 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:45,434 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:57:45,434 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:57:45,434 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=753, Invalid=1139, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:57:45,434 INFO L87 Difference]: Start difference. First operand 369 states and 370 transitions. Second operand 44 states. [2018-07-24 10:57:46,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:46,121 INFO L93 Difference]: Finished difference Result 379 states and 380 transitions. [2018-07-24 10:57:46,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:57:46,122 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 366 [2018-07-24 10:57:46,122 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:46,124 INFO L225 Difference]: With dead ends: 379 [2018-07-24 10:57:46,124 INFO L226 Difference]: Without dead ends: 377 [2018-07-24 10:57:46,125 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1543 GetRequests, 1351 SyntacticMatches, 148 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2996 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=766, Invalid=1304, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:57:46,125 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 377 states. [2018-07-24 10:57:46,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 377 to 377. [2018-07-24 10:57:46,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 377 states. [2018-07-24 10:57:46,137 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 377 states to 377 states and 378 transitions. [2018-07-24 10:57:46,137 INFO L78 Accepts]: Start accepts. Automaton has 377 states and 378 transitions. Word has length 366 [2018-07-24 10:57:46,137 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:46,137 INFO L471 AbstractCegarLoop]: Abstraction has 377 states and 378 transitions. [2018-07-24 10:57:46,138 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:57:46,138 INFO L276 IsEmpty]: Start isEmpty. Operand 377 states and 378 transitions. [2018-07-24 10:57:46,139 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 375 [2018-07-24 10:57:46,139 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:46,139 INFO L353 BasicCegarLoop]: trace histogram [37, 37, 37, 37, 37, 36, 36, 36, 36, 36, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:46,139 INFO L414 AbstractCegarLoop]: === Iteration 74 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_invgen_down_true_unreach_call_true_termination_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:46,140 INFO L82 PathProgramCache]: Analyzing trace with hash -1550932089, now seen corresponding path program 71 times [2018-07-24 10:57:46,140 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:46,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:46,140 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:46,140 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:46,140 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:46,156 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat Received shutdown request... [2018-07-24 10:57:47,013 WARN L540 AbstractCegarLoop]: Verification canceled [2018-07-24 10:57:47,018 WARN L202 ceAbstractionStarter]: Timeout [2018-07-24 10:57:47,018 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 10:57:47 BoogieIcfgContainer [2018-07-24 10:57:47,018 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 10:57:47,019 INFO L168 Benchmark]: Toolchain (without parser) took 232173.45 ms. Allocated memory was 1.5 GB in the beginning and 2.4 GB in the end (delta: 856.2 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -755.2 MB). Peak memory consumption was 101.0 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:47,020 INFO L168 Benchmark]: CDTParser took 0.27 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:57:47,020 INFO L168 Benchmark]: CACSL2BoogieTranslator took 247.89 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:47,020 INFO L168 Benchmark]: Boogie Procedure Inliner took 21.59 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:57:47,021 INFO L168 Benchmark]: Boogie Preprocessor took 20.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:57:47,021 INFO L168 Benchmark]: RCFGBuilder took 330.46 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 752.4 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -805.9 MB). Peak memory consumption was 26.9 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:47,021 INFO L168 Benchmark]: TraceAbstraction took 231547.40 ms. Allocated memory was 2.3 GB in the beginning and 2.4 GB in the end (delta: 103.8 MB). Free memory was 2.2 GB in the beginning and 2.2 GB in the end (delta: 40.1 MB). Peak memory consumption was 143.9 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:47,023 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.27 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 247.89 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 21.59 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 20.19 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 330.46 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 752.4 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -805.9 MB). Peak memory consumption was 26.9 MB. Max. memory is 7.1 GB. * TraceAbstraction took 231547.40 ms. Allocated memory was 2.3 GB in the beginning and 2.4 GB in the end (delta: 103.8 MB). Free memory was 2.2 GB in the beginning and 2.2 GB in the end (delta: 40.1 MB). Peak memory consumption was 143.9 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - TimeoutResultAtElement [Line: 5]: Timeout (TraceAbstraction) Unable to prove that call of __VERIFIER_error() unreachable (line 5). Cancelled while BasicCegarLoop was analyzing trace of length 375 with TraceHistMax 37, while InterpolatingTraceCheckCraig was constructing Craig interpolants, while NestedInterpolantsBuilder was constructing predicates for 373 interpolants. - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 23 locations, 1 error locations. TIMEOUT Result, 231.4s OverallTime, 74 OverallIterations, 37 TraceHistogramMax, 52.6s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 3522 SDtfs, 2862 SDslu, 31979 SDs, 0 SdLazy, 40033 SolverSat, 3255 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 27.5s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 58256 GetRequests, 49776 SyntacticMatches, 5460 SemanticMatches, 3020 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 126108 ImplicationChecksByTransitivity, 144.1s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=377occurred in iteration=73, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.7s AutomataMinimizationTime, 73 MinimizatonAttempts, 5 StatesRemovedByMinimization, 1 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.7s SsaConstructionTime, 25.1s SatisfiabilityAnalysisTime, 144.6s InterpolantComputationTime, 40993 NumberOfCodeBlocks, 40993 NumberOfCodeBlocksAsserted, 1519 NumberOfCheckSat, 67940 ConstructedInterpolants, 0 QuantifiedInterpolants, 36810118 SizeOfPredicates, 420 NumberOfNonLiveVariables, 57960 ConjunctsInSsa, 5880 ConjunctsInUnsatCore, 353 InterpolantComputations, 3 PerfectInterpolantSequences, 532982/764752 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate could not prove your program: Timeout Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/down_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_10-57-47-031.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/down_true-unreach-call_true-termination.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_10-57-47-031.csv Completed graceful shutdown