java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-lit/gj2007_true-unreach-call_true-termination.c.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:55:12,638 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:55:12,640 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:55:12,652 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:55:12,652 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:55:12,653 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:55:12,654 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:55:12,656 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:55:12,658 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:55:12,659 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:55:12,660 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:55:12,660 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:55:12,661 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:55:12,662 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:55:12,663 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:55:12,664 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:55:12,666 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:55:12,669 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:55:12,671 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:55:12,678 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:55:12,679 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:55:12,681 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:55:12,686 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:55:12,687 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:55:12,687 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:55:12,688 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:55:12,691 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:55:12,693 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:55:12,694 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:55:12,696 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:55:12,696 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:55:12,697 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... 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[2018-07-24 10:55:12,702 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:55:12,730 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:55:12,730 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:55:12,731 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:55:12,734 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:55:12,735 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:55:12,735 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:55:12,735 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:55:12,735 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:55:12,735 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:55:12,736 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:55:12,736 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:55:12,740 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:55:12,740 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:55:12,740 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:55:12,740 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:55:12,741 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:55:12,741 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:55:12,741 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:55:12,742 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:55:12,743 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:55:12,743 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:55:12,743 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:55:12,743 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:55:12,743 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:55:12,744 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:55:12,744 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:55:12,744 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:55:12,744 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:55:12,744 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:55:12,745 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:55:12,745 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:55:12,745 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:55:12,745 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:55:12,811 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:55:12,827 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:55:12,831 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:55:12,833 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:55:12,833 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:55:12,834 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-lit/gj2007_true-unreach-call_true-termination.c.i [2018-07-24 10:55:13,179 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a714d3edd/46a9c03d58fc446ca66a96503cc29635/FLAG25d70ca22 [2018-07-24 10:55:13,348 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:55:13,349 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-lit/gj2007_true-unreach-call_true-termination.c.i [2018-07-24 10:55:13,357 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a714d3edd/46a9c03d58fc446ca66a96503cc29635/FLAG25d70ca22 [2018-07-24 10:55:13,376 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/a714d3edd/46a9c03d58fc446ca66a96503cc29635 [2018-07-24 10:55:13,389 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:55:13,391 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:55:13,392 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:55:13,392 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:55:13,400 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:55:13,401 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,403 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@29c00700 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13, skipping insertion in model container [2018-07-24 10:55:13,404 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,597 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:55:13,638 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:55:13,656 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:55:13,663 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:55:13,677 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13 WrapperNode [2018-07-24 10:55:13,678 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:55:13,679 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:55:13,679 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:55:13,679 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:55:13,689 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,695 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,702 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:55:13,703 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:55:13,703 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:55:13,703 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:55:13,714 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,714 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,715 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,715 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,717 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,722 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,723 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... [2018-07-24 10:55:13,727 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:55:13,727 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:55:13,728 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:55:13,728 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:55:13,729 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:55:13,803 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:55:13,804 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:55:13,804 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assert [2018-07-24 10:55:13,804 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assert [2018-07-24 10:55:13,805 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:55:13,805 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:55:13,805 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:55:13,805 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:55:14,144 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:55:14,145 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:55:14 BoogieIcfgContainer [2018-07-24 10:55:14,145 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:55:14,146 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:55:14,146 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:55:14,149 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:55:14,150 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:55:13" (1/3) ... [2018-07-24 10:55:14,150 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3e901e48 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:55:14, skipping insertion in model container [2018-07-24 10:55:14,151 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:55:13" (2/3) ... [2018-07-24 10:55:14,151 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3e901e48 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:55:14, skipping insertion in model container [2018-07-24 10:55:14,151 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:55:14" (3/3) ... [2018-07-24 10:55:14,153 INFO L112 eAbstractionObserver]: Analyzing ICFG gj2007_true-unreach-call_true-termination.c.i [2018-07-24 10:55:14,163 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:55:14,170 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:55:14,219 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:55:14,220 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:55:14,220 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:55:14,220 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:55:14,221 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:55:14,221 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:55:14,221 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:55:14,221 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:55:14,221 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:55:14,238 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states. [2018-07-24 10:55:14,243 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:55:14,243 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:14,244 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:14,245 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:14,250 INFO L82 PathProgramCache]: Analyzing trace with hash 177171015, now seen corresponding path program 1 times [2018-07-24 10:55:14,253 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:14,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:14,308 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:14,308 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:14,308 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:14,337 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:14,368 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:14,370 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:55:14,370 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:55:14,371 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:55:14,375 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:55:14,390 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:55:14,391 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:55:14,394 INFO L87 Difference]: Start difference. First operand 20 states. Second operand 2 states. [2018-07-24 10:55:14,416 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:14,416 INFO L93 Difference]: Finished difference Result 32 states and 36 transitions. [2018-07-24 10:55:14,417 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:55:14,418 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:55:14,418 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:14,427 INFO L225 Difference]: With dead ends: 32 [2018-07-24 10:55:14,428 INFO L226 Difference]: Without dead ends: 13 [2018-07-24 10:55:14,431 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:55:14,450 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-24 10:55:14,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-24 10:55:14,469 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-24 10:55:14,470 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2018-07-24 10:55:14,472 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 14 transitions. Word has length 10 [2018-07-24 10:55:14,472 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:14,472 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 14 transitions. [2018-07-24 10:55:14,472 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:55:14,473 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 14 transitions. [2018-07-24 10:55:14,473 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:55:14,473 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:14,474 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:14,474 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:14,474 INFO L82 PathProgramCache]: Analyzing trace with hash 780197648, now seen corresponding path program 1 times [2018-07-24 10:55:14,474 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:14,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:14,476 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:14,476 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:14,476 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:14,488 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:14,561 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:14,562 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:55:14,562 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:55:14,562 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:55:14,564 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:55:14,565 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:55:14,565 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:55:14,565 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. Second operand 3 states. [2018-07-24 10:55:14,669 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:14,669 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2018-07-24 10:55:14,670 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:55:14,670 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:55:14,670 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:14,671 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:55:14,671 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:55:14,672 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:55:14,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:55:14,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-07-24 10:55:14,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-07-24 10:55:14,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2018-07-24 10:55:14,680 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 17 transitions. Word has length 11 [2018-07-24 10:55:14,683 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:14,684 INFO L471 AbstractCegarLoop]: Abstraction has 16 states and 17 transitions. [2018-07-24 10:55:14,684 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:55:14,684 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 17 transitions. [2018-07-24 10:55:14,689 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:55:14,690 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:14,690 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:14,690 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:14,690 INFO L82 PathProgramCache]: Analyzing trace with hash -1310425472, now seen corresponding path program 1 times [2018-07-24 10:55:14,691 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:14,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:14,692 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:14,692 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:14,692 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:14,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:14,759 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:14,759 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:14,759 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:14,771 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:14,771 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:14,796 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:14,803 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:14,860 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:14,861 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:14,911 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 2 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:14,936 INFO L309 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-07-24 10:55:14,937 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [4] total 6 [2018-07-24 10:55:14,937 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:55:14,937 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:55:14,938 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:55:14,938 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:55:14,938 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. Second operand 3 states. [2018-07-24 10:55:14,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:14,990 INFO L93 Difference]: Finished difference Result 24 states and 26 transitions. [2018-07-24 10:55:14,991 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:55:14,992 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-07-24 10:55:14,992 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:14,993 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:55:14,993 INFO L226 Difference]: Without dead ends: 19 [2018-07-24 10:55:14,994 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 31 GetRequests, 27 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:55:14,994 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-24 10:55:15,003 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 18. [2018-07-24 10:55:15,003 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:55:15,004 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 19 transitions. [2018-07-24 10:55:15,004 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 19 transitions. Word has length 14 [2018-07-24 10:55:15,005 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:15,005 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 19 transitions. [2018-07-24 10:55:15,005 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:55:15,005 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 19 transitions. [2018-07-24 10:55:15,006 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:55:15,006 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:15,006 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:15,006 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:15,007 INFO L82 PathProgramCache]: Analyzing trace with hash 31973266, now seen corresponding path program 1 times [2018-07-24 10:55:15,007 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:15,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,010 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:15,010 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,010 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:15,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,070 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,071 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,071 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:15,081 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:15,081 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:15,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,105 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:15,110 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,110 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:15,236 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,266 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,266 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:15,299 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:15,299 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:15,321 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,325 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:15,330 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,330 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:15,356 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 4 proven. 3 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,361 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:15,361 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:55:15,361 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:15,362 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:55:15,362 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:55:15,362 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:55:15,363 INFO L87 Difference]: Start difference. First operand 18 states and 19 transitions. Second operand 4 states. [2018-07-24 10:55:15,479 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:15,479 INFO L93 Difference]: Finished difference Result 31 states and 34 transitions. [2018-07-24 10:55:15,480 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:55:15,480 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 17 [2018-07-24 10:55:15,480 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:15,481 INFO L225 Difference]: With dead ends: 31 [2018-07-24 10:55:15,482 INFO L226 Difference]: Without dead ends: 21 [2018-07-24 10:55:15,483 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 70 GetRequests, 66 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=15, Invalid=15, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:55:15,484 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21 states. [2018-07-24 10:55:15,490 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21 to 21. [2018-07-24 10:55:15,491 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 21 states. [2018-07-24 10:55:15,491 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21 states to 21 states and 22 transitions. [2018-07-24 10:55:15,492 INFO L78 Accepts]: Start accepts. Automaton has 21 states and 22 transitions. Word has length 17 [2018-07-24 10:55:15,492 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:15,492 INFO L471 AbstractCegarLoop]: Abstraction has 21 states and 22 transitions. [2018-07-24 10:55:15,492 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:55:15,492 INFO L276 IsEmpty]: Start isEmpty. Operand 21 states and 22 transitions. [2018-07-24 10:55:15,493 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:55:15,495 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:15,495 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:15,496 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:15,496 INFO L82 PathProgramCache]: Analyzing trace with hash 1385310978, now seen corresponding path program 2 times [2018-07-24 10:55:15,496 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:15,497 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,497 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:15,498 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,498 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:15,510 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:15,654 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,654 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,654 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:15,662 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:15,663 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:15,675 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:15,676 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:15,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:15,683 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,684 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:15,760 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,781 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:15,781 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:15,798 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:15,798 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:15,818 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:15,819 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:15,822 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:15,828 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:15,829 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:15,855 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 9 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (6)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:55:15,860 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:15,860 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:55:15,861 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:15,861 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:55:15,861 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:55:15,862 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:55:15,862 INFO L87 Difference]: Start difference. First operand 21 states and 22 transitions. Second operand 5 states. [2018-07-24 10:55:15,944 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:15,944 INFO L93 Difference]: Finished difference Result 34 states and 37 transitions. [2018-07-24 10:55:15,944 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:55:15,945 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 20 [2018-07-24 10:55:15,945 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:15,945 INFO L225 Difference]: With dead ends: 34 [2018-07-24 10:55:15,945 INFO L226 Difference]: Without dead ends: 24 [2018-07-24 10:55:15,946 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 83 GetRequests, 77 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:55:15,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-07-24 10:55:15,950 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-07-24 10:55:15,950 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:55:15,951 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 25 transitions. [2018-07-24 10:55:15,951 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 25 transitions. Word has length 20 [2018-07-24 10:55:15,951 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:15,951 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 25 transitions. [2018-07-24 10:55:15,952 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:55:15,952 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 25 transitions. [2018-07-24 10:55:15,952 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:55:15,953 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:15,953 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:15,953 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:15,953 INFO L82 PathProgramCache]: Analyzing trace with hash 1811081618, now seen corresponding path program 3 times [2018-07-24 10:55:15,953 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:15,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,955 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:15,955 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:15,955 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:15,963 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:16,046 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 8 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:16,047 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:16,047 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:16,062 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:16,062 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:16,114 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:55:16,115 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:16,117 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,208 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-07-24 10:55:16,208 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,266 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-07-24 10:55:16,287 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:16,287 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:16,304 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:16,304 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:16,322 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:55:16,322 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:16,325 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,330 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-07-24 10:55:16,331 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,371 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 15 proven. 2 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-07-24 10:55:16,373 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:16,373 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 4, 4, 4, 4] total 10 [2018-07-24 10:55:16,373 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:16,374 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:55:16,374 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:55:16,374 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:55:16,375 INFO L87 Difference]: Start difference. First operand 24 states and 25 transitions. Second operand 8 states. [2018-07-24 10:55:16,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:16,433 INFO L93 Difference]: Finished difference Result 41 states and 47 transitions. [2018-07-24 10:55:16,435 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:55:16,435 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 23 [2018-07-24 10:55:16,435 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:16,438 INFO L225 Difference]: With dead ends: 41 [2018-07-24 10:55:16,438 INFO L226 Difference]: Without dead ends: 31 [2018-07-24 10:55:16,439 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 96 GetRequests, 88 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:55:16,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31 states. [2018-07-24 10:55:16,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31 to 30. [2018-07-24 10:55:16,445 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:55:16,445 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 32 transitions. [2018-07-24 10:55:16,446 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 32 transitions. Word has length 23 [2018-07-24 10:55:16,446 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:16,446 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 32 transitions. [2018-07-24 10:55:16,446 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:55:16,447 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 32 transitions. [2018-07-24 10:55:16,447 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:55:16,447 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:16,448 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 4, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:16,448 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:16,448 INFO L82 PathProgramCache]: Analyzing trace with hash -928950832, now seen corresponding path program 4 times [2018-07-24 10:55:16,448 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:16,449 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:16,449 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:16,450 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:16,450 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:16,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:16,686 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:16,687 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:16,687 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:16,700 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:16,700 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:16,743 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:16,744 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:16,748 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:16,757 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:16,757 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:16,997 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,019 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:17,020 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:17,036 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:17,036 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:17,058 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:17,058 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:17,062 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:17,069 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,069 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:17,089 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 30 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,090 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:17,090 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:55:17,090 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:17,091 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:55:17,091 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:55:17,092 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:55:17,092 INFO L87 Difference]: Start difference. First operand 30 states and 32 transitions. Second operand 7 states. [2018-07-24 10:55:17,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:17,141 INFO L93 Difference]: Finished difference Result 46 states and 51 transitions. [2018-07-24 10:55:17,142 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:55:17,142 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 29 [2018-07-24 10:55:17,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:17,143 INFO L225 Difference]: With dead ends: 46 [2018-07-24 10:55:17,143 INFO L226 Difference]: Without dead ends: 33 [2018-07-24 10:55:17,143 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 121 GetRequests, 111 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:55:17,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 33 states. [2018-07-24 10:55:17,148 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 33 to 33. [2018-07-24 10:55:17,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 33 states. [2018-07-24 10:55:17,149 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 33 states to 33 states and 35 transitions. [2018-07-24 10:55:17,150 INFO L78 Accepts]: Start accepts. Automaton has 33 states and 35 transitions. Word has length 29 [2018-07-24 10:55:17,150 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:17,150 INFO L471 AbstractCegarLoop]: Abstraction has 33 states and 35 transitions. [2018-07-24 10:55:17,150 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:55:17,150 INFO L276 IsEmpty]: Start isEmpty. Operand 33 states and 35 transitions. [2018-07-24 10:55:17,151 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 10:55:17,151 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:17,151 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 5, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:17,152 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:17,152 INFO L82 PathProgramCache]: Analyzing trace with hash 646314304, now seen corresponding path program 5 times [2018-07-24 10:55:17,152 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:17,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,153 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:17,153 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,154 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:17,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:17,238 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,239 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:17,239 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:17,250 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:17,250 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:17,268 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-07-24 10:55:17,269 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:17,271 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:17,279 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,279 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:17,456 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,479 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:17,479 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:17,498 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:17,498 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:17,536 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 8 check-sat command(s) [2018-07-24 10:55:17,537 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:17,541 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:17,549 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,549 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:17,619 INFO L134 CoverageAnalysis]: Checked inductivity of 77 backedges. 30 proven. 45 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,624 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:17,624 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:55:17,624 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:17,625 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:55:17,625 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:55:17,627 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:55:17,627 INFO L87 Difference]: Start difference. First operand 33 states and 35 transitions. Second operand 8 states. [2018-07-24 10:55:17,810 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:17,811 INFO L93 Difference]: Finished difference Result 49 states and 54 transitions. [2018-07-24 10:55:17,813 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:55:17,813 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 32 [2018-07-24 10:55:17,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:17,814 INFO L225 Difference]: With dead ends: 49 [2018-07-24 10:55:17,814 INFO L226 Difference]: Without dead ends: 36 [2018-07-24 10:55:17,815 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 134 GetRequests, 122 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:55:17,816 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-07-24 10:55:17,820 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-07-24 10:55:17,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:55:17,822 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-07-24 10:55:17,822 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 32 [2018-07-24 10:55:17,822 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:17,822 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-07-24 10:55:17,823 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:55:17,823 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-07-24 10:55:17,824 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:55:17,824 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:17,825 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:17,825 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:17,825 INFO L82 PathProgramCache]: Analyzing trace with hash -1737662512, now seen corresponding path program 6 times [2018-07-24 10:55:17,825 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:17,826 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,826 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:17,827 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:17,827 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:17,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:17,951 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 63 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:55:17,952 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:17,952 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:17,959 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:17,960 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:17,976 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-07-24 10:55:17,976 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:17,978 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:18,212 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:18,212 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:18,458 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:18,478 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:18,478 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:18,493 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:18,494 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:18,545 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-07-24 10:55:18,545 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:18,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:18,558 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:18,558 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:18,583 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 23 proven. 77 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:18,585 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:18,585 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 10, 10, 10, 10] total 25 [2018-07-24 10:55:18,586 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:18,586 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:55:18,586 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:55:18,587 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:55:18,587 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 17 states. [2018-07-24 10:55:18,848 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:18,848 INFO L93 Difference]: Finished difference Result 71 states and 89 transitions. [2018-07-24 10:55:18,848 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:55:18,849 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 35 [2018-07-24 10:55:18,849 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:18,849 INFO L225 Difference]: With dead ends: 71 [2018-07-24 10:55:18,850 INFO L226 Difference]: Without dead ends: 58 [2018-07-24 10:55:18,851 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 147 GetRequests, 124 SyntacticMatches, 0 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=300, Invalid=300, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:55:18,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 58 states. [2018-07-24 10:55:18,858 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 58 to 57. [2018-07-24 10:55:18,858 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 57 states. [2018-07-24 10:55:18,860 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 57 states to 57 states and 65 transitions. [2018-07-24 10:55:18,861 INFO L78 Accepts]: Start accepts. Automaton has 57 states and 65 transitions. Word has length 35 [2018-07-24 10:55:18,861 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:18,861 INFO L471 AbstractCegarLoop]: Abstraction has 57 states and 65 transitions. [2018-07-24 10:55:18,861 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:55:18,861 INFO L276 IsEmpty]: Start isEmpty. Operand 57 states and 65 transitions. [2018-07-24 10:55:18,863 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 10:55:18,863 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:18,863 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:18,863 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:18,864 INFO L82 PathProgramCache]: Analyzing trace with hash 1355709312, now seen corresponding path program 7 times [2018-07-24 10:55:18,864 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:18,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:18,865 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:18,865 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:18,865 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:18,885 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:19,022 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,023 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:19,023 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:19,030 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:19,030 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:19,061 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:19,063 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:19,074 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,074 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:19,321 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,344 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:19,344 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:19,361 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:19,361 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:19,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:19,398 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:19,408 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,409 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:19,442 INFO L134 CoverageAnalysis]: Checked inductivity of 345 backedges. 184 proven. 84 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,444 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:19,444 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:55:19,444 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:19,445 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:55:19,445 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:55:19,445 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:55:19,446 INFO L87 Difference]: Start difference. First operand 57 states and 65 transitions. Second operand 10 states. [2018-07-24 10:55:19,514 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:19,514 INFO L93 Difference]: Finished difference Result 91 states and 108 transitions. [2018-07-24 10:55:19,514 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:55:19,514 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 56 [2018-07-24 10:55:19,515 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:19,516 INFO L225 Difference]: With dead ends: 91 [2018-07-24 10:55:19,516 INFO L226 Difference]: Without dead ends: 60 [2018-07-24 10:55:19,517 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 232 GetRequests, 216 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:55:19,517 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60 states. [2018-07-24 10:55:19,523 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60 to 60. [2018-07-24 10:55:19,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:55:19,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 68 transitions. [2018-07-24 10:55:19,525 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 68 transitions. Word has length 56 [2018-07-24 10:55:19,525 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:19,525 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 68 transitions. [2018-07-24 10:55:19,525 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:55:19,525 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 68 transitions. [2018-07-24 10:55:19,526 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:55:19,527 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:19,527 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:19,527 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:19,527 INFO L82 PathProgramCache]: Analyzing trace with hash -678481392, now seen corresponding path program 8 times [2018-07-24 10:55:19,527 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:19,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:19,528 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:19,528 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:19,529 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:19,539 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:19,665 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,665 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:19,665 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:19,674 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:19,674 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:19,711 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:19,712 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:19,714 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:19,725 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,725 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:19,907 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,927 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:19,928 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:19,943 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:19,943 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:19,984 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:19,984 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:19,988 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:19,999 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:19,999 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:20,044 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 207 proven. 108 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:20,045 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:20,046 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:55:20,046 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:20,046 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:55:20,047 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:55:20,048 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:55:20,048 INFO L87 Difference]: Start difference. First operand 60 states and 68 transitions. Second operand 11 states. [2018-07-24 10:55:20,322 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:20,322 INFO L93 Difference]: Finished difference Result 94 states and 111 transitions. [2018-07-24 10:55:20,323 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:55:20,323 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 59 [2018-07-24 10:55:20,324 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:20,324 INFO L225 Difference]: With dead ends: 94 [2018-07-24 10:55:20,325 INFO L226 Difference]: Without dead ends: 63 [2018-07-24 10:55:20,327 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 245 GetRequests, 227 SyntacticMatches, 0 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=190, Invalid=190, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:55:20,328 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-07-24 10:55:20,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-07-24 10:55:20,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:55:20,335 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 71 transitions. [2018-07-24 10:55:20,335 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 71 transitions. Word has length 59 [2018-07-24 10:55:20,335 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:20,335 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 71 transitions. [2018-07-24 10:55:20,335 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:55:20,336 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 71 transitions. [2018-07-24 10:55:20,337 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-24 10:55:20,337 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:20,337 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:20,337 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:20,337 INFO L82 PathProgramCache]: Analyzing trace with hash 734802304, now seen corresponding path program 9 times [2018-07-24 10:55:20,338 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:20,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:20,339 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:20,339 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:20,339 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:20,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:20,641 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 230 proven. 135 refuted. 0 times theorem prover too weak. 77 trivial. 0 not checked. [2018-07-24 10:55:20,641 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:20,641 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:20,649 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:20,649 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:20,673 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-07-24 10:55:20,674 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:20,677 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:21,158 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-07-24 10:55:21,158 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:21,575 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-07-24 10:55:21,597 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:21,597 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:21,614 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:21,614 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:21,700 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 14 check-sat command(s) [2018-07-24 10:55:21,701 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:21,704 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:21,710 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-07-24 10:55:21,710 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:21,757 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 234 proven. 100 refuted. 0 times theorem prover too weak. 108 trivial. 0 not checked. [2018-07-24 10:55:21,759 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:21,759 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 11, 11, 11] total 30 [2018-07-24 10:55:21,760 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:21,760 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:55:21,760 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:55:21,761 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:21,761 INFO L87 Difference]: Start difference. First operand 63 states and 71 transitions. Second operand 21 states. [2018-07-24 10:55:21,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:21,961 INFO L93 Difference]: Finished difference Result 101 states and 121 transitions. [2018-07-24 10:55:21,961 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:55:21,961 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 62 [2018-07-24 10:55:21,962 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:21,962 INFO L225 Difference]: With dead ends: 101 [2018-07-24 10:55:21,962 INFO L226 Difference]: Without dead ends: 70 [2018-07-24 10:55:21,963 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 258 GetRequests, 230 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:21,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70 states. [2018-07-24 10:55:21,968 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70 to 69. [2018-07-24 10:55:21,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 69 states. [2018-07-24 10:55:21,969 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 69 states to 69 states and 78 transitions. [2018-07-24 10:55:21,970 INFO L78 Accepts]: Start accepts. Automaton has 69 states and 78 transitions. Word has length 62 [2018-07-24 10:55:21,970 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:21,970 INFO L471 AbstractCegarLoop]: Abstraction has 69 states and 78 transitions. [2018-07-24 10:55:21,970 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:55:21,970 INFO L276 IsEmpty]: Start isEmpty. Operand 69 states and 78 transitions. [2018-07-24 10:55:21,971 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 69 [2018-07-24 10:55:21,971 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:21,972 INFO L353 BasicCegarLoop]: trace histogram [20, 19, 10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:21,972 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:21,972 INFO L82 PathProgramCache]: Analyzing trace with hash -319096830, now seen corresponding path program 10 times [2018-07-24 10:55:21,972 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:21,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:21,973 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:21,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:21,973 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:21,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:22,147 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:22,147 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:22,147 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:22,156 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:22,156 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:22,186 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:22,187 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:22,189 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:22,199 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:22,199 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:22,432 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:22,453 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:22,453 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:22,468 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:22,469 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:22,517 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:22,517 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:22,522 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:22,546 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:22,546 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:22,615 INFO L134 CoverageAnalysis]: Checked inductivity of 551 backedges. 286 proven. 165 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:22,617 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:22,618 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:55:22,618 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:22,618 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:55:22,618 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:55:22,619 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:55:22,619 INFO L87 Difference]: Start difference. First operand 69 states and 78 transitions. Second operand 13 states. [2018-07-24 10:55:22,895 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:22,895 INFO L93 Difference]: Finished difference Result 106 states and 125 transitions. [2018-07-24 10:55:22,896 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:55:22,896 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 68 [2018-07-24 10:55:22,896 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:22,897 INFO L225 Difference]: With dead ends: 106 [2018-07-24 10:55:22,897 INFO L226 Difference]: Without dead ends: 72 [2018-07-24 10:55:22,898 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 283 GetRequests, 261 SyntacticMatches, 0 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=276, Invalid=276, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:55:22,899 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 72 states. [2018-07-24 10:55:22,904 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 72 to 72. [2018-07-24 10:55:22,904 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-24 10:55:22,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 81 transitions. [2018-07-24 10:55:22,905 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 81 transitions. Word has length 68 [2018-07-24 10:55:22,905 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:22,906 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 81 transitions. [2018-07-24 10:55:22,906 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:55:22,906 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 81 transitions. [2018-07-24 10:55:22,907 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:55:22,907 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:22,907 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 11, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:22,907 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:22,908 INFO L82 PathProgramCache]: Analyzing trace with hash -1542564206, now seen corresponding path program 11 times [2018-07-24 10:55:22,908 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:22,908 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:22,909 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:22,909 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:22,909 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:22,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:23,049 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:23,050 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:23,050 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:23,057 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:23,057 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:23,131 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-07-24 10:55:23,132 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:23,134 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:23,144 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:23,144 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,411 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:23,431 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:23,431 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:23,446 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:23,446 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:23,618 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 21 check-sat command(s) [2018-07-24 10:55:23,618 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:23,622 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:23,633 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:23,633 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:23,690 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 312 proven. 198 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:23,693 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:23,694 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:55:23,694 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:23,694 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:55:23,695 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:55:23,695 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:55:23,695 INFO L87 Difference]: Start difference. First operand 72 states and 81 transitions. Second operand 14 states. [2018-07-24 10:55:23,822 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:23,822 INFO L93 Difference]: Finished difference Result 109 states and 128 transitions. [2018-07-24 10:55:23,822 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:55:23,823 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 71 [2018-07-24 10:55:23,823 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:23,824 INFO L225 Difference]: With dead ends: 109 [2018-07-24 10:55:23,824 INFO L226 Difference]: Without dead ends: 75 [2018-07-24 10:55:23,825 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 296 GetRequests, 272 SyntacticMatches, 0 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=325, Invalid=325, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:55:23,825 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-07-24 10:55:23,833 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2018-07-24 10:55:23,834 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-24 10:55:23,834 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 84 transitions. [2018-07-24 10:55:23,835 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 84 transitions. Word has length 71 [2018-07-24 10:55:23,835 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:23,835 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 84 transitions. [2018-07-24 10:55:23,835 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:55:23,835 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 84 transitions. [2018-07-24 10:55:23,836 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:55:23,840 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:23,840 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 12, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:23,841 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:23,841 INFO L82 PathProgramCache]: Analyzing trace with hash 1528278530, now seen corresponding path program 12 times [2018-07-24 10:55:23,841 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:23,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:23,842 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:23,842 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:23,842 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:23,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:24,036 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:24,036 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:24,036 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:24,044 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:24,044 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:24,073 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:55:24,074 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:24,076 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:24,087 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:24,087 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:24,640 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:24,664 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:24,664 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:24,679 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:24,679 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:24,822 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 20 check-sat command(s) [2018-07-24 10:55:24,822 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:24,826 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:24,836 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:24,836 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:24,873 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 338 proven. 234 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:24,875 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:24,875 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:55:24,875 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:24,876 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:55:24,876 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:55:24,877 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:55:24,877 INFO L87 Difference]: Start difference. First operand 75 states and 84 transitions. Second operand 15 states. [2018-07-24 10:55:24,948 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:24,948 INFO L93 Difference]: Finished difference Result 112 states and 131 transitions. [2018-07-24 10:55:24,948 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:55:24,949 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 74 [2018-07-24 10:55:24,949 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:24,949 INFO L225 Difference]: With dead ends: 112 [2018-07-24 10:55:24,949 INFO L226 Difference]: Without dead ends: 78 [2018-07-24 10:55:24,950 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 309 GetRequests, 283 SyntacticMatches, 0 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=378, Invalid=378, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:55:24,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-07-24 10:55:24,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2018-07-24 10:55:24,955 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-24 10:55:24,956 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 87 transitions. [2018-07-24 10:55:24,956 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 87 transitions. Word has length 74 [2018-07-24 10:55:24,956 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:24,956 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 87 transitions. [2018-07-24 10:55:24,956 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:55:24,956 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 87 transitions. [2018-07-24 10:55:24,957 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 10:55:24,957 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:24,958 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 13, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:24,958 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:24,958 INFO L82 PathProgramCache]: Analyzing trace with hash -2094145390, now seen corresponding path program 13 times [2018-07-24 10:55:24,958 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:24,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:24,959 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:24,959 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:24,959 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:24,968 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:25,146 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,147 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:25,147 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:25,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:25,156 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:25,180 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:25,182 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:25,192 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,192 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:25,480 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,501 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:25,502 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:25,517 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:25,517 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:25,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:25,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:25,569 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,569 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:25,607 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 364 proven. 273 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,608 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:25,608 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:55:25,609 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:25,609 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:55:25,609 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:55:25,609 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:25,610 INFO L87 Difference]: Start difference. First operand 78 states and 87 transitions. Second operand 16 states. [2018-07-24 10:55:25,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:25,695 INFO L93 Difference]: Finished difference Result 115 states and 134 transitions. [2018-07-24 10:55:25,696 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:55:25,696 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 77 [2018-07-24 10:55:25,697 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:25,697 INFO L225 Difference]: With dead ends: 115 [2018-07-24 10:55:25,697 INFO L226 Difference]: Without dead ends: 81 [2018-07-24 10:55:25,698 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 322 GetRequests, 294 SyntacticMatches, 0 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=435, Invalid=435, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:55:25,699 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81 states. [2018-07-24 10:55:25,702 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81 to 81. [2018-07-24 10:55:25,703 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 81 states. [2018-07-24 10:55:25,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81 states to 81 states and 90 transitions. [2018-07-24 10:55:25,704 INFO L78 Accepts]: Start accepts. Automaton has 81 states and 90 transitions. Word has length 77 [2018-07-24 10:55:25,704 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:25,704 INFO L471 AbstractCegarLoop]: Abstraction has 81 states and 90 transitions. [2018-07-24 10:55:25,704 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:55:25,704 INFO L276 IsEmpty]: Start isEmpty. Operand 81 states and 90 transitions. [2018-07-24 10:55:25,705 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 81 [2018-07-24 10:55:25,705 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:25,705 INFO L353 BasicCegarLoop]: trace histogram [24, 23, 14, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:25,706 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:25,706 INFO L82 PathProgramCache]: Analyzing trace with hash 1918100482, now seen corresponding path program 14 times [2018-07-24 10:55:25,706 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:25,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:25,707 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:25,707 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:25,707 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:25,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:25,880 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,880 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:25,880 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:25,889 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:25,889 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:25,922 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:25,923 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:25,925 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:25,939 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:25,940 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:26,419 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:26,439 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:26,439 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:26,454 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:26,455 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:26,503 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:26,503 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:26,507 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:26,518 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:26,519 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:26,555 INFO L134 CoverageAnalysis]: Checked inductivity of 805 backedges. 390 proven. 315 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:26,556 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:26,556 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:55:26,556 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:26,557 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:55:26,557 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:55:26,557 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:55:26,558 INFO L87 Difference]: Start difference. First operand 81 states and 90 transitions. Second operand 17 states. [2018-07-24 10:55:26,621 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:26,621 INFO L93 Difference]: Finished difference Result 118 states and 137 transitions. [2018-07-24 10:55:26,622 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:55:26,623 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 80 [2018-07-24 10:55:26,623 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:26,624 INFO L225 Difference]: With dead ends: 118 [2018-07-24 10:55:26,624 INFO L226 Difference]: Without dead ends: 84 [2018-07-24 10:55:26,625 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 335 GetRequests, 305 SyntacticMatches, 0 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=496, Invalid=496, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:55:26,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 84 states. [2018-07-24 10:55:26,638 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 84 to 84. [2018-07-24 10:55:26,638 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-24 10:55:26,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 93 transitions. [2018-07-24 10:55:26,639 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 93 transitions. Word has length 80 [2018-07-24 10:55:26,639 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:26,639 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 93 transitions. [2018-07-24 10:55:26,639 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:55:26,639 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 93 transitions. [2018-07-24 10:55:26,644 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-24 10:55:26,644 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:26,644 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 15, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:26,644 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:26,644 INFO L82 PathProgramCache]: Analyzing trace with hash 1795025554, now seen corresponding path program 15 times [2018-07-24 10:55:26,644 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:26,645 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:26,647 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:26,647 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:26,648 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:26,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:26,862 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 416 proven. 360 refuted. 0 times theorem prover too weak. 100 trivial. 0 not checked. [2018-07-24 10:55:26,862 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:26,862 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:26,869 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:26,869 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:26,892 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-07-24 10:55:26,892 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:26,894 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:27,506 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-07-24 10:55:27,506 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:28,301 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-07-24 10:55:28,320 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:28,320 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:28,336 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:28,336 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:28,432 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 15 check-sat command(s) [2018-07-24 10:55:28,433 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:28,436 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:28,445 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-07-24 10:55:28,446 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:28,483 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 435 proven. 126 refuted. 0 times theorem prover too weak. 315 trivial. 0 not checked. [2018-07-24 10:55:28,484 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:28,484 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12, 12, 12, 12] total 38 [2018-07-24 10:55:28,485 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:28,485 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:55:28,485 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:55:28,486 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:28,486 INFO L87 Difference]: Start difference. First operand 84 states and 93 transitions. Second operand 28 states. [2018-07-24 10:55:28,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:28,727 INFO L93 Difference]: Finished difference Result 125 states and 147 transitions. [2018-07-24 10:55:28,728 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:55:28,728 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 83 [2018-07-24 10:55:28,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:28,729 INFO L225 Difference]: With dead ends: 125 [2018-07-24 10:55:28,729 INFO L226 Difference]: Without dead ends: 91 [2018-07-24 10:55:28,730 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 348 GetRequests, 312 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:28,731 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91 states. [2018-07-24 10:55:28,735 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91 to 90. [2018-07-24 10:55:28,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-07-24 10:55:28,736 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 100 transitions. [2018-07-24 10:55:28,736 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 100 transitions. Word has length 83 [2018-07-24 10:55:28,737 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:28,737 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 100 transitions. [2018-07-24 10:55:28,737 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:55:28,737 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 100 transitions. [2018-07-24 10:55:28,738 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:55:28,738 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:28,738 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 16, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:28,738 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:28,738 INFO L82 PathProgramCache]: Analyzing trace with hash -1352794928, now seen corresponding path program 16 times [2018-07-24 10:55:28,739 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:28,739 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:28,739 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:28,740 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:28,740 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:28,748 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:29,809 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:29,809 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:29,809 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:29,819 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:29,819 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:29,842 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:29,843 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:29,844 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:29,854 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:29,854 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:30,693 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:30,713 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:30,713 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:30,728 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:30,728 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:30,778 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:30,778 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:30,782 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:30,794 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:30,794 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:30,854 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 493 proven. 408 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:30,856 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:30,857 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:55:30,857 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:30,857 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:55:30,858 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:55:30,858 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:30,858 INFO L87 Difference]: Start difference. First operand 90 states and 100 transitions. Second operand 19 states. [2018-07-24 10:55:30,970 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:30,971 INFO L93 Difference]: Finished difference Result 130 states and 151 transitions. [2018-07-24 10:55:30,971 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:55:30,971 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 89 [2018-07-24 10:55:30,971 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:30,972 INFO L225 Difference]: With dead ends: 130 [2018-07-24 10:55:30,972 INFO L226 Difference]: Without dead ends: 93 [2018-07-24 10:55:30,973 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 339 SyntacticMatches, 0 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=630, Invalid=630, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:55:30,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 93 states. [2018-07-24 10:55:30,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 93 to 93. [2018-07-24 10:55:30,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 93 states. [2018-07-24 10:55:30,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 93 states to 93 states and 103 transitions. [2018-07-24 10:55:30,977 INFO L78 Accepts]: Start accepts. Automaton has 93 states and 103 transitions. Word has length 89 [2018-07-24 10:55:30,977 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:30,977 INFO L471 AbstractCegarLoop]: Abstraction has 93 states and 103 transitions. [2018-07-24 10:55:30,977 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:55:30,977 INFO L276 IsEmpty]: Start isEmpty. Operand 93 states and 103 transitions. [2018-07-24 10:55:30,978 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 93 [2018-07-24 10:55:30,978 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:30,978 INFO L353 BasicCegarLoop]: trace histogram [28, 27, 17, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:30,978 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:30,979 INFO L82 PathProgramCache]: Analyzing trace with hash -135636928, now seen corresponding path program 17 times [2018-07-24 10:55:30,979 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:30,979 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:30,979 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:30,980 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:30,980 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:30,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:31,233 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:31,234 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:31,234 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:31,241 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:31,241 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:31,281 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-07-24 10:55:31,281 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:31,283 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:31,296 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:31,296 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:31,690 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:31,710 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:31,711 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:31,725 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:31,726 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:31,913 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 28 check-sat command(s) [2018-07-24 10:55:31,913 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:31,917 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:31,932 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:31,932 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:31,964 INFO L134 CoverageAnalysis]: Checked inductivity of 1107 backedges. 522 proven. 459 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:31,965 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:31,965 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:55:31,965 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:31,965 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:55:31,966 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:55:31,966 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:31,966 INFO L87 Difference]: Start difference. First operand 93 states and 103 transitions. Second operand 20 states. [2018-07-24 10:55:32,091 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:32,091 INFO L93 Difference]: Finished difference Result 133 states and 154 transitions. [2018-07-24 10:55:32,091 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:55:32,091 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 92 [2018-07-24 10:55:32,092 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:32,093 INFO L225 Difference]: With dead ends: 133 [2018-07-24 10:55:32,093 INFO L226 Difference]: Without dead ends: 96 [2018-07-24 10:55:32,094 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 386 GetRequests, 350 SyntacticMatches, 0 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=703, Invalid=703, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:55:32,094 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96 states. [2018-07-24 10:55:32,097 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96 to 96. [2018-07-24 10:55:32,098 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 96 states. [2018-07-24 10:55:32,098 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96 states to 96 states and 106 transitions. [2018-07-24 10:55:32,098 INFO L78 Accepts]: Start accepts. Automaton has 96 states and 106 transitions. Word has length 92 [2018-07-24 10:55:32,099 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:32,099 INFO L471 AbstractCegarLoop]: Abstraction has 96 states and 106 transitions. [2018-07-24 10:55:32,099 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:55:32,099 INFO L276 IsEmpty]: Start isEmpty. Operand 96 states and 106 transitions. [2018-07-24 10:55:32,099 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 96 [2018-07-24 10:55:32,100 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:32,100 INFO L353 BasicCegarLoop]: trace histogram [29, 28, 18, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:32,100 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:32,100 INFO L82 PathProgramCache]: Analyzing trace with hash 2104428240, now seen corresponding path program 18 times [2018-07-24 10:55:32,100 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:32,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:32,101 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:32,101 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:32,101 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:32,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:32,571 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:32,571 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:32,571 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:32,580 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:32,580 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:32,628 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-07-24 10:55:32,628 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:32,631 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:32,650 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:32,651 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:33,668 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:33,688 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:33,688 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:33,703 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:33,703 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:33,937 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 29 check-sat command(s) [2018-07-24 10:55:33,937 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:33,941 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:33,951 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:33,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:33,971 INFO L134 CoverageAnalysis]: Checked inductivity of 1190 backedges. 551 proven. 513 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:33,972 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:33,973 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 21, 21, 21, 21] total 40 [2018-07-24 10:55:33,973 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:33,973 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:55:33,974 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:55:33,975 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:55:33,975 INFO L87 Difference]: Start difference. First operand 96 states and 106 transitions. Second operand 21 states. [2018-07-24 10:55:34,067 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:34,068 INFO L93 Difference]: Finished difference Result 136 states and 157 transitions. [2018-07-24 10:55:34,068 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 21 states. [2018-07-24 10:55:34,068 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 95 [2018-07-24 10:55:34,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:34,070 INFO L225 Difference]: With dead ends: 136 [2018-07-24 10:55:34,070 INFO L226 Difference]: Without dead ends: 99 [2018-07-24 10:55:34,071 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 399 GetRequests, 361 SyntacticMatches, 0 SemanticMatches, 38 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=780, Invalid=780, Unknown=0, NotChecked=0, Total=1560 [2018-07-24 10:55:34,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99 states. [2018-07-24 10:55:34,075 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99 to 99. [2018-07-24 10:55:34,075 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 99 states. [2018-07-24 10:55:34,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99 states to 99 states and 109 transitions. [2018-07-24 10:55:34,076 INFO L78 Accepts]: Start accepts. Automaton has 99 states and 109 transitions. Word has length 95 [2018-07-24 10:55:34,076 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:34,076 INFO L471 AbstractCegarLoop]: Abstraction has 99 states and 109 transitions. [2018-07-24 10:55:34,076 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:55:34,076 INFO L276 IsEmpty]: Start isEmpty. Operand 99 states and 109 transitions. [2018-07-24 10:55:34,077 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 99 [2018-07-24 10:55:34,077 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:34,077 INFO L353 BasicCegarLoop]: trace histogram [30, 29, 19, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:34,077 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:34,078 INFO L82 PathProgramCache]: Analyzing trace with hash 684002880, now seen corresponding path program 19 times [2018-07-24 10:55:34,078 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:34,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:34,078 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:34,078 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:34,078 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:34,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:34,410 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:34,411 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:34,411 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:34,419 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:34,419 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:34,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:34,445 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:34,454 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:34,455 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:35,255 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:35,274 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:35,274 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:35,289 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:35,290 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:35,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:35,339 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:35,354 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:35,355 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:35,366 INFO L134 CoverageAnalysis]: Checked inductivity of 1276 backedges. 580 proven. 570 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:35,367 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:35,367 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [22, 22, 22, 22, 22] total 42 [2018-07-24 10:55:35,368 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:35,368 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 10:55:35,368 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 10:55:35,369 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:55:35,369 INFO L87 Difference]: Start difference. First operand 99 states and 109 transitions. Second operand 22 states. [2018-07-24 10:55:35,458 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:35,458 INFO L93 Difference]: Finished difference Result 139 states and 160 transitions. [2018-07-24 10:55:35,458 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:55:35,459 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 98 [2018-07-24 10:55:35,459 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:35,460 INFO L225 Difference]: With dead ends: 139 [2018-07-24 10:55:35,460 INFO L226 Difference]: Without dead ends: 102 [2018-07-24 10:55:35,461 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 412 GetRequests, 372 SyntacticMatches, 0 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=861, Invalid=861, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:55:35,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102 states. [2018-07-24 10:55:35,464 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102 to 102. [2018-07-24 10:55:35,464 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 102 states. [2018-07-24 10:55:35,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102 states to 102 states and 112 transitions. [2018-07-24 10:55:35,465 INFO L78 Accepts]: Start accepts. Automaton has 102 states and 112 transitions. Word has length 98 [2018-07-24 10:55:35,465 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:35,465 INFO L471 AbstractCegarLoop]: Abstraction has 102 states and 112 transitions. [2018-07-24 10:55:35,465 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 10:55:35,465 INFO L276 IsEmpty]: Start isEmpty. Operand 102 states and 112 transitions. [2018-07-24 10:55:35,466 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 102 [2018-07-24 10:55:35,466 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:35,466 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 20, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:35,466 INFO L414 AbstractCegarLoop]: === Iteration 23 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:35,467 INFO L82 PathProgramCache]: Analyzing trace with hash -1190096688, now seen corresponding path program 20 times [2018-07-24 10:55:35,467 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:35,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:35,467 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:35,467 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:35,468 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:35,475 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:35,733 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:35,733 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:35,733 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:35,743 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:35,743 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:35,766 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:35,767 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:35,768 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:35,782 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:35,783 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:36,383 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:36,404 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:36,405 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:36,420 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:36,420 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:36,473 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:36,474 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:36,478 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:36,492 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:36,494 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:36,525 INFO L134 CoverageAnalysis]: Checked inductivity of 1365 backedges. 609 proven. 630 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (42)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:55:36,527 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:36,527 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 23, 23, 23, 23] total 44 [2018-07-24 10:55:36,527 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:36,528 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:55:36,528 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:55:36,529 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:55:36,529 INFO L87 Difference]: Start difference. First operand 102 states and 112 transitions. Second operand 23 states. [2018-07-24 10:55:36,641 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:36,641 INFO L93 Difference]: Finished difference Result 142 states and 163 transitions. [2018-07-24 10:55:36,641 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:55:36,641 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 101 [2018-07-24 10:55:36,641 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:36,642 INFO L225 Difference]: With dead ends: 142 [2018-07-24 10:55:36,642 INFO L226 Difference]: Without dead ends: 105 [2018-07-24 10:55:36,644 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 425 GetRequests, 383 SyntacticMatches, 0 SemanticMatches, 42 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.8s TimeCoverageRelationStatistics Valid=946, Invalid=946, Unknown=0, NotChecked=0, Total=1892 [2018-07-24 10:55:36,644 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 105 states. [2018-07-24 10:55:36,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 105 to 105. [2018-07-24 10:55:36,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 105 states. [2018-07-24 10:55:36,648 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 105 states to 105 states and 115 transitions. [2018-07-24 10:55:36,648 INFO L78 Accepts]: Start accepts. Automaton has 105 states and 115 transitions. Word has length 101 [2018-07-24 10:55:36,648 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:36,648 INFO L471 AbstractCegarLoop]: Abstraction has 105 states and 115 transitions. [2018-07-24 10:55:36,648 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:55:36,649 INFO L276 IsEmpty]: Start isEmpty. Operand 105 states and 115 transitions. [2018-07-24 10:55:36,649 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 105 [2018-07-24 10:55:36,649 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:36,649 INFO L353 BasicCegarLoop]: trace histogram [32, 31, 21, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:36,649 INFO L414 AbstractCegarLoop]: === Iteration 24 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:36,650 INFO L82 PathProgramCache]: Analyzing trace with hash 2084521024, now seen corresponding path program 21 times [2018-07-24 10:55:36,650 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:36,650 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:36,651 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:36,651 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:36,651 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:36,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:36,921 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 638 proven. 693 refuted. 0 times theorem prover too weak. 126 trivial. 0 not checked. [2018-07-24 10:55:36,922 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:36,922 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:36,929 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:36,929 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:36,955 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-07-24 10:55:36,955 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:36,958 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:37,217 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-07-24 10:55:37,217 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:37,590 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-07-24 10:55:37,621 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:37,621 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:37,641 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:37,641 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:37,756 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 17 check-sat command(s) [2018-07-24 10:55:37,757 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:37,760 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:37,770 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-07-24 10:55:37,770 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:37,832 INFO L134 CoverageAnalysis]: Checked inductivity of 1457 backedges. 672 proven. 155 refuted. 0 times theorem prover too weak. 630 trivial. 0 not checked. [2018-07-24 10:55:37,835 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:37,835 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 13, 13, 13, 13] total 46 [2018-07-24 10:55:37,835 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:37,836 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:55:37,836 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:55:37,837 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:55:37,837 INFO L87 Difference]: Start difference. First operand 105 states and 115 transitions. Second operand 35 states. [2018-07-24 10:55:38,064 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:38,065 INFO L93 Difference]: Finished difference Result 149 states and 173 transitions. [2018-07-24 10:55:38,065 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:55:38,065 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 104 [2018-07-24 10:55:38,066 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:38,066 INFO L225 Difference]: With dead ends: 149 [2018-07-24 10:55:38,067 INFO L226 Difference]: Without dead ends: 112 [2018-07-24 10:55:38,068 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 438 GetRequests, 394 SyntacticMatches, 0 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=1035, Invalid=1035, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:55:38,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 112 states. [2018-07-24 10:55:38,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 112 to 111. [2018-07-24 10:55:38,072 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 111 states. [2018-07-24 10:55:38,073 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111 states to 111 states and 122 transitions. [2018-07-24 10:55:38,073 INFO L78 Accepts]: Start accepts. Automaton has 111 states and 122 transitions. Word has length 104 [2018-07-24 10:55:38,073 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:38,074 INFO L471 AbstractCegarLoop]: Abstraction has 111 states and 122 transitions. [2018-07-24 10:55:38,074 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:55:38,074 INFO L276 IsEmpty]: Start isEmpty. Operand 111 states and 122 transitions. [2018-07-24 10:55:38,074 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 111 [2018-07-24 10:55:38,074 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:38,075 INFO L353 BasicCegarLoop]: trace histogram [34, 33, 22, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:38,075 INFO L414 AbstractCegarLoop]: === Iteration 25 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:38,075 INFO L82 PathProgramCache]: Analyzing trace with hash -2079809214, now seen corresponding path program 22 times [2018-07-24 10:55:38,075 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:38,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:38,076 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:38,076 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:38,076 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:38,084 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:38,711 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:38,711 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:38,712 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:38,720 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:38,720 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:38,745 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:38,745 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:38,747 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:38,761 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:38,762 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:39,506 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:39,526 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:39,526 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:39,541 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:39,541 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:39,594 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:39,594 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:39,598 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:39,612 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:39,613 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:39,655 INFO L134 CoverageAnalysis]: Checked inductivity of 1650 backedges. 736 proven. 759 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:39,657 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:39,657 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 25, 25, 25, 25] total 48 [2018-07-24 10:55:39,657 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:39,657 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 10:55:39,658 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 10:55:39,658 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:55:39,658 INFO L87 Difference]: Start difference. First operand 111 states and 122 transitions. Second operand 25 states. [2018-07-24 10:55:39,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:39,791 INFO L93 Difference]: Finished difference Result 154 states and 177 transitions. [2018-07-24 10:55:39,792 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 25 states. [2018-07-24 10:55:39,792 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 110 [2018-07-24 10:55:39,792 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:39,793 INFO L225 Difference]: With dead ends: 154 [2018-07-24 10:55:39,793 INFO L226 Difference]: Without dead ends: 114 [2018-07-24 10:55:39,794 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 463 GetRequests, 417 SyntacticMatches, 0 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.3s TimeCoverageRelationStatistics Valid=1128, Invalid=1128, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 10:55:39,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114 states. [2018-07-24 10:55:39,797 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114 to 114. [2018-07-24 10:55:39,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 114 states. [2018-07-24 10:55:39,798 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114 states to 114 states and 125 transitions. [2018-07-24 10:55:39,798 INFO L78 Accepts]: Start accepts. Automaton has 114 states and 125 transitions. Word has length 110 [2018-07-24 10:55:39,798 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:39,799 INFO L471 AbstractCegarLoop]: Abstraction has 114 states and 125 transitions. [2018-07-24 10:55:39,799 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 10:55:39,799 INFO L276 IsEmpty]: Start isEmpty. Operand 114 states and 125 transitions. [2018-07-24 10:55:39,799 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-07-24 10:55:39,799 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:39,800 INFO L353 BasicCegarLoop]: trace histogram [35, 34, 23, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:39,800 INFO L414 AbstractCegarLoop]: === Iteration 26 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:39,800 INFO L82 PathProgramCache]: Analyzing trace with hash -1361785902, now seen corresponding path program 23 times [2018-07-24 10:55:39,800 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:39,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:39,801 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:39,801 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:39,801 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:39,808 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:40,262 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:40,263 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:40,263 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:40,271 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:40,271 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:40,318 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 35 check-sat command(s) [2018-07-24 10:55:40,318 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:40,321 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:40,337 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:40,337 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:41,043 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:41,064 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:41,064 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:41,082 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:41,083 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:41,338 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 35 check-sat command(s) [2018-07-24 10:55:41,338 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:41,342 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:41,358 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:41,358 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:41,438 INFO L134 CoverageAnalysis]: Checked inductivity of 1751 backedges. 768 proven. 828 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:41,440 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:41,440 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [26, 26, 26, 26, 26] total 50 [2018-07-24 10:55:41,440 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:41,441 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:55:41,442 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:55:41,443 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:55:41,443 INFO L87 Difference]: Start difference. First operand 114 states and 125 transitions. Second operand 26 states. [2018-07-24 10:55:42,402 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:42,402 INFO L93 Difference]: Finished difference Result 157 states and 180 transitions. [2018-07-24 10:55:42,403 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 10:55:42,403 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 113 [2018-07-24 10:55:42,403 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:42,404 INFO L225 Difference]: With dead ends: 157 [2018-07-24 10:55:42,405 INFO L226 Difference]: Without dead ends: 117 [2018-07-24 10:55:42,407 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 476 GetRequests, 428 SyntacticMatches, 0 SemanticMatches, 48 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=1225, Invalid=1225, Unknown=0, NotChecked=0, Total=2450 [2018-07-24 10:55:42,407 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 117 states. [2018-07-24 10:55:42,410 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 117 to 117. [2018-07-24 10:55:42,410 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 117 states. [2018-07-24 10:55:42,410 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117 states to 117 states and 128 transitions. [2018-07-24 10:55:42,411 INFO L78 Accepts]: Start accepts. Automaton has 117 states and 128 transitions. Word has length 113 [2018-07-24 10:55:42,411 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:42,411 INFO L471 AbstractCegarLoop]: Abstraction has 117 states and 128 transitions. [2018-07-24 10:55:42,411 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:55:42,411 INFO L276 IsEmpty]: Start isEmpty. Operand 117 states and 128 transitions. [2018-07-24 10:55:42,412 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 117 [2018-07-24 10:55:42,412 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:42,412 INFO L353 BasicCegarLoop]: trace histogram [36, 35, 24, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:42,412 INFO L414 AbstractCegarLoop]: === Iteration 27 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:42,412 INFO L82 PathProgramCache]: Analyzing trace with hash 333567810, now seen corresponding path program 24 times [2018-07-24 10:55:42,413 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:42,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:42,413 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:42,413 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:42,414 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:42,422 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:42,785 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 800 proven. 900 refuted. 0 times theorem prover too weak. 155 trivial. 0 not checked. [2018-07-24 10:55:42,786 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:42,786 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:42,793 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:42,794 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:43,200 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-07-24 10:55:43,201 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:43,204 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:44,083 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 852 proven. 805 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-07-24 10:55:44,084 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,402 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 852 proven. 805 refuted. 0 times theorem prover too weak. 198 trivial. 0 not checked. [2018-07-24 10:55:45,423 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:45,423 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 50 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:45,438 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:55:45,439 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:55:45,763 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 35 check-sat command(s) [2018-07-24 10:55:45,764 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:45,767 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:45,779 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 884 proven. 737 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-07-24 10:55:45,780 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:45,846 INFO L134 CoverageAnalysis]: Checked inductivity of 1855 backedges. 884 proven. 737 refuted. 0 times theorem prover too weak. 234 trivial. 0 not checked. [2018-07-24 10:55:45,847 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:45,848 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 26, 26, 25, 25] total 75 [2018-07-24 10:55:45,848 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:45,848 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:55:45,849 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:55:45,852 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=2775, Invalid=2775, Unknown=0, NotChecked=0, Total=5550 [2018-07-24 10:55:45,853 INFO L87 Difference]: Start difference. First operand 117 states and 128 transitions. Second operand 51 states. [2018-07-24 10:55:46,266 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:46,266 INFO L93 Difference]: Finished difference Result 200 states and 250 transitions. [2018-07-24 10:55:46,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:55:46,266 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 116 [2018-07-24 10:55:46,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:46,268 INFO L225 Difference]: With dead ends: 200 [2018-07-24 10:55:46,268 INFO L226 Difference]: Without dead ends: 160 [2018-07-24 10:55:46,270 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 489 GetRequests, 416 SyntacticMatches, 0 SemanticMatches, 73 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=2775, Invalid=2775, Unknown=0, NotChecked=0, Total=5550 [2018-07-24 10:55:46,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 160 states. [2018-07-24 10:55:46,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 160 to 159. [2018-07-24 10:55:46,275 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 159 states. [2018-07-24 10:55:46,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 159 states to 159 states and 183 transitions. [2018-07-24 10:55:46,276 INFO L78 Accepts]: Start accepts. Automaton has 159 states and 183 transitions. Word has length 116 [2018-07-24 10:55:46,276 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:46,276 INFO L471 AbstractCegarLoop]: Abstraction has 159 states and 183 transitions. [2018-07-24 10:55:46,276 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:55:46,276 INFO L276 IsEmpty]: Start isEmpty. Operand 159 states and 183 transitions. [2018-07-24 10:55:46,277 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 159 [2018-07-24 10:55:46,277 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:46,277 INFO L353 BasicCegarLoop]: trace histogram [50, 49, 25, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:46,278 INFO L414 AbstractCegarLoop]: === Iteration 28 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:46,278 INFO L82 PathProgramCache]: Analyzing trace with hash -923756672, now seen corresponding path program 25 times [2018-07-24 10:55:46,278 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:46,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:46,279 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:46,279 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:46,279 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:46,290 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:46,747 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:46,747 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:46,748 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:46,755 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:46,755 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:46,794 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:46,796 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:46,816 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:46,817 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:47,842 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:47,876 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:47,877 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 52 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:47,904 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:47,905 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:55:47,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:47,991 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:48,021 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:48,021 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:48,136 INFO L134 CoverageAnalysis]: Checked inductivity of 3626 backedges. 1846 proven. 975 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:48,138 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:48,138 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [28, 28, 28, 28, 28] total 52 [2018-07-24 10:55:48,138 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:48,138 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 10:55:48,139 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 10:55:48,139 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:48,140 INFO L87 Difference]: Start difference. First operand 159 states and 183 transitions. Second operand 28 states. [2018-07-24 10:55:48,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:48,246 INFO L93 Difference]: Finished difference Result 241 states and 290 transitions. [2018-07-24 10:55:48,246 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 10:55:48,246 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 158 [2018-07-24 10:55:48,246 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:48,247 INFO L225 Difference]: With dead ends: 241 [2018-07-24 10:55:48,247 INFO L226 Difference]: Without dead ends: 162 [2018-07-24 10:55:48,249 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 658 GetRequests, 604 SyntacticMatches, 4 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:48,249 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162 states. [2018-07-24 10:55:48,254 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162 to 162. [2018-07-24 10:55:48,255 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 162 states. [2018-07-24 10:55:48,255 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 162 states to 162 states and 186 transitions. [2018-07-24 10:55:48,256 INFO L78 Accepts]: Start accepts. Automaton has 162 states and 186 transitions. Word has length 158 [2018-07-24 10:55:48,256 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:48,256 INFO L471 AbstractCegarLoop]: Abstraction has 162 states and 186 transitions. [2018-07-24 10:55:48,256 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 10:55:48,256 INFO L276 IsEmpty]: Start isEmpty. Operand 162 states and 186 transitions. [2018-07-24 10:55:48,257 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 162 [2018-07-24 10:55:48,257 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:48,258 INFO L353 BasicCegarLoop]: trace histogram [51, 50, 26, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:48,258 INFO L414 AbstractCegarLoop]: === Iteration 29 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:48,258 INFO L82 PathProgramCache]: Analyzing trace with hash -60333552, now seen corresponding path program 26 times [2018-07-24 10:55:48,258 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:48,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:48,259 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:55:48,259 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:48,259 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:48,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:49,444 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:49,444 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:49,444 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:49,451 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:49,452 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:49,491 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:49,491 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:49,495 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:49,518 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:49,519 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:50,809 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:50,829 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:50,829 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:50,844 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:55:50,844 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:50,931 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:55:50,931 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:50,937 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:50,961 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:50,961 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:51,103 INFO L134 CoverageAnalysis]: Checked inductivity of 3775 backedges. 1917 proven. 1053 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:51,104 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:51,104 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [29, 29, 29, 29, 29] total 52 [2018-07-24 10:55:51,104 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:51,105 INFO L450 AbstractCegarLoop]: Interpolant automaton has 29 states [2018-07-24 10:55:51,105 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 29 interpolants. [2018-07-24 10:55:51,106 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:51,106 INFO L87 Difference]: Start difference. First operand 162 states and 186 transitions. Second operand 29 states. [2018-07-24 10:55:51,233 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:51,234 INFO L93 Difference]: Finished difference Result 244 states and 293 transitions. [2018-07-24 10:55:51,234 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 29 states. [2018-07-24 10:55:51,234 INFO L78 Accepts]: Start accepts. Automaton has 29 states. Word has length 161 [2018-07-24 10:55:51,234 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:51,235 INFO L225 Difference]: With dead ends: 244 [2018-07-24 10:55:51,236 INFO L226 Difference]: Without dead ends: 165 [2018-07-24 10:55:51,237 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 671 GetRequests, 613 SyntacticMatches, 8 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:51,237 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 165 states. [2018-07-24 10:55:51,242 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 165 to 165. [2018-07-24 10:55:51,243 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 165 states. [2018-07-24 10:55:51,244 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 165 states to 165 states and 189 transitions. [2018-07-24 10:55:51,244 INFO L78 Accepts]: Start accepts. Automaton has 165 states and 189 transitions. Word has length 161 [2018-07-24 10:55:51,244 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:51,244 INFO L471 AbstractCegarLoop]: Abstraction has 165 states and 189 transitions. [2018-07-24 10:55:51,244 INFO L472 AbstractCegarLoop]: Interpolant automaton has 29 states. [2018-07-24 10:55:51,244 INFO L276 IsEmpty]: Start isEmpty. Operand 165 states and 189 transitions. [2018-07-24 10:55:51,245 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 165 [2018-07-24 10:55:51,245 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:51,245 INFO L353 BasicCegarLoop]: trace histogram [52, 51, 27, 24, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:51,246 INFO L414 AbstractCegarLoop]: === Iteration 30 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:51,246 INFO L82 PathProgramCache]: Analyzing trace with hash -381301376, now seen corresponding path program 27 times [2018-07-24 10:55:51,246 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:51,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:51,247 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:51,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:51,247 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:51,257 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:51,908 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1988 proven. 1134 refuted. 0 times theorem prover too weak. 805 trivial. 0 not checked. [2018-07-24 10:55:51,908 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:51,909 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:51,916 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:51,916 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:52,000 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 38 check-sat command(s) [2018-07-24 10:55:52,000 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:52,003 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:52,803 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-07-24 10:55:52,803 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:54,061 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-07-24 10:55:54,082 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:54,082 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 56 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:54,097 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:55:54,097 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:55:54,575 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 38 check-sat command(s) [2018-07-24 10:55:54,575 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:54,579 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:54,596 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-07-24 10:55:54,597 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:54,620 INFO L134 CoverageAnalysis]: Checked inductivity of 3927 backedges. 1998 proven. 876 refuted. 0 times theorem prover too weak. 1053 trivial. 0 not checked. [2018-07-24 10:55:54,621 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:54,622 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [30, 27, 27, 27, 27] total 80 [2018-07-24 10:55:54,622 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:54,622 INFO L450 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-07-24 10:55:54,622 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-07-24 10:55:54,623 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:55:54,623 INFO L87 Difference]: Start difference. First operand 165 states and 189 transitions. Second operand 55 states. [2018-07-24 10:55:55,251 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:55,252 INFO L93 Difference]: Finished difference Result 251 states and 303 transitions. [2018-07-24 10:55:55,252 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:55:55,252 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 164 [2018-07-24 10:55:55,252 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:55,253 INFO L225 Difference]: With dead ends: 251 [2018-07-24 10:55:55,253 INFO L226 Difference]: Without dead ends: 172 [2018-07-24 10:55:55,255 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 684 GetRequests, 606 SyntacticMatches, 0 SemanticMatches, 78 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=3160, Invalid=3160, Unknown=0, NotChecked=0, Total=6320 [2018-07-24 10:55:55,255 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 172 states. [2018-07-24 10:55:55,259 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 172 to 171. [2018-07-24 10:55:55,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 171 states. [2018-07-24 10:55:55,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 171 states to 171 states and 196 transitions. [2018-07-24 10:55:55,260 INFO L78 Accepts]: Start accepts. Automaton has 171 states and 196 transitions. Word has length 164 [2018-07-24 10:55:55,261 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:55,261 INFO L471 AbstractCegarLoop]: Abstraction has 171 states and 196 transitions. [2018-07-24 10:55:55,261 INFO L472 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-07-24 10:55:55,261 INFO L276 IsEmpty]: Start isEmpty. Operand 171 states and 196 transitions. [2018-07-24 10:55:55,262 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 171 [2018-07-24 10:55:55,262 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:55,262 INFO L353 BasicCegarLoop]: trace histogram [54, 53, 28, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:55,263 INFO L414 AbstractCegarLoop]: === Iteration 31 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:55,263 INFO L82 PathProgramCache]: Analyzing trace with hash 1420576770, now seen corresponding path program 28 times [2018-07-24 10:55:55,263 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:55,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:55,264 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:55,264 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:55,264 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:55,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:56,852 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:56,852 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:56,852 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:56,860 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:56,860 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:56,901 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:56,901 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:56,904 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:56,924 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:56,924 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:57,695 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:57,715 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:57,716 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:57,730 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:55:57,730 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:55:57,823 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:55:57,823 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:57,828 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:57,854 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:57,855 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:58,156 INFO L134 CoverageAnalysis]: Checked inductivity of 4240 backedges. 2146 proven. 1218 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:58,158 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:55:58,158 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [31, 31, 31, 31, 31] total 52 [2018-07-24 10:55:58,158 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:55:58,158 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:55:58,159 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:55:58,159 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:58,160 INFO L87 Difference]: Start difference. First operand 171 states and 196 transitions. Second operand 31 states. [2018-07-24 10:55:58,265 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:55:58,266 INFO L93 Difference]: Finished difference Result 256 states and 307 transitions. [2018-07-24 10:55:58,266 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 31 states. [2018-07-24 10:55:58,266 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 170 [2018-07-24 10:55:58,267 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:55:58,268 INFO L225 Difference]: With dead ends: 256 [2018-07-24 10:55:58,268 INFO L226 Difference]: Without dead ends: 174 [2018-07-24 10:55:58,269 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 709 GetRequests, 643 SyntacticMatches, 16 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 392 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:55:58,269 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 174 states. [2018-07-24 10:55:58,274 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 174 to 174. [2018-07-24 10:55:58,274 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 174 states. [2018-07-24 10:55:58,275 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 174 states to 174 states and 199 transitions. [2018-07-24 10:55:58,275 INFO L78 Accepts]: Start accepts. Automaton has 174 states and 199 transitions. Word has length 170 [2018-07-24 10:55:58,275 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:55:58,275 INFO L471 AbstractCegarLoop]: Abstraction has 174 states and 199 transitions. [2018-07-24 10:55:58,275 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:55:58,275 INFO L276 IsEmpty]: Start isEmpty. Operand 174 states and 199 transitions. [2018-07-24 10:55:58,276 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 174 [2018-07-24 10:55:58,276 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:55:58,277 INFO L353 BasicCegarLoop]: trace histogram [55, 54, 29, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:55:58,277 INFO L414 AbstractCegarLoop]: === Iteration 32 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:55:58,277 INFO L82 PathProgramCache]: Analyzing trace with hash -1812481390, now seen corresponding path program 29 times [2018-07-24 10:55:58,277 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:55:58,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:58,278 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:55:58,278 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:55:58,278 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:55:58,287 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:55:58,741 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:58,741 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:58,742 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:55:58,749 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:58,750 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:58,840 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-07-24 10:55:58,841 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:58,844 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:58,875 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:58,876 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:59,634 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:55:59,654 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:59,654 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:59,668 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:59,669 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:00,255 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 55 check-sat command(s) [2018-07-24 10:56:00,255 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:00,260 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:00,286 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:00,287 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:00,632 INFO L134 CoverageAnalysis]: Checked inductivity of 4401 backedges. 2220 proven. 1305 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:00,633 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:00,633 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [32, 32, 32, 32, 32] total 52 [2018-07-24 10:56:00,633 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:00,634 INFO L450 AbstractCegarLoop]: Interpolant automaton has 32 states [2018-07-24 10:56:00,634 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 32 interpolants. [2018-07-24 10:56:00,634 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:00,634 INFO L87 Difference]: Start difference. First operand 174 states and 199 transitions. Second operand 32 states. [2018-07-24 10:56:00,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:00,823 INFO L93 Difference]: Finished difference Result 259 states and 310 transitions. [2018-07-24 10:56:00,823 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 32 states. [2018-07-24 10:56:00,823 INFO L78 Accepts]: Start accepts. Automaton has 32 states. Word has length 173 [2018-07-24 10:56:00,824 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:00,825 INFO L225 Difference]: With dead ends: 259 [2018-07-24 10:56:00,825 INFO L226 Difference]: Without dead ends: 177 [2018-07-24 10:56:00,825 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 722 GetRequests, 652 SyntacticMatches, 20 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 490 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:00,826 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 177 states. [2018-07-24 10:56:00,830 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 177 to 177. [2018-07-24 10:56:00,830 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 177 states. [2018-07-24 10:56:00,831 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 177 states to 177 states and 202 transitions. [2018-07-24 10:56:00,831 INFO L78 Accepts]: Start accepts. Automaton has 177 states and 202 transitions. Word has length 173 [2018-07-24 10:56:00,832 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:00,832 INFO L471 AbstractCegarLoop]: Abstraction has 177 states and 202 transitions. [2018-07-24 10:56:00,832 INFO L472 AbstractCegarLoop]: Interpolant automaton has 32 states. [2018-07-24 10:56:00,832 INFO L276 IsEmpty]: Start isEmpty. Operand 177 states and 202 transitions. [2018-07-24 10:56:00,833 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 177 [2018-07-24 10:56:00,833 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:00,833 INFO L353 BasicCegarLoop]: trace histogram [56, 55, 30, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:00,833 INFO L414 AbstractCegarLoop]: === Iteration 33 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:00,833 INFO L82 PathProgramCache]: Analyzing trace with hash 1088454146, now seen corresponding path program 30 times [2018-07-24 10:56:00,833 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:00,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:00,834 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:00,834 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:00,835 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:00,845 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:01,409 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:01,410 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:01,410 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:01,417 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:01,417 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:01,532 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-07-24 10:56:01,533 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:01,536 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:01,567 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:01,567 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:02,734 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:02,754 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:02,754 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:02,770 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:02,771 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:03,421 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 55 check-sat command(s) [2018-07-24 10:56:03,421 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:03,426 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:03,455 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:03,455 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:03,728 INFO L134 CoverageAnalysis]: Checked inductivity of 4565 backedges. 2294 proven. 1395 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:03,729 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:03,730 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 33, 33, 33, 33] total 52 [2018-07-24 10:56:03,730 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:03,730 INFO L450 AbstractCegarLoop]: Interpolant automaton has 33 states [2018-07-24 10:56:03,731 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 33 interpolants. [2018-07-24 10:56:03,731 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:03,731 INFO L87 Difference]: Start difference. First operand 177 states and 202 transitions. Second operand 33 states. [2018-07-24 10:56:03,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:03,935 INFO L93 Difference]: Finished difference Result 262 states and 313 transitions. [2018-07-24 10:56:03,936 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 33 states. [2018-07-24 10:56:03,936 INFO L78 Accepts]: Start accepts. Automaton has 33 states. Word has length 176 [2018-07-24 10:56:03,936 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:03,938 INFO L225 Difference]: With dead ends: 262 [2018-07-24 10:56:03,938 INFO L226 Difference]: Without dead ends: 180 [2018-07-24 10:56:03,939 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 735 GetRequests, 661 SyntacticMatches, 24 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 588 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:03,939 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 180 states. [2018-07-24 10:56:03,943 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 180 to 180. [2018-07-24 10:56:03,943 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-07-24 10:56:03,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 205 transitions. [2018-07-24 10:56:03,944 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 205 transitions. Word has length 176 [2018-07-24 10:56:03,945 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:03,945 INFO L471 AbstractCegarLoop]: Abstraction has 180 states and 205 transitions. [2018-07-24 10:56:03,945 INFO L472 AbstractCegarLoop]: Interpolant automaton has 33 states. [2018-07-24 10:56:03,945 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 205 transitions. [2018-07-24 10:56:03,946 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 180 [2018-07-24 10:56:03,946 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:03,946 INFO L353 BasicCegarLoop]: trace histogram [57, 56, 31, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:03,947 INFO L414 AbstractCegarLoop]: === Iteration 34 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:03,947 INFO L82 PathProgramCache]: Analyzing trace with hash -472922990, now seen corresponding path program 31 times [2018-07-24 10:56:03,947 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:03,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:03,948 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:03,948 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:03,948 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:03,961 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:04,768 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:04,768 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:04,768 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:04,775 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:04,776 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:04,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:04,817 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:04,845 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:04,846 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:06,129 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:06,151 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:06,151 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:06,167 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:06,167 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:06,259 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:06,265 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:06,285 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:06,286 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:06,588 INFO L134 CoverageAnalysis]: Checked inductivity of 4732 backedges. 2368 proven. 1488 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:06,590 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:06,590 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [34, 34, 34, 34, 34] total 52 [2018-07-24 10:56:06,590 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:06,590 INFO L450 AbstractCegarLoop]: Interpolant automaton has 34 states [2018-07-24 10:56:06,591 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 34 interpolants. [2018-07-24 10:56:06,591 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:06,592 INFO L87 Difference]: Start difference. First operand 180 states and 205 transitions. Second operand 34 states. [2018-07-24 10:56:06,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:06,720 INFO L93 Difference]: Finished difference Result 265 states and 316 transitions. [2018-07-24 10:56:06,720 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 34 states. [2018-07-24 10:56:06,721 INFO L78 Accepts]: Start accepts. Automaton has 34 states. Word has length 179 [2018-07-24 10:56:06,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:06,722 INFO L225 Difference]: With dead ends: 265 [2018-07-24 10:56:06,722 INFO L226 Difference]: Without dead ends: 183 [2018-07-24 10:56:06,723 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 748 GetRequests, 670 SyntacticMatches, 28 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 686 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:06,723 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 183 states. [2018-07-24 10:56:06,727 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 183 to 183. [2018-07-24 10:56:06,727 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 183 states. [2018-07-24 10:56:06,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 183 states to 183 states and 208 transitions. [2018-07-24 10:56:06,728 INFO L78 Accepts]: Start accepts. Automaton has 183 states and 208 transitions. Word has length 179 [2018-07-24 10:56:06,728 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:06,728 INFO L471 AbstractCegarLoop]: Abstraction has 183 states and 208 transitions. [2018-07-24 10:56:06,728 INFO L472 AbstractCegarLoop]: Interpolant automaton has 34 states. [2018-07-24 10:56:06,729 INFO L276 IsEmpty]: Start isEmpty. Operand 183 states and 208 transitions. [2018-07-24 10:56:06,729 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-07-24 10:56:06,730 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:06,730 INFO L353 BasicCegarLoop]: trace histogram [58, 57, 32, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:06,730 INFO L414 AbstractCegarLoop]: === Iteration 35 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:06,730 INFO L82 PathProgramCache]: Analyzing trace with hash -963365886, now seen corresponding path program 32 times [2018-07-24 10:56:06,730 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:06,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:06,731 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:06,731 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:06,731 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:06,741 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:07,391 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:07,391 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:07,391 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:07,399 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:07,399 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:07,441 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:07,442 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:07,444 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:07,473 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:07,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:08,675 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:08,695 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:08,695 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 66 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:08,710 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:08,710 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:08,799 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:08,799 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:08,804 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:08,835 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:08,835 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:09,274 INFO L134 CoverageAnalysis]: Checked inductivity of 4902 backedges. 2442 proven. 1584 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:09,276 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:09,276 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [35, 35, 35, 35, 35] total 52 [2018-07-24 10:56:09,276 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:09,277 INFO L450 AbstractCegarLoop]: Interpolant automaton has 35 states [2018-07-24 10:56:09,277 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 35 interpolants. [2018-07-24 10:56:09,277 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:09,278 INFO L87 Difference]: Start difference. First operand 183 states and 208 transitions. Second operand 35 states. [2018-07-24 10:56:09,407 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:09,407 INFO L93 Difference]: Finished difference Result 268 states and 319 transitions. [2018-07-24 10:56:09,408 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 10:56:09,408 INFO L78 Accepts]: Start accepts. Automaton has 35 states. Word has length 182 [2018-07-24 10:56:09,408 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:09,409 INFO L225 Difference]: With dead ends: 268 [2018-07-24 10:56:09,410 INFO L226 Difference]: Without dead ends: 186 [2018-07-24 10:56:09,410 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 761 GetRequests, 679 SyntacticMatches, 32 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 784 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:09,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 186 states. [2018-07-24 10:56:09,415 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 186 to 186. [2018-07-24 10:56:09,415 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 186 states. [2018-07-24 10:56:09,416 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 186 states to 186 states and 211 transitions. [2018-07-24 10:56:09,416 INFO L78 Accepts]: Start accepts. Automaton has 186 states and 211 transitions. Word has length 182 [2018-07-24 10:56:09,416 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:09,416 INFO L471 AbstractCegarLoop]: Abstraction has 186 states and 211 transitions. [2018-07-24 10:56:09,417 INFO L472 AbstractCegarLoop]: Interpolant automaton has 35 states. [2018-07-24 10:56:09,417 INFO L276 IsEmpty]: Start isEmpty. Operand 186 states and 211 transitions. [2018-07-24 10:56:09,417 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 186 [2018-07-24 10:56:09,418 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:09,418 INFO L353 BasicCegarLoop]: trace histogram [59, 58, 33, 25, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:09,418 INFO L414 AbstractCegarLoop]: === Iteration 36 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:09,418 INFO L82 PathProgramCache]: Analyzing trace with hash -268939630, now seen corresponding path program 33 times [2018-07-24 10:56:09,418 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:09,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:09,419 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:09,419 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:09,419 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:09,430 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:10,055 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2516 proven. 1683 refuted. 0 times theorem prover too weak. 876 trivial. 0 not checked. [2018-07-24 10:56:10,055 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:10,055 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:10,062 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:10,062 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:10,128 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 39 check-sat command(s) [2018-07-24 10:56:10,128 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:10,131 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:11,303 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-07-24 10:56:11,303 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:12,571 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-07-24 10:56:12,591 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:12,591 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:12,606 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:12,606 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:13,010 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 39 check-sat command(s) [2018-07-24 10:56:13,010 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:13,014 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:13,055 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-07-24 10:56:13,055 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:13,236 INFO L134 CoverageAnalysis]: Checked inductivity of 5075 backedges. 2541 proven. 950 refuted. 0 times theorem prover too weak. 1584 trivial. 0 not checked. [2018-07-24 10:56:13,238 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:13,238 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 28, 28, 28, 28] total 86 [2018-07-24 10:56:13,238 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:13,238 INFO L450 AbstractCegarLoop]: Interpolant automaton has 62 states [2018-07-24 10:56:13,239 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 62 interpolants. [2018-07-24 10:56:13,240 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:56:13,240 INFO L87 Difference]: Start difference. First operand 186 states and 211 transitions. Second operand 62 states. [2018-07-24 10:56:13,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:13,668 INFO L93 Difference]: Finished difference Result 275 states and 329 transitions. [2018-07-24 10:56:13,669 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 62 states. [2018-07-24 10:56:13,669 INFO L78 Accepts]: Start accepts. Automaton has 62 states. Word has length 185 [2018-07-24 10:56:13,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:13,670 INFO L225 Difference]: With dead ends: 275 [2018-07-24 10:56:13,670 INFO L226 Difference]: Without dead ends: 193 [2018-07-24 10:56:13,671 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 774 GetRequests, 686 SyntacticMatches, 4 SemanticMatches, 84 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 98 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=3655, Invalid=3655, Unknown=0, NotChecked=0, Total=7310 [2018-07-24 10:56:13,672 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 193 states. [2018-07-24 10:56:13,676 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 193 to 192. [2018-07-24 10:56:13,676 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 192 states. [2018-07-24 10:56:13,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 192 states to 192 states and 218 transitions. [2018-07-24 10:56:13,677 INFO L78 Accepts]: Start accepts. Automaton has 192 states and 218 transitions. Word has length 185 [2018-07-24 10:56:13,678 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:13,678 INFO L471 AbstractCegarLoop]: Abstraction has 192 states and 218 transitions. [2018-07-24 10:56:13,678 INFO L472 AbstractCegarLoop]: Interpolant automaton has 62 states. [2018-07-24 10:56:13,678 INFO L276 IsEmpty]: Start isEmpty. Operand 192 states and 218 transitions. [2018-07-24 10:56:13,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 192 [2018-07-24 10:56:13,679 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:13,679 INFO L353 BasicCegarLoop]: trace histogram [61, 60, 34, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:13,679 INFO L414 AbstractCegarLoop]: === Iteration 37 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:13,680 INFO L82 PathProgramCache]: Analyzing trace with hash -1217123120, now seen corresponding path program 34 times [2018-07-24 10:56:13,680 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:13,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:13,681 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:13,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:13,681 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:13,691 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:14,463 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:14,463 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:14,463 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:14,470 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:14,470 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:14,515 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:14,516 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:14,518 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:14,548 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:14,549 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:16,072 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:16,092 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:16,092 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:16,107 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:16,107 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:16,209 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:16,210 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:16,216 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:16,236 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:16,236 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:16,657 INFO L134 CoverageAnalysis]: Checked inductivity of 5430 backedges. 2695 proven. 1785 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:16,659 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:16,659 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [37, 37, 37, 37, 37] total 52 [2018-07-24 10:56:16,659 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:16,659 INFO L450 AbstractCegarLoop]: Interpolant automaton has 37 states [2018-07-24 10:56:16,660 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 37 interpolants. [2018-07-24 10:56:16,660 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:16,660 INFO L87 Difference]: Start difference. First operand 192 states and 218 transitions. Second operand 37 states. [2018-07-24 10:56:16,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:16,824 INFO L93 Difference]: Finished difference Result 280 states and 333 transitions. [2018-07-24 10:56:16,826 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 10:56:16,826 INFO L78 Accepts]: Start accepts. Automaton has 37 states. Word has length 191 [2018-07-24 10:56:16,826 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:16,827 INFO L225 Difference]: With dead ends: 280 [2018-07-24 10:56:16,827 INFO L226 Difference]: Without dead ends: 195 [2018-07-24 10:56:16,828 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 799 GetRequests, 709 SyntacticMatches, 40 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 980 ImplicationChecksByTransitivity, 2.6s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:16,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 195 states. [2018-07-24 10:56:16,832 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 195 to 195. [2018-07-24 10:56:16,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 195 states. [2018-07-24 10:56:16,833 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 195 states to 195 states and 221 transitions. [2018-07-24 10:56:16,833 INFO L78 Accepts]: Start accepts. Automaton has 195 states and 221 transitions. Word has length 191 [2018-07-24 10:56:16,833 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:16,834 INFO L471 AbstractCegarLoop]: Abstraction has 195 states and 221 transitions. [2018-07-24 10:56:16,834 INFO L472 AbstractCegarLoop]: Interpolant automaton has 37 states. [2018-07-24 10:56:16,834 INFO L276 IsEmpty]: Start isEmpty. Operand 195 states and 221 transitions. [2018-07-24 10:56:16,835 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 195 [2018-07-24 10:56:16,835 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:16,835 INFO L353 BasicCegarLoop]: trace histogram [62, 61, 35, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:16,835 INFO L414 AbstractCegarLoop]: === Iteration 38 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:16,835 INFO L82 PathProgramCache]: Analyzing trace with hash -1117981632, now seen corresponding path program 35 times [2018-07-24 10:56:16,836 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:16,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:16,836 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:16,836 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:16,836 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:16,847 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:17,507 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:17,507 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:17,507 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:17,514 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:17,514 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:17,611 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-07-24 10:56:17,611 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:17,614 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:17,638 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:17,638 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:18,487 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:18,507 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:18,507 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 72 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:18,523 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:18,523 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:19,232 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 62 check-sat command(s) [2018-07-24 10:56:19,232 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:19,239 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:19,265 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:19,266 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:19,727 INFO L134 CoverageAnalysis]: Checked inductivity of 5612 backedges. 2772 proven. 1890 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:19,728 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:19,729 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [38, 38, 38, 38, 38] total 52 [2018-07-24 10:56:19,729 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:19,729 INFO L450 AbstractCegarLoop]: Interpolant automaton has 38 states [2018-07-24 10:56:19,730 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 38 interpolants. [2018-07-24 10:56:19,730 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:19,730 INFO L87 Difference]: Start difference. First operand 195 states and 221 transitions. Second operand 38 states. [2018-07-24 10:56:19,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:19,874 INFO L93 Difference]: Finished difference Result 283 states and 336 transitions. [2018-07-24 10:56:19,876 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 38 states. [2018-07-24 10:56:19,876 INFO L78 Accepts]: Start accepts. Automaton has 38 states. Word has length 194 [2018-07-24 10:56:19,877 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:19,878 INFO L225 Difference]: With dead ends: 283 [2018-07-24 10:56:19,878 INFO L226 Difference]: Without dead ends: 198 [2018-07-24 10:56:19,879 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 812 GetRequests, 718 SyntacticMatches, 44 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1078 ImplicationChecksByTransitivity, 1.8s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:19,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 198 states. [2018-07-24 10:56:19,884 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 198 to 198. [2018-07-24 10:56:19,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 198 states. [2018-07-24 10:56:19,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 198 states to 198 states and 224 transitions. [2018-07-24 10:56:19,885 INFO L78 Accepts]: Start accepts. Automaton has 198 states and 224 transitions. Word has length 194 [2018-07-24 10:56:19,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:19,885 INFO L471 AbstractCegarLoop]: Abstraction has 198 states and 224 transitions. [2018-07-24 10:56:19,885 INFO L472 AbstractCegarLoop]: Interpolant automaton has 38 states. [2018-07-24 10:56:19,886 INFO L276 IsEmpty]: Start isEmpty. Operand 198 states and 224 transitions. [2018-07-24 10:56:19,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-07-24 10:56:19,887 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:19,887 INFO L353 BasicCegarLoop]: trace histogram [63, 62, 36, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:19,887 INFO L414 AbstractCegarLoop]: === Iteration 39 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:19,887 INFO L82 PathProgramCache]: Analyzing trace with hash 1763555024, now seen corresponding path program 36 times [2018-07-24 10:56:19,887 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:19,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:19,888 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:19,888 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:19,888 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:19,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:21,177 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:21,178 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:21,178 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 73 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:21,185 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:21,185 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:21,292 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-07-24 10:56:21,292 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:21,296 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:21,329 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:21,329 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:22,183 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:22,203 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:22,203 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 74 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 74 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:22,218 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:22,218 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:22,983 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 61 check-sat command(s) [2018-07-24 10:56:22,984 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:22,989 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:23,014 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:23,014 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:23,567 INFO L134 CoverageAnalysis]: Checked inductivity of 5797 backedges. 2849 proven. 1998 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:23,568 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:23,569 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 39, 39, 39, 39] total 52 [2018-07-24 10:56:23,569 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:23,569 INFO L450 AbstractCegarLoop]: Interpolant automaton has 39 states [2018-07-24 10:56:23,570 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 39 interpolants. [2018-07-24 10:56:23,570 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:23,571 INFO L87 Difference]: Start difference. First operand 198 states and 224 transitions. Second operand 39 states. [2018-07-24 10:56:23,692 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:23,692 INFO L93 Difference]: Finished difference Result 286 states and 339 transitions. [2018-07-24 10:56:23,692 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 39 states. [2018-07-24 10:56:23,692 INFO L78 Accepts]: Start accepts. Automaton has 39 states. Word has length 197 [2018-07-24 10:56:23,693 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:23,694 INFO L225 Difference]: With dead ends: 286 [2018-07-24 10:56:23,694 INFO L226 Difference]: Without dead ends: 201 [2018-07-24 10:56:23,695 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 825 GetRequests, 727 SyntacticMatches, 48 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1176 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:23,695 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 201 states. [2018-07-24 10:56:23,700 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 201 to 201. [2018-07-24 10:56:23,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 201 states. [2018-07-24 10:56:23,701 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 201 states to 201 states and 227 transitions. [2018-07-24 10:56:23,701 INFO L78 Accepts]: Start accepts. Automaton has 201 states and 227 transitions. Word has length 197 [2018-07-24 10:56:23,701 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:23,701 INFO L471 AbstractCegarLoop]: Abstraction has 201 states and 227 transitions. [2018-07-24 10:56:23,702 INFO L472 AbstractCegarLoop]: Interpolant automaton has 39 states. [2018-07-24 10:56:23,702 INFO L276 IsEmpty]: Start isEmpty. Operand 201 states and 227 transitions. [2018-07-24 10:56:23,703 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 201 [2018-07-24 10:56:23,703 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:23,703 INFO L353 BasicCegarLoop]: trace histogram [64, 63, 37, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:23,703 INFO L414 AbstractCegarLoop]: === Iteration 40 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:23,703 INFO L82 PathProgramCache]: Analyzing trace with hash 2110728768, now seen corresponding path program 37 times [2018-07-24 10:56:23,703 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:23,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:23,704 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:23,704 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:23,704 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:23,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:24,586 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:24,587 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:24,587 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 75 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:24,596 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:24,597 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:24,642 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:24,645 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:24,670 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:24,670 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:25,544 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:25,563 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:25,564 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 76 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 76 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:25,579 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:25,579 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:25,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:25,676 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:25,701 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:25,701 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:26,473 INFO L134 CoverageAnalysis]: Checked inductivity of 5985 backedges. 2926 proven. 2109 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:26,475 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:26,475 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [40, 40, 40, 40, 40] total 52 [2018-07-24 10:56:26,475 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:26,475 INFO L450 AbstractCegarLoop]: Interpolant automaton has 40 states [2018-07-24 10:56:26,476 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 40 interpolants. [2018-07-24 10:56:26,476 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:26,476 INFO L87 Difference]: Start difference. First operand 201 states and 227 transitions. Second operand 40 states. [2018-07-24 10:56:26,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:26,591 INFO L93 Difference]: Finished difference Result 289 states and 342 transitions. [2018-07-24 10:56:26,592 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 10:56:26,592 INFO L78 Accepts]: Start accepts. Automaton has 40 states. Word has length 200 [2018-07-24 10:56:26,592 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:26,593 INFO L225 Difference]: With dead ends: 289 [2018-07-24 10:56:26,593 INFO L226 Difference]: Without dead ends: 204 [2018-07-24 10:56:26,593 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 838 GetRequests, 736 SyntacticMatches, 52 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1274 ImplicationChecksByTransitivity, 2.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:26,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 204 states. [2018-07-24 10:56:26,598 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 204 to 204. [2018-07-24 10:56:26,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 204 states. [2018-07-24 10:56:26,599 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 204 states to 204 states and 230 transitions. [2018-07-24 10:56:26,599 INFO L78 Accepts]: Start accepts. Automaton has 204 states and 230 transitions. Word has length 200 [2018-07-24 10:56:26,599 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:26,599 INFO L471 AbstractCegarLoop]: Abstraction has 204 states and 230 transitions. [2018-07-24 10:56:26,599 INFO L472 AbstractCegarLoop]: Interpolant automaton has 40 states. [2018-07-24 10:56:26,599 INFO L276 IsEmpty]: Start isEmpty. Operand 204 states and 230 transitions. [2018-07-24 10:56:26,600 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 204 [2018-07-24 10:56:26,600 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:26,601 INFO L353 BasicCegarLoop]: trace histogram [65, 64, 38, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:26,601 INFO L414 AbstractCegarLoop]: === Iteration 41 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:26,601 INFO L82 PathProgramCache]: Analyzing trace with hash -1812479792, now seen corresponding path program 38 times [2018-07-24 10:56:26,601 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:26,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:26,602 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:26,602 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:26,602 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:26,612 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:27,331 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:27,332 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:27,332 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 77 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:27,352 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:27,352 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:27,406 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:27,406 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:27,408 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:27,433 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:27,433 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:28,299 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:28,319 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:28,319 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 78 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 78 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:28,334 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:28,334 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:28,440 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:28,441 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:28,447 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:28,473 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:28,473 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:28,995 INFO L134 CoverageAnalysis]: Checked inductivity of 6176 backedges. 3003 proven. 2223 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:28,996 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:28,996 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [41, 41, 41, 41, 41] total 52 [2018-07-24 10:56:28,996 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:28,997 INFO L450 AbstractCegarLoop]: Interpolant automaton has 41 states [2018-07-24 10:56:28,997 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 41 interpolants. [2018-07-24 10:56:28,997 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:28,998 INFO L87 Difference]: Start difference. First operand 204 states and 230 transitions. Second operand 41 states. [2018-07-24 10:56:29,159 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:29,160 INFO L93 Difference]: Finished difference Result 292 states and 345 transitions. [2018-07-24 10:56:29,167 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 41 states. [2018-07-24 10:56:29,167 INFO L78 Accepts]: Start accepts. Automaton has 41 states. Word has length 203 [2018-07-24 10:56:29,168 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:29,169 INFO L225 Difference]: With dead ends: 292 [2018-07-24 10:56:29,169 INFO L226 Difference]: Without dead ends: 207 [2018-07-24 10:56:29,169 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 851 GetRequests, 745 SyntacticMatches, 56 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1372 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:29,170 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207 states. [2018-07-24 10:56:29,174 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207 to 207. [2018-07-24 10:56:29,174 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 207 states. [2018-07-24 10:56:29,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 207 states to 207 states and 233 transitions. [2018-07-24 10:56:29,175 INFO L78 Accepts]: Start accepts. Automaton has 207 states and 233 transitions. Word has length 203 [2018-07-24 10:56:29,175 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:29,175 INFO L471 AbstractCegarLoop]: Abstraction has 207 states and 233 transitions. [2018-07-24 10:56:29,175 INFO L472 AbstractCegarLoop]: Interpolant automaton has 41 states. [2018-07-24 10:56:29,175 INFO L276 IsEmpty]: Start isEmpty. Operand 207 states and 233 transitions. [2018-07-24 10:56:29,176 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 207 [2018-07-24 10:56:29,176 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:29,176 INFO L353 BasicCegarLoop]: trace histogram [66, 65, 39, 26, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:29,176 INFO L414 AbstractCegarLoop]: === Iteration 42 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:29,177 INFO L82 PathProgramCache]: Analyzing trace with hash 826335296, now seen corresponding path program 39 times [2018-07-24 10:56:29,177 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:29,177 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:29,177 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:29,178 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:29,178 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:29,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:31,896 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3080 proven. 2340 refuted. 0 times theorem prover too weak. 950 trivial. 0 not checked. [2018-07-24 10:56:31,896 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:31,896 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 79 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:31,904 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:31,904 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:32,144 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 41 check-sat command(s) [2018-07-24 10:56:32,144 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:32,147 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:33,240 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-07-24 10:56:33,240 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:34,731 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-07-24 10:56:34,752 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:34,752 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 80 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 80 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:34,767 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:34,767 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:35,207 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 41 check-sat command(s) [2018-07-24 10:56:35,207 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:35,212 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:35,235 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-07-24 10:56:35,235 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:35,470 INFO L134 CoverageAnalysis]: Checked inductivity of 6370 backedges. 3120 proven. 1027 refuted. 0 times theorem prover too weak. 2223 trivial. 0 not checked. [2018-07-24 10:56:35,472 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:35,472 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 29, 29, 29, 29] total 92 [2018-07-24 10:56:35,472 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:35,472 INFO L450 AbstractCegarLoop]: Interpolant automaton has 69 states [2018-07-24 10:56:35,473 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 69 interpolants. [2018-07-24 10:56:35,473 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:56:35,473 INFO L87 Difference]: Start difference. First operand 207 states and 233 transitions. Second operand 69 states. [2018-07-24 10:56:36,048 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:36,048 INFO L93 Difference]: Finished difference Result 299 states and 355 transitions. [2018-07-24 10:56:36,049 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 69 states. [2018-07-24 10:56:36,049 INFO L78 Accepts]: Start accepts. Automaton has 69 states. Word has length 206 [2018-07-24 10:56:36,049 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:36,050 INFO L225 Difference]: With dead ends: 299 [2018-07-24 10:56:36,051 INFO L226 Difference]: Without dead ends: 214 [2018-07-24 10:56:36,051 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 864 GetRequests, 766 SyntacticMatches, 8 SemanticMatches, 90 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 196 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=4186, Invalid=4186, Unknown=0, NotChecked=0, Total=8372 [2018-07-24 10:56:36,051 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 214 states. [2018-07-24 10:56:36,057 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 214 to 213. [2018-07-24 10:56:36,057 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 213 states. [2018-07-24 10:56:36,057 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 213 states to 213 states and 240 transitions. [2018-07-24 10:56:36,058 INFO L78 Accepts]: Start accepts. Automaton has 213 states and 240 transitions. Word has length 206 [2018-07-24 10:56:36,058 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:36,058 INFO L471 AbstractCegarLoop]: Abstraction has 213 states and 240 transitions. [2018-07-24 10:56:36,058 INFO L472 AbstractCegarLoop]: Interpolant automaton has 69 states. [2018-07-24 10:56:36,058 INFO L276 IsEmpty]: Start isEmpty. Operand 213 states and 240 transitions. [2018-07-24 10:56:36,059 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 213 [2018-07-24 10:56:36,059 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:36,059 INFO L353 BasicCegarLoop]: trace histogram [68, 67, 40, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:36,060 INFO L414 AbstractCegarLoop]: === Iteration 43 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:36,060 INFO L82 PathProgramCache]: Analyzing trace with hash -370478782, now seen corresponding path program 40 times [2018-07-24 10:56:36,060 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:36,060 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:36,061 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:36,061 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:36,061 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:36,072 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:37,894 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:37,895 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:37,895 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 81 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:37,902 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:37,902 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:37,952 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:37,953 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:37,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:37,983 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:37,983 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:38,916 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:38,936 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:38,936 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 82 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 82 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:38,951 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:38,952 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:39,063 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:39,063 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:39,069 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:39,097 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:39,097 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:39,732 INFO L134 CoverageAnalysis]: Checked inductivity of 6767 backedges. 3280 proven. 2460 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:39,733 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:39,733 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [43, 43, 43, 43, 43] total 52 [2018-07-24 10:56:39,733 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:39,734 INFO L450 AbstractCegarLoop]: Interpolant automaton has 43 states [2018-07-24 10:56:39,734 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 43 interpolants. [2018-07-24 10:56:39,734 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:39,735 INFO L87 Difference]: Start difference. First operand 213 states and 240 transitions. Second operand 43 states. [2018-07-24 10:56:39,880 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:39,881 INFO L93 Difference]: Finished difference Result 304 states and 359 transitions. [2018-07-24 10:56:39,883 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 43 states. [2018-07-24 10:56:39,883 INFO L78 Accepts]: Start accepts. Automaton has 43 states. Word has length 212 [2018-07-24 10:56:39,883 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:39,884 INFO L225 Difference]: With dead ends: 304 [2018-07-24 10:56:39,884 INFO L226 Difference]: Without dead ends: 216 [2018-07-24 10:56:39,885 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 889 GetRequests, 775 SyntacticMatches, 64 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1568 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:39,885 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-07-24 10:56:39,890 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 216. [2018-07-24 10:56:39,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 216 states. [2018-07-24 10:56:39,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 216 states to 216 states and 243 transitions. [2018-07-24 10:56:39,891 INFO L78 Accepts]: Start accepts. Automaton has 216 states and 243 transitions. Word has length 212 [2018-07-24 10:56:39,891 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:39,891 INFO L471 AbstractCegarLoop]: Abstraction has 216 states and 243 transitions. [2018-07-24 10:56:39,891 INFO L472 AbstractCegarLoop]: Interpolant automaton has 43 states. [2018-07-24 10:56:39,892 INFO L276 IsEmpty]: Start isEmpty. Operand 216 states and 243 transitions. [2018-07-24 10:56:39,892 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-07-24 10:56:39,893 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:39,893 INFO L353 BasicCegarLoop]: trace histogram [69, 68, 41, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:39,893 INFO L414 AbstractCegarLoop]: === Iteration 44 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:39,893 INFO L82 PathProgramCache]: Analyzing trace with hash -208261166, now seen corresponding path program 41 times [2018-07-24 10:56:39,893 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:39,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:39,894 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:39,894 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:39,894 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:39,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:41,793 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:41,793 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:41,793 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 83 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:41,801 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:41,801 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:41,918 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 69 check-sat command(s) [2018-07-24 10:56:41,918 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:41,922 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:41,948 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:41,948 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:42,829 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:42,849 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:42,850 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 84 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 84 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:42,865 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:42,865 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:43,721 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 69 check-sat command(s) [2018-07-24 10:56:43,721 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:43,727 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:43,755 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:43,756 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:44,437 INFO L134 CoverageAnalysis]: Checked inductivity of 6970 backedges. 3360 proven. 2583 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:44,439 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:44,439 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [44, 44, 44, 44, 44] total 52 [2018-07-24 10:56:44,439 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:44,439 INFO L450 AbstractCegarLoop]: Interpolant automaton has 44 states [2018-07-24 10:56:44,440 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 44 interpolants. [2018-07-24 10:56:44,440 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:44,440 INFO L87 Difference]: Start difference. First operand 216 states and 243 transitions. Second operand 44 states. [2018-07-24 10:56:44,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:44,569 INFO L93 Difference]: Finished difference Result 307 states and 362 transitions. [2018-07-24 10:56:44,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 44 states. [2018-07-24 10:56:44,569 INFO L78 Accepts]: Start accepts. Automaton has 44 states. Word has length 215 [2018-07-24 10:56:44,570 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:44,570 INFO L225 Difference]: With dead ends: 307 [2018-07-24 10:56:44,571 INFO L226 Difference]: Without dead ends: 219 [2018-07-24 10:56:44,571 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 902 GetRequests, 784 SyntacticMatches, 68 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1666 ImplicationChecksByTransitivity, 3.3s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:44,572 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 219 states. [2018-07-24 10:56:44,577 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 219 to 219. [2018-07-24 10:56:44,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 219 states. [2018-07-24 10:56:44,577 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219 states to 219 states and 246 transitions. [2018-07-24 10:56:44,578 INFO L78 Accepts]: Start accepts. Automaton has 219 states and 246 transitions. Word has length 215 [2018-07-24 10:56:44,578 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:44,578 INFO L471 AbstractCegarLoop]: Abstraction has 219 states and 246 transitions. [2018-07-24 10:56:44,578 INFO L472 AbstractCegarLoop]: Interpolant automaton has 44 states. [2018-07-24 10:56:44,578 INFO L276 IsEmpty]: Start isEmpty. Operand 219 states and 246 transitions. [2018-07-24 10:56:44,579 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 219 [2018-07-24 10:56:44,579 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:44,579 INFO L353 BasicCegarLoop]: trace histogram [70, 69, 42, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:44,580 INFO L414 AbstractCegarLoop]: === Iteration 45 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:44,580 INFO L82 PathProgramCache]: Analyzing trace with hash 578529090, now seen corresponding path program 42 times [2018-07-24 10:56:44,580 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:44,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:44,581 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:44,581 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:44,581 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:44,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:45,731 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:45,731 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:45,731 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 85 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:45,739 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:45,740 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:45,859 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 68 check-sat command(s) [2018-07-24 10:56:45,859 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:45,863 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:45,905 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:45,906 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:47,232 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:47,252 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:47,252 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 86 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 86 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:47,267 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:47,267 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:48,193 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 68 check-sat command(s) [2018-07-24 10:56:48,193 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:48,199 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:48,228 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:48,228 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:48,922 INFO L134 CoverageAnalysis]: Checked inductivity of 7176 backedges. 3440 proven. 2709 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:48,923 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:48,923 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [45, 45, 45, 45, 45] total 52 [2018-07-24 10:56:48,924 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:48,924 INFO L450 AbstractCegarLoop]: Interpolant automaton has 45 states [2018-07-24 10:56:48,924 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 45 interpolants. [2018-07-24 10:56:48,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:48,925 INFO L87 Difference]: Start difference. First operand 219 states and 246 transitions. Second operand 45 states. [2018-07-24 10:56:49,051 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:49,052 INFO L93 Difference]: Finished difference Result 310 states and 365 transitions. [2018-07-24 10:56:49,052 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 45 states. [2018-07-24 10:56:49,052 INFO L78 Accepts]: Start accepts. Automaton has 45 states. Word has length 218 [2018-07-24 10:56:49,053 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:49,054 INFO L225 Difference]: With dead ends: 310 [2018-07-24 10:56:49,054 INFO L226 Difference]: Without dead ends: 222 [2018-07-24 10:56:49,055 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 915 GetRequests, 793 SyntacticMatches, 72 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1764 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:49,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states. [2018-07-24 10:56:49,060 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 222. [2018-07-24 10:56:49,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 222 states. [2018-07-24 10:56:49,061 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 222 states to 222 states and 249 transitions. [2018-07-24 10:56:49,061 INFO L78 Accepts]: Start accepts. Automaton has 222 states and 249 transitions. Word has length 218 [2018-07-24 10:56:49,061 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:49,061 INFO L471 AbstractCegarLoop]: Abstraction has 222 states and 249 transitions. [2018-07-24 10:56:49,061 INFO L472 AbstractCegarLoop]: Interpolant automaton has 45 states. [2018-07-24 10:56:49,061 INFO L276 IsEmpty]: Start isEmpty. Operand 222 states and 249 transitions. [2018-07-24 10:56:49,062 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 222 [2018-07-24 10:56:49,063 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:49,063 INFO L353 BasicCegarLoop]: trace histogram [71, 70, 43, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:49,063 INFO L414 AbstractCegarLoop]: === Iteration 46 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:49,063 INFO L82 PathProgramCache]: Analyzing trace with hash -2084455982, now seen corresponding path program 43 times [2018-07-24 10:56:49,063 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:49,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:49,064 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:49,064 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:49,064 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:49,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:50,613 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:50,614 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:50,614 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 87 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:50,623 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:50,624 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:50,671 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:50,674 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:50,701 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:50,701 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:51,841 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:51,863 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:51,863 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 88 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 88 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:51,879 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:51,880 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:51,986 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:51,992 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:52,023 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:52,023 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:52,753 INFO L134 CoverageAnalysis]: Checked inductivity of 7385 backedges. 3520 proven. 2838 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:52,755 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:52,755 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [46, 46, 46, 46, 46] total 52 [2018-07-24 10:56:52,755 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:52,755 INFO L450 AbstractCegarLoop]: Interpolant automaton has 46 states [2018-07-24 10:56:52,756 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 46 interpolants. [2018-07-24 10:56:52,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:52,756 INFO L87 Difference]: Start difference. First operand 222 states and 249 transitions. Second operand 46 states. [2018-07-24 10:56:52,887 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:52,887 INFO L93 Difference]: Finished difference Result 313 states and 368 transitions. [2018-07-24 10:56:52,889 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 46 states. [2018-07-24 10:56:52,889 INFO L78 Accepts]: Start accepts. Automaton has 46 states. Word has length 221 [2018-07-24 10:56:52,889 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:52,890 INFO L225 Difference]: With dead ends: 313 [2018-07-24 10:56:52,890 INFO L226 Difference]: Without dead ends: 225 [2018-07-24 10:56:52,891 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 928 GetRequests, 802 SyntacticMatches, 76 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1862 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:52,891 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 225 states. [2018-07-24 10:56:52,896 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 225 to 225. [2018-07-24 10:56:52,896 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 225 states. [2018-07-24 10:56:52,897 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225 states to 225 states and 252 transitions. [2018-07-24 10:56:52,897 INFO L78 Accepts]: Start accepts. Automaton has 225 states and 252 transitions. Word has length 221 [2018-07-24 10:56:52,897 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:52,897 INFO L471 AbstractCegarLoop]: Abstraction has 225 states and 252 transitions. [2018-07-24 10:56:52,897 INFO L472 AbstractCegarLoop]: Interpolant automaton has 46 states. [2018-07-24 10:56:52,897 INFO L276 IsEmpty]: Start isEmpty. Operand 225 states and 252 transitions. [2018-07-24 10:56:52,898 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 225 [2018-07-24 10:56:52,898 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:52,899 INFO L353 BasicCegarLoop]: trace histogram [72, 71, 44, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:52,899 INFO L414 AbstractCegarLoop]: === Iteration 47 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:52,899 INFO L82 PathProgramCache]: Analyzing trace with hash 1563155778, now seen corresponding path program 44 times [2018-07-24 10:56:52,899 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:52,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:52,900 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:52,900 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:52,900 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:52,911 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:53,916 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:53,916 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:53,916 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 89 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:53,923 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:53,923 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:53,976 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:53,976 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:53,979 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:54,011 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:54,011 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:54,935 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:54,954 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:54,955 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 90 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 90 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:54,969 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:54,969 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:55,086 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:55,086 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:55,092 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:55,124 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:55,124 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:55,904 INFO L134 CoverageAnalysis]: Checked inductivity of 7597 backedges. 3600 proven. 2970 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:55,906 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:55,906 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [47, 47, 47, 47, 47] total 52 [2018-07-24 10:56:55,906 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:55,906 INFO L450 AbstractCegarLoop]: Interpolant automaton has 47 states [2018-07-24 10:56:55,907 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 47 interpolants. [2018-07-24 10:56:55,907 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:55,907 INFO L87 Difference]: Start difference. First operand 225 states and 252 transitions. Second operand 47 states. [2018-07-24 10:56:56,054 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:56,054 INFO L93 Difference]: Finished difference Result 316 states and 371 transitions. [2018-07-24 10:56:56,055 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 47 states. [2018-07-24 10:56:56,055 INFO L78 Accepts]: Start accepts. Automaton has 47 states. Word has length 224 [2018-07-24 10:56:56,055 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:56,057 INFO L225 Difference]: With dead ends: 316 [2018-07-24 10:56:56,057 INFO L226 Difference]: Without dead ends: 228 [2018-07-24 10:56:56,057 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 941 GetRequests, 811 SyntacticMatches, 80 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1960 ImplicationChecksByTransitivity, 2.5s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:56,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228 states. [2018-07-24 10:56:56,062 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228 to 228. [2018-07-24 10:56:56,062 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 228 states. [2018-07-24 10:56:56,063 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228 states to 228 states and 255 transitions. [2018-07-24 10:56:56,063 INFO L78 Accepts]: Start accepts. Automaton has 228 states and 255 transitions. Word has length 224 [2018-07-24 10:56:56,064 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:56,064 INFO L471 AbstractCegarLoop]: Abstraction has 228 states and 255 transitions. [2018-07-24 10:56:56,064 INFO L472 AbstractCegarLoop]: Interpolant automaton has 47 states. [2018-07-24 10:56:56,064 INFO L276 IsEmpty]: Start isEmpty. Operand 228 states and 255 transitions. [2018-07-24 10:56:56,065 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 228 [2018-07-24 10:56:56,065 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:56,065 INFO L353 BasicCegarLoop]: trace histogram [73, 72, 45, 27, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:56,066 INFO L414 AbstractCegarLoop]: === Iteration 48 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:56,066 INFO L82 PathProgramCache]: Analyzing trace with hash 597541842, now seen corresponding path program 45 times [2018-07-24 10:56:56,066 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:56,066 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:56,067 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:56,067 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:56,067 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:56,078 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:57,358 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3680 proven. 3105 refuted. 0 times theorem prover too weak. 1027 trivial. 0 not checked. [2018-07-24 10:56:57,359 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:57,359 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 91 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:57,368 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:57,368 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:57,440 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2018-07-24 10:56:57,440 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:57,443 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:58,632 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-07-24 10:56:58,632 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:00,230 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-07-24 10:57:00,250 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:00,250 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 92 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 92 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:00,264 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:00,264 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:00,713 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 42 check-sat command(s) [2018-07-24 10:57:00,713 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:00,718 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:00,748 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-07-24 10:57:00,748 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:01,082 INFO L134 CoverageAnalysis]: Checked inductivity of 7812 backedges. 3735 proven. 1107 refuted. 0 times theorem prover too weak. 2970 trivial. 0 not checked. [2018-07-24 10:57:01,083 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:01,083 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [48, 30, 30, 30, 30] total 98 [2018-07-24 10:57:01,084 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:01,084 INFO L450 AbstractCegarLoop]: Interpolant automaton has 76 states [2018-07-24 10:57:01,085 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 76 interpolants. [2018-07-24 10:57:01,085 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:57:01,085 INFO L87 Difference]: Start difference. First operand 228 states and 255 transitions. Second operand 76 states. [2018-07-24 10:57:01,672 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:01,672 INFO L93 Difference]: Finished difference Result 323 states and 381 transitions. [2018-07-24 10:57:01,672 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 76 states. [2018-07-24 10:57:01,672 INFO L78 Accepts]: Start accepts. Automaton has 76 states. Word has length 227 [2018-07-24 10:57:01,672 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:01,673 INFO L225 Difference]: With dead ends: 323 [2018-07-24 10:57:01,673 INFO L226 Difference]: Without dead ends: 235 [2018-07-24 10:57:01,674 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 954 GetRequests, 846 SyntacticMatches, 12 SemanticMatches, 96 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 294 ImplicationChecksByTransitivity, 4.2s TimeCoverageRelationStatistics Valid=4753, Invalid=4753, Unknown=0, NotChecked=0, Total=9506 [2018-07-24 10:57:01,674 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 235 states. [2018-07-24 10:57:01,679 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 235 to 234. [2018-07-24 10:57:01,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 234 states. [2018-07-24 10:57:01,680 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 234 states to 234 states and 262 transitions. [2018-07-24 10:57:01,680 INFO L78 Accepts]: Start accepts. Automaton has 234 states and 262 transitions. Word has length 227 [2018-07-24 10:57:01,680 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:01,680 INFO L471 AbstractCegarLoop]: Abstraction has 234 states and 262 transitions. [2018-07-24 10:57:01,680 INFO L472 AbstractCegarLoop]: Interpolant automaton has 76 states. [2018-07-24 10:57:01,681 INFO L276 IsEmpty]: Start isEmpty. Operand 234 states and 262 transitions. [2018-07-24 10:57:01,682 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 234 [2018-07-24 10:57:01,682 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:01,682 INFO L353 BasicCegarLoop]: trace histogram [75, 74, 46, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:01,682 INFO L414 AbstractCegarLoop]: === Iteration 49 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:01,682 INFO L82 PathProgramCache]: Analyzing trace with hash 830503824, now seen corresponding path program 46 times [2018-07-24 10:57:01,683 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:01,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:01,683 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:01,683 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:01,683 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:01,694 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:02,782 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:02,782 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:02,783 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 93 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:02,789 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:02,790 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:02,839 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:02,840 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:02,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:02,887 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:02,888 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:03,853 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:03,873 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:03,873 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 94 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 94 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:03,888 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:03,888 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:04,005 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:04,005 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:04,011 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:04,044 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:04,044 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:04,870 INFO L134 CoverageAnalysis]: Checked inductivity of 8251 backedges. 3901 proven. 3243 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:04,872 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:04,872 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [49, 49, 49, 49, 49] total 52 [2018-07-24 10:57:04,872 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:04,873 INFO L450 AbstractCegarLoop]: Interpolant automaton has 49 states [2018-07-24 10:57:04,873 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 49 interpolants. [2018-07-24 10:57:04,873 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:04,873 INFO L87 Difference]: Start difference. First operand 234 states and 262 transitions. Second operand 49 states. [2018-07-24 10:57:05,028 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:05,029 INFO L93 Difference]: Finished difference Result 328 states and 385 transitions. [2018-07-24 10:57:05,029 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 49 states. [2018-07-24 10:57:05,029 INFO L78 Accepts]: Start accepts. Automaton has 49 states. Word has length 233 [2018-07-24 10:57:05,030 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:05,031 INFO L225 Difference]: With dead ends: 328 [2018-07-24 10:57:05,031 INFO L226 Difference]: Without dead ends: 237 [2018-07-24 10:57:05,031 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 979 GetRequests, 841 SyntacticMatches, 88 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2156 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:05,032 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 237 states. [2018-07-24 10:57:05,036 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 237 to 237. [2018-07-24 10:57:05,036 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 237 states. [2018-07-24 10:57:05,037 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 237 states to 237 states and 265 transitions. [2018-07-24 10:57:05,037 INFO L78 Accepts]: Start accepts. Automaton has 237 states and 265 transitions. Word has length 233 [2018-07-24 10:57:05,037 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:05,037 INFO L471 AbstractCegarLoop]: Abstraction has 237 states and 265 transitions. [2018-07-24 10:57:05,037 INFO L472 AbstractCegarLoop]: Interpolant automaton has 49 states. [2018-07-24 10:57:05,037 INFO L276 IsEmpty]: Start isEmpty. Operand 237 states and 265 transitions. [2018-07-24 10:57:05,038 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 237 [2018-07-24 10:57:05,038 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:05,038 INFO L353 BasicCegarLoop]: trace histogram [76, 75, 47, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:05,038 INFO L414 AbstractCegarLoop]: === Iteration 50 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:05,039 INFO L82 PathProgramCache]: Analyzing trace with hash 2132866816, now seen corresponding path program 47 times [2018-07-24 10:57:05,039 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:05,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:05,039 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:05,039 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:05,039 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:05,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:06,072 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:06,073 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:06,073 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 95 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 95 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:06,082 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:06,082 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:06,208 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 76 check-sat command(s) [2018-07-24 10:57:06,208 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:06,211 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:06,257 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:06,257 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:07,478 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:07,498 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:07,498 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 96 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 96 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:07,513 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:07,513 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:08,499 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 76 check-sat command(s) [2018-07-24 10:57:08,500 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:08,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:08,540 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:08,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:09,372 INFO L134 CoverageAnalysis]: Checked inductivity of 8475 backedges. 3984 proven. 3384 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:09,373 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:09,374 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [50, 50, 50, 50, 50] total 52 [2018-07-24 10:57:09,374 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:09,374 INFO L450 AbstractCegarLoop]: Interpolant automaton has 50 states [2018-07-24 10:57:09,374 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 50 interpolants. [2018-07-24 10:57:09,374 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:09,375 INFO L87 Difference]: Start difference. First operand 237 states and 265 transitions. Second operand 50 states. [2018-07-24 10:57:09,568 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:09,568 INFO L93 Difference]: Finished difference Result 331 states and 388 transitions. [2018-07-24 10:57:09,568 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 50 states. [2018-07-24 10:57:09,569 INFO L78 Accepts]: Start accepts. Automaton has 50 states. Word has length 236 [2018-07-24 10:57:09,569 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:09,570 INFO L225 Difference]: With dead ends: 331 [2018-07-24 10:57:09,570 INFO L226 Difference]: Without dead ends: 240 [2018-07-24 10:57:09,571 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 992 GetRequests, 850 SyntacticMatches, 92 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2254 ImplicationChecksByTransitivity, 2.9s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:09,571 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 240 states. [2018-07-24 10:57:09,575 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 240 to 240. [2018-07-24 10:57:09,576 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 240 states. [2018-07-24 10:57:09,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 240 states to 240 states and 268 transitions. [2018-07-24 10:57:09,577 INFO L78 Accepts]: Start accepts. Automaton has 240 states and 268 transitions. Word has length 236 [2018-07-24 10:57:09,577 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:09,577 INFO L471 AbstractCegarLoop]: Abstraction has 240 states and 268 transitions. [2018-07-24 10:57:09,577 INFO L472 AbstractCegarLoop]: Interpolant automaton has 50 states. [2018-07-24 10:57:09,577 INFO L276 IsEmpty]: Start isEmpty. Operand 240 states and 268 transitions. [2018-07-24 10:57:09,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 240 [2018-07-24 10:57:09,578 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:09,579 INFO L353 BasicCegarLoop]: trace histogram [77, 76, 48, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:09,579 INFO L414 AbstractCegarLoop]: === Iteration 51 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:09,579 INFO L82 PathProgramCache]: Analyzing trace with hash 94209424, now seen corresponding path program 48 times [2018-07-24 10:57:09,579 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:09,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:09,580 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:09,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:09,580 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:09,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:10,600 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:10,600 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:10,600 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 97 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 97 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:10,607 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:10,607 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:10,850 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 76 check-sat command(s) [2018-07-24 10:57:10,850 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:10,854 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:10,902 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:10,902 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:11,850 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:11,870 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:11,870 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 98 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 98 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:11,884 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:11,885 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:12,997 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 76 check-sat command(s) [2018-07-24 10:57:12,998 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:13,004 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:13,039 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:13,039 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:13,950 INFO L134 CoverageAnalysis]: Checked inductivity of 8702 backedges. 4067 proven. 3528 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:13,951 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:13,952 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [51, 51, 51, 51, 51] total 52 [2018-07-24 10:57:13,952 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:13,952 INFO L450 AbstractCegarLoop]: Interpolant automaton has 51 states [2018-07-24 10:57:13,953 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 51 interpolants. [2018-07-24 10:57:13,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:13,953 INFO L87 Difference]: Start difference. First operand 240 states and 268 transitions. Second operand 51 states. [2018-07-24 10:57:14,135 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:14,136 INFO L93 Difference]: Finished difference Result 334 states and 391 transitions. [2018-07-24 10:57:14,136 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 51 states. [2018-07-24 10:57:14,136 INFO L78 Accepts]: Start accepts. Automaton has 51 states. Word has length 239 [2018-07-24 10:57:14,136 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:14,138 INFO L225 Difference]: With dead ends: 334 [2018-07-24 10:57:14,138 INFO L226 Difference]: Without dead ends: 243 [2018-07-24 10:57:14,138 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1005 GetRequests, 859 SyntacticMatches, 96 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2352 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:14,139 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 243 states. [2018-07-24 10:57:14,144 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 243 to 243. [2018-07-24 10:57:14,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 243 states. [2018-07-24 10:57:14,145 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 243 states to 243 states and 271 transitions. [2018-07-24 10:57:14,145 INFO L78 Accepts]: Start accepts. Automaton has 243 states and 271 transitions. Word has length 239 [2018-07-24 10:57:14,145 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:14,145 INFO L471 AbstractCegarLoop]: Abstraction has 243 states and 271 transitions. [2018-07-24 10:57:14,146 INFO L472 AbstractCegarLoop]: Interpolant automaton has 51 states. [2018-07-24 10:57:14,146 INFO L276 IsEmpty]: Start isEmpty. Operand 243 states and 271 transitions. [2018-07-24 10:57:14,147 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 243 [2018-07-24 10:57:14,147 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:14,147 INFO L353 BasicCegarLoop]: trace histogram [78, 77, 49, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:14,147 INFO L414 AbstractCegarLoop]: === Iteration 52 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:14,148 INFO L82 PathProgramCache]: Analyzing trace with hash 1584377088, now seen corresponding path program 49 times [2018-07-24 10:57:14,148 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:14,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:14,148 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:14,148 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:14,149 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:14,160 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:15,209 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:15,209 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:15,209 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 99 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 99 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:15,216 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:15,216 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:15,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:15,273 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:15,309 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:15,309 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:16,298 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:16,318 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:16,318 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 100 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 100 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:16,333 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:16,333 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:57:16,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:16,450 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:16,483 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:16,483 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:17,710 INFO L134 CoverageAnalysis]: Checked inductivity of 8932 backedges. 4150 proven. 3675 refuted. 0 times theorem prover too weak. 1107 trivial. 0 not checked. [2018-07-24 10:57:17,711 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:17,711 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [52, 52, 52, 52, 52] total 52 [2018-07-24 10:57:17,711 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:17,712 INFO L450 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-07-24 10:57:17,712 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-07-24 10:57:17,712 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:17,712 INFO L87 Difference]: Start difference. First operand 243 states and 271 transitions. Second operand 52 states. [2018-07-24 10:57:17,864 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:17,865 INFO L93 Difference]: Finished difference Result 337 states and 394 transitions. [2018-07-24 10:57:17,865 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-07-24 10:57:17,865 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 242 [2018-07-24 10:57:17,865 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:17,867 INFO L225 Difference]: With dead ends: 337 [2018-07-24 10:57:17,867 INFO L226 Difference]: Without dead ends: 246 [2018-07-24 10:57:17,868 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1018 GetRequests, 868 SyntacticMatches, 100 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2450 ImplicationChecksByTransitivity, 3.1s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:17,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 246 states. [2018-07-24 10:57:17,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 246 to 246. [2018-07-24 10:57:17,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 246 states. [2018-07-24 10:57:17,873 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 246 states to 246 states and 274 transitions. [2018-07-24 10:57:17,873 INFO L78 Accepts]: Start accepts. Automaton has 246 states and 274 transitions. Word has length 242 [2018-07-24 10:57:17,873 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:17,873 INFO L471 AbstractCegarLoop]: Abstraction has 246 states and 274 transitions. [2018-07-24 10:57:17,873 INFO L472 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-07-24 10:57:17,873 INFO L276 IsEmpty]: Start isEmpty. Operand 246 states and 274 transitions. [2018-07-24 10:57:17,874 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 246 [2018-07-24 10:57:17,874 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:17,875 INFO L353 BasicCegarLoop]: trace histogram [79, 78, 50, 28, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:17,875 INFO L414 AbstractCegarLoop]: === Iteration 53 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:17,875 INFO L82 PathProgramCache]: Analyzing trace with hash -1907683440, now seen corresponding path program 50 times [2018-07-24 10:57:17,875 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:17,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:17,876 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:57:17,876 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:17,876 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:17,891 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:18,430 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 4416 proven. 1365 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-07-24 10:57:18,431 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:18,431 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 101 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 101 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:18,450 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:18,450 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:18,509 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:18,509 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:18,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:20,218 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:20,218 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:22,747 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:22,767 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:22,767 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 102 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 102 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:22,781 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:57:22,782 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:22,906 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:57:22,906 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:22,913 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:22,960 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:22,960 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:24,123 INFO L134 CoverageAnalysis]: Checked inductivity of 9165 backedges. 0 proven. 9165 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:24,125 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:24,125 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [33, 81, 81, 81, 81] total 102 [2018-07-24 10:57:24,125 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:24,126 INFO L450 AbstractCegarLoop]: Interpolant automaton has 83 states [2018-07-24 10:57:24,127 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 83 interpolants. [2018-07-24 10:57:24,127 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:57:24,127 INFO L87 Difference]: Start difference. First operand 246 states and 274 transitions. Second operand 83 states. [2018-07-24 10:57:25,993 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:25,993 INFO L93 Difference]: Finished difference Result 261 states and 295 transitions. [2018-07-24 10:57:25,994 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 83 states. [2018-07-24 10:57:25,994 INFO L78 Accepts]: Start accepts. Automaton has 83 states. Word has length 245 [2018-07-24 10:57:25,994 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:25,995 INFO L225 Difference]: With dead ends: 261 [2018-07-24 10:57:25,995 INFO L226 Difference]: Without dead ends: 256 [2018-07-24 10:57:25,996 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1011 GetRequests, 791 SyntacticMatches, 120 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19604 ImplicationChecksByTransitivity, 5.7s TimeCoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:57:25,996 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 256 states. [2018-07-24 10:57:26,000 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 256 to 255. [2018-07-24 10:57:26,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 255 states. [2018-07-24 10:57:26,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 255 states to 255 states and 286 transitions. [2018-07-24 10:57:26,001 INFO L78 Accepts]: Start accepts. Automaton has 255 states and 286 transitions. Word has length 245 [2018-07-24 10:57:26,001 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:26,001 INFO L471 AbstractCegarLoop]: Abstraction has 255 states and 286 transitions. [2018-07-24 10:57:26,001 INFO L472 AbstractCegarLoop]: Interpolant automaton has 83 states. [2018-07-24 10:57:26,001 INFO L276 IsEmpty]: Start isEmpty. Operand 255 states and 286 transitions. [2018-07-24 10:57:26,003 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 255 [2018-07-24 10:57:26,003 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:26,003 INFO L353 BasicCegarLoop]: trace histogram [82, 81, 50, 31, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:26,003 INFO L414 AbstractCegarLoop]: === Iteration 54 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:26,004 INFO L82 PathProgramCache]: Analyzing trace with hash -980452926, now seen corresponding path program 51 times [2018-07-24 10:57:26,004 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:26,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:26,004 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:26,004 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:26,004 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:26,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:26,730 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4848 proven. 1650 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-07-24 10:57:26,731 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:26,731 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 103 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 103 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:26,738 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:26,738 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:26,822 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2018-07-24 10:57:26,822 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:26,826 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:26,859 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-07-24 10:57:26,859 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:28,004 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-07-24 10:57:28,024 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:28,024 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 104 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 104 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:28,040 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:57:28,040 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:57:28,610 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 48 check-sat command(s) [2018-07-24 10:57:28,610 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:28,616 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:28,660 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-07-24 10:57:28,660 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:29,029 INFO L134 CoverageAnalysis]: Checked inductivity of 9882 backedges. 4750 proven. 1457 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-07-24 10:57:29,031 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:29,031 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [36, 34, 34, 34, 34] total 52 [2018-07-24 10:57:29,031 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:29,031 INFO L450 AbstractCegarLoop]: Interpolant automaton has 36 states [2018-07-24 10:57:29,032 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 36 interpolants. [2018-07-24 10:57:29,032 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:29,032 INFO L87 Difference]: Start difference. First operand 255 states and 286 transitions. Second operand 36 states. [2018-07-24 10:57:29,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:29,219 INFO L93 Difference]: Finished difference Result 270 states and 307 transitions. [2018-07-24 10:57:29,219 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 36 states. [2018-07-24 10:57:29,219 INFO L78 Accepts]: Start accepts. Automaton has 36 states. Word has length 254 [2018-07-24 10:57:29,220 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:29,221 INFO L225 Difference]: With dead ends: 270 [2018-07-24 10:57:29,222 INFO L226 Difference]: Without dead ends: 265 [2018-07-24 10:57:29,222 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1050 GetRequests, 968 SyntacticMatches, 32 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 752 ImplicationChecksByTransitivity, 2.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:29,222 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 265 states. [2018-07-24 10:57:29,226 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 265 to 264. [2018-07-24 10:57:29,226 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 264 states. [2018-07-24 10:57:29,226 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 264 states to 264 states and 298 transitions. [2018-07-24 10:57:29,226 INFO L78 Accepts]: Start accepts. Automaton has 264 states and 298 transitions. Word has length 254 [2018-07-24 10:57:29,227 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:29,227 INFO L471 AbstractCegarLoop]: Abstraction has 264 states and 298 transitions. [2018-07-24 10:57:29,227 INFO L472 AbstractCegarLoop]: Interpolant automaton has 36 states. [2018-07-24 10:57:29,227 INFO L276 IsEmpty]: Start isEmpty. Operand 264 states and 298 transitions. [2018-07-24 10:57:29,228 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 264 [2018-07-24 10:57:29,228 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:29,228 INFO L353 BasicCegarLoop]: trace histogram [85, 84, 50, 34, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:29,228 INFO L414 AbstractCegarLoop]: === Iteration 55 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:29,229 INFO L82 PathProgramCache]: Analyzing trace with hash -1711642672, now seen corresponding path program 52 times [2018-07-24 10:57:29,229 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:29,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,229 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:29,229 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:29,229 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:29,243 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:29,896 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 5280 proven. 1962 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-07-24 10:57:29,896 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:29,897 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 105 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 105 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:29,903 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:29,904 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:29,966 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:29,967 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:29,970 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:31,119 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:31,119 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:33,198 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:33,219 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:33,219 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 106 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 106 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:33,233 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:57:33,233 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:57:33,369 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:57:33,369 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:33,377 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:33,437 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:33,437 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:34,786 INFO L134 CoverageAnalysis]: Checked inductivity of 10626 backedges. 0 proven. 10626 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:34,787 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:34,787 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [39, 87, 87, 87, 87] total 102 [2018-07-24 10:57:34,787 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:34,788 INFO L450 AbstractCegarLoop]: Interpolant automaton has 89 states [2018-07-24 10:57:34,788 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 89 interpolants. [2018-07-24 10:57:34,789 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:57:34,789 INFO L87 Difference]: Start difference. First operand 264 states and 298 transitions. Second operand 89 states. [2018-07-24 10:57:35,636 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:35,636 INFO L93 Difference]: Finished difference Result 279 states and 319 transitions. [2018-07-24 10:57:35,636 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 89 states. [2018-07-24 10:57:35,636 INFO L78 Accepts]: Start accepts. Automaton has 89 states. Word has length 263 [2018-07-24 10:57:35,637 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:35,638 INFO L225 Difference]: With dead ends: 279 [2018-07-24 10:57:35,638 INFO L226 Difference]: Without dead ends: 274 [2018-07-24 10:57:35,638 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1089 GetRequests, 845 SyntacticMatches, 144 SemanticMatches, 100 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22544 ImplicationChecksByTransitivity, 4.9s TimeCoverageRelationStatistics Valid=5151, Invalid=5151, Unknown=0, NotChecked=0, Total=10302 [2018-07-24 10:57:35,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-07-24 10:57:35,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 273. [2018-07-24 10:57:35,644 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 273 states. [2018-07-24 10:57:35,644 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 273 states to 273 states and 310 transitions. [2018-07-24 10:57:35,645 INFO L78 Accepts]: Start accepts. Automaton has 273 states and 310 transitions. Word has length 263 [2018-07-24 10:57:35,645 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:35,645 INFO L471 AbstractCegarLoop]: Abstraction has 273 states and 310 transitions. [2018-07-24 10:57:35,645 INFO L472 AbstractCegarLoop]: Interpolant automaton has 89 states. [2018-07-24 10:57:35,645 INFO L276 IsEmpty]: Start isEmpty. Operand 273 states and 310 transitions. [2018-07-24 10:57:35,647 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 273 [2018-07-24 10:57:35,647 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:35,647 INFO L353 BasicCegarLoop]: trace histogram [88, 87, 50, 37, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:35,647 INFO L414 AbstractCegarLoop]: === Iteration 56 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:35,647 INFO L82 PathProgramCache]: Analyzing trace with hash -1073780350, now seen corresponding path program 53 times [2018-07-24 10:57:35,647 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:35,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:35,648 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:35,648 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:35,648 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:35,664 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:36,344 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5712 proven. 2301 refuted. 0 times theorem prover too weak. 3384 trivial. 0 not checked. [2018-07-24 10:57:36,344 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:36,344 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 107 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 107 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:36,351 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:36,352 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:36,501 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 88 check-sat command(s) [2018-07-24 10:57:36,502 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:36,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:36,895 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5662 proven. 3626 refuted. 0 times theorem prover too weak. 2109 trivial. 0 not checked. [2018-07-24 10:57:36,895 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:38,133 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5662 proven. 3626 refuted. 0 times theorem prover too weak. 2109 trivial. 0 not checked. [2018-07-24 10:57:38,154 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:38,154 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 108 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 108 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:38,169 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:57:38,169 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:39,507 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 88 check-sat command(s) [2018-07-24 10:57:39,508 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:39,514 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:39,553 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5650 proven. 2072 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-07-24 10:57:39,554 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:40,466 INFO L134 CoverageAnalysis]: Checked inductivity of 11397 backedges. 5650 proven. 2072 refuted. 0 times theorem prover too weak. 3675 trivial. 0 not checked. [2018-07-24 10:57:40,468 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:40,468 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [42, 52, 52, 40, 40] total 52 [2018-07-24 10:57:40,468 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:40,469 INFO L450 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-07-24 10:57:40,469 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-07-24 10:57:40,469 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:40,469 INFO L87 Difference]: Start difference. First operand 273 states and 310 transitions. Second operand 52 states. [2018-07-24 10:57:40,831 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:40,831 INFO L93 Difference]: Finished difference Result 317 states and 379 transitions. [2018-07-24 10:57:40,832 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-07-24 10:57:40,832 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 272 [2018-07-24 10:57:40,832 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:40,834 INFO L225 Difference]: With dead ends: 317 [2018-07-24 10:57:40,834 INFO L226 Difference]: Without dead ends: 312 [2018-07-24 10:57:40,835 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1128 GetRequests, 990 SyntacticMatches, 88 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1928 ImplicationChecksByTransitivity, 3.0s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:40,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 312 states. [2018-07-24 10:57:40,840 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 312 to 312. [2018-07-24 10:57:40,840 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 312 states. [2018-07-24 10:57:40,840 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 312 states to 312 states and 362 transitions. [2018-07-24 10:57:40,841 INFO L78 Accepts]: Start accepts. Automaton has 312 states and 362 transitions. Word has length 272 [2018-07-24 10:57:40,841 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:40,841 INFO L471 AbstractCegarLoop]: Abstraction has 312 states and 362 transitions. [2018-07-24 10:57:40,841 INFO L472 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-07-24 10:57:40,841 INFO L276 IsEmpty]: Start isEmpty. Operand 312 states and 362 transitions. [2018-07-24 10:57:40,843 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 312 [2018-07-24 10:57:40,843 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:40,843 INFO L353 BasicCegarLoop]: trace histogram [101, 100, 50, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:40,843 INFO L414 AbstractCegarLoop]: === Iteration 57 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:40,844 INFO L82 PathProgramCache]: Analyzing trace with hash -539017776, now seen corresponding path program 54 times [2018-07-24 10:57:40,844 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:40,844 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:40,844 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:40,845 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:40,845 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:40,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:43,694 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-07-24 10:57:43,694 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:43,694 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 109 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 109 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:43,702 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:43,703 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:43,907 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 101 check-sat command(s) [2018-07-24 10:57:43,907 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:43,912 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:44,179 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-07-24 10:57:44,179 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:44,633 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-07-24 10:57:44,653 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:44,653 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 110 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 110 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:57:44,668 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:44,668 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:57:46,674 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 101 check-sat command(s) [2018-07-24 10:57:46,674 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:46,683 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:47,014 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-07-24 10:57:47,014 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:47,358 INFO L134 CoverageAnalysis]: Checked inductivity of 15050 backedges. 0 proven. 11225 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-07-24 10:57:47,360 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:47,360 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [55, 55, 55, 55, 55] total 57 [2018-07-24 10:57:47,360 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:47,361 INFO L450 AbstractCegarLoop]: Interpolant automaton has 55 states [2018-07-24 10:57:47,361 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 55 interpolants. [2018-07-24 10:57:47,361 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=113, Invalid=3079, Unknown=0, NotChecked=0, Total=3192 [2018-07-24 10:57:47,362 INFO L87 Difference]: Start difference. First operand 312 states and 362 transitions. Second operand 55 states. [2018-07-24 10:57:49,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:49,847 INFO L93 Difference]: Finished difference Result 4294 states and 5669 transitions. [2018-07-24 10:57:49,847 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 55 states. [2018-07-24 10:57:49,847 INFO L78 Accepts]: Start accepts. Automaton has 55 states. Word has length 311 [2018-07-24 10:57:49,848 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:49,866 INFO L225 Difference]: With dead ends: 4294 [2018-07-24 10:57:49,866 INFO L226 Difference]: Without dead ends: 4289 [2018-07-24 10:57:49,868 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1298 GetRequests, 1234 SyntacticMatches, 8 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=119, Invalid=3187, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 10:57:49,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4289 states. [2018-07-24 10:57:49,938 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4289 to 315. [2018-07-24 10:57:49,938 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 315 states. [2018-07-24 10:57:49,939 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 315 states to 315 states and 366 transitions. [2018-07-24 10:57:49,939 INFO L78 Accepts]: Start accepts. Automaton has 315 states and 366 transitions. Word has length 311 [2018-07-24 10:57:49,940 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:49,940 INFO L471 AbstractCegarLoop]: Abstraction has 315 states and 366 transitions. [2018-07-24 10:57:49,940 INFO L472 AbstractCegarLoop]: Interpolant automaton has 55 states. [2018-07-24 10:57:49,940 INFO L276 IsEmpty]: Start isEmpty. Operand 315 states and 366 transitions. [2018-07-24 10:57:49,942 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 315 [2018-07-24 10:57:49,942 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:49,942 INFO L353 BasicCegarLoop]: trace histogram [102, 101, 51, 50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:49,942 INFO L414 AbstractCegarLoop]: === Iteration 58 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:49,943 INFO L82 PathProgramCache]: Analyzing trace with hash -1331356094, now seen corresponding path program 55 times [2018-07-24 10:57:49,943 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:49,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,944 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:49,944 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:49,944 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:49,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:51,570 INFO L134 CoverageAnalysis]: Checked inductivity of 15352 backedges. 11527 proven. 0 refuted. 0 times theorem prover too weak. 3825 trivial. 0 not checked. [2018-07-24 10:57:51,570 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:57:51,570 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [52] imperfect sequences [] total 52 [2018-07-24 10:57:51,570 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:57:51,571 INFO L450 AbstractCegarLoop]: Interpolant automaton has 52 states [2018-07-24 10:57:51,571 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 52 interpolants. [2018-07-24 10:57:51,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:51,572 INFO L87 Difference]: Start difference. First operand 315 states and 366 transitions. Second operand 52 states. [2018-07-24 10:57:51,874 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:51,874 INFO L93 Difference]: Finished difference Result 464 states and 564 transitions. [2018-07-24 10:57:51,875 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 52 states. [2018-07-24 10:57:51,875 INFO L78 Accepts]: Start accepts. Automaton has 52 states. Word has length 314 [2018-07-24 10:57:51,876 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:51,876 INFO L225 Difference]: With dead ends: 464 [2018-07-24 10:57:51,876 INFO L226 Difference]: Without dead ends: 0 [2018-07-24 10:57:51,877 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 52 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=1326, Invalid=1326, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:57:51,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 0 states. [2018-07-24 10:57:51,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 0 to 0. [2018-07-24 10:57:51,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 0 states. [2018-07-24 10:57:51,878 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 0 states to 0 states and 0 transitions. [2018-07-24 10:57:51,879 INFO L78 Accepts]: Start accepts. Automaton has 0 states and 0 transitions. Word has length 314 [2018-07-24 10:57:51,879 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:51,879 INFO L471 AbstractCegarLoop]: Abstraction has 0 states and 0 transitions. [2018-07-24 10:57:51,879 INFO L472 AbstractCegarLoop]: Interpolant automaton has 52 states. [2018-07-24 10:57:51,879 INFO L276 IsEmpty]: Start isEmpty. Operand 0 states and 0 transitions. [2018-07-24 10:57:51,879 INFO L282 IsEmpty]: Finished isEmpty. No accepting run. [2018-07-24 10:57:51,884 INFO L343 DoubleDeckerVisitor]: Before removal of dead ends 0 states and 0 transitions. [2018-07-24 10:57:52,710 WARN L169 SmtUtils]: Spent 786.00 ms on a formula simplification. DAG size of input: 1832 DAG size of output: 407 [2018-07-24 10:57:55,650 WARN L169 SmtUtils]: Spent 2.81 s on a formula simplification. DAG size of input: 407 DAG size of output: 357 [2018-07-24 10:57:55,656 INFO L421 ceAbstractionStarter]: For program point ULTIMATE.initEXIT(line -1) no Hoare annotation was computed. [2018-07-24 10:57:55,656 INFO L424 ceAbstractionStarter]: At program point ULTIMATE.initFINAL(line -1) the Hoare annotation is: true [2018-07-24 10:57:55,656 INFO L421 ceAbstractionStarter]: For program point __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertEXIT(lines 3 8) no Hoare annotation was computed. [2018-07-24 10:57:55,656 INFO L421 ceAbstractionStarter]: For program point L4(lines 4 6) no Hoare annotation was computed. [2018-07-24 10:57:55,656 INFO L421 ceAbstractionStarter]: For program point L5(line 5) no Hoare annotation was computed. [2018-07-24 10:57:55,657 INFO L421 ceAbstractionStarter]: For program point L4''(lines 3 8) no Hoare annotation was computed. [2018-07-24 10:57:55,657 INFO L421 ceAbstractionStarter]: For program point __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION(line 5) no Hoare annotation was computed. [2018-07-24 10:57:55,657 INFO L424 ceAbstractionStarter]: At program point __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_lit_gj_____true_unreach_call_true_termination_c_i____VERIFIER_assertENTRY(lines 3 8) the Hoare annotation is: true [2018-07-24 10:57:55,657 INFO L424 ceAbstractionStarter]: At program point L-1(line -1) the Hoare annotation is: true [2018-07-24 10:57:55,657 INFO L424 ceAbstractionStarter]: At program point ULTIMATE.startENTRY(line -1) the Hoare annotation is: true [2018-07-24 10:57:55,657 INFO L421 ceAbstractionStarter]: For program point ULTIMATE.startFINAL(line -1) no Hoare annotation was computed. [2018-07-24 10:57:55,657 INFO L421 ceAbstractionStarter]: For program point ULTIMATE.startEXIT(line -1) no Hoare annotation was computed. [2018-07-24 10:57:55,657 INFO L417 ceAbstractionStarter]: At program point L13''(lines 13 20) the Hoare annotation is: (and (<= main_~y~0 100) (< 99 main_~y~0)) [2018-07-24 10:57:55,657 INFO L421 ceAbstractionStarter]: For program point mainFINAL(lines 10 23) no Hoare annotation was computed. [2018-07-24 10:57:55,659 INFO L417 ceAbstractionStarter]: At program point L14''(lines 13 20) the Hoare annotation is: (or (and (and (<= main_~x~0 99) (<= 99 main_~y~0) (<= main_~y~0 99)) (<= 99 main_~x~0)) (and (and (<= main_~y~0 92) (<= 92 main_~y~0) (<= main_~x~0 92)) (<= 92 main_~x~0)) (and (<= 65 main_~x~0) (and (<= main_~y~0 65) (<= 65 main_~y~0) (<= main_~x~0 65))) (and (and (<= main_~y~0 100) (< 99 main_~y~0)) (<= 100 main_~x~0)) (and (<= 64 main_~x~0) (and (<= main_~x~0 64) (<= 64 main_~y~0) (<= main_~y~0 64))) (and (<= 76 main_~x~0) (and (<= main_~y~0 76) (<= main_~x~0 76) (<= 76 main_~y~0))) (and (<= 87 main_~x~0) (and (<= main_~x~0 87) (<= main_~y~0 87) (<= 87 main_~y~0))) (and (and (<= main_~y~0 78) (<= 78 main_~y~0) (<= main_~x~0 78)) (<= 78 main_~x~0)) (and (<= 72 main_~x~0) (and (<= main_~y~0 72) (<= main_~x~0 72) (<= 72 main_~y~0))) (and (and (<= main_~y~0 69) (<= 69 main_~y~0) (<= main_~x~0 69)) (<= 69 main_~x~0)) (and (<= 60 main_~x~0) (and (<= main_~x~0 60) (<= main_~y~0 60) (<= 60 main_~y~0))) (and (<= 67 main_~x~0) (and (<= main_~y~0 67) (<= main_~x~0 67) (<= 67 main_~y~0))) (and (and (<= main_~y~0 55) (<= 55 main_~y~0) (<= main_~x~0 55)) (<= 55 main_~x~0)) (and (and (<= 73 main_~y~0) (<= main_~x~0 73) (<= main_~y~0 73)) (<= 73 main_~x~0)) (and (<= 66 main_~x~0) (and (<= main_~y~0 66) (<= 66 main_~y~0) (<= main_~x~0 66))) (and (and (<= main_~x~0 70) (<= main_~y~0 70) (<= 70 main_~y~0)) (<= 70 main_~x~0)) (and (and (<= main_~x~0 95) (<= main_~y~0 95) (<= 95 main_~y~0)) (<= 95 main_~x~0)) (and (and (<= 90 main_~y~0) (<= main_~y~0 90) (<= main_~x~0 90)) (<= 90 main_~x~0)) (and (and (<= main_~y~0 59) (<= main_~x~0 59) (<= 59 main_~y~0)) (<= 59 main_~x~0)) (and (<= 85 main_~x~0) (and (<= 85 main_~y~0) (<= main_~x~0 85) (<= main_~y~0 85))) (and (<= 63 main_~x~0) (and (<= main_~y~0 63) (<= main_~x~0 63) (<= 63 main_~y~0))) (and (and (<= main_~y~0 77) (<= main_~x~0 77) (<= 77 main_~y~0)) (<= 77 main_~x~0)) (and (<= 53 main_~x~0) (and (<= main_~y~0 53) (<= main_~x~0 53) (<= 53 main_~y~0))) (and (and (<= main_~x~0 79) (<= main_~y~0 79) (<= 79 main_~y~0)) (<= 79 main_~x~0)) (and (<= 68 main_~x~0) (and (<= 68 main_~y~0) (<= main_~y~0 68) (<= main_~x~0 68))) (and (<= 51 main_~x~0) (and (<= 51 main_~y~0) (<= main_~x~0 51) (<= main_~y~0 51))) (and (<= 54 main_~x~0) (and (<= main_~x~0 54) (<= 54 main_~y~0) (<= main_~y~0 54))) (and (and (<= 56 main_~y~0) (<= main_~x~0 56) (<= main_~y~0 56)) (<= 56 main_~x~0)) (and (<= 61 main_~x~0) (and (<= main_~y~0 61) (<= 61 main_~y~0) (<= main_~x~0 61))) (and (<= 88 main_~x~0) (and (<= main_~x~0 88) (<= main_~y~0 88) (<= 88 main_~y~0))) (and (<= main_~y~0 50) (<= main_~x~0 50) (<= 50 main_~y~0)) (and (<= 80 main_~x~0) (and (<= main_~x~0 80) (<= 80 main_~y~0) (<= main_~y~0 80))) (and (<= 94 main_~x~0) (and (<= main_~x~0 94) (<= main_~y~0 94) (<= 94 main_~y~0))) (and (<= 89 main_~x~0) (and (<= 89 main_~y~0) (<= main_~y~0 89) (<= main_~x~0 89))) (and (and (<= 86 main_~y~0) (<= main_~x~0 86) (<= main_~y~0 86)) (<= 86 main_~x~0)) (and (<= 58 main_~x~0) (and (<= main_~x~0 58) (<= main_~y~0 58) (<= 58 main_~y~0))) (and (and (<= main_~x~0 91) (<= 91 main_~y~0) (<= main_~y~0 91)) (<= 91 main_~x~0)) (and (and (<= 52 main_~y~0) (<= main_~y~0 52) (<= main_~x~0 52)) (<= 52 main_~x~0)) (and (<= 93 main_~x~0) (and (<= main_~x~0 93) (<= 93 main_~y~0) (<= main_~y~0 93))) (and (<= 74 main_~x~0) (and (<= 74 main_~y~0) (<= main_~y~0 74) (<= main_~x~0 74))) (and (and (<= main_~y~0 71) (<= main_~x~0 71) (<= 71 main_~y~0)) (<= 71 main_~x~0)) (and (<= 57 main_~x~0) (and (<= 57 main_~y~0) (<= main_~x~0 57) (<= main_~y~0 57))) (and (<= 97 main_~x~0) (and (<= 97 main_~y~0) (<= main_~x~0 97) (<= main_~y~0 97))) (and (and (<= main_~x~0 81) (<= 81 main_~y~0) (<= main_~y~0 81)) (<= 81 main_~x~0)) (and (<= 84 main_~x~0) (and (<= main_~y~0 84) (<= 84 main_~y~0) (<= main_~x~0 84))) (and (and (<= 96 main_~y~0) (<= main_~x~0 96) (<= main_~y~0 96)) (<= 96 main_~x~0)) (and (<= 83 main_~x~0) (and (<= main_~y~0 83) (<= 83 main_~y~0) (<= main_~x~0 83))) (and (<= 62 main_~x~0) (and (<= main_~y~0 62) (<= main_~x~0 62) (<= 62 main_~y~0))) (and (and (<= main_~x~0 98) (<= main_~y~0 98) (<= 98 main_~y~0)) (<= 98 main_~x~0)) (and (and (<= 75 main_~y~0) (<= main_~x~0 75) (<= main_~y~0 75)) (<= 75 main_~x~0)) (and (and (<= 82 main_~y~0) (<= main_~y~0 82) (<= main_~x~0 82)) (<= 82 main_~x~0))) [2018-07-24 10:57:55,659 INFO L421 ceAbstractionStarter]: For program point L21(line 21) no Hoare annotation was computed. [2018-07-24 10:57:55,659 INFO L421 ceAbstractionStarter]: For program point L14(lines 14 19) no Hoare annotation was computed. [2018-07-24 10:57:55,659 INFO L421 ceAbstractionStarter]: For program point L13(lines 13 20) no Hoare annotation was computed. [2018-07-24 10:57:55,659 INFO L421 ceAbstractionStarter]: For program point mainEXIT(lines 10 23) no Hoare annotation was computed. [2018-07-24 10:57:55,659 INFO L424 ceAbstractionStarter]: At program point mainENTRY(lines 10 23) the Hoare annotation is: true [2018-07-24 10:57:55,685 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 10:57:55 BoogieIcfgContainer [2018-07-24 10:57:55,685 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 10:57:55,686 INFO L168 Benchmark]: Toolchain (without parser) took 162295.68 ms. Allocated memory was 1.5 GB in the beginning and 2.6 GB in the end (delta: 1.0 GB). Free memory was 1.4 GB in the beginning and 2.4 GB in the end (delta: -969.6 MB). Peak memory consumption was 848.0 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:55,686 INFO L168 Benchmark]: CDTParser took 0.23 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:57:55,687 INFO L168 Benchmark]: CACSL2BoogieTranslator took 286.22 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:55,687 INFO L168 Benchmark]: Boogie Procedure Inliner took 23.91 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:57:55,688 INFO L168 Benchmark]: Boogie Preprocessor took 24.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 10:57:55,688 INFO L168 Benchmark]: RCFGBuilder took 417.78 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 781.2 MB). Free memory was 1.4 GB in the beginning and 2.3 GB in the end (delta: -834.0 MB). Peak memory consumption was 26.9 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:55,688 INFO L168 Benchmark]: TraceAbstraction took 161538.86 ms. Allocated memory was 2.3 GB in the beginning and 2.6 GB in the end (delta: 235.4 MB). Free memory was 2.3 GB in the beginning and 2.4 GB in the end (delta: -146.2 MB). Peak memory consumption was 890.3 MB. Max. memory is 7.1 GB. [2018-07-24 10:57:55,691 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.23 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 286.22 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 23.91 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 24.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * RCFGBuilder took 417.78 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 781.2 MB). Free memory was 1.4 GB in the beginning and 2.3 GB in the end (delta: -834.0 MB). Peak memory consumption was 26.9 MB. Max. memory is 7.1 GB. * TraceAbstraction took 161538.86 ms. Allocated memory was 2.3 GB in the beginning and 2.6 GB in the end (delta: 235.4 MB). Free memory was 2.3 GB in the beginning and 2.4 GB in the end (delta: -146.2 MB). Peak memory consumption was 890.3 MB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - PositiveResult [Line: 5]: call of __VERIFIER_error() unreachable For all program executions holds that call of __VERIFIER_error() unreachable at this location - AllSpecificationsHoldResult: All specifications hold 1 specifications checked. All of them hold - InvariantResult [Line: 13]: Loop Invariant Derived loop invariant: ((((((((((((((((((((((((((((((((((((((((((((((((((((x <= 99 && 99 <= y) && y <= 99) && 99 <= x) || (((y <= 92 && 92 <= y) && x <= 92) && 92 <= x)) || (65 <= x && (y <= 65 && 65 <= y) && x <= 65)) || ((y <= 100 && 99 < y) && 100 <= x)) || (64 <= x && (x <= 64 && 64 <= y) && y <= 64)) || (76 <= x && (y <= 76 && x <= 76) && 76 <= y)) || (87 <= x && (x <= 87 && y <= 87) && 87 <= y)) || (((y <= 78 && 78 <= y) && x <= 78) && 78 <= x)) || (72 <= x && (y <= 72 && x <= 72) && 72 <= y)) || (((y <= 69 && 69 <= y) && x <= 69) && 69 <= x)) || (60 <= x && (x <= 60 && y <= 60) && 60 <= y)) || (67 <= x && (y <= 67 && x <= 67) && 67 <= y)) || (((y <= 55 && 55 <= y) && x <= 55) && 55 <= x)) || (((73 <= y && x <= 73) && y <= 73) && 73 <= x)) || (66 <= x && (y <= 66 && 66 <= y) && x <= 66)) || (((x <= 70 && y <= 70) && 70 <= y) && 70 <= x)) || (((x <= 95 && y <= 95) && 95 <= y) && 95 <= x)) || (((90 <= y && y <= 90) && x <= 90) && 90 <= x)) || (((y <= 59 && x <= 59) && 59 <= y) && 59 <= x)) || (85 <= x && (85 <= y && x <= 85) && y <= 85)) || (63 <= x && (y <= 63 && x <= 63) && 63 <= y)) || (((y <= 77 && x <= 77) && 77 <= y) && 77 <= x)) || (53 <= x && (y <= 53 && x <= 53) && 53 <= y)) || (((x <= 79 && y <= 79) && 79 <= y) && 79 <= x)) || (68 <= x && (68 <= y && y <= 68) && x <= 68)) || (51 <= x && (51 <= y && x <= 51) && y <= 51)) || (54 <= x && (x <= 54 && 54 <= y) && y <= 54)) || (((56 <= y && x <= 56) && y <= 56) && 56 <= x)) || (61 <= x && (y <= 61 && 61 <= y) && x <= 61)) || (88 <= x && (x <= 88 && y <= 88) && 88 <= y)) || ((y <= 50 && x <= 50) && 50 <= y)) || (80 <= x && (x <= 80 && 80 <= y) && y <= 80)) || (94 <= x && (x <= 94 && y <= 94) && 94 <= y)) || (89 <= x && (89 <= y && y <= 89) && x <= 89)) || (((86 <= y && x <= 86) && y <= 86) && 86 <= x)) || (58 <= x && (x <= 58 && y <= 58) && 58 <= y)) || (((x <= 91 && 91 <= y) && y <= 91) && 91 <= x)) || (((52 <= y && y <= 52) && x <= 52) && 52 <= x)) || (93 <= x && (x <= 93 && 93 <= y) && y <= 93)) || (74 <= x && (74 <= y && y <= 74) && x <= 74)) || (((y <= 71 && x <= 71) && 71 <= y) && 71 <= x)) || (57 <= x && (57 <= y && x <= 57) && y <= 57)) || (97 <= x && (97 <= y && x <= 97) && y <= 97)) || (((x <= 81 && 81 <= y) && y <= 81) && 81 <= x)) || (84 <= x && (y <= 84 && 84 <= y) && x <= 84)) || (((96 <= y && x <= 96) && y <= 96) && 96 <= x)) || (83 <= x && (y <= 83 && 83 <= y) && x <= 83)) || (62 <= x && (y <= 62 && x <= 62) && 62 <= y)) || (((x <= 98 && y <= 98) && 98 <= y) && 98 <= x)) || (((75 <= y && x <= 75) && y <= 75) && 75 <= x)) || (((82 <= y && y <= 82) && x <= 82) && 82 <= x) - StatisticsResult: Ultimate Automizer benchmark data CFG has 4 procedures, 20 locations, 1 error locations. SAFE Result, 161.4s OverallTime, 58 OverallIterations, 102 TraceHistogramMax, 16.1s AutomataDifference, 0.0s DeadEndRemovalTime, 3.7s HoareAnnotationTime, HoareTripleCheckerStatistics: 887 SDtfs, 708 SDslu, 15252 SDs, 0 SdLazy, 7859 SolverSat, 1969 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 11.7s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 33778 GetRequests, 29753 SyntacticMatches, 1524 SemanticMatches, 2501 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 72563 ImplicationChecksByTransitivity, 107.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=315occurred in iteration=57, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.4s AutomataMinimizationTime, 58 MinimizatonAttempts, 3988 StatesRemovedByMinimization, 15 NontrivialMinimizations, HoareAnnotationStatistics: 0.0s HoareAnnotationTime, 7 LocationsWithAnnotation, 64 PreInvPairs, 166 NumberOfFragments, 720 HoareAnnotationTreeSize, 64 FomulaSimplifications, 13400 FormulaSimplificationTreeSizeReduction, 0.8s HoareSimplificationTime, 7 FomulaSimplificationsInter, 200 FormulaSimplificationTreeSizeReductionInter, 2.9s HoareSimplificationTimeInter, RefinementEngineStatistics: TraceCheckStatistics: 0.5s SsaConstructionTime, 19.9s SatisfiabilityAnalysisTime, 116.5s InterpolantComputationTime, 24528 NumberOfCodeBlocks, 23544 NumberOfCodeBlocksAsserted, 2455 NumberOfCheckSat, 40376 ConstructedInterpolants, 0 QuantifiedInterpolants, 18639664 SizeOfPredicates, 58 NumberOfNonLiveVariables, 29976 ConjunctsInSsa, 3252 ConjunctsInUnsatCore, 276 InterpolantComputations, 5 PerfectInterpolantSequences, 700100/1151308 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be correct! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/gj2007_true-unreach-call_true-termination.c.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_10-57-55-707.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/gj2007_true-unreach-call_true-termination.c.i_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_10-57-55-707.csv Received shutdown request...