java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/overflow_true-unreach-call1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:52:25,618 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:52:25,621 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:52:25,639 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:52:25,640 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:52:25,641 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:52:25,642 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:52:25,645 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:52:25,647 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:52:25,648 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:52:25,651 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:52:25,651 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:52:25,653 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:52:25,654 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:52:25,657 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:52:25,664 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:52:25,665 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:52:25,668 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:52:25,670 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:52:25,672 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:52:25,675 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:52:25,676 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:52:25,679 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:52:25,679 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:52:25,679 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:52:25,680 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:52:25,682 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:52:25,682 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:52:25,683 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:52:25,685 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:52:25,685 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:52:25,686 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:52:25,688 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:52:25,688 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:52:25,690 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:52:25,690 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:52:25,691 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:52:25,719 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:52:25,719 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:52:25,720 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:52:25,720 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:52:25,720 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:52:25,721 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:52:25,721 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:52:25,721 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:52:25,722 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:52:25,722 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:52:25,722 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:52:25,723 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:52:25,723 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:52:25,723 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:52:25,723 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:52:25,724 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:52:25,724 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:52:25,724 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:52:25,724 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:52:25,724 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:52:25,724 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:52:25,725 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:52:25,725 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:52:25,725 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:52:25,725 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:52:25,725 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:52:25,726 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:52:25,726 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:52:25,726 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:52:25,726 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:52:25,728 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:52:25,728 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:52:25,728 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:52:25,779 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:52:25,792 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:52:25,796 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:52:25,798 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:52:25,798 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:52:25,799 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/overflow_true-unreach-call1.i [2018-07-24 10:52:26,168 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/786bc5038/354d34992d1d48dbb6d6f025ceb3b34f/FLAG8b62a220b [2018-07-24 10:52:26,314 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:52:26,315 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/overflow_true-unreach-call1.i [2018-07-24 10:52:26,320 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/786bc5038/354d34992d1d48dbb6d6f025ceb3b34f/FLAG8b62a220b [2018-07-24 10:52:26,334 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/786bc5038/354d34992d1d48dbb6d6f025ceb3b34f [2018-07-24 10:52:26,343 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:52:26,345 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:52:26,346 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:52:26,346 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:52:26,352 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:52:26,354 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,357 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@342c2a2f and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26, skipping insertion in model container [2018-07-24 10:52:26,357 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,514 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:52:26,549 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:52:26,563 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:52:26,567 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:52:26,579 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26 WrapperNode [2018-07-24 10:52:26,579 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:52:26,580 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:52:26,581 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:52:26,581 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:52:26,589 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,595 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,601 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:52:26,601 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:52:26,602 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:52:26,602 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:52:26,611 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,612 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,613 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,613 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,614 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,619 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,620 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... [2018-07-24 10:52:26,622 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:52:26,622 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:52:26,622 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:52:26,622 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:52:26,623 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:52:26,693 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:52:26,694 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:52:26,694 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assert [2018-07-24 10:52:26,694 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assert [2018-07-24 10:52:26,694 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:52:26,694 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:52:26,694 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:52:26,695 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:52:26,917 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:52:26,917 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:52:26 BoogieIcfgContainer [2018-07-24 10:52:26,918 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:52:26,918 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:52:26,918 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:52:26,922 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:52:26,922 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:52:26" (1/3) ... [2018-07-24 10:52:26,923 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7db9edaa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:52:26, skipping insertion in model container [2018-07-24 10:52:26,923 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:26" (2/3) ... [2018-07-24 10:52:26,923 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@7db9edaa and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:52:26, skipping insertion in model container [2018-07-24 10:52:26,924 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:52:26" (3/3) ... [2018-07-24 10:52:26,925 INFO L112 eAbstractionObserver]: Analyzing ICFG overflow_true-unreach-call1.i [2018-07-24 10:52:26,935 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:52:26,943 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:52:27,002 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:52:27,002 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:52:27,003 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:52:27,003 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:52:27,003 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:52:27,003 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:52:27,003 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:52:27,004 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:52:27,004 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:52:27,020 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states. [2018-07-24 10:52:27,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:52:27,026 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:27,027 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:27,027 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:27,032 INFO L82 PathProgramCache]: Analyzing trace with hash 314686959, now seen corresponding path program 1 times [2018-07-24 10:52:27,035 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:27,091 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:27,092 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:27,092 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:27,092 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:27,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:27,149 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:27,151 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:52:27,151 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:52:27,151 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:27,155 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:52:27,167 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:52:27,168 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:52:27,170 INFO L87 Difference]: Start difference. First operand 18 states. Second operand 2 states. [2018-07-24 10:52:27,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:27,190 INFO L93 Difference]: Finished difference Result 29 states and 32 transitions. [2018-07-24 10:52:27,191 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:52:27,192 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:52:27,193 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:27,201 INFO L225 Difference]: With dead ends: 29 [2018-07-24 10:52:27,201 INFO L226 Difference]: Without dead ends: 12 [2018-07-24 10:52:27,205 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:52:27,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 12 states. [2018-07-24 10:52:27,239 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 12 to 12. [2018-07-24 10:52:27,240 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 12 states. [2018-07-24 10:52:27,241 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 12 states to 12 states and 12 transitions. [2018-07-24 10:52:27,243 INFO L78 Accepts]: Start accepts. Automaton has 12 states and 12 transitions. Word has length 10 [2018-07-24 10:52:27,243 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:27,244 INFO L471 AbstractCegarLoop]: Abstraction has 12 states and 12 transitions. [2018-07-24 10:52:27,244 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:52:27,244 INFO L276 IsEmpty]: Start isEmpty. Operand 12 states and 12 transitions. [2018-07-24 10:52:27,244 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:52:27,245 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:27,245 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:27,245 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:27,245 INFO L82 PathProgramCache]: Analyzing trace with hash 926255632, now seen corresponding path program 1 times [2018-07-24 10:52:27,246 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:27,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:27,247 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:27,247 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:27,247 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:27,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:27,384 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:27,384 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:52:27,385 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:52:27,385 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:27,387 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:52:27,387 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:52:27,387 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:52:27,388 INFO L87 Difference]: Start difference. First operand 12 states and 12 transitions. Second operand 3 states. [2018-07-24 10:52:27,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:27,436 INFO L93 Difference]: Finished difference Result 19 states and 19 transitions. [2018-07-24 10:52:27,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:52:27,437 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:52:27,437 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:27,438 INFO L225 Difference]: With dead ends: 19 [2018-07-24 10:52:27,438 INFO L226 Difference]: Without dead ends: 14 [2018-07-24 10:52:27,439 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:52:27,440 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14 states. [2018-07-24 10:52:27,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14 to 14. [2018-07-24 10:52:27,443 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 14 states. [2018-07-24 10:52:27,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14 states to 14 states and 14 transitions. [2018-07-24 10:52:27,444 INFO L78 Accepts]: Start accepts. Automaton has 14 states and 14 transitions. Word has length 11 [2018-07-24 10:52:27,444 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:27,444 INFO L471 AbstractCegarLoop]: Abstraction has 14 states and 14 transitions. [2018-07-24 10:52:27,444 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:52:27,445 INFO L276 IsEmpty]: Start isEmpty. Operand 14 states and 14 transitions. [2018-07-24 10:52:27,445 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 14 [2018-07-24 10:52:27,445 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:27,445 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:27,446 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:27,446 INFO L82 PathProgramCache]: Analyzing trace with hash -1883357962, now seen corresponding path program 1 times [2018-07-24 10:52:27,446 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:27,447 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:27,447 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:27,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:27,448 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:27,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:27,595 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:27,595 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:27,596 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:27,607 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:27,607 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:27,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:27,634 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:27,732 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:27,733 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:28,026 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,058 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:28,059 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:28,091 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:28,091 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:28,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:28,116 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:28,163 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,163 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:28,185 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (3)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:52:28,189 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:28,189 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:52:28,190 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:28,190 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:52:28,190 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:52:28,191 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:52:28,191 INFO L87 Difference]: Start difference. First operand 14 states and 14 transitions. Second operand 4 states. [2018-07-24 10:52:28,242 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:28,242 INFO L93 Difference]: Finished difference Result 21 states and 21 transitions. [2018-07-24 10:52:28,243 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:52:28,243 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 13 [2018-07-24 10:52:28,243 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:28,244 INFO L225 Difference]: With dead ends: 21 [2018-07-24 10:52:28,244 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:52:28,245 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 55 GetRequests, 48 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:52:28,245 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:52:28,248 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-07-24 10:52:28,248 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-07-24 10:52:28,249 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 16 transitions. [2018-07-24 10:52:28,249 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 16 transitions. Word has length 13 [2018-07-24 10:52:28,249 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:28,250 INFO L471 AbstractCegarLoop]: Abstraction has 16 states and 16 transitions. [2018-07-24 10:52:28,250 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:52:28,250 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 16 transitions. [2018-07-24 10:52:28,251 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-07-24 10:52:28,251 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:28,251 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:28,251 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:28,252 INFO L82 PathProgramCache]: Analyzing trace with hash -387592612, now seen corresponding path program 2 times [2018-07-24 10:52:28,252 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:28,253 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:28,254 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:28,254 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:28,254 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:28,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:28,480 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,480 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:28,481 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:28,500 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:28,501 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:28,517 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:28,518 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:28,519 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:28,586 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,586 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:28,768 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,789 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:28,789 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:28,814 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:28,814 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:28,845 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:28,845 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:28,849 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:28,886 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,886 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:28,909 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 6 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:28,912 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:28,912 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:52:28,913 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:28,913 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:52:28,914 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:52:28,914 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:28,914 INFO L87 Difference]: Start difference. First operand 16 states and 16 transitions. Second operand 5 states. [2018-07-24 10:52:28,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:28,960 INFO L93 Difference]: Finished difference Result 23 states and 23 transitions. [2018-07-24 10:52:28,962 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:52:28,962 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 15 [2018-07-24 10:52:28,963 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:28,963 INFO L225 Difference]: With dead ends: 23 [2018-07-24 10:52:28,963 INFO L226 Difference]: Without dead ends: 18 [2018-07-24 10:52:28,964 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 64 GetRequests, 55 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:28,964 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18 states. [2018-07-24 10:52:28,967 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18 to 18. [2018-07-24 10:52:28,968 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 18 states. [2018-07-24 10:52:28,968 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18 states to 18 states and 18 transitions. [2018-07-24 10:52:28,969 INFO L78 Accepts]: Start accepts. Automaton has 18 states and 18 transitions. Word has length 15 [2018-07-24 10:52:28,969 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:28,969 INFO L471 AbstractCegarLoop]: Abstraction has 18 states and 18 transitions. [2018-07-24 10:52:28,969 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:52:28,970 INFO L276 IsEmpty]: Start isEmpty. Operand 18 states and 18 transitions. [2018-07-24 10:52:28,970 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:52:28,970 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:28,971 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:28,971 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:28,971 INFO L82 PathProgramCache]: Analyzing trace with hash -1771135422, now seen corresponding path program 3 times [2018-07-24 10:52:28,971 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:28,972 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:28,973 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:28,973 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:28,973 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:28,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:29,100 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:29,101 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:29,101 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:29,115 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:29,115 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:29,127 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:52:29,127 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:29,128 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:29,140 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:29,141 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:29,360 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:29,381 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:29,381 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:29,397 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:29,398 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:29,430 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 4 check-sat command(s) [2018-07-24 10:52:29,431 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:29,434 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:29,469 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:29,469 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:29,509 INFO L134 CoverageAnalysis]: Checked inductivity of 12 backedges. 0 proven. 12 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:29,516 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:29,517 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 10:52:29,517 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:29,518 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 10:52:29,518 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 10:52:29,518 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:52:29,519 INFO L87 Difference]: Start difference. First operand 18 states and 18 transitions. Second operand 6 states. [2018-07-24 10:52:29,610 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:29,610 INFO L93 Difference]: Finished difference Result 25 states and 25 transitions. [2018-07-24 10:52:29,611 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:52:29,611 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 17 [2018-07-24 10:52:29,612 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:29,613 INFO L225 Difference]: With dead ends: 25 [2018-07-24 10:52:29,613 INFO L226 Difference]: Without dead ends: 20 [2018-07-24 10:52:29,614 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 73 GetRequests, 62 SyntacticMatches, 3 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=33, Invalid=57, Unknown=0, NotChecked=0, Total=90 [2018-07-24 10:52:29,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 20 states. [2018-07-24 10:52:29,617 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 20 to 20. [2018-07-24 10:52:29,617 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 20 states. [2018-07-24 10:52:29,618 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 20 states to 20 states and 20 transitions. [2018-07-24 10:52:29,619 INFO L78 Accepts]: Start accepts. Automaton has 20 states and 20 transitions. Word has length 17 [2018-07-24 10:52:29,619 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:29,619 INFO L471 AbstractCegarLoop]: Abstraction has 20 states and 20 transitions. [2018-07-24 10:52:29,619 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 10:52:29,619 INFO L276 IsEmpty]: Start isEmpty. Operand 20 states and 20 transitions. [2018-07-24 10:52:29,620 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 20 [2018-07-24 10:52:29,620 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:29,620 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:29,620 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:29,621 INFO L82 PathProgramCache]: Analyzing trace with hash 84085928, now seen corresponding path program 4 times [2018-07-24 10:52:29,621 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:29,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:29,622 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:29,622 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:29,622 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:29,633 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:29,919 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:29,919 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:29,919 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:29,939 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:29,939 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:29,978 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:29,979 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:29,981 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:30,050 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,050 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:30,318 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,338 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:30,338 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:30,360 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:30,360 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:30,378 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:30,379 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:30,382 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:30,399 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,400 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:30,407 INFO L134 CoverageAnalysis]: Checked inductivity of 20 backedges. 0 proven. 20 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,409 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:30,409 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 10:52:30,409 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:30,410 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:52:30,410 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:52:30,411 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:52:30,412 INFO L87 Difference]: Start difference. First operand 20 states and 20 transitions. Second operand 7 states. [2018-07-24 10:52:30,497 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:30,497 INFO L93 Difference]: Finished difference Result 27 states and 27 transitions. [2018-07-24 10:52:30,498 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:52:30,498 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 19 [2018-07-24 10:52:30,498 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:30,499 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:52:30,499 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:52:30,500 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 82 GetRequests, 69 SyntacticMatches, 3 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 5 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=46, Invalid=86, Unknown=0, NotChecked=0, Total=132 [2018-07-24 10:52:30,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:52:30,504 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-07-24 10:52:30,504 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-07-24 10:52:30,505 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 22 transitions. [2018-07-24 10:52:30,505 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 22 transitions. Word has length 19 [2018-07-24 10:52:30,505 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:30,506 INFO L471 AbstractCegarLoop]: Abstraction has 22 states and 22 transitions. [2018-07-24 10:52:30,506 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:52:30,506 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 22 transitions. [2018-07-24 10:52:30,507 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-07-24 10:52:30,507 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:30,507 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:30,507 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:30,507 INFO L82 PathProgramCache]: Analyzing trace with hash 540375438, now seen corresponding path program 5 times [2018-07-24 10:52:30,508 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:30,508 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:30,508 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:30,509 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:30,509 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:30,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:30,683 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,684 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:30,684 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:30,693 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:30,693 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:30,715 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:52:30,715 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:30,717 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:30,734 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,734 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:30,898 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:30,926 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:30,926 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:30,942 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:30,942 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:30,982 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 6 check-sat command(s) [2018-07-24 10:52:30,982 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:30,985 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:31,008 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:31,009 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:31,017 INFO L134 CoverageAnalysis]: Checked inductivity of 30 backedges. 0 proven. 30 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:31,019 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:31,020 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:52:31,020 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:31,020 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:52:31,021 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:52:31,021 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:31,022 INFO L87 Difference]: Start difference. First operand 22 states and 22 transitions. Second operand 8 states. [2018-07-24 10:52:31,114 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:31,114 INFO L93 Difference]: Finished difference Result 29 states and 29 transitions. [2018-07-24 10:52:31,118 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 10:52:31,118 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 21 [2018-07-24 10:52:31,118 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:31,118 INFO L225 Difference]: With dead ends: 29 [2018-07-24 10:52:31,119 INFO L226 Difference]: Without dead ends: 24 [2018-07-24 10:52:31,119 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 91 GetRequests, 76 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:31,119 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 24 states. [2018-07-24 10:52:31,122 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 24 to 24. [2018-07-24 10:52:31,123 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:52:31,124 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 24 transitions. [2018-07-24 10:52:31,124 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 24 transitions. Word has length 21 [2018-07-24 10:52:31,124 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:31,124 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 24 transitions. [2018-07-24 10:52:31,124 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:52:31,124 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 24 transitions. [2018-07-24 10:52:31,125 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:52:31,125 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:31,125 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:31,126 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:31,126 INFO L82 PathProgramCache]: Analyzing trace with hash 947930356, now seen corresponding path program 6 times [2018-07-24 10:52:31,126 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:31,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:31,127 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:31,127 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:31,127 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:31,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:31,401 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:31,401 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:31,401 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:31,414 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:31,415 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:52:43,461 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:52:43,461 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:43,463 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:43,485 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:43,485 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:43,683 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:43,705 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:43,706 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:43,721 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:52:43,721 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:52:43,788 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 7 check-sat command(s) [2018-07-24 10:52:43,789 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:43,792 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:43,809 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:43,809 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:43,826 INFO L134 CoverageAnalysis]: Checked inductivity of 42 backedges. 0 proven. 42 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:43,828 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:43,828 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 9, 9, 9] total 16 [2018-07-24 10:52:43,828 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:43,829 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 10:52:43,829 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 10:52:43,829 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:52:43,829 INFO L87 Difference]: Start difference. First operand 24 states and 24 transitions. Second operand 9 states. [2018-07-24 10:52:43,913 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:43,913 INFO L93 Difference]: Finished difference Result 31 states and 31 transitions. [2018-07-24 10:52:43,917 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:52:43,918 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 23 [2018-07-24 10:52:43,918 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:43,918 INFO L225 Difference]: With dead ends: 31 [2018-07-24 10:52:43,919 INFO L226 Difference]: Without dead ends: 26 [2018-07-24 10:52:43,920 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 100 GetRequests, 83 SyntacticMatches, 3 SemanticMatches, 14 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 7 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=78, Invalid=162, Unknown=0, NotChecked=0, Total=240 [2018-07-24 10:52:43,921 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26 states. [2018-07-24 10:52:43,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26 to 26. [2018-07-24 10:52:43,924 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 26 states. [2018-07-24 10:52:43,925 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26 states to 26 states and 26 transitions. [2018-07-24 10:52:43,925 INFO L78 Accepts]: Start accepts. Automaton has 26 states and 26 transitions. Word has length 23 [2018-07-24 10:52:43,925 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:43,926 INFO L471 AbstractCegarLoop]: Abstraction has 26 states and 26 transitions. [2018-07-24 10:52:43,926 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 10:52:43,926 INFO L276 IsEmpty]: Start isEmpty. Operand 26 states and 26 transitions. [2018-07-24 10:52:43,927 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 26 [2018-07-24 10:52:43,927 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:43,927 INFO L353 BasicCegarLoop]: trace histogram [8, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:43,927 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:43,927 INFO L82 PathProgramCache]: Analyzing trace with hash 1766182618, now seen corresponding path program 7 times [2018-07-24 10:52:43,927 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:43,928 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:43,929 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:43,929 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:43,929 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:43,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:44,134 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,134 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:44,135 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:44,143 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:44,143 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:44,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:44,154 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:44,173 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,173 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:44,535 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,555 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:44,555 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:44,571 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:44,571 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:44,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:44,597 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:44,623 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,623 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:44,630 INFO L134 CoverageAnalysis]: Checked inductivity of 56 backedges. 0 proven. 56 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,632 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:44,632 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 10:52:44,632 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:44,632 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 10:52:44,633 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 10:52:44,633 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:52:44,633 INFO L87 Difference]: Start difference. First operand 26 states and 26 transitions. Second operand 10 states. [2018-07-24 10:52:44,730 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:44,730 INFO L93 Difference]: Finished difference Result 33 states and 33 transitions. [2018-07-24 10:52:44,734 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:52:44,734 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 25 [2018-07-24 10:52:44,734 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:44,734 INFO L225 Difference]: With dead ends: 33 [2018-07-24 10:52:44,735 INFO L226 Difference]: Without dead ends: 28 [2018-07-24 10:52:44,735 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 109 GetRequests, 90 SyntacticMatches, 3 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=97, Invalid=209, Unknown=0, NotChecked=0, Total=306 [2018-07-24 10:52:44,735 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28 states. [2018-07-24 10:52:44,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28 to 28. [2018-07-24 10:52:44,739 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 28 states. [2018-07-24 10:52:44,740 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28 states to 28 states and 28 transitions. [2018-07-24 10:52:44,740 INFO L78 Accepts]: Start accepts. Automaton has 28 states and 28 transitions. Word has length 25 [2018-07-24 10:52:44,740 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:44,741 INFO L471 AbstractCegarLoop]: Abstraction has 28 states and 28 transitions. [2018-07-24 10:52:44,741 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 10:52:44,741 INFO L276 IsEmpty]: Start isEmpty. Operand 28 states and 28 transitions. [2018-07-24 10:52:44,742 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 28 [2018-07-24 10:52:44,742 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:44,742 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:44,742 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:44,742 INFO L82 PathProgramCache]: Analyzing trace with hash 2127591232, now seen corresponding path program 8 times [2018-07-24 10:52:44,743 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:44,743 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:44,744 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:44,744 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:44,744 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:44,754 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:44,903 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,904 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:44,904 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:44,917 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:44,918 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:44,929 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:44,930 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:44,931 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:44,961 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,962 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:45,233 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,254 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:45,254 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:45,271 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:45,271 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:45,296 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:45,296 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:45,300 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:45,366 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,366 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:45,426 INFO L134 CoverageAnalysis]: Checked inductivity of 72 backedges. 0 proven. 72 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,429 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:45,430 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 20 [2018-07-24 10:52:45,430 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:45,434 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:52:45,434 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:52:45,434 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:52:45,435 INFO L87 Difference]: Start difference. First operand 28 states and 28 transitions. Second operand 11 states. [2018-07-24 10:52:46,121 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:46,121 INFO L93 Difference]: Finished difference Result 35 states and 35 transitions. [2018-07-24 10:52:46,122 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:52:46,122 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 27 [2018-07-24 10:52:46,123 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:46,123 INFO L225 Difference]: With dead ends: 35 [2018-07-24 10:52:46,123 INFO L226 Difference]: Without dead ends: 30 [2018-07-24 10:52:46,124 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 118 GetRequests, 97 SyntacticMatches, 3 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 9 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=118, Invalid=262, Unknown=0, NotChecked=0, Total=380 [2018-07-24 10:52:46,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2018-07-24 10:52:46,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2018-07-24 10:52:46,127 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:52:46,128 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 30 transitions. [2018-07-24 10:52:46,128 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 30 transitions. Word has length 27 [2018-07-24 10:52:46,129 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:46,129 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 30 transitions. [2018-07-24 10:52:46,129 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:52:46,129 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 30 transitions. [2018-07-24 10:52:46,130 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:52:46,130 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:46,130 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:46,130 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:46,131 INFO L82 PathProgramCache]: Analyzing trace with hash 1548918310, now seen corresponding path program 9 times [2018-07-24 10:52:46,131 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:46,131 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,132 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:46,132 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,132 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:46,142 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:46,508 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,508 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:46,508 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:46,516 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:46,516 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:46,564 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:52:46,564 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:46,566 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,591 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,591 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:47,000 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,021 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:47,021 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:47,037 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:47,037 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:47,146 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 10 check-sat command(s) [2018-07-24 10:52:47,146 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:47,150 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:47,165 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,166 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:47,180 INFO L134 CoverageAnalysis]: Checked inductivity of 90 backedges. 0 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,181 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:47,182 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 22 [2018-07-24 10:52:47,182 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:47,182 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:52:47,183 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:52:47,183 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:52:47,184 INFO L87 Difference]: Start difference. First operand 30 states and 30 transitions. Second operand 12 states. [2018-07-24 10:52:47,375 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:47,375 INFO L93 Difference]: Finished difference Result 37 states and 37 transitions. [2018-07-24 10:52:47,377 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:52:47,377 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 29 [2018-07-24 10:52:47,377 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:47,378 INFO L225 Difference]: With dead ends: 37 [2018-07-24 10:52:47,378 INFO L226 Difference]: Without dead ends: 32 [2018-07-24 10:52:47,379 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 127 GetRequests, 104 SyntacticMatches, 3 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 10 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=141, Invalid=321, Unknown=0, NotChecked=0, Total=462 [2018-07-24 10:52:47,379 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32 states. [2018-07-24 10:52:47,382 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32 to 32. [2018-07-24 10:52:47,383 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 32 states. [2018-07-24 10:52:47,383 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32 states to 32 states and 32 transitions. [2018-07-24 10:52:47,383 INFO L78 Accepts]: Start accepts. Automaton has 32 states and 32 transitions. Word has length 29 [2018-07-24 10:52:47,384 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:47,384 INFO L471 AbstractCegarLoop]: Abstraction has 32 states and 32 transitions. [2018-07-24 10:52:47,384 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:52:47,384 INFO L276 IsEmpty]: Start isEmpty. Operand 32 states and 32 transitions. [2018-07-24 10:52:47,385 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-07-24 10:52:47,385 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:47,385 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:47,385 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:47,386 INFO L82 PathProgramCache]: Analyzing trace with hash -504978548, now seen corresponding path program 10 times [2018-07-24 10:52:47,386 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:47,386 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:47,387 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:47,387 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:47,387 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:47,396 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:47,596 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,597 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:47,597 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:47,605 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:47,605 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:47,616 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:47,617 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:47,618 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:47,645 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,645 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:48,066 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,087 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:48,087 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:48,104 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:48,104 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:48,137 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:48,137 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:48,140 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:48,171 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,171 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:48,203 INFO L134 CoverageAnalysis]: Checked inductivity of 110 backedges. 0 proven. 110 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,205 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:48,205 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 24 [2018-07-24 10:52:48,205 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:48,205 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 10:52:48,206 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 10:52:48,206 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:52:48,206 INFO L87 Difference]: Start difference. First operand 32 states and 32 transitions. Second operand 13 states. [2018-07-24 10:52:48,393 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:48,393 INFO L93 Difference]: Finished difference Result 39 states and 39 transitions. [2018-07-24 10:52:48,394 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:52:48,394 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 31 [2018-07-24 10:52:48,394 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:48,395 INFO L225 Difference]: With dead ends: 39 [2018-07-24 10:52:48,395 INFO L226 Difference]: Without dead ends: 34 [2018-07-24 10:52:48,397 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 136 GetRequests, 111 SyntacticMatches, 3 SemanticMatches, 22 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=166, Invalid=386, Unknown=0, NotChecked=0, Total=552 [2018-07-24 10:52:48,397 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34 states. [2018-07-24 10:52:48,400 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34 to 34. [2018-07-24 10:52:48,401 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 34 states. [2018-07-24 10:52:48,401 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 34 states to 34 states and 34 transitions. [2018-07-24 10:52:48,401 INFO L78 Accepts]: Start accepts. Automaton has 34 states and 34 transitions. Word has length 31 [2018-07-24 10:52:48,402 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:48,402 INFO L471 AbstractCegarLoop]: Abstraction has 34 states and 34 transitions. [2018-07-24 10:52:48,402 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 10:52:48,402 INFO L276 IsEmpty]: Start isEmpty. Operand 34 states and 34 transitions. [2018-07-24 10:52:48,403 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 34 [2018-07-24 10:52:48,403 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:48,403 INFO L353 BasicCegarLoop]: trace histogram [12, 11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:48,403 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:48,403 INFO L82 PathProgramCache]: Analyzing trace with hash 1385097074, now seen corresponding path program 11 times [2018-07-24 10:52:48,404 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:48,404 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,405 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:48,405 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,405 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:48,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:48,978 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,978 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:48,978 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:48,985 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:48,985 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:53,313 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:53:53,313 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:55,887 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:55,897 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:55,897 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:56,359 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,362 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:56,362 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:56,378 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:56,378 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:56,508 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 12 check-sat command(s) [2018-07-24 10:53:56,509 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:56,512 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:56,525 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,526 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:56,568 INFO L134 CoverageAnalysis]: Checked inductivity of 132 backedges. 0 proven. 132 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:56,570 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:56,570 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 26 [2018-07-24 10:53:56,570 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:56,571 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 10:53:56,571 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 10:53:56,571 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:53:56,572 INFO L87 Difference]: Start difference. First operand 34 states and 34 transitions. Second operand 14 states. [2018-07-24 10:53:56,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:56,761 INFO L93 Difference]: Finished difference Result 41 states and 41 transitions. [2018-07-24 10:53:56,764 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 10:53:56,764 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 33 [2018-07-24 10:53:56,765 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:56,765 INFO L225 Difference]: With dead ends: 41 [2018-07-24 10:53:56,765 INFO L226 Difference]: Without dead ends: 36 [2018-07-24 10:53:56,766 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 145 GetRequests, 118 SyntacticMatches, 3 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 12 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=193, Invalid=457, Unknown=0, NotChecked=0, Total=650 [2018-07-24 10:53:56,766 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36 states. [2018-07-24 10:53:56,769 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36 to 36. [2018-07-24 10:53:56,770 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:53:56,770 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 36 transitions. [2018-07-24 10:53:56,770 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 36 transitions. Word has length 33 [2018-07-24 10:53:56,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:56,771 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 36 transitions. [2018-07-24 10:53:56,771 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 10:53:56,771 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 36 transitions. [2018-07-24 10:53:56,771 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:53:56,771 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:56,772 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:56,772 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:56,772 INFO L82 PathProgramCache]: Analyzing trace with hash 976603608, now seen corresponding path program 12 times [2018-07-24 10:53:56,772 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:56,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:56,773 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:56,773 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:56,773 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:56,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:57,092 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:57,092 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:57,092 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:57,100 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:57,101 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:20,546 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:54:20,546 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:20,561 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:20,587 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:20,587 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:21,055 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:21,076 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:21,076 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:21,092 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:54:21,092 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:54:21,278 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 13 check-sat command(s) [2018-07-24 10:54:21,278 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:21,281 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:21,294 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:21,294 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:21,305 INFO L134 CoverageAnalysis]: Checked inductivity of 156 backedges. 0 proven. 156 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:21,307 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:21,307 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 15, 15, 15, 15] total 28 [2018-07-24 10:54:21,307 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:21,307 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:54:21,308 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:54:21,308 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:54:21,308 INFO L87 Difference]: Start difference. First operand 36 states and 36 transitions. Second operand 15 states. [2018-07-24 10:54:21,505 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:21,506 INFO L93 Difference]: Finished difference Result 43 states and 43 transitions. [2018-07-24 10:54:21,506 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:54:21,507 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 35 [2018-07-24 10:54:21,507 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:21,508 INFO L225 Difference]: With dead ends: 43 [2018-07-24 10:54:21,508 INFO L226 Difference]: Without dead ends: 38 [2018-07-24 10:54:21,508 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 154 GetRequests, 125 SyntacticMatches, 3 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 13 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=222, Invalid=534, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:54:21,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38 states. [2018-07-24 10:54:21,512 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38 to 38. [2018-07-24 10:54:21,512 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 38 states. [2018-07-24 10:54:21,512 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38 states to 38 states and 38 transitions. [2018-07-24 10:54:21,513 INFO L78 Accepts]: Start accepts. Automaton has 38 states and 38 transitions. Word has length 35 [2018-07-24 10:54:21,513 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:21,513 INFO L471 AbstractCegarLoop]: Abstraction has 38 states and 38 transitions. [2018-07-24 10:54:21,513 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:54:21,513 INFO L276 IsEmpty]: Start isEmpty. Operand 38 states and 38 transitions. [2018-07-24 10:54:21,514 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 38 [2018-07-24 10:54:21,514 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:21,514 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:21,514 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:21,515 INFO L82 PathProgramCache]: Analyzing trace with hash -743593282, now seen corresponding path program 13 times [2018-07-24 10:54:21,515 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:21,515 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:21,516 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:21,516 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:21,516 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:21,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:21,950 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:21,950 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:21,950 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:21,958 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:21,959 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:21,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:21,972 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:21,982 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:21,983 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:22,512 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:22,533 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:22,533 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:22,554 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:22,554 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:54:22,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:22,594 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:22,653 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:22,654 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:22,713 INFO L134 CoverageAnalysis]: Checked inductivity of 182 backedges. 0 proven. 182 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:22,714 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:22,714 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:54:22,714 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:22,715 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:54:22,715 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:54:22,716 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:54:22,716 INFO L87 Difference]: Start difference. First operand 38 states and 38 transitions. Second operand 16 states. [2018-07-24 10:54:22,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:22,952 INFO L93 Difference]: Finished difference Result 45 states and 45 transitions. [2018-07-24 10:54:22,952 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:54:22,953 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 37 [2018-07-24 10:54:22,953 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:22,953 INFO L225 Difference]: With dead ends: 45 [2018-07-24 10:54:22,954 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:54:22,954 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 132 SyntacticMatches, 3 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:54:22,954 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:54:22,958 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 40. [2018-07-24 10:54:22,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 40 states. [2018-07-24 10:54:22,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40 states to 40 states and 40 transitions. [2018-07-24 10:54:22,959 INFO L78 Accepts]: Start accepts. Automaton has 40 states and 40 transitions. Word has length 37 [2018-07-24 10:54:22,959 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:22,959 INFO L471 AbstractCegarLoop]: Abstraction has 40 states and 40 transitions. [2018-07-24 10:54:22,959 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:54:22,959 INFO L276 IsEmpty]: Start isEmpty. Operand 40 states and 40 transitions. [2018-07-24 10:54:22,960 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 40 [2018-07-24 10:54:22,960 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:22,960 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:22,960 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:22,960 INFO L82 PathProgramCache]: Analyzing trace with hash -290395612, now seen corresponding path program 14 times [2018-07-24 10:54:22,960 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:22,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:22,961 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:54:22,961 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:22,962 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:22,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:23,322 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:23,322 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:23,322 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:23,333 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:23,333 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:23,346 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:23,346 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:23,347 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:23,377 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:23,377 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:23,991 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:24,011 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:24,011 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:24,027 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:54:24,027 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:54:24,060 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:54:24,060 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:24,064 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:24,091 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:24,091 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:24,105 INFO L134 CoverageAnalysis]: Checked inductivity of 210 backedges. 0 proven. 210 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:24,107 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:24,107 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 17, 17, 17, 17] total 32 [2018-07-24 10:54:24,107 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:24,108 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 10:54:24,108 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 10:54:24,109 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:24,109 INFO L87 Difference]: Start difference. First operand 40 states and 40 transitions. Second operand 17 states. [2018-07-24 10:54:24,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:24,284 INFO L93 Difference]: Finished difference Result 47 states and 47 transitions. [2018-07-24 10:54:24,284 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 17 states. [2018-07-24 10:54:24,284 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 39 [2018-07-24 10:54:24,285 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:24,285 INFO L225 Difference]: With dead ends: 47 [2018-07-24 10:54:24,285 INFO L226 Difference]: Without dead ends: 42 [2018-07-24 10:54:24,286 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 172 GetRequests, 139 SyntacticMatches, 3 SemanticMatches, 30 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 15 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=286, Invalid=706, Unknown=0, NotChecked=0, Total=992 [2018-07-24 10:54:24,286 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-07-24 10:54:24,289 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2018-07-24 10:54:24,290 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:54:24,290 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 42 transitions. [2018-07-24 10:54:24,290 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 42 transitions. Word has length 39 [2018-07-24 10:54:24,291 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:24,291 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 42 transitions. [2018-07-24 10:54:24,291 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 10:54:24,291 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 42 transitions. [2018-07-24 10:54:24,291 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:54:24,292 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:24,292 INFO L353 BasicCegarLoop]: trace histogram [16, 15, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:24,292 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:24,292 INFO L82 PathProgramCache]: Analyzing trace with hash 1440868362, now seen corresponding path program 15 times [2018-07-24 10:54:24,292 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:24,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:24,293 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:24,293 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:24,293 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:24,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:25,161 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:25,162 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:25,162 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:25,171 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:25,171 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:51,768 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:54:51,768 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:51,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:51,955 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:51,955 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:52,593 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:52,597 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:52,597 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:52,613 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:54:52,613 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:54:52,863 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 16 check-sat command(s) [2018-07-24 10:54:52,863 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:52,867 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:52,894 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:52,895 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:52,939 INFO L134 CoverageAnalysis]: Checked inductivity of 240 backedges. 0 proven. 240 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:52,943 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:52,943 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 34 [2018-07-24 10:54:52,943 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:52,944 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 10:54:52,944 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 10:54:52,945 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:52,945 INFO L87 Difference]: Start difference. First operand 42 states and 42 transitions. Second operand 18 states. [2018-07-24 10:54:53,227 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:53,228 INFO L93 Difference]: Finished difference Result 49 states and 49 transitions. [2018-07-24 10:54:53,228 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:54:53,228 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 41 [2018-07-24 10:54:53,229 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:53,229 INFO L225 Difference]: With dead ends: 49 [2018-07-24 10:54:53,229 INFO L226 Difference]: Without dead ends: 44 [2018-07-24 10:54:53,230 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 181 GetRequests, 146 SyntacticMatches, 3 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=321, Invalid=801, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 10:54:53,230 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44 states. [2018-07-24 10:54:53,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44 to 44. [2018-07-24 10:54:53,234 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 44 states. [2018-07-24 10:54:53,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 44 states to 44 states and 44 transitions. [2018-07-24 10:54:53,235 INFO L78 Accepts]: Start accepts. Automaton has 44 states and 44 transitions. Word has length 41 [2018-07-24 10:54:53,235 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:53,235 INFO L471 AbstractCegarLoop]: Abstraction has 44 states and 44 transitions. [2018-07-24 10:54:53,235 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 10:54:53,235 INFO L276 IsEmpty]: Start isEmpty. Operand 44 states and 44 transitions. [2018-07-24 10:54:53,236 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 44 [2018-07-24 10:54:53,236 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:53,236 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:53,236 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:53,237 INFO L82 PathProgramCache]: Analyzing trace with hash -1261763472, now seen corresponding path program 16 times [2018-07-24 10:54:53,237 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:53,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:53,238 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:53,238 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:53,238 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:53,245 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:53,531 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:53,531 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:53,531 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:53,538 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:53,539 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:53,556 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:53,557 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:53,559 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:53,627 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:53,627 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,434 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:54,455 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:54,456 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:54:54,470 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:54:54,471 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:54:54,505 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:54:54,505 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:54:54,508 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:54:54,540 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:54,541 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:54:54,594 INFO L134 CoverageAnalysis]: Checked inductivity of 272 backedges. 0 proven. 272 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:54,595 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:54:54,596 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 19, 19, 19, 19] total 36 [2018-07-24 10:54:54,596 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:54:54,596 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:54:54,597 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:54:54,597 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:54:54,597 INFO L87 Difference]: Start difference. First operand 44 states and 44 transitions. Second operand 19 states. [2018-07-24 10:54:54,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:54:54,872 INFO L93 Difference]: Finished difference Result 51 states and 51 transitions. [2018-07-24 10:54:54,872 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:54:54,872 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 43 [2018-07-24 10:54:54,873 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:54:54,873 INFO L225 Difference]: With dead ends: 51 [2018-07-24 10:54:54,873 INFO L226 Difference]: Without dead ends: 46 [2018-07-24 10:54:54,874 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 190 GetRequests, 153 SyntacticMatches, 3 SemanticMatches, 34 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=358, Invalid=902, Unknown=0, NotChecked=0, Total=1260 [2018-07-24 10:54:54,874 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 46 states. [2018-07-24 10:54:54,878 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 46 to 46. [2018-07-24 10:54:54,879 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 46 states. [2018-07-24 10:54:54,879 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46 states to 46 states and 46 transitions. [2018-07-24 10:54:54,879 INFO L78 Accepts]: Start accepts. Automaton has 46 states and 46 transitions. Word has length 43 [2018-07-24 10:54:54,880 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:54:54,880 INFO L471 AbstractCegarLoop]: Abstraction has 46 states and 46 transitions. [2018-07-24 10:54:54,880 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:54:54,880 INFO L276 IsEmpty]: Start isEmpty. Operand 46 states and 46 transitions. [2018-07-24 10:54:54,880 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-07-24 10:54:54,881 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:54:54,881 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:54:54,881 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:54:54,881 INFO L82 PathProgramCache]: Analyzing trace with hash -35741866, now seen corresponding path program 17 times [2018-07-24 10:54:54,881 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:54:54,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:54,882 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:54:54,882 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:54:54,882 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:54:54,889 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:54:55,191 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:54:55,191 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:54:55,191 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:54:55,198 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:54:55,198 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:58,680 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:56:58,680 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:59,106 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:59,114 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:59,114 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:59,867 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:59,889 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:59,889 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:59,906 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:59,906 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:57:00,240 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:57:00,240 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:57:00,244 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:57:00,289 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:00,290 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:57:00,344 INFO L134 CoverageAnalysis]: Checked inductivity of 306 backedges. 0 proven. 306 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:00,345 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:57:00,345 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 20, 20] total 38 [2018-07-24 10:57:00,345 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:57:00,346 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:57:00,347 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:57:00,347 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:57:00,347 INFO L87 Difference]: Start difference. First operand 46 states and 46 transitions. Second operand 20 states. [2018-07-24 10:57:01,004 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:57:01,005 INFO L93 Difference]: Finished difference Result 53 states and 53 transitions. [2018-07-24 10:57:01,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 10:57:01,005 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 45 [2018-07-24 10:57:01,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:57:01,006 INFO L225 Difference]: With dead ends: 53 [2018-07-24 10:57:01,006 INFO L226 Difference]: Without dead ends: 48 [2018-07-24 10:57:01,007 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 199 GetRequests, 160 SyntacticMatches, 3 SemanticMatches, 36 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 18 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=397, Invalid=1009, Unknown=0, NotChecked=0, Total=1406 [2018-07-24 10:57:01,008 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48 states. [2018-07-24 10:57:01,011 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48 to 48. [2018-07-24 10:57:01,011 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:57:01,011 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 48 transitions. [2018-07-24 10:57:01,012 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 48 transitions. Word has length 45 [2018-07-24 10:57:01,012 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:57:01,012 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 48 transitions. [2018-07-24 10:57:01,012 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:57:01,012 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 48 transitions. [2018-07-24 10:57:01,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-24 10:57:01,013 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:57:01,013 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:57:01,013 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_overflow_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:57:01,013 INFO L82 PathProgramCache]: Analyzing trace with hash 1349982396, now seen corresponding path program 18 times [2018-07-24 10:57:01,013 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:57:01,014 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:01,014 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:57:01,014 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:57:01,014 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:57:01,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:57:01,336 INFO L134 CoverageAnalysis]: Checked inductivity of 342 backedges. 0 proven. 342 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:57:01,337 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:57:01,337 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:57:01,344 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:57:01,344 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown