java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/loop-acceleration/phases_true-unreach-call1.i -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 10:52:43,261 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 10:52:43,262 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 10:52:43,274 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 10:52:43,274 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 10:52:43,275 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 10:52:43,277 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 10:52:43,279 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 10:52:43,280 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 10:52:43,281 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 10:52:43,282 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 10:52:43,282 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 10:52:43,283 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 10:52:43,284 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 10:52:43,285 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 10:52:43,286 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 10:52:43,287 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 10:52:43,289 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 10:52:43,291 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 10:52:43,292 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 10:52:43,293 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 10:52:43,294 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 10:52:43,297 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 10:52:43,297 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 10:52:43,297 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 10:52:43,298 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 10:52:43,299 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 10:52:43,300 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 10:52:43,301 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 10:52:43,302 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 10:52:43,302 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 10:52:43,303 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 10:52:43,303 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 10:52:43,303 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 10:52:43,304 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 10:52:43,305 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 10:52:43,305 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 10:52:43,334 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 10:52:43,334 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 10:52:43,335 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 10:52:43,335 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 10:52:43,336 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 10:52:43,336 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 10:52:43,336 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 10:52:43,337 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 10:52:43,337 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 10:52:43,337 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 10:52:43,337 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 10:52:43,338 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 10:52:43,338 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 10:52:43,338 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 10:52:43,339 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 10:52:43,339 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 10:52:43,339 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 10:52:43,339 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 10:52:43,340 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 10:52:43,340 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 10:52:43,341 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 10:52:43,341 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 10:52:43,341 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 10:52:43,341 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:52:43,341 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 10:52:43,342 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 10:52:43,342 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 10:52:43,342 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 10:52:43,342 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 10:52:43,343 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 10:52:43,343 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 10:52:43,343 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 10:52:43,343 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 10:52:43,407 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 10:52:43,424 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 10:52:43,432 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 10:52:43,433 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 10:52:43,434 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 10:52:43,434 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/loop-acceleration/phases_true-unreach-call1.i [2018-07-24 10:52:43,786 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1c77085f1/8a5b5724bcfd4df483a78fdf1fb85d15/FLAGd2ae3b5cb [2018-07-24 10:52:43,928 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 10:52:43,929 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/loop-acceleration/phases_true-unreach-call1.i [2018-07-24 10:52:43,934 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1c77085f1/8a5b5724bcfd4df483a78fdf1fb85d15/FLAGd2ae3b5cb [2018-07-24 10:52:43,948 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/1c77085f1/8a5b5724bcfd4df483a78fdf1fb85d15 [2018-07-24 10:52:43,956 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 10:52:43,958 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 10:52:43,959 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 10:52:43,959 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 10:52:43,965 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 10:52:43,966 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:52:43" (1/1) ... [2018-07-24 10:52:43,970 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@5fec139b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:43, skipping insertion in model container [2018-07-24 10:52:43,971 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 10:52:43" (1/1) ... [2018-07-24 10:52:44,154 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 10:52:44,200 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:52:44,215 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 10:52:44,219 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 10:52:44,231 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44 WrapperNode [2018-07-24 10:52:44,232 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 10:52:44,233 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 10:52:44,233 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 10:52:44,233 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 10:52:44,242 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,248 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,254 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 10:52:44,254 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 10:52:44,254 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 10:52:44,255 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 10:52:44,264 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,264 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,265 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,265 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,267 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,272 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,273 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... [2018-07-24 10:52:44,275 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 10:52:44,275 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 10:52:44,275 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 10:52:44,275 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 10:52:44,276 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 10:52:44,343 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 10:52:44,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 10:52:44,344 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 10:52:44,344 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 10:52:44,344 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 10:52:44,344 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 10:52:44,344 INFO L130 BoogieDeclarations]: Found specification of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assert [2018-07-24 10:52:44,345 INFO L138 BoogieDeclarations]: Found implementation of procedure __U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assert [2018-07-24 10:52:44,616 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 10:52:44,617 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:52:44 BoogieIcfgContainer [2018-07-24 10:52:44,617 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 10:52:44,618 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 10:52:44,618 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 10:52:44,621 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 10:52:44,621 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 10:52:43" (1/3) ... [2018-07-24 10:52:44,622 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ae07390 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:52:44, skipping insertion in model container [2018-07-24 10:52:44,622 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 10:52:44" (2/3) ... [2018-07-24 10:52:44,623 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@3ae07390 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 10:52:44, skipping insertion in model container [2018-07-24 10:52:44,623 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 10:52:44" (3/3) ... [2018-07-24 10:52:44,625 INFO L112 eAbstractionObserver]: Analyzing ICFG phases_true-unreach-call1.i [2018-07-24 10:52:44,633 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 10:52:44,639 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 10:52:44,683 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 10:52:44,683 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 10:52:44,684 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 10:52:44,684 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 10:52:44,684 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 10:52:44,684 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 10:52:44,684 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 10:52:44,684 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 10:52:44,684 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 10:52:44,702 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states. [2018-07-24 10:52:44,708 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 11 [2018-07-24 10:52:44,708 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:44,709 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:44,709 INFO L414 AbstractCegarLoop]: === Iteration 1 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:44,714 INFO L82 PathProgramCache]: Analyzing trace with hash 1713253442, now seen corresponding path program 1 times [2018-07-24 10:52:44,717 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:44,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:44,768 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:44,768 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:44,768 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:44,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:44,823 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:44,825 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:52:44,825 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2018-07-24 10:52:44,825 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:44,829 INFO L450 AbstractCegarLoop]: Interpolant automaton has 2 states [2018-07-24 10:52:44,843 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2018-07-24 10:52:44,843 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:52:44,846 INFO L87 Difference]: Start difference. First operand 19 states. Second operand 2 states. [2018-07-24 10:52:44,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:44,868 INFO L93 Difference]: Finished difference Result 30 states and 34 transitions. [2018-07-24 10:52:44,868 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2018-07-24 10:52:44,869 INFO L78 Accepts]: Start accepts. Automaton has 2 states. Word has length 10 [2018-07-24 10:52:44,870 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:44,878 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:52:44,878 INFO L226 Difference]: Without dead ends: 13 [2018-07-24 10:52:44,882 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 2 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 0 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2018-07-24 10:52:44,900 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13 states. [2018-07-24 10:52:44,916 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13 to 13. [2018-07-24 10:52:44,917 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 13 states. [2018-07-24 10:52:44,918 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13 states to 13 states and 14 transitions. [2018-07-24 10:52:44,920 INFO L78 Accepts]: Start accepts. Automaton has 13 states and 14 transitions. Word has length 10 [2018-07-24 10:52:44,920 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:44,920 INFO L471 AbstractCegarLoop]: Abstraction has 13 states and 14 transitions. [2018-07-24 10:52:44,921 INFO L472 AbstractCegarLoop]: Interpolant automaton has 2 states. [2018-07-24 10:52:44,921 INFO L276 IsEmpty]: Start isEmpty. Operand 13 states and 14 transitions. [2018-07-24 10:52:44,921 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 12 [2018-07-24 10:52:44,922 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:44,922 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:44,922 INFO L414 AbstractCegarLoop]: === Iteration 2 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:44,922 INFO L82 PathProgramCache]: Analyzing trace with hash 1144102878, now seen corresponding path program 1 times [2018-07-24 10:52:44,923 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:44,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:44,924 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:44,924 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:44,924 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:44,948 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:45,101 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,103 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 10:52:45,104 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 10:52:45,104 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:45,108 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:52:45,108 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:52:45,109 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:52:45,109 INFO L87 Difference]: Start difference. First operand 13 states and 14 transitions. Second operand 3 states. [2018-07-24 10:52:45,175 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:45,175 INFO L93 Difference]: Finished difference Result 24 states and 28 transitions. [2018-07-24 10:52:45,176 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:52:45,176 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 11 [2018-07-24 10:52:45,176 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:45,177 INFO L225 Difference]: With dead ends: 24 [2018-07-24 10:52:45,177 INFO L226 Difference]: Without dead ends: 16 [2018-07-24 10:52:45,178 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 4 GetRequests, 2 SyntacticMatches, 1 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 10:52:45,178 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16 states. [2018-07-24 10:52:45,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16 to 16. [2018-07-24 10:52:45,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 16 states. [2018-07-24 10:52:45,185 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16 states to 16 states and 17 transitions. [2018-07-24 10:52:45,186 INFO L78 Accepts]: Start accepts. Automaton has 16 states and 17 transitions. Word has length 11 [2018-07-24 10:52:45,186 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:45,186 INFO L471 AbstractCegarLoop]: Abstraction has 16 states and 17 transitions. [2018-07-24 10:52:45,186 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:52:45,186 INFO L276 IsEmpty]: Start isEmpty. Operand 16 states and 17 transitions. [2018-07-24 10:52:45,187 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 10:52:45,188 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:45,188 INFO L353 BasicCegarLoop]: trace histogram [2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:45,189 INFO L414 AbstractCegarLoop]: === Iteration 3 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:45,189 INFO L82 PathProgramCache]: Analyzing trace with hash -2056921797, now seen corresponding path program 1 times [2018-07-24 10:52:45,189 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:45,190 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:45,190 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:45,191 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:45,191 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:45,203 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:45,338 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,338 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:45,338 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:45,352 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:45,352 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:45,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:45,387 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:45,432 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,433 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:45,517 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,540 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:45,540 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:45,558 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:45,559 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:45,575 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:45,579 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:45,604 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,605 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:45,660 INFO L134 CoverageAnalysis]: Checked inductivity of 2 backedges. 0 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,666 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:45,666 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 6 [2018-07-24 10:52:45,666 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:45,667 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 10:52:45,667 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 10:52:45,668 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:52:45,668 INFO L87 Difference]: Start difference. First operand 16 states and 17 transitions. Second operand 4 states. [2018-07-24 10:52:45,759 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:45,760 INFO L93 Difference]: Finished difference Result 27 states and 31 transitions. [2018-07-24 10:52:45,761 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 10:52:45,761 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 14 [2018-07-24 10:52:45,762 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:45,762 INFO L225 Difference]: With dead ends: 27 [2018-07-24 10:52:45,763 INFO L226 Difference]: Without dead ends: 19 [2018-07-24 10:52:45,763 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 52 SyntacticMatches, 3 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=13, Invalid=17, Unknown=0, NotChecked=0, Total=30 [2018-07-24 10:52:45,764 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19 states. [2018-07-24 10:52:45,767 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19 to 19. [2018-07-24 10:52:45,768 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 19 states. [2018-07-24 10:52:45,769 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 19 states to 19 states and 20 transitions. [2018-07-24 10:52:45,770 INFO L78 Accepts]: Start accepts. Automaton has 19 states and 20 transitions. Word has length 14 [2018-07-24 10:52:45,770 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:45,770 INFO L471 AbstractCegarLoop]: Abstraction has 19 states and 20 transitions. [2018-07-24 10:52:45,770 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 10:52:45,771 INFO L276 IsEmpty]: Start isEmpty. Operand 19 states and 20 transitions. [2018-07-24 10:52:45,772 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 18 [2018-07-24 10:52:45,772 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:45,772 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:45,773 INFO L414 AbstractCegarLoop]: === Iteration 4 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:45,773 INFO L82 PathProgramCache]: Analyzing trace with hash 1670825662, now seen corresponding path program 2 times [2018-07-24 10:52:45,773 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:45,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:45,775 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:45,775 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:45,775 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:45,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:45,912 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:45,912 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:45,912 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:45,933 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:45,934 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:45,977 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:45,978 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:45,981 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,060 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,060 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:46,166 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,189 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:46,189 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:46,204 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:46,204 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:46,225 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:46,225 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:46,228 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,270 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,270 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:46,316 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 0 proven. 7 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,318 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:46,318 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 10:52:46,318 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:46,319 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 10:52:46,319 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 10:52:46,320 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:46,320 INFO L87 Difference]: Start difference. First operand 19 states and 20 transitions. Second operand 5 states. [2018-07-24 10:52:46,369 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:46,370 INFO L93 Difference]: Finished difference Result 30 states and 34 transitions. [2018-07-24 10:52:46,370 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 10:52:46,371 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 17 [2018-07-24 10:52:46,371 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:46,372 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:52:46,372 INFO L226 Difference]: Without dead ends: 22 [2018-07-24 10:52:46,373 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 72 GetRequests, 63 SyntacticMatches, 3 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 3 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=22, Invalid=34, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:46,373 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 22 states. [2018-07-24 10:52:46,376 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 22 to 22. [2018-07-24 10:52:46,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 22 states. [2018-07-24 10:52:46,378 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22 states to 22 states and 23 transitions. [2018-07-24 10:52:46,378 INFO L78 Accepts]: Start accepts. Automaton has 22 states and 23 transitions. Word has length 17 [2018-07-24 10:52:46,378 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:46,378 INFO L471 AbstractCegarLoop]: Abstraction has 22 states and 23 transitions. [2018-07-24 10:52:46,378 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 10:52:46,378 INFO L276 IsEmpty]: Start isEmpty. Operand 22 states and 23 transitions. [2018-07-24 10:52:46,379 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 21 [2018-07-24 10:52:46,379 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:46,379 INFO L353 BasicCegarLoop]: trace histogram [4, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:46,379 INFO L414 AbstractCegarLoop]: === Iteration 5 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:46,380 INFO L82 PathProgramCache]: Analyzing trace with hash 26004059, now seen corresponding path program 3 times [2018-07-24 10:52:46,380 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:46,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,381 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:46,381 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,381 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:46,392 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:46,594 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 0 proven. 15 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,595 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:46,595 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:46,604 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:46,604 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:46,613 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 2 check-sat command(s) [2018-07-24 10:52:46,613 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:46,614 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,639 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-07-24 10:52:46,640 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:46,665 INFO L134 CoverageAnalysis]: Checked inductivity of 15 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 9 trivial. 0 not checked. [2018-07-24 10:52:46,686 INFO L309 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-07-24 10:52:46,687 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [6] total 8 [2018-07-24 10:52:46,687 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 10:52:46,687 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 10:52:46,688 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 10:52:46,688 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:46,688 INFO L87 Difference]: Start difference. First operand 22 states and 23 transitions. Second operand 3 states. [2018-07-24 10:52:46,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:46,725 INFO L93 Difference]: Finished difference Result 30 states and 32 transitions. [2018-07-24 10:52:46,726 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 10:52:46,726 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 20 [2018-07-24 10:52:46,726 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:46,727 INFO L225 Difference]: With dead ends: 30 [2018-07-24 10:52:46,727 INFO L226 Difference]: Without dead ends: 25 [2018-07-24 10:52:46,727 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 46 GetRequests, 39 SyntacticMatches, 1 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=21, Invalid=35, Unknown=0, NotChecked=0, Total=56 [2018-07-24 10:52:46,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25 states. [2018-07-24 10:52:46,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25 to 24. [2018-07-24 10:52:46,731 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 24 states. [2018-07-24 10:52:46,732 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24 states to 24 states and 25 transitions. [2018-07-24 10:52:46,732 INFO L78 Accepts]: Start accepts. Automaton has 24 states and 25 transitions. Word has length 20 [2018-07-24 10:52:46,733 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:46,733 INFO L471 AbstractCegarLoop]: Abstraction has 24 states and 25 transitions. [2018-07-24 10:52:46,733 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 10:52:46,733 INFO L276 IsEmpty]: Start isEmpty. Operand 24 states and 25 transitions. [2018-07-24 10:52:46,734 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 24 [2018-07-24 10:52:46,734 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:46,734 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:46,734 INFO L414 AbstractCegarLoop]: === Iteration 6 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:46,735 INFO L82 PathProgramCache]: Analyzing trace with hash -2092450784, now seen corresponding path program 1 times [2018-07-24 10:52:46,735 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:46,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,736 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:46,736 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:46,736 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:46,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:46,900 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 0 proven. 26 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,900 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:46,900 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:46,908 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:46,908 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:46,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:46,919 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:46,951 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 8 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:46,952 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:47,326 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 8 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,360 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:47,360 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:47,388 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:47,388 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:52:47,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:47,418 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:47,494 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 8 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,494 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:47,594 INFO L134 CoverageAnalysis]: Checked inductivity of 26 backedges. 8 proven. 18 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,608 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:47,608 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 7, 6, 6] total 15 [2018-07-24 10:52:47,608 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:47,609 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 10:52:47,609 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 10:52:47,610 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=77, Invalid=133, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:52:47,610 INFO L87 Difference]: Start difference. First operand 24 states and 25 transitions. Second operand 7 states. [2018-07-24 10:52:47,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:47,727 INFO L93 Difference]: Finished difference Result 37 states and 40 transitions. [2018-07-24 10:52:47,727 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 10:52:47,728 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 23 [2018-07-24 10:52:47,728 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:47,729 INFO L225 Difference]: With dead ends: 37 [2018-07-24 10:52:47,729 INFO L226 Difference]: Without dead ends: 27 [2018-07-24 10:52:47,730 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 98 GetRequests, 81 SyntacticMatches, 4 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=77, Invalid=133, Unknown=0, NotChecked=0, Total=210 [2018-07-24 10:52:47,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 27 states. [2018-07-24 10:52:47,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 27 to 27. [2018-07-24 10:52:47,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 27 states. [2018-07-24 10:52:47,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27 states to 27 states and 28 transitions. [2018-07-24 10:52:47,735 INFO L78 Accepts]: Start accepts. Automaton has 27 states and 28 transitions. Word has length 23 [2018-07-24 10:52:47,735 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:47,735 INFO L471 AbstractCegarLoop]: Abstraction has 27 states and 28 transitions. [2018-07-24 10:52:47,735 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 10:52:47,735 INFO L276 IsEmpty]: Start isEmpty. Operand 27 states and 28 transitions. [2018-07-24 10:52:47,736 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 27 [2018-07-24 10:52:47,736 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:47,737 INFO L353 BasicCegarLoop]: trace histogram [6, 5, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:47,737 INFO L414 AbstractCegarLoop]: === Iteration 7 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:47,737 INFO L82 PathProgramCache]: Analyzing trace with hash 1956763133, now seen corresponding path program 2 times [2018-07-24 10:52:47,737 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:47,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:47,738 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:52:47,738 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:47,739 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:47,749 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:47,917 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,917 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:47,917 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:47,926 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:47,926 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:47,953 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:47,953 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:47,955 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:47,998 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:47,998 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:48,200 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,221 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:48,221 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:48,236 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:52:48,237 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:52:48,261 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:52:48,261 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:48,264 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:48,294 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,295 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:48,315 INFO L134 CoverageAnalysis]: Checked inductivity of 40 backedges. 0 proven. 40 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,316 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:48,317 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 10:52:48,317 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:48,317 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 10:52:48,317 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 10:52:48,318 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:48,318 INFO L87 Difference]: Start difference. First operand 27 states and 28 transitions. Second operand 8 states. [2018-07-24 10:52:48,436 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:48,437 INFO L93 Difference]: Finished difference Result 40 states and 43 transitions. [2018-07-24 10:52:48,437 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 10:52:48,437 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 26 [2018-07-24 10:52:48,438 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:48,438 INFO L225 Difference]: With dead ends: 40 [2018-07-24 10:52:48,438 INFO L226 Difference]: Without dead ends: 30 [2018-07-24 10:52:48,439 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 111 GetRequests, 96 SyntacticMatches, 3 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:48,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30 states. [2018-07-24 10:52:48,443 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30 to 30. [2018-07-24 10:52:48,444 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 30 states. [2018-07-24 10:52:48,444 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30 states to 30 states and 31 transitions. [2018-07-24 10:52:48,445 INFO L78 Accepts]: Start accepts. Automaton has 30 states and 31 transitions. Word has length 26 [2018-07-24 10:52:48,445 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:48,445 INFO L471 AbstractCegarLoop]: Abstraction has 30 states and 31 transitions. [2018-07-24 10:52:48,445 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 10:52:48,446 INFO L276 IsEmpty]: Start isEmpty. Operand 30 states and 31 transitions. [2018-07-24 10:52:48,446 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 30 [2018-07-24 10:52:48,446 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:48,447 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:48,447 INFO L414 AbstractCegarLoop]: === Iteration 8 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:48,447 INFO L82 PathProgramCache]: Analyzing trace with hash -657878272, now seen corresponding path program 3 times [2018-07-24 10:52:48,447 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:48,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,448 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:48,448 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:48,448 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:48,459 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:48,883 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 0 proven. 57 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:48,884 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:48,884 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:48,895 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:48,895 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:48,910 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:52:48,910 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:48,912 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:48,974 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 10:52:48,974 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:49,065 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 10:52:49,085 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:49,085 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:49,103 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:52:49,104 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:52:49,133 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 3 check-sat command(s) [2018-07-24 10:52:49,134 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:49,138 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:49,149 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 10:52:49,149 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:49,160 INFO L134 CoverageAnalysis]: Checked inductivity of 57 backedges. 25 proven. 2 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 10:52:49,162 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:49,162 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 4, 4, 4, 4] total 13 [2018-07-24 10:52:49,162 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:49,163 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:52:49,163 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:52:49,163 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=51, Invalid=105, Unknown=0, NotChecked=0, Total=156 [2018-07-24 10:52:49,164 INFO L87 Difference]: Start difference. First operand 30 states and 31 transitions. Second operand 11 states. [2018-07-24 10:52:49,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:49,454 INFO L93 Difference]: Finished difference Result 50 states and 57 transitions. [2018-07-24 10:52:49,459 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 10:52:49,460 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 29 [2018-07-24 10:52:49,460 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:49,461 INFO L225 Difference]: With dead ends: 50 [2018-07-24 10:52:49,461 INFO L226 Difference]: Without dead ends: 40 [2018-07-24 10:52:49,461 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 125 GetRequests, 112 SyntacticMatches, 1 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=61, Invalid=121, Unknown=0, NotChecked=0, Total=182 [2018-07-24 10:52:49,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40 states. [2018-07-24 10:52:49,466 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40 to 36. [2018-07-24 10:52:49,466 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 36 states. [2018-07-24 10:52:49,467 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36 states to 36 states and 38 transitions. [2018-07-24 10:52:49,467 INFO L78 Accepts]: Start accepts. Automaton has 36 states and 38 transitions. Word has length 29 [2018-07-24 10:52:49,467 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:49,468 INFO L471 AbstractCegarLoop]: Abstraction has 36 states and 38 transitions. [2018-07-24 10:52:49,468 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:52:49,468 INFO L276 IsEmpty]: Start isEmpty. Operand 36 states and 38 transitions. [2018-07-24 10:52:49,469 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 36 [2018-07-24 10:52:49,469 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:49,469 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 6, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:49,469 INFO L414 AbstractCegarLoop]: === Iteration 9 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:49,470 INFO L82 PathProgramCache]: Analyzing trace with hash -249977826, now seen corresponding path program 4 times [2018-07-24 10:52:49,470 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:49,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:49,471 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:49,471 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:49,471 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:49,482 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:49,645 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 0 proven. 100 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:49,645 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:49,645 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:49,659 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:49,660 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:49,689 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:49,689 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:49,691 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:49,756 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 63 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:52:49,756 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:50,294 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 63 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:52:50,315 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:50,315 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:52:50,330 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:52:50,330 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:52:50,359 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:52:50,359 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:52:50,362 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:52:50,383 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 63 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:52:50,383 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:52:50,637 INFO L134 CoverageAnalysis]: Checked inductivity of 100 backedges. 35 proven. 63 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:52:50,639 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:52:50,639 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9, 10, 9, 9] total 25 [2018-07-24 10:52:50,639 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:52:50,640 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 10:52:50,640 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 10:52:50,640 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=201, Invalid=399, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:52:50,641 INFO L87 Difference]: Start difference. First operand 36 states and 38 transitions. Second operand 11 states. [2018-07-24 10:52:50,836 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:52:50,836 INFO L93 Difference]: Finished difference Result 52 states and 57 transitions. [2018-07-24 10:52:50,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 10:52:50,837 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 35 [2018-07-24 10:52:50,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:52:50,839 INFO L225 Difference]: With dead ends: 52 [2018-07-24 10:52:50,839 INFO L226 Difference]: Without dead ends: 39 [2018-07-24 10:52:50,840 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 150 GetRequests, 123 SyntacticMatches, 4 SemanticMatches, 23 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 20 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=201, Invalid=399, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:52:50,840 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 39 states. [2018-07-24 10:52:50,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 39 to 39. [2018-07-24 10:52:50,845 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 39 states. [2018-07-24 10:52:50,846 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39 states to 39 states and 41 transitions. [2018-07-24 10:52:50,846 INFO L78 Accepts]: Start accepts. Automaton has 39 states and 41 transitions. Word has length 35 [2018-07-24 10:52:50,846 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:52:50,847 INFO L471 AbstractCegarLoop]: Abstraction has 39 states and 41 transitions. [2018-07-24 10:52:50,847 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 10:52:50,847 INFO L276 IsEmpty]: Start isEmpty. Operand 39 states and 41 transitions. [2018-07-24 10:52:50,848 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 39 [2018-07-24 10:52:50,848 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:52:50,848 INFO L353 BasicCegarLoop]: trace histogram [10, 9, 7, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:52:50,848 INFO L414 AbstractCegarLoop]: === Iteration 10 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:52:50,848 INFO L82 PathProgramCache]: Analyzing trace with hash 1580391035, now seen corresponding path program 5 times [2018-07-24 10:52:50,849 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:52:50,849 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:50,850 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:52:50,850 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:52:50,850 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:52:50,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:52:51,095 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 0 proven. 126 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:52:51,096 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:52:51,096 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:52:51,104 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:52:51,105 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:23,495 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:53:23,496 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:23,738 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:23,987 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 18 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:23,987 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:24,953 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 18 proven. 108 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:24,956 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:24,957 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:24,973 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:24,973 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:25,081 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 10 check-sat command(s) [2018-07-24 10:53:25,081 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:25,085 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:25,108 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 40 proven. 84 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:53:25,108 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:25,492 INFO L134 CoverageAnalysis]: Checked inductivity of 126 backedges. 40 proven. 84 refuted. 0 times theorem prover too weak. 2 trivial. 0 not checked. [2018-07-24 10:53:25,495 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:25,496 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 12, 10, 10] total 29 [2018-07-24 10:53:25,496 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:25,496 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 10:53:25,497 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 10:53:25,497 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=254, Invalid=558, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:53:25,498 INFO L87 Difference]: Start difference. First operand 39 states and 41 transitions. Second operand 12 states. [2018-07-24 10:53:25,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:25,833 INFO L93 Difference]: Finished difference Result 55 states and 60 transitions. [2018-07-24 10:53:25,833 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 10:53:25,834 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 38 [2018-07-24 10:53:25,834 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:25,835 INFO L225 Difference]: With dead ends: 55 [2018-07-24 10:53:25,835 INFO L226 Difference]: Without dead ends: 42 [2018-07-24 10:53:25,836 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 163 GetRequests, 132 SyntacticMatches, 4 SemanticMatches, 27 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 25 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=254, Invalid=558, Unknown=0, NotChecked=0, Total=812 [2018-07-24 10:53:25,837 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42 states. [2018-07-24 10:53:25,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42 to 42. [2018-07-24 10:53:25,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 42 states. [2018-07-24 10:53:25,843 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42 states to 42 states and 44 transitions. [2018-07-24 10:53:25,843 INFO L78 Accepts]: Start accepts. Automaton has 42 states and 44 transitions. Word has length 38 [2018-07-24 10:53:25,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:25,844 INFO L471 AbstractCegarLoop]: Abstraction has 42 states and 44 transitions. [2018-07-24 10:53:25,844 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 10:53:25,844 INFO L276 IsEmpty]: Start isEmpty. Operand 42 states and 44 transitions. [2018-07-24 10:53:25,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 10:53:25,845 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:25,845 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 8, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:25,845 INFO L414 AbstractCegarLoop]: === Iteration 11 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:25,846 INFO L82 PathProgramCache]: Analyzing trace with hash 1194339070, now seen corresponding path program 6 times [2018-07-24 10:53:25,846 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:25,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:25,847 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:25,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:25,847 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:25,857 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:26,095 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 0 proven. 155 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:26,095 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:26,096 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:26,111 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:26,112 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:53:26,166 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-07-24 10:53:26,166 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:26,168 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:26,278 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 64 proven. 7 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:53:26,278 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:26,346 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 64 proven. 7 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:53:26,366 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:26,366 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:26,382 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:53:26,382 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:53:26,501 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 9 check-sat command(s) [2018-07-24 10:53:26,501 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:26,504 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:26,509 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 64 proven. 7 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:53:26,509 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:26,524 INFO L134 CoverageAnalysis]: Checked inductivity of 155 backedges. 64 proven. 7 refuted. 0 times theorem prover too weak. 84 trivial. 0 not checked. [2018-07-24 10:53:26,526 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:26,526 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 5, 5, 5, 5] total 19 [2018-07-24 10:53:26,526 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:26,527 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:53:26,527 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:53:26,527 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=101, Invalid=241, Unknown=0, NotChecked=0, Total=342 [2018-07-24 10:53:26,528 INFO L87 Difference]: Start difference. First operand 42 states and 44 transitions. Second operand 16 states. [2018-07-24 10:53:27,105 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:27,105 INFO L93 Difference]: Finished difference Result 65 states and 74 transitions. [2018-07-24 10:53:27,106 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:53:27,106 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 41 [2018-07-24 10:53:27,106 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:27,108 INFO L225 Difference]: With dead ends: 65 [2018-07-24 10:53:27,108 INFO L226 Difference]: Without dead ends: 52 [2018-07-24 10:53:27,109 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 179 GetRequests, 159 SyntacticMatches, 1 SemanticMatches, 19 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 4 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=129, Invalid=291, Unknown=0, NotChecked=0, Total=420 [2018-07-24 10:53:27,109 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52 states. [2018-07-24 10:53:27,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52 to 48. [2018-07-24 10:53:27,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 48 states. [2018-07-24 10:53:27,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 48 states to 48 states and 51 transitions. [2018-07-24 10:53:27,115 INFO L78 Accepts]: Start accepts. Automaton has 48 states and 51 transitions. Word has length 41 [2018-07-24 10:53:27,115 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:27,115 INFO L471 AbstractCegarLoop]: Abstraction has 48 states and 51 transitions. [2018-07-24 10:53:27,115 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:53:27,115 INFO L276 IsEmpty]: Start isEmpty. Operand 48 states and 51 transitions. [2018-07-24 10:53:27,116 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 48 [2018-07-24 10:53:27,116 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:27,117 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 9, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:27,117 INFO L414 AbstractCegarLoop]: === Iteration 12 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:27,117 INFO L82 PathProgramCache]: Analyzing trace with hash -565963040, now seen corresponding path program 7 times [2018-07-24 10:53:27,117 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:27,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:27,118 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:27,118 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:27,119 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:27,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:27,492 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 0 proven. 222 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:27,493 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:27,493 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:27,510 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:27,510 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:27,524 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:27,526 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:27,572 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 80 proven. 135 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-07-24 10:53:27,573 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:28,103 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 80 proven. 135 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-07-24 10:53:28,123 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:28,123 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:28,139 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:28,139 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:53:28,168 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:28,172 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:28,190 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 80 proven. 135 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-07-24 10:53:28,190 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:28,818 INFO L134 CoverageAnalysis]: Checked inductivity of 222 backedges. 80 proven. 135 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-07-24 10:53:28,819 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:28,819 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 12, 13, 12, 12] total 35 [2018-07-24 10:53:28,819 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:28,820 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 10:53:28,820 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 10:53:28,821 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=382, Invalid=808, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:53:28,821 INFO L87 Difference]: Start difference. First operand 48 states and 51 transitions. Second operand 15 states. [2018-07-24 10:53:29,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:29,096 INFO L93 Difference]: Finished difference Result 67 states and 74 transitions. [2018-07-24 10:53:29,096 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 10:53:29,096 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 47 [2018-07-24 10:53:29,097 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:29,098 INFO L225 Difference]: With dead ends: 67 [2018-07-24 10:53:29,098 INFO L226 Difference]: Without dead ends: 51 [2018-07-24 10:53:29,100 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 202 GetRequests, 165 SyntacticMatches, 4 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 29 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=382, Invalid=808, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:53:29,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51 states. [2018-07-24 10:53:29,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51 to 51. [2018-07-24 10:53:29,105 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 51 states. [2018-07-24 10:53:29,106 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51 states to 51 states and 54 transitions. [2018-07-24 10:53:29,106 INFO L78 Accepts]: Start accepts. Automaton has 51 states and 54 transitions. Word has length 47 [2018-07-24 10:53:29,107 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:29,107 INFO L471 AbstractCegarLoop]: Abstraction has 51 states and 54 transitions. [2018-07-24 10:53:29,107 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 10:53:29,107 INFO L276 IsEmpty]: Start isEmpty. Operand 51 states and 54 transitions. [2018-07-24 10:53:29,108 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 51 [2018-07-24 10:53:29,108 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:29,108 INFO L353 BasicCegarLoop]: trace histogram [14, 13, 10, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:29,108 INFO L414 AbstractCegarLoop]: === Iteration 13 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:29,109 INFO L82 PathProgramCache]: Analyzing trace with hash -1227511363, now seen corresponding path program 8 times [2018-07-24 10:53:29,109 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:29,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:29,110 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:53:29,110 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:29,110 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:29,120 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:29,594 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:29,594 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:29,594 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:29,608 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:29,608 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:29,623 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:29,624 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:29,626 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:29,645 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:29,646 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:30,358 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:30,378 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:30,378 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:30,394 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:53:30,394 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:53:30,435 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:53:30,435 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:30,440 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:30,481 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:30,481 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:30,541 INFO L134 CoverageAnalysis]: Checked inductivity of 260 backedges. 0 proven. 260 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:30,545 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:30,545 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 16, 16, 16, 16] total 30 [2018-07-24 10:53:30,545 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:30,546 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 10:53:30,546 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 10:53:30,546 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:53:30,547 INFO L87 Difference]: Start difference. First operand 51 states and 54 transitions. Second operand 16 states. [2018-07-24 10:53:30,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:30,887 INFO L93 Difference]: Finished difference Result 70 states and 77 transitions. [2018-07-24 10:53:30,887 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 10:53:30,887 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 50 [2018-07-24 10:53:30,888 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:30,888 INFO L225 Difference]: With dead ends: 70 [2018-07-24 10:53:30,889 INFO L226 Difference]: Without dead ends: 54 [2018-07-24 10:53:30,889 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 215 GetRequests, 184 SyntacticMatches, 3 SemanticMatches, 28 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 14 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=253, Invalid=617, Unknown=0, NotChecked=0, Total=870 [2018-07-24 10:53:30,890 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 54 states. [2018-07-24 10:53:30,894 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 54 to 54. [2018-07-24 10:53:30,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 54 states. [2018-07-24 10:53:30,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 54 states to 54 states and 57 transitions. [2018-07-24 10:53:30,896 INFO L78 Accepts]: Start accepts. Automaton has 54 states and 57 transitions. Word has length 50 [2018-07-24 10:53:30,896 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:30,896 INFO L471 AbstractCegarLoop]: Abstraction has 54 states and 57 transitions. [2018-07-24 10:53:30,896 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 10:53:30,896 INFO L276 IsEmpty]: Start isEmpty. Operand 54 states and 57 transitions. [2018-07-24 10:53:30,897 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 54 [2018-07-24 10:53:30,897 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:30,897 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 11, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:30,898 INFO L414 AbstractCegarLoop]: === Iteration 14 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:30,898 INFO L82 PathProgramCache]: Analyzing trace with hash 191319488, now seen corresponding path program 9 times [2018-07-24 10:53:30,898 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:30,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:30,899 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:30,899 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:30,899 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:30,908 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:31,205 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 0 proven. 301 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:31,205 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:31,205 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:31,214 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:31,214 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:31,229 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:53:31,229 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:31,231 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:31,379 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 121 proven. 15 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2018-07-24 10:53:31,379 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:31,540 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 121 proven. 15 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2018-07-24 10:53:31,560 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:31,560 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:31,575 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:53:31,575 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:53:31,653 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 10:53:31,653 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:31,657 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:31,668 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 121 proven. 15 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2018-07-24 10:53:31,668 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:31,722 INFO L134 CoverageAnalysis]: Checked inductivity of 301 backedges. 121 proven. 15 refuted. 0 times theorem prover too weak. 165 trivial. 0 not checked. [2018-07-24 10:53:31,724 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:31,724 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [17, 6, 6, 6, 6] total 25 [2018-07-24 10:53:31,724 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:31,725 INFO L450 AbstractCegarLoop]: Interpolant automaton has 21 states [2018-07-24 10:53:31,725 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 21 interpolants. [2018-07-24 10:53:31,725 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=167, Invalid=433, Unknown=0, NotChecked=0, Total=600 [2018-07-24 10:53:31,726 INFO L87 Difference]: Start difference. First operand 54 states and 57 transitions. Second operand 21 states. [2018-07-24 10:53:35,003 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:35,003 INFO L93 Difference]: Finished difference Result 80 states and 91 transitions. [2018-07-24 10:53:35,003 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:53:35,003 INFO L78 Accepts]: Start accepts. Automaton has 21 states. Word has length 53 [2018-07-24 10:53:35,004 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:35,004 INFO L225 Difference]: With dead ends: 80 [2018-07-24 10:53:35,004 INFO L226 Difference]: Without dead ends: 64 [2018-07-24 10:53:35,005 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 234 GetRequests, 206 SyntacticMatches, 2 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 11 ImplicationChecksByTransitivity, 0.9s TimeCoverageRelationStatistics Valid=221, Invalid=535, Unknown=0, NotChecked=0, Total=756 [2018-07-24 10:53:35,005 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 64 states. [2018-07-24 10:53:35,013 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 64 to 60. [2018-07-24 10:53:35,013 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 60 states. [2018-07-24 10:53:35,014 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60 states to 60 states and 64 transitions. [2018-07-24 10:53:35,014 INFO L78 Accepts]: Start accepts. Automaton has 60 states and 64 transitions. Word has length 53 [2018-07-24 10:53:35,014 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:35,015 INFO L471 AbstractCegarLoop]: Abstraction has 60 states and 64 transitions. [2018-07-24 10:53:35,015 INFO L472 AbstractCegarLoop]: Interpolant automaton has 21 states. [2018-07-24 10:53:35,015 INFO L276 IsEmpty]: Start isEmpty. Operand 60 states and 64 transitions. [2018-07-24 10:53:35,017 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 60 [2018-07-24 10:53:35,017 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:35,020 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 12, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:35,020 INFO L414 AbstractCegarLoop]: === Iteration 15 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:35,020 INFO L82 PathProgramCache]: Analyzing trace with hash 794925150, now seen corresponding path program 10 times [2018-07-24 10:53:35,021 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:35,021 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:35,022 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:35,022 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:35,022 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:35,039 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:35,514 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 0 proven. 392 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:35,514 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:35,514 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:35,529 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:35,529 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:35,547 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:35,547 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:35,549 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:35,581 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 143 proven. 234 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:53:35,581 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:38,744 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 143 proven. 234 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:53:38,764 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:38,764 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:53:38,781 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:53:38,782 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:53:38,821 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:53:38,821 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:53:38,825 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:53:38,857 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 143 proven. 234 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:53:38,857 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:53:39,752 INFO L134 CoverageAnalysis]: Checked inductivity of 392 backedges. 143 proven. 234 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:53:39,754 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:53:39,754 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [19, 15, 16, 15, 15] total 45 [2018-07-24 10:53:39,754 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:53:39,754 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 10:53:39,755 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 10:53:39,756 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=620, Invalid=1359, Unknown=1, NotChecked=0, Total=1980 [2018-07-24 10:53:39,756 INFO L87 Difference]: Start difference. First operand 60 states and 64 transitions. Second operand 19 states. [2018-07-24 10:53:41,012 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:53:41,012 INFO L93 Difference]: Finished difference Result 82 states and 91 transitions. [2018-07-24 10:53:41,013 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 15 states. [2018-07-24 10:53:41,014 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 59 [2018-07-24 10:53:41,014 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:53:41,015 INFO L225 Difference]: With dead ends: 82 [2018-07-24 10:53:41,015 INFO L226 Difference]: Without dead ends: 63 [2018-07-24 10:53:41,017 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 254 GetRequests, 207 SyntacticMatches, 4 SemanticMatches, 43 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 38 ImplicationChecksByTransitivity, 4.4s TimeCoverageRelationStatistics Valid=620, Invalid=1359, Unknown=1, NotChecked=0, Total=1980 [2018-07-24 10:53:41,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 63 states. [2018-07-24 10:53:41,023 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 63 to 63. [2018-07-24 10:53:41,023 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 63 states. [2018-07-24 10:53:41,024 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 63 states to 63 states and 67 transitions. [2018-07-24 10:53:41,024 INFO L78 Accepts]: Start accepts. Automaton has 63 states and 67 transitions. Word has length 59 [2018-07-24 10:53:41,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:53:41,025 INFO L471 AbstractCegarLoop]: Abstraction has 63 states and 67 transitions. [2018-07-24 10:53:41,025 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 10:53:41,025 INFO L276 IsEmpty]: Start isEmpty. Operand 63 states and 67 transitions. [2018-07-24 10:53:41,026 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 63 [2018-07-24 10:53:41,026 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:53:41,026 INFO L353 BasicCegarLoop]: trace histogram [18, 17, 13, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:53:41,026 INFO L414 AbstractCegarLoop]: === Iteration 16 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:53:41,026 INFO L82 PathProgramCache]: Analyzing trace with hash 1464125371, now seen corresponding path program 11 times [2018-07-24 10:53:41,026 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:53:41,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:41,027 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:53:41,027 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:53:41,028 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:53:41,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:53:41,535 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:53:41,536 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:53:41,536 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:53:41,544 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:53:41,544 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:55,596 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:55:55,596 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:58,162 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:58,191 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:58,191 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:55:59,090 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 0 proven. 442 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:55:59,111 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:55:59,111 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:55:59,127 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:55:59,127 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:55:59,496 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 18 check-sat command(s) [2018-07-24 10:55:59,496 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:55:59,500 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:55:59,546 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 154 proven. 273 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:55:59,546 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:00,954 INFO L134 CoverageAnalysis]: Checked inductivity of 442 backedges. 154 proven. 273 refuted. 0 times theorem prover too weak. 15 trivial. 0 not checked. [2018-07-24 10:56:00,956 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:00,956 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [20, 20, 20, 16, 16] total 52 [2018-07-24 10:56:00,956 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:00,956 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 10:56:00,957 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 10:56:00,957 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=874, Invalid=1778, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:00,958 INFO L87 Difference]: Start difference. First operand 63 states and 67 transitions. Second operand 20 states. [2018-07-24 10:56:01,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:01,696 INFO L93 Difference]: Finished difference Result 85 states and 94 transitions. [2018-07-24 10:56:01,704 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 16 states. [2018-07-24 10:56:01,704 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 62 [2018-07-24 10:56:01,704 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:01,705 INFO L225 Difference]: With dead ends: 85 [2018-07-24 10:56:01,705 INFO L226 Difference]: Without dead ends: 66 [2018-07-24 10:56:01,707 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 267 GetRequests, 214 SyntacticMatches, 3 SemanticMatches, 50 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 105 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=874, Invalid=1778, Unknown=0, NotChecked=0, Total=2652 [2018-07-24 10:56:01,708 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66 states. [2018-07-24 10:56:01,716 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66 to 66. [2018-07-24 10:56:01,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 66 states. [2018-07-24 10:56:01,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66 states to 66 states and 70 transitions. [2018-07-24 10:56:01,718 INFO L78 Accepts]: Start accepts. Automaton has 66 states and 70 transitions. Word has length 62 [2018-07-24 10:56:01,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:01,718 INFO L471 AbstractCegarLoop]: Abstraction has 66 states and 70 transitions. [2018-07-24 10:56:01,718 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 10:56:01,718 INFO L276 IsEmpty]: Start isEmpty. Operand 66 states and 70 transitions. [2018-07-24 10:56:01,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 66 [2018-07-24 10:56:01,721 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:01,722 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 14, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:01,722 INFO L414 AbstractCegarLoop]: === Iteration 17 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:01,722 INFO L82 PathProgramCache]: Analyzing trace with hash 369721150, now seen corresponding path program 12 times [2018-07-24 10:56:01,722 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:01,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:01,723 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:01,723 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:01,723 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:01,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:02,119 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 0 proven. 495 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:02,119 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:02,119 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:02,127 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:02,127 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:04,645 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2018-07-24 10:56:04,645 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:04,687 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:04,882 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 196 proven. 26 refuted. 0 times theorem prover too weak. 273 trivial. 0 not checked. [2018-07-24 10:56:04,882 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:05,093 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 196 proven. 26 refuted. 0 times theorem prover too weak. 273 trivial. 0 not checked. [2018-07-24 10:56:05,115 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:05,115 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:05,131 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 10:56:05,131 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 10:56:05,452 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 15 check-sat command(s) [2018-07-24 10:56:05,452 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:05,456 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:05,476 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 196 proven. 26 refuted. 0 times theorem prover too weak. 273 trivial. 0 not checked. [2018-07-24 10:56:05,477 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:05,534 INFO L134 CoverageAnalysis]: Checked inductivity of 495 backedges. 196 proven. 26 refuted. 0 times theorem prover too weak. 273 trivial. 0 not checked. [MP cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (30)] Exception during sending of exit command (exit): Broken pipe [2018-07-24 10:56:05,538 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:05,538 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [21, 7, 7, 7, 7] total 31 [2018-07-24 10:56:05,538 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:05,538 INFO L450 AbstractCegarLoop]: Interpolant automaton has 26 states [2018-07-24 10:56:05,539 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 26 interpolants. [2018-07-24 10:56:05,539 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=249, Invalid=681, Unknown=0, NotChecked=0, Total=930 [2018-07-24 10:56:05,539 INFO L87 Difference]: Start difference. First operand 66 states and 70 transitions. Second operand 26 states. [2018-07-24 10:56:07,523 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:07,523 INFO L93 Difference]: Finished difference Result 95 states and 108 transitions. [2018-07-24 10:56:07,524 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 10:56:07,524 INFO L78 Accepts]: Start accepts. Automaton has 26 states. Word has length 65 [2018-07-24 10:56:07,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:07,525 INFO L225 Difference]: With dead ends: 95 [2018-07-24 10:56:07,525 INFO L226 Difference]: Without dead ends: 76 [2018-07-24 10:56:07,526 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 287 GetRequests, 253 SyntacticMatches, 1 SemanticMatches, 33 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=337, Invalid=853, Unknown=0, NotChecked=0, Total=1190 [2018-07-24 10:56:07,526 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76 states. [2018-07-24 10:56:07,532 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76 to 72. [2018-07-24 10:56:07,532 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 72 states. [2018-07-24 10:56:07,533 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 72 states to 72 states and 77 transitions. [2018-07-24 10:56:07,533 INFO L78 Accepts]: Start accepts. Automaton has 72 states and 77 transitions. Word has length 65 [2018-07-24 10:56:07,533 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:07,533 INFO L471 AbstractCegarLoop]: Abstraction has 72 states and 77 transitions. [2018-07-24 10:56:07,533 INFO L472 AbstractCegarLoop]: Interpolant automaton has 26 states. [2018-07-24 10:56:07,534 INFO L276 IsEmpty]: Start isEmpty. Operand 72 states and 77 transitions. [2018-07-24 10:56:07,535 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 72 [2018-07-24 10:56:07,535 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:07,535 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 15, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:07,535 INFO L414 AbstractCegarLoop]: === Iteration 18 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:07,536 INFO L82 PathProgramCache]: Analyzing trace with hash -512392800, now seen corresponding path program 13 times [2018-07-24 10:56:07,536 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:07,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:07,537 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:07,537 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:07,537 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:07,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:07,986 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 0 proven. 610 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:07,986 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:07,986 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:08,004 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:08,004 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:08,022 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:08,023 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:08,072 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 224 proven. 360 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 10:56:08,072 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:09,638 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 224 proven. 360 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 10:56:09,658 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:09,659 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:09,676 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:09,676 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 10:56:09,717 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:09,721 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:09,751 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 224 proven. 360 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 10:56:09,751 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:11,564 INFO L134 CoverageAnalysis]: Checked inductivity of 610 backedges. 224 proven. 360 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 10:56:11,566 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:11,566 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [23, 18, 19, 18, 18] total 55 [2018-07-24 10:56:11,566 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:11,566 INFO L450 AbstractCegarLoop]: Interpolant automaton has 23 states [2018-07-24 10:56:11,567 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 23 interpolants. [2018-07-24 10:56:11,569 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=915, Invalid=2055, Unknown=0, NotChecked=0, Total=2970 [2018-07-24 10:56:11,569 INFO L87 Difference]: Start difference. First operand 72 states and 77 transitions. Second operand 23 states. [2018-07-24 10:56:12,248 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:12,248 INFO L93 Difference]: Finished difference Result 97 states and 108 transitions. [2018-07-24 10:56:12,250 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 10:56:12,250 INFO L78 Accepts]: Start accepts. Automaton has 23 states. Word has length 71 [2018-07-24 10:56:12,250 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:12,251 INFO L225 Difference]: With dead ends: 97 [2018-07-24 10:56:12,251 INFO L226 Difference]: Without dead ends: 75 [2018-07-24 10:56:12,253 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 306 GetRequests, 249 SyntacticMatches, 4 SemanticMatches, 53 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 47 ImplicationChecksByTransitivity, 3.7s TimeCoverageRelationStatistics Valid=915, Invalid=2055, Unknown=0, NotChecked=0, Total=2970 [2018-07-24 10:56:12,253 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 75 states. [2018-07-24 10:56:12,258 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 75 to 75. [2018-07-24 10:56:12,259 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 75 states. [2018-07-24 10:56:12,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 75 states to 75 states and 80 transitions. [2018-07-24 10:56:12,259 INFO L78 Accepts]: Start accepts. Automaton has 75 states and 80 transitions. Word has length 71 [2018-07-24 10:56:12,260 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:12,260 INFO L471 AbstractCegarLoop]: Abstraction has 75 states and 80 transitions. [2018-07-24 10:56:12,260 INFO L472 AbstractCegarLoop]: Interpolant automaton has 23 states. [2018-07-24 10:56:12,260 INFO L276 IsEmpty]: Start isEmpty. Operand 75 states and 80 transitions. [2018-07-24 10:56:12,261 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 75 [2018-07-24 10:56:12,261 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:12,261 INFO L353 BasicCegarLoop]: trace histogram [22, 21, 16, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:12,261 INFO L414 AbstractCegarLoop]: === Iteration 19 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:12,262 INFO L82 PathProgramCache]: Analyzing trace with hash 10718589, now seen corresponding path program 14 times [2018-07-24 10:56:12,262 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:12,262 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:12,262 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 10:56:12,263 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:12,263 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:12,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:12,654 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:12,655 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:12,655 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:12,664 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:12,664 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:12,683 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:12,683 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:12,685 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:12,707 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:12,708 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:14,144 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:14,164 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:14,165 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:14,179 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 10:56:14,179 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 10:56:14,229 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 10:56:14,229 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:14,233 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:14,262 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:14,262 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:14,283 INFO L134 CoverageAnalysis]: Checked inductivity of 672 backedges. 0 proven. 672 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:14,285 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:14,285 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [24, 24, 24, 24, 24] total 46 [2018-07-24 10:56:14,285 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:14,285 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 10:56:14,286 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 10:56:14,286 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:56:14,287 INFO L87 Difference]: Start difference. First operand 75 states and 80 transitions. Second operand 24 states. [2018-07-24 10:56:14,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:14,837 INFO L93 Difference]: Finished difference Result 100 states and 111 transitions. [2018-07-24 10:56:14,838 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 19 states. [2018-07-24 10:56:14,838 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 74 [2018-07-24 10:56:14,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:14,839 INFO L225 Difference]: With dead ends: 100 [2018-07-24 10:56:14,839 INFO L226 Difference]: Without dead ends: 78 [2018-07-24 10:56:14,841 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 319 GetRequests, 272 SyntacticMatches, 3 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 22 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=573, Invalid=1497, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 10:56:14,841 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 78 states. [2018-07-24 10:56:14,847 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 78 to 78. [2018-07-24 10:56:14,847 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 78 states. [2018-07-24 10:56:14,848 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78 states to 78 states and 83 transitions. [2018-07-24 10:56:14,848 INFO L78 Accepts]: Start accepts. Automaton has 78 states and 83 transitions. Word has length 74 [2018-07-24 10:56:14,848 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:14,848 INFO L471 AbstractCegarLoop]: Abstraction has 78 states and 83 transitions. [2018-07-24 10:56:14,848 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 10:56:14,848 INFO L276 IsEmpty]: Start isEmpty. Operand 78 states and 83 transitions. [2018-07-24 10:56:14,849 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 10:56:14,849 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:14,850 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 17, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:14,850 INFO L414 AbstractCegarLoop]: === Iteration 20 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:14,850 INFO L82 PathProgramCache]: Analyzing trace with hash 1880758400, now seen corresponding path program 15 times [2018-07-24 10:56:14,850 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:14,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:14,851 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:14,851 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:14,851 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:14,860 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:15,978 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 0 proven. 737 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:15,978 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:15,979 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:15,987 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:15,987 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:16,016 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:56:16,016 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:16,017 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:16,453 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 289 proven. 40 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2018-07-24 10:56:16,454 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:16,759 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 289 proven. 40 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2018-07-24 10:56:16,780 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:16,780 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:16,795 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 10:56:16,795 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 10:56:16,926 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 9 check-sat command(s) [2018-07-24 10:56:16,926 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:16,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:16,938 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 289 proven. 40 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2018-07-24 10:56:16,939 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:16,950 INFO L134 CoverageAnalysis]: Checked inductivity of 737 backedges. 289 proven. 40 refuted. 0 times theorem prover too weak. 408 trivial. 0 not checked. [2018-07-24 10:56:16,952 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:16,952 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [25, 8, 8, 8, 8] total 37 [2018-07-24 10:56:16,952 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:16,952 INFO L450 AbstractCegarLoop]: Interpolant automaton has 31 states [2018-07-24 10:56:16,953 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 31 interpolants. [2018-07-24 10:56:16,953 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=347, Invalid=985, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 10:56:16,954 INFO L87 Difference]: Start difference. First operand 78 states and 83 transitions. Second operand 31 states. [2018-07-24 10:56:29,423 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:29,424 INFO L93 Difference]: Finished difference Result 110 states and 125 transitions. [2018-07-24 10:56:29,424 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 27 states. [2018-07-24 10:56:29,424 INFO L78 Accepts]: Start accepts. Automaton has 31 states. Word has length 77 [2018-07-24 10:56:29,424 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:29,425 INFO L225 Difference]: With dead ends: 110 [2018-07-24 10:56:29,425 INFO L226 Difference]: Without dead ends: 88 [2018-07-24 10:56:29,426 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 344 GetRequests, 300 SyntacticMatches, 4 SemanticMatches, 40 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 32 ImplicationChecksByTransitivity, 3.2s TimeCoverageRelationStatistics Valid=477, Invalid=1245, Unknown=0, NotChecked=0, Total=1722 [2018-07-24 10:56:29,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 88 states. [2018-07-24 10:56:29,430 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 88 to 84. [2018-07-24 10:56:29,431 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 84 states. [2018-07-24 10:56:29,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84 states to 84 states and 90 transitions. [2018-07-24 10:56:29,431 INFO L78 Accepts]: Start accepts. Automaton has 84 states and 90 transitions. Word has length 77 [2018-07-24 10:56:29,431 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:29,432 INFO L471 AbstractCegarLoop]: Abstraction has 84 states and 90 transitions. [2018-07-24 10:56:29,432 INFO L472 AbstractCegarLoop]: Interpolant automaton has 31 states. [2018-07-24 10:56:29,432 INFO L276 IsEmpty]: Start isEmpty. Operand 84 states and 90 transitions. [2018-07-24 10:56:29,433 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 84 [2018-07-24 10:56:29,433 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:29,433 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 18, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:29,433 INFO L414 AbstractCegarLoop]: === Iteration 21 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:29,433 INFO L82 PathProgramCache]: Analyzing trace with hash -1326089058, now seen corresponding path program 16 times [2018-07-24 10:56:29,433 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:29,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:29,434 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:29,434 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:29,434 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:29,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:30,261 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 48 proven. 828 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:30,262 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:30,262 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:30,270 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:30,270 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:30,292 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:30,292 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:30,294 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:30,339 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 323 proven. 513 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:56:30,339 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:32,853 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 323 proven. 513 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:56:32,875 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:32,875 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 10:56:32,890 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 10:56:32,890 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 10:56:32,941 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 10:56:32,941 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 10:56:32,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 10:56:32,966 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 323 proven. 513 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:56:32,967 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 10:56:35,073 INFO L134 CoverageAnalysis]: Checked inductivity of 876 backedges. 323 proven. 513 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 10:56:35,076 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 10:56:35,076 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [27, 21, 22, 21, 21] total 65 [2018-07-24 10:56:35,076 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 10:56:35,077 INFO L450 AbstractCegarLoop]: Interpolant automaton has 27 states [2018-07-24 10:56:35,078 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 27 interpolants. [2018-07-24 10:56:35,079 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=1291, Invalid=2869, Unknown=0, NotChecked=0, Total=4160 [2018-07-24 10:56:35,079 INFO L87 Difference]: Start difference. First operand 84 states and 90 transitions. Second operand 27 states. [2018-07-24 10:56:35,746 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 10:56:35,746 INFO L93 Difference]: Finished difference Result 115 states and 129 transitions. [2018-07-24 10:56:35,746 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 22 states. [2018-07-24 10:56:35,746 INFO L78 Accepts]: Start accepts. Automaton has 27 states. Word has length 83 [2018-07-24 10:56:35,747 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 10:56:35,748 INFO L225 Difference]: With dead ends: 115 [2018-07-24 10:56:35,748 INFO L226 Difference]: Without dead ends: 90 [2018-07-24 10:56:35,750 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 357 GetRequests, 291 SyntacticMatches, 3 SemanticMatches, 63 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 60 ImplicationChecksByTransitivity, 5.3s TimeCoverageRelationStatistics Valid=1291, Invalid=2869, Unknown=0, NotChecked=0, Total=4160 [2018-07-24 10:56:35,750 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 90 states. [2018-07-24 10:56:35,756 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 90 to 90. [2018-07-24 10:56:35,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 90 states. [2018-07-24 10:56:35,757 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90 states to 90 states and 96 transitions. [2018-07-24 10:56:35,757 INFO L78 Accepts]: Start accepts. Automaton has 90 states and 96 transitions. Word has length 83 [2018-07-24 10:56:35,757 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 10:56:35,757 INFO L471 AbstractCegarLoop]: Abstraction has 90 states and 96 transitions. [2018-07-24 10:56:35,757 INFO L472 AbstractCegarLoop]: Interpolant automaton has 27 states. [2018-07-24 10:56:35,758 INFO L276 IsEmpty]: Start isEmpty. Operand 90 states and 96 transitions. [2018-07-24 10:56:35,759 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 90 [2018-07-24 10:56:35,759 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 10:56:35,759 INFO L353 BasicCegarLoop]: trace histogram [27, 26, 20, 6, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 10:56:35,759 INFO L414 AbstractCegarLoop]: === Iteration 22 === [__U_MULTI_f_storage_repos_ultimate_trunk_examples_svcomp_loop_acceleration_phases_true_unreach_call__i____VERIFIER_assertErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 10:56:35,759 INFO L82 PathProgramCache]: Analyzing trace with hash -502348930, now seen corresponding path program 17 times [2018-07-24 10:56:35,760 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 10:56:35,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:35,760 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 10:56:35,760 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 10:56:35,761 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 10:56:35,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 10:56:36,770 INFO L134 CoverageAnalysis]: Checked inductivity of 1027 backedges. 52 proven. 975 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 10:56:36,770 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 10:56:36,770 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 10:56:36,779 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 10:56:36,780 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) Received shutdown request... Cannot interrupt operation gracefully because timeout expired. Forcing shutdown