java -Xmx8000000000 -jar ./plugins/org.eclipse.equinox.launcher_1.3.100.v20150511-1540.jar -data @noDefault -ultimatedata ./data -tc ../../../trunk/examples/toolchains/AutomizerCInline.xml --generate-csv --csv-dir csv -s ../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf -i ../../../trunk/examples/svcomp/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c -------------------------------------------------------------------------------- This is Ultimate 0.1.23-dd2f093 [2018-07-24 15:16:10,043 INFO L170 SettingsManager]: Resetting all preferences to default values... [2018-07-24 15:16:10,045 INFO L174 SettingsManager]: Resetting UltimateCore preferences to default values [2018-07-24 15:16:10,058 INFO L177 SettingsManager]: Ultimate Commandline Interface provides no preferences, ignoring... [2018-07-24 15:16:10,058 INFO L174 SettingsManager]: Resetting Boogie Preprocessor preferences to default values [2018-07-24 15:16:10,059 INFO L174 SettingsManager]: Resetting Boogie Procedure Inliner preferences to default values [2018-07-24 15:16:10,060 INFO L174 SettingsManager]: Resetting Abstract Interpretation preferences to default values [2018-07-24 15:16:10,062 INFO L174 SettingsManager]: Resetting LassoRanker preferences to default values [2018-07-24 15:16:10,064 INFO L174 SettingsManager]: Resetting Reaching Definitions preferences to default values [2018-07-24 15:16:10,064 INFO L174 SettingsManager]: Resetting SyntaxChecker preferences to default values [2018-07-24 15:16:10,065 INFO L177 SettingsManager]: Büchi Program Product provides no preferences, ignoring... [2018-07-24 15:16:10,066 INFO L174 SettingsManager]: Resetting LTL2Aut preferences to default values [2018-07-24 15:16:10,067 INFO L174 SettingsManager]: Resetting PEA to Boogie preferences to default values [2018-07-24 15:16:10,067 INFO L174 SettingsManager]: Resetting BlockEncodingV2 preferences to default values [2018-07-24 15:16:10,069 INFO L174 SettingsManager]: Resetting ChcToBoogie preferences to default values [2018-07-24 15:16:10,069 INFO L174 SettingsManager]: Resetting AutomataScriptInterpreter preferences to default values [2018-07-24 15:16:10,070 INFO L174 SettingsManager]: Resetting BuchiAutomizer preferences to default values [2018-07-24 15:16:10,072 INFO L174 SettingsManager]: Resetting CACSL2BoogieTranslator preferences to default values [2018-07-24 15:16:10,074 INFO L174 SettingsManager]: Resetting CodeCheck preferences to default values [2018-07-24 15:16:10,076 INFO L174 SettingsManager]: Resetting InvariantSynthesis preferences to default values [2018-07-24 15:16:10,077 INFO L174 SettingsManager]: Resetting RCFGBuilder preferences to default values [2018-07-24 15:16:10,078 INFO L174 SettingsManager]: Resetting TraceAbstraction preferences to default values [2018-07-24 15:16:10,080 INFO L177 SettingsManager]: TraceAbstractionConcurrent provides no preferences, ignoring... [2018-07-24 15:16:10,081 INFO L177 SettingsManager]: TraceAbstractionWithAFAs provides no preferences, ignoring... [2018-07-24 15:16:10,081 INFO L174 SettingsManager]: Resetting TreeAutomizer preferences to default values [2018-07-24 15:16:10,082 INFO L174 SettingsManager]: Resetting IcfgTransformer preferences to default values [2018-07-24 15:16:10,083 INFO L174 SettingsManager]: Resetting Boogie Printer preferences to default values [2018-07-24 15:16:10,084 INFO L174 SettingsManager]: Resetting ReqPrinter preferences to default values [2018-07-24 15:16:10,084 INFO L174 SettingsManager]: Resetting Witness Printer preferences to default values [2018-07-24 15:16:10,086 INFO L177 SettingsManager]: Boogie PL CUP Parser provides no preferences, ignoring... [2018-07-24 15:16:10,086 INFO L174 SettingsManager]: Resetting CDTParser preferences to default values [2018-07-24 15:16:10,087 INFO L177 SettingsManager]: AutomataScriptParser provides no preferences, ignoring... [2018-07-24 15:16:10,087 INFO L177 SettingsManager]: ReqParser provides no preferences, ignoring... [2018-07-24 15:16:10,087 INFO L174 SettingsManager]: Resetting SmtParser preferences to default values [2018-07-24 15:16:10,088 INFO L174 SettingsManager]: Resetting Witness Parser preferences to default values [2018-07-24 15:16:10,089 INFO L181 SettingsManager]: Finished resetting all preferences to default values... [2018-07-24 15:16:10,089 INFO L98 SettingsManager]: Beginning loading settings from /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/settings/ai/taipanbench/svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf [2018-07-24 15:16:10,119 INFO L110 SettingsManager]: Loading preferences was successful [2018-07-24 15:16:10,119 INFO L112 SettingsManager]: Preferences different from defaults after loading the file: [2018-07-24 15:16:10,120 INFO L131 SettingsManager]: Preferences of Boogie Procedure Inliner differ from their defaults: [2018-07-24 15:16:10,121 INFO L133 SettingsManager]: * User list type=DISABLED [2018-07-24 15:16:10,122 INFO L133 SettingsManager]: * calls to implemented procedures=false [2018-07-24 15:16:10,122 INFO L131 SettingsManager]: Preferences of Abstract Interpretation differ from their defaults: [2018-07-24 15:16:10,122 INFO L133 SettingsManager]: * Abstract domain for RCFG-of-the-future=PoormanAbstractDomain [2018-07-24 15:16:10,122 INFO L133 SettingsManager]: * Abstract domain=CompoundDomain [2018-07-24 15:16:10,122 INFO L133 SettingsManager]: * Log string format=TERM [2018-07-24 15:16:10,123 INFO L133 SettingsManager]: * Check feasibility of abstract posts with an SMT solver=true [2018-07-24 15:16:10,123 INFO L133 SettingsManager]: * Interval Domain=false [2018-07-24 15:16:10,124 INFO L131 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2018-07-24 15:16:10,124 INFO L133 SettingsManager]: * Overapproximate operations on floating types=true [2018-07-24 15:16:10,124 INFO L133 SettingsManager]: * Check division by zero=IGNORE [2018-07-24 15:16:10,125 INFO L133 SettingsManager]: * Pointer to allocated memory at dereference=IGNORE [2018-07-24 15:16:10,125 INFO L133 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=IGNORE [2018-07-24 15:16:10,125 INFO L133 SettingsManager]: * Check array bounds for arrays that are off heap=IGNORE [2018-07-24 15:16:10,126 INFO L133 SettingsManager]: * Check if freed pointer was valid=false [2018-07-24 15:16:10,126 INFO L133 SettingsManager]: * Pointer base address is valid at dereference=IGNORE [2018-07-24 15:16:10,126 INFO L131 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2018-07-24 15:16:10,126 INFO L133 SettingsManager]: * Size of a code block=SequenceOfStatements [2018-07-24 15:16:10,128 INFO L133 SettingsManager]: * To the following directory=./dump/ [2018-07-24 15:16:10,128 INFO L133 SettingsManager]: * SMT solver=External_DefaultMode [2018-07-24 15:16:10,128 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 15:16:10,128 INFO L131 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2018-07-24 15:16:10,129 INFO L133 SettingsManager]: * Compute Interpolants along a Counterexample=FPandBP [2018-07-24 15:16:10,129 INFO L133 SettingsManager]: * Positions where we compute the Hoare Annotation=LoopsAndPotentialCycles [2018-07-24 15:16:10,129 INFO L133 SettingsManager]: * Trace refinement strategy=RUBBER_TAIPAN [2018-07-24 15:16:10,129 INFO L133 SettingsManager]: * SMT solver=External_ModelsAndUnsatCoreMode [2018-07-24 15:16:10,129 INFO L133 SettingsManager]: * Command for external solver=z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in [2018-07-24 15:16:10,129 INFO L133 SettingsManager]: * Compute Hoare Annotation of negated interpolant automaton, abstraction and CFG=true [2018-07-24 15:16:10,130 INFO L133 SettingsManager]: * To the following directory=dump/ [2018-07-24 15:16:10,130 INFO L133 SettingsManager]: * Abstract interpretation Mode=USE_PREDICATES [2018-07-24 15:16:10,205 INFO L81 nceAwareModelManager]: Repository-Root is: /tmp [2018-07-24 15:16:10,222 INFO L258 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2018-07-24 15:16:10,228 INFO L214 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2018-07-24 15:16:10,230 INFO L271 PluginConnector]: Initializing CDTParser... [2018-07-24 15:16:10,231 INFO L276 PluginConnector]: CDTParser initialized [2018-07-24 15:16:10,232 INFO L418 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/../../../trunk/examples/svcomp/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-07-24 15:16:10,575 INFO L220 CDTParser]: Created temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/51aae7510/5498908fd6834151b22d9ed113a88cd9/FLAG53e3ed58b [2018-07-24 15:16:10,772 INFO L276 CDTParser]: Found 1 translation units. [2018-07-24 15:16:10,773 INFO L158 CDTParser]: Scanning /storage/repos/ultimate/trunk/examples/svcomp/psyco/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-07-24 15:16:10,793 INFO L324 CDTParser]: About to delete temporary CDT project at /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/51aae7510/5498908fd6834151b22d9ed113a88cd9/FLAG53e3ed58b [2018-07-24 15:16:10,809 INFO L332 CDTParser]: Successfully deleted /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/data/51aae7510/5498908fd6834151b22d9ed113a88cd9 [2018-07-24 15:16:10,819 INFO L296 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2018-07-24 15:16:10,821 INFO L131 ToolchainWalker]: Walking toolchain with 5 elements. [2018-07-24 15:16:10,822 INFO L113 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2018-07-24 15:16:10,822 INFO L271 PluginConnector]: Initializing CACSL2BoogieTranslator... [2018-07-24 15:16:10,829 INFO L276 PluginConnector]: CACSL2BoogieTranslator initialized [2018-07-24 15:16:10,830 INFO L185 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 03:16:10" (1/1) ... [2018-07-24 15:16:10,833 INFO L205 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@15f06eb7 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:10, skipping insertion in model container [2018-07-24 15:16:10,833 INFO L185 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 24.07 03:16:10" (1/1) ... [2018-07-24 15:16:11,060 INFO L179 PRDispatcher]: Starting pre-run dispatcher in SV-COMP mode [2018-07-24 15:16:11,224 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 15:16:11,241 INFO L422 MainDispatcher]: Starting main dispatcher in SV-COMP mode [2018-07-24 15:16:11,322 INFO L175 PostProcessor]: Settings: Checked method=main [2018-07-24 15:16:11,360 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11 WrapperNode [2018-07-24 15:16:11,361 INFO L132 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2018-07-24 15:16:11,362 INFO L113 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2018-07-24 15:16:11,362 INFO L271 PluginConnector]: Initializing Boogie Procedure Inliner... [2018-07-24 15:16:11,362 INFO L276 PluginConnector]: Boogie Procedure Inliner initialized [2018-07-24 15:16:11,372 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,389 INFO L185 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,396 INFO L132 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2018-07-24 15:16:11,397 INFO L113 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2018-07-24 15:16:11,397 INFO L271 PluginConnector]: Initializing Boogie Preprocessor... [2018-07-24 15:16:11,397 INFO L276 PluginConnector]: Boogie Preprocessor initialized [2018-07-24 15:16:11,406 INFO L185 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,407 INFO L185 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,411 INFO L185 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,411 INFO L185 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,426 INFO L185 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,437 INFO L185 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,443 INFO L185 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... [2018-07-24 15:16:11,451 INFO L132 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2018-07-24 15:16:11,452 INFO L113 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2018-07-24 15:16:11,452 INFO L271 PluginConnector]: Initializing RCFGBuilder... [2018-07-24 15:16:11,452 INFO L276 PluginConnector]: RCFGBuilder initialized [2018-07-24 15:16:11,453 INFO L185 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (1/1) ... No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 1 with z3 SMTLIB2_COMPLIANT=true -memory:2024 -smt2 -in -t:2000 [2018-07-24 15:16:11,630 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.init [2018-07-24 15:16:11,631 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.init [2018-07-24 15:16:11,631 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2018-07-24 15:16:11,631 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2018-07-24 15:16:11,631 INFO L130 BoogieDeclarations]: Found specification of procedure main [2018-07-24 15:16:11,631 INFO L138 BoogieDeclarations]: Found implementation of procedure main [2018-07-24 15:16:13,170 INFO L261 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2018-07-24 15:16:13,172 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 03:16:13 BoogieIcfgContainer [2018-07-24 15:16:13,172 INFO L132 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2018-07-24 15:16:13,173 INFO L113 PluginConnector]: ------------------------TraceAbstraction---------------------------- [2018-07-24 15:16:13,173 INFO L271 PluginConnector]: Initializing TraceAbstraction... [2018-07-24 15:16:13,176 INFO L276 PluginConnector]: TraceAbstraction initialized [2018-07-24 15:16:13,177 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "CDTParser AST 24.07 03:16:10" (1/3) ... [2018-07-24 15:16:13,177 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5f9781ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 03:16:13, skipping insertion in model container [2018-07-24 15:16:13,178 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 24.07 03:16:11" (2/3) ... [2018-07-24 15:16:13,178 INFO L205 PluginConnector]: Invalid model from TraceAbstraction for observer de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction.TraceAbstractionObserver@5f9781ee and model type de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction AST 24.07 03:16:13, skipping insertion in model container [2018-07-24 15:16:13,178 INFO L185 PluginConnector]: Executing the observer TraceAbstractionObserver from plugin TraceAbstraction for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 24.07 03:16:13" (3/3) ... [2018-07-24 15:16:13,180 INFO L112 eAbstractionObserver]: Analyzing ICFG psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c [2018-07-24 15:16:13,190 INFO L132 ceAbstractionStarter]: Automizer settings: Hoare:true NWA Interpolation:FPandBP Determinization: PREDICATE_ABSTRACTION [2018-07-24 15:16:13,199 INFO L144 ceAbstractionStarter]: Appying trace abstraction to program that has 1 error locations. [2018-07-24 15:16:13,247 INFO L128 ementStrategyFactory]: Using default assertion order modulation [2018-07-24 15:16:13,248 INFO L373 AbstractCegarLoop]: Interprodecural is true [2018-07-24 15:16:13,248 INFO L374 AbstractCegarLoop]: Hoare is true [2018-07-24 15:16:13,248 INFO L375 AbstractCegarLoop]: Compute interpolants for FPandBP [2018-07-24 15:16:13,248 INFO L376 AbstractCegarLoop]: Backedges is STRAIGHT_LINE [2018-07-24 15:16:13,248 INFO L377 AbstractCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2018-07-24 15:16:13,249 INFO L378 AbstractCegarLoop]: Difference is false [2018-07-24 15:16:13,249 INFO L379 AbstractCegarLoop]: Minimize is MINIMIZE_SEVPA [2018-07-24 15:16:13,249 INFO L384 AbstractCegarLoop]: ======== Iteration 0==of CEGAR loop == AllErrorsAtOnce======== [2018-07-24 15:16:13,271 INFO L276 IsEmpty]: Start isEmpty. Operand 115 states. [2018-07-24 15:16:13,278 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 15 [2018-07-24 15:16:13,278 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:13,279 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:13,279 INFO L414 AbstractCegarLoop]: === Iteration 1 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:13,285 INFO L82 PathProgramCache]: Analyzing trace with hash -662778961, now seen corresponding path program 1 times [2018-07-24 15:16:13,288 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:13,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:13,338 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:13,338 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:13,339 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:13,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:13,459 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:13,461 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:13,462 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:13,462 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:13,467 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:13,478 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:13,479 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:13,481 INFO L87 Difference]: Start difference. First operand 115 states. Second operand 3 states. [2018-07-24 15:16:14,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:14,569 INFO L93 Difference]: Finished difference Result 331 states and 635 transitions. [2018-07-24 15:16:14,569 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:14,572 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 14 [2018-07-24 15:16:14,573 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:14,587 INFO L225 Difference]: With dead ends: 331 [2018-07-24 15:16:14,588 INFO L226 Difference]: Without dead ends: 206 [2018-07-24 15:16:14,592 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:14,610 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 206 states. [2018-07-24 15:16:14,644 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 206 to 182. [2018-07-24 15:16:14,645 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 182 states. [2018-07-24 15:16:14,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 182 states to 182 states and 314 transitions. [2018-07-24 15:16:14,651 INFO L78 Accepts]: Start accepts. Automaton has 182 states and 314 transitions. Word has length 14 [2018-07-24 15:16:14,652 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:14,653 INFO L471 AbstractCegarLoop]: Abstraction has 182 states and 314 transitions. [2018-07-24 15:16:14,653 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:14,653 INFO L276 IsEmpty]: Start isEmpty. Operand 182 states and 314 transitions. [2018-07-24 15:16:14,654 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 16 [2018-07-24 15:16:14,654 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:14,654 INFO L353 BasicCegarLoop]: trace histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:14,655 INFO L414 AbstractCegarLoop]: === Iteration 2 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:14,655 INFO L82 PathProgramCache]: Analyzing trace with hash -1058783719, now seen corresponding path program 1 times [2018-07-24 15:16:14,655 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:14,656 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:14,657 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:14,657 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:14,657 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:14,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:14,746 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:14,746 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:14,747 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:14,747 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:14,749 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:14,749 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:14,749 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:14,750 INFO L87 Difference]: Start difference. First operand 182 states and 314 transitions. Second operand 3 states. [2018-07-24 15:16:14,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:15,000 INFO L93 Difference]: Finished difference Result 365 states and 632 transitions. [2018-07-24 15:16:15,000 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:15,001 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 15 [2018-07-24 15:16:15,001 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:15,003 INFO L225 Difference]: With dead ends: 365 [2018-07-24 15:16:15,004 INFO L226 Difference]: Without dead ends: 189 [2018-07-24 15:16:15,006 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:15,007 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 189 states. [2018-07-24 15:16:15,021 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 189 to 189. [2018-07-24 15:16:15,021 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 189 states. [2018-07-24 15:16:15,023 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 189 states to 189 states and 322 transitions. [2018-07-24 15:16:15,024 INFO L78 Accepts]: Start accepts. Automaton has 189 states and 322 transitions. Word has length 15 [2018-07-24 15:16:15,024 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:15,024 INFO L471 AbstractCegarLoop]: Abstraction has 189 states and 322 transitions. [2018-07-24 15:16:15,024 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:15,024 INFO L276 IsEmpty]: Start isEmpty. Operand 189 states and 322 transitions. [2018-07-24 15:16:15,025 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 22 [2018-07-24 15:16:15,026 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:15,026 INFO L353 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:15,026 INFO L414 AbstractCegarLoop]: === Iteration 3 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:15,026 INFO L82 PathProgramCache]: Analyzing trace with hash -426524154, now seen corresponding path program 1 times [2018-07-24 15:16:15,027 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:15,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:15,028 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:15,028 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:15,028 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:15,076 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:15,236 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:15,237 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:15,237 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:15,237 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:15,237 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:15,238 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:15,238 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:15,238 INFO L87 Difference]: Start difference. First operand 189 states and 322 transitions. Second operand 3 states. [2018-07-24 15:16:15,842 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:15,843 INFO L93 Difference]: Finished difference Result 290 states and 484 transitions. [2018-07-24 15:16:15,843 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:15,843 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 21 [2018-07-24 15:16:15,844 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:15,846 INFO L225 Difference]: With dead ends: 290 [2018-07-24 15:16:15,846 INFO L226 Difference]: Without dead ends: 274 [2018-07-24 15:16:15,847 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:15,848 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 274 states. [2018-07-24 15:16:15,863 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 274 to 259. [2018-07-24 15:16:15,863 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 259 states. [2018-07-24 15:16:15,865 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 259 states to 259 states and 436 transitions. [2018-07-24 15:16:15,866 INFO L78 Accepts]: Start accepts. Automaton has 259 states and 436 transitions. Word has length 21 [2018-07-24 15:16:15,866 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:15,866 INFO L471 AbstractCegarLoop]: Abstraction has 259 states and 436 transitions. [2018-07-24 15:16:15,866 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:15,866 INFO L276 IsEmpty]: Start isEmpty. Operand 259 states and 436 transitions. [2018-07-24 15:16:15,867 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 23 [2018-07-24 15:16:15,868 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:15,868 INFO L353 BasicCegarLoop]: trace histogram [2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:15,868 INFO L414 AbstractCegarLoop]: === Iteration 4 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:15,868 INFO L82 PathProgramCache]: Analyzing trace with hash -1881066880, now seen corresponding path program 1 times [2018-07-24 15:16:15,868 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:15,869 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:15,870 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:15,870 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:15,870 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:15,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:15,922 INFO L134 CoverageAnalysis]: Checked inductivity of 3 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:15,922 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:15,922 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:15,923 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:15,923 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:15,923 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:15,924 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:15,924 INFO L87 Difference]: Start difference. First operand 259 states and 436 transitions. Second operand 3 states. [2018-07-24 15:16:16,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:16,031 INFO L93 Difference]: Finished difference Result 468 states and 791 transitions. [2018-07-24 15:16:16,032 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:16,032 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 22 [2018-07-24 15:16:16,032 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:16,034 INFO L225 Difference]: With dead ends: 468 [2018-07-24 15:16:16,034 INFO L226 Difference]: Without dead ends: 216 [2018-07-24 15:16:16,036 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:16,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216 states. [2018-07-24 15:16:16,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216 to 214. [2018-07-24 15:16:16,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 214 states. [2018-07-24 15:16:16,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214 states to 214 states and 355 transitions. [2018-07-24 15:16:16,049 INFO L78 Accepts]: Start accepts. Automaton has 214 states and 355 transitions. Word has length 22 [2018-07-24 15:16:16,049 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:16,050 INFO L471 AbstractCegarLoop]: Abstraction has 214 states and 355 transitions. [2018-07-24 15:16:16,050 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:16,050 INFO L276 IsEmpty]: Start isEmpty. Operand 214 states and 355 transitions. [2018-07-24 15:16:16,051 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 29 [2018-07-24 15:16:16,052 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:16,052 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:16,052 INFO L414 AbstractCegarLoop]: === Iteration 5 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:16,052 INFO L82 PathProgramCache]: Analyzing trace with hash 30525515, now seen corresponding path program 1 times [2018-07-24 15:16:16,053 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:16,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:16,054 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:16,054 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:16,054 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:16,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:16,241 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 11 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:16,241 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:16,241 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 2 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:16,251 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:16,252 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:16,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:16,322 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:16,361 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-07-24 15:16:16,361 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:16,390 INFO L134 CoverageAnalysis]: Checked inductivity of 13 backedges. 10 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-07-24 15:16:16,417 INFO L309 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-07-24 15:16:16,417 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [4] total 6 [2018-07-24 15:16:16,417 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:16,418 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:16,418 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:16,418 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-07-24 15:16:16,419 INFO L87 Difference]: Start difference. First operand 214 states and 355 transitions. Second operand 3 states. [2018-07-24 15:16:16,501 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:16,501 INFO L93 Difference]: Finished difference Result 389 states and 646 transitions. [2018-07-24 15:16:16,502 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:16,502 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 28 [2018-07-24 15:16:16,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:16,505 INFO L225 Difference]: With dead ends: 389 [2018-07-24 15:16:16,505 INFO L226 Difference]: Without dead ends: 182 [2018-07-24 15:16:16,506 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 59 GetRequests, 55 SyntacticMatches, 0 SemanticMatches, 4 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=11, Invalid=19, Unknown=0, NotChecked=0, Total=30 [2018-07-24 15:16:16,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 182 states. [2018-07-24 15:16:16,520 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 182 to 180. [2018-07-24 15:16:16,521 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 180 states. [2018-07-24 15:16:16,522 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 180 states to 180 states and 291 transitions. [2018-07-24 15:16:16,526 INFO L78 Accepts]: Start accepts. Automaton has 180 states and 291 transitions. Word has length 28 [2018-07-24 15:16:16,527 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:16,527 INFO L471 AbstractCegarLoop]: Abstraction has 180 states and 291 transitions. [2018-07-24 15:16:16,527 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:16,527 INFO L276 IsEmpty]: Start isEmpty. Operand 180 states and 291 transitions. [2018-07-24 15:16:16,528 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-07-24 15:16:16,529 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:16,529 INFO L353 BasicCegarLoop]: trace histogram [3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:16,529 INFO L414 AbstractCegarLoop]: === Iteration 6 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:16,529 INFO L82 PathProgramCache]: Analyzing trace with hash 1381236108, now seen corresponding path program 1 times [2018-07-24 15:16:16,529 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:16,530 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:16,531 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:16,531 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:16,531 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:16,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:16,669 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:16,670 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:16,670 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 3 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:16,686 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:16,687 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:16,740 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:16,744 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:16,749 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:16,750 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:17,023 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 8 proven. 2 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:17,052 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:17,052 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 4 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:17,076 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:17,076 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:17,154 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:17,161 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:17,234 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:17,235 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:17,352 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:17,354 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:17,354 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 8 [2018-07-24 15:16:17,355 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:17,355 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 15:16:17,355 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 15:16:17,355 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-07-24 15:16:17,356 INFO L87 Difference]: Start difference. First operand 180 states and 291 transitions. Second operand 4 states. [2018-07-24 15:16:17,731 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:17,731 INFO L93 Difference]: Finished difference Result 435 states and 706 transitions. [2018-07-24 15:16:17,732 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 15:16:17,733 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 30 [2018-07-24 15:16:17,733 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:17,736 INFO L225 Difference]: With dead ends: 435 [2018-07-24 15:16:17,736 INFO L226 Difference]: Without dead ends: 282 [2018-07-24 15:16:17,737 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 114 SyntacticMatches, 2 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=19, Invalid=37, Unknown=0, NotChecked=0, Total=56 [2018-07-24 15:16:17,738 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 282 states. [2018-07-24 15:16:17,746 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 282 to 245. [2018-07-24 15:16:17,747 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 245 states. [2018-07-24 15:16:17,748 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 408 transitions. [2018-07-24 15:16:17,748 INFO L78 Accepts]: Start accepts. Automaton has 245 states and 408 transitions. Word has length 30 [2018-07-24 15:16:17,749 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:17,749 INFO L471 AbstractCegarLoop]: Abstraction has 245 states and 408 transitions. [2018-07-24 15:16:17,749 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 15:16:17,749 INFO L276 IsEmpty]: Start isEmpty. Operand 245 states and 408 transitions. [2018-07-24 15:16:17,750 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 31 [2018-07-24 15:16:17,750 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:17,751 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:17,751 INFO L414 AbstractCegarLoop]: === Iteration 7 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:17,751 INFO L82 PathProgramCache]: Analyzing trace with hash 2061294478, now seen corresponding path program 1 times [2018-07-24 15:16:17,751 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:17,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:17,752 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:17,752 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:17,753 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:17,770 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:17,912 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:17,913 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:17,913 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 5 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:17,928 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:17,928 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:17,979 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:17,985 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:18,074 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:18,076 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:18,118 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:18,139 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:18,140 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 6 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:18,156 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:18,156 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:18,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:18,229 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:18,235 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:18,235 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:18,311 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:18,313 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:18,313 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 5 [2018-07-24 15:16:18,313 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:18,313 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 15:16:18,314 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 15:16:18,314 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-07-24 15:16:18,314 INFO L87 Difference]: Start difference. First operand 245 states and 408 transitions. Second operand 5 states. [2018-07-24 15:16:18,653 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:18,654 INFO L93 Difference]: Finished difference Result 464 states and 780 transitions. [2018-07-24 15:16:18,654 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 15:16:18,655 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 30 [2018-07-24 15:16:18,655 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:18,660 INFO L225 Difference]: With dead ends: 464 [2018-07-24 15:16:18,660 INFO L226 Difference]: Without dead ends: 452 [2018-07-24 15:16:18,661 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 122 GetRequests, 115 SyntacticMatches, 4 SemanticMatches, 3 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=8, Invalid=12, Unknown=0, NotChecked=0, Total=20 [2018-07-24 15:16:18,661 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 452 states. [2018-07-24 15:16:18,674 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 452 to 438. [2018-07-24 15:16:18,674 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 438 states. [2018-07-24 15:16:18,677 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 438 states to 438 states and 730 transitions. [2018-07-24 15:16:18,677 INFO L78 Accepts]: Start accepts. Automaton has 438 states and 730 transitions. Word has length 30 [2018-07-24 15:16:18,677 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:18,678 INFO L471 AbstractCegarLoop]: Abstraction has 438 states and 730 transitions. [2018-07-24 15:16:18,678 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 15:16:18,678 INFO L276 IsEmpty]: Start isEmpty. Operand 438 states and 730 transitions. [2018-07-24 15:16:18,679 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 32 [2018-07-24 15:16:18,679 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:18,679 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:18,680 INFO L414 AbstractCegarLoop]: === Iteration 8 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:18,680 INFO L82 PathProgramCache]: Analyzing trace with hash -512937066, now seen corresponding path program 1 times [2018-07-24 15:16:18,680 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:18,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:18,681 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:18,681 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:18,681 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:18,709 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:18,847 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:18,847 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:18,847 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 7 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:18,855 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:18,856 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:18,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:18,908 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:19,133 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:19,134 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:19,242 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:19,263 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:19,264 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 8 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:19,280 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:19,280 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:19,363 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:19,370 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:19,401 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:19,401 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:19,469 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 6 proven. 4 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:19,471 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:19,471 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 7 [2018-07-24 15:16:19,471 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:19,472 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 15:16:19,472 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 15:16:19,474 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-07-24 15:16:19,474 INFO L87 Difference]: Start difference. First operand 438 states and 730 transitions. Second operand 5 states. [2018-07-24 15:16:19,769 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:19,769 INFO L93 Difference]: Finished difference Result 495 states and 817 transitions. [2018-07-24 15:16:19,770 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 15:16:19,770 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 31 [2018-07-24 15:16:19,770 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:19,773 INFO L225 Difference]: With dead ends: 495 [2018-07-24 15:16:19,774 INFO L226 Difference]: Without dead ends: 490 [2018-07-24 15:16:19,774 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 126 GetRequests, 119 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 6 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=15, Invalid=27, Unknown=0, NotChecked=0, Total=42 [2018-07-24 15:16:19,775 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 490 states. [2018-07-24 15:16:19,788 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 490 to 484. [2018-07-24 15:16:19,788 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 484 states. [2018-07-24 15:16:19,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 484 states to 484 states and 802 transitions. [2018-07-24 15:16:19,791 INFO L78 Accepts]: Start accepts. Automaton has 484 states and 802 transitions. Word has length 31 [2018-07-24 15:16:19,792 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:19,792 INFO L471 AbstractCegarLoop]: Abstraction has 484 states and 802 transitions. [2018-07-24 15:16:19,792 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 15:16:19,792 INFO L276 IsEmpty]: Start isEmpty. Operand 484 states and 802 transitions. [2018-07-24 15:16:19,793 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 33 [2018-07-24 15:16:19,793 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:19,794 INFO L353 BasicCegarLoop]: trace histogram [3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:19,794 INFO L414 AbstractCegarLoop]: === Iteration 9 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:19,794 INFO L82 PathProgramCache]: Analyzing trace with hash 325020427, now seen corresponding path program 1 times [2018-07-24 15:16:19,794 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:19,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:19,795 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:19,795 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:19,796 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:19,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:19,877 INFO L134 CoverageAnalysis]: Checked inductivity of 10 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2018-07-24 15:16:19,877 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:19,877 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:19,878 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:19,878 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:19,879 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:19,879 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:19,879 INFO L87 Difference]: Start difference. First operand 484 states and 802 transitions. Second operand 3 states. [2018-07-24 15:16:20,140 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:20,141 INFO L93 Difference]: Finished difference Result 949 states and 1566 transitions. [2018-07-24 15:16:20,141 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:20,141 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 32 [2018-07-24 15:16:20,142 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:20,145 INFO L225 Difference]: With dead ends: 949 [2018-07-24 15:16:20,145 INFO L226 Difference]: Without dead ends: 495 [2018-07-24 15:16:20,147 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:20,148 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states. [2018-07-24 15:16:20,161 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 493. [2018-07-24 15:16:20,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-07-24 15:16:20,165 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 794 transitions. [2018-07-24 15:16:20,165 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 794 transitions. Word has length 32 [2018-07-24 15:16:20,165 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:20,165 INFO L471 AbstractCegarLoop]: Abstraction has 493 states and 794 transitions. [2018-07-24 15:16:20,166 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:20,166 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 794 transitions. [2018-07-24 15:16:20,167 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 41 [2018-07-24 15:16:20,167 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:20,167 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:20,167 INFO L414 AbstractCegarLoop]: === Iteration 10 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:20,168 INFO L82 PathProgramCache]: Analyzing trace with hash 2019699710, now seen corresponding path program 1 times [2018-07-24 15:16:20,168 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:20,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:20,169 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:20,169 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:20,169 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:20,184 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:20,261 INFO L134 CoverageAnalysis]: Checked inductivity of 24 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:20,261 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:20,261 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:20,262 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:20,262 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:20,262 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:20,262 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:20,263 INFO L87 Difference]: Start difference. First operand 493 states and 794 transitions. Second operand 3 states. [2018-07-24 15:16:20,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:20,527 INFO L93 Difference]: Finished difference Result 939 states and 1525 transitions. [2018-07-24 15:16:20,527 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:20,527 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 40 [2018-07-24 15:16:20,528 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:20,531 INFO L225 Difference]: With dead ends: 939 [2018-07-24 15:16:20,531 INFO L226 Difference]: Without dead ends: 495 [2018-07-24 15:16:20,533 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:20,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 495 states. [2018-07-24 15:16:20,546 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 495 to 493. [2018-07-24 15:16:20,546 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 493 states. [2018-07-24 15:16:20,549 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 493 states to 493 states and 788 transitions. [2018-07-24 15:16:20,549 INFO L78 Accepts]: Start accepts. Automaton has 493 states and 788 transitions. Word has length 40 [2018-07-24 15:16:20,549 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:20,549 INFO L471 AbstractCegarLoop]: Abstraction has 493 states and 788 transitions. [2018-07-24 15:16:20,549 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:20,550 INFO L276 IsEmpty]: Start isEmpty. Operand 493 states and 788 transitions. [2018-07-24 15:16:20,550 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 42 [2018-07-24 15:16:20,550 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:20,551 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:20,551 INFO L414 AbstractCegarLoop]: === Iteration 11 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:20,551 INFO L82 PathProgramCache]: Analyzing trace with hash 937434793, now seen corresponding path program 1 times [2018-07-24 15:16:20,551 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:20,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:20,552 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:20,552 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:20,552 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:20,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:21,034 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 14 proven. 8 refuted. 0 times theorem prover too weak. 1 trivial. 0 not checked. [2018-07-24 15:16:21,034 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:21,034 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 9 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:21,044 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:21,044 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:21,089 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:21,093 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:21,148 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:21,148 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:21,627 WARN L169 SmtUtils]: Spent 267.00 ms on a formula simplification. DAG size of input: 62 DAG size of output: 6 [2018-07-24 15:16:21,764 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:21,796 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:21,797 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 10 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:21,822 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:21,822 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:21,922 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:21,930 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:21,948 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:21,948 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:22,068 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 8 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:22,070 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:22,071 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 5, 5, 5, 5] total 10 [2018-07-24 15:16:22,071 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:22,071 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 15:16:22,073 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 15:16:22,074 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=27, Invalid=63, Unknown=0, NotChecked=0, Total=90 [2018-07-24 15:16:22,074 INFO L87 Difference]: Start difference. First operand 493 states and 788 transitions. Second operand 7 states. [2018-07-24 15:16:23,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:23,720 INFO L93 Difference]: Finished difference Result 1026 states and 1635 transitions. [2018-07-24 15:16:23,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 15:16:23,721 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 41 [2018-07-24 15:16:23,722 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:23,725 INFO L225 Difference]: With dead ends: 1026 [2018-07-24 15:16:23,726 INFO L226 Difference]: Without dead ends: 575 [2018-07-24 15:16:23,727 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 159 SyntacticMatches, 3 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 23 ImplicationChecksByTransitivity, 1.0s TimeCoverageRelationStatistics Valid=32, Invalid=78, Unknown=0, NotChecked=0, Total=110 [2018-07-24 15:16:23,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 575 states. [2018-07-24 15:16:23,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 575 to 544. [2018-07-24 15:16:23,743 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-07-24 15:16:23,745 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 867 transitions. [2018-07-24 15:16:23,746 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 867 transitions. Word has length 41 [2018-07-24 15:16:23,746 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:23,746 INFO L471 AbstractCegarLoop]: Abstraction has 544 states and 867 transitions. [2018-07-24 15:16:23,746 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 15:16:23,747 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 867 transitions. [2018-07-24 15:16:23,747 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 43 [2018-07-24 15:16:23,747 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:23,747 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:23,748 INFO L414 AbstractCegarLoop]: === Iteration 12 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:23,748 INFO L82 PathProgramCache]: Analyzing trace with hash -992845957, now seen corresponding path program 1 times [2018-07-24 15:16:23,748 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:23,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:23,749 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:23,749 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:23,750 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:23,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:23,865 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 15:16:23,865 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:23,866 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 11 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:23,879 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:23,879 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:23,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:23,921 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:23,934 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 15:16:23,934 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:24,061 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 15:16:24,096 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:24,096 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 12 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:24,127 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:24,128 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:24,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:24,236 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:24,359 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 15:16:24,359 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:24,497 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 10 refuted. 0 times theorem prover too weak. 4 trivial. 0 not checked. [2018-07-24 15:16:24,499 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:24,500 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [4, 4, 4, 4, 4] total 4 [2018-07-24 15:16:24,500 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:24,500 INFO L450 AbstractCegarLoop]: Interpolant automaton has 4 states [2018-07-24 15:16:24,501 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2018-07-24 15:16:24,501 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-07-24 15:16:24,502 INFO L87 Difference]: Start difference. First operand 544 states and 867 transitions. Second operand 4 states. [2018-07-24 15:16:24,989 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:24,989 INFO L93 Difference]: Finished difference Result 558 states and 879 transitions. [2018-07-24 15:16:24,989 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2018-07-24 15:16:24,990 INFO L78 Accepts]: Start accepts. Automaton has 4 states. Word has length 42 [2018-07-24 15:16:24,990 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:24,994 INFO L225 Difference]: With dead ends: 558 [2018-07-24 15:16:24,994 INFO L226 Difference]: Without dead ends: 546 [2018-07-24 15:16:24,994 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 171 GetRequests, 160 SyntacticMatches, 9 SemanticMatches, 2 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2018-07-24 15:16:24,995 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 546 states. [2018-07-24 15:16:25,010 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 546 to 544. [2018-07-24 15:16:25,010 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-07-24 15:16:25,012 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 841 transitions. [2018-07-24 15:16:25,012 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 841 transitions. Word has length 42 [2018-07-24 15:16:25,012 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:25,012 INFO L471 AbstractCegarLoop]: Abstraction has 544 states and 841 transitions. [2018-07-24 15:16:25,013 INFO L472 AbstractCegarLoop]: Interpolant automaton has 4 states. [2018-07-24 15:16:25,013 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 841 transitions. [2018-07-24 15:16:25,013 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 45 [2018-07-24 15:16:25,013 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:25,013 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:25,014 INFO L414 AbstractCegarLoop]: === Iteration 13 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:25,014 INFO L82 PathProgramCache]: Analyzing trace with hash -275920596, now seen corresponding path program 1 times [2018-07-24 15:16:25,014 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:25,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:25,015 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:25,015 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:25,015 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:25,056 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:25,224 WARN L169 SmtUtils]: Spent 101.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-07-24 15:16:25,362 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:25,362 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:25,362 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 13 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:25,371 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:25,371 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:25,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:25,420 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:25,469 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:25,469 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:25,879 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:25,900 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:25,901 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 14 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:25,916 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:25,916 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:26,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:26,026 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:26,066 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:26,066 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:26,361 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 9 proven. 14 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:26,366 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:26,367 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 15:16:26,367 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:26,368 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 15:16:26,368 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 15:16:26,368 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-07-24 15:16:26,368 INFO L87 Difference]: Start difference. First operand 544 states and 841 transitions. Second operand 5 states. [2018-07-24 15:16:26,782 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:26,783 INFO L93 Difference]: Finished difference Result 553 states and 848 transitions. [2018-07-24 15:16:26,783 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 15:16:26,783 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 44 [2018-07-24 15:16:26,784 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:26,787 INFO L225 Difference]: With dead ends: 553 [2018-07-24 15:16:26,788 INFO L226 Difference]: Without dead ends: 551 [2018-07-24 15:16:26,788 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 180 GetRequests, 168 SyntacticMatches, 6 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 8 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=16, Invalid=40, Unknown=0, NotChecked=0, Total=56 [2018-07-24 15:16:26,789 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-07-24 15:16:26,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 545. [2018-07-24 15:16:26,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 545 states. [2018-07-24 15:16:26,806 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 842 transitions. [2018-07-24 15:16:26,806 INFO L78 Accepts]: Start accepts. Automaton has 545 states and 842 transitions. Word has length 44 [2018-07-24 15:16:26,807 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:26,807 INFO L471 AbstractCegarLoop]: Abstraction has 545 states and 842 transitions. [2018-07-24 15:16:26,807 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 15:16:26,807 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 842 transitions. [2018-07-24 15:16:26,808 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 46 [2018-07-24 15:16:26,808 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:26,808 INFO L353 BasicCegarLoop]: trace histogram [4, 4, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:26,808 INFO L414 AbstractCegarLoop]: === Iteration 14 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:26,808 INFO L82 PathProgramCache]: Analyzing trace with hash 161633879, now seen corresponding path program 1 times [2018-07-24 15:16:26,809 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:26,809 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:26,810 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:26,810 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:26,810 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:26,821 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:26,888 INFO L134 CoverageAnalysis]: Checked inductivity of 23 backedges. 13 proven. 0 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:26,889 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:26,889 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:26,889 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:26,889 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:26,890 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:26,890 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:26,890 INFO L87 Difference]: Start difference. First operand 545 states and 842 transitions. Second operand 3 states. [2018-07-24 15:16:27,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:27,026 INFO L93 Difference]: Finished difference Result 1053 states and 1621 transitions. [2018-07-24 15:16:27,026 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:27,027 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 45 [2018-07-24 15:16:27,027 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:27,029 INFO L225 Difference]: With dead ends: 1053 [2018-07-24 15:16:27,030 INFO L226 Difference]: Without dead ends: 557 [2018-07-24 15:16:27,031 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:27,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states. [2018-07-24 15:16:27,047 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 555. [2018-07-24 15:16:27,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 555 states. [2018-07-24 15:16:27,049 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 555 states to 555 states and 835 transitions. [2018-07-24 15:16:27,049 INFO L78 Accepts]: Start accepts. Automaton has 555 states and 835 transitions. Word has length 45 [2018-07-24 15:16:27,049 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:27,049 INFO L471 AbstractCegarLoop]: Abstraction has 555 states and 835 transitions. [2018-07-24 15:16:27,049 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:27,049 INFO L276 IsEmpty]: Start isEmpty. Operand 555 states and 835 transitions. [2018-07-24 15:16:27,050 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 56 [2018-07-24 15:16:27,050 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:27,050 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:27,051 INFO L414 AbstractCegarLoop]: === Iteration 15 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:27,051 INFO L82 PathProgramCache]: Analyzing trace with hash 1614817955, now seen corresponding path program 1 times [2018-07-24 15:16:27,051 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:27,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:27,052 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:27,052 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:27,052 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:27,064 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:27,142 INFO L134 CoverageAnalysis]: Checked inductivity of 45 backedges. 22 proven. 0 refuted. 0 times theorem prover too weak. 23 trivial. 0 not checked. [2018-07-24 15:16:27,143 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 0 imperfect interpolant sequences. [2018-07-24 15:16:27,143 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2018-07-24 15:16:27,143 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:16:27,143 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:16:27,144 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:16:27,144 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:27,144 INFO L87 Difference]: Start difference. First operand 555 states and 835 transitions. Second operand 3 states. [2018-07-24 15:16:27,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:27,286 INFO L93 Difference]: Finished difference Result 799 states and 1202 transitions. [2018-07-24 15:16:27,289 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:16:27,290 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 55 [2018-07-24 15:16:27,290 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:27,291 INFO L225 Difference]: With dead ends: 799 [2018-07-24 15:16:27,291 INFO L226 Difference]: Without dead ends: 313 [2018-07-24 15:16:27,293 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 3 GetRequests, 2 SyntacticMatches, 0 SemanticMatches, 1 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.0s TimeCoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2018-07-24 15:16:27,293 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 313 states. [2018-07-24 15:16:27,301 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 313 to 311. [2018-07-24 15:16:27,302 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 311 states. [2018-07-24 15:16:27,303 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 311 states to 311 states and 454 transitions. [2018-07-24 15:16:27,303 INFO L78 Accepts]: Start accepts. Automaton has 311 states and 454 transitions. Word has length 55 [2018-07-24 15:16:27,303 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:27,303 INFO L471 AbstractCegarLoop]: Abstraction has 311 states and 454 transitions. [2018-07-24 15:16:27,304 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:16:27,304 INFO L276 IsEmpty]: Start isEmpty. Operand 311 states and 454 transitions. [2018-07-24 15:16:27,304 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 15:16:27,304 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:27,304 INFO L353 BasicCegarLoop]: trace histogram [5, 4, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:27,305 INFO L414 AbstractCegarLoop]: === Iteration 16 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:27,305 INFO L82 PathProgramCache]: Analyzing trace with hash 1860919614, now seen corresponding path program 1 times [2018-07-24 15:16:27,305 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:27,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:27,306 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:27,306 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:27,306 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:27,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:27,567 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:27,568 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:27,568 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 15 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:27,584 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:27,584 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:27,639 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:27,642 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:27,652 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:27,652 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:27,800 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:27,821 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:27,821 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 16 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:27,839 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:27,839 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:27,939 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:27,945 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:27,950 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:27,950 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:27,978 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 23 proven. 14 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:27,979 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:27,979 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 5, 5, 5] total 8 [2018-07-24 15:16:27,979 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:27,980 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 15:16:27,980 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 15:16:27,980 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 15:16:27,980 INFO L87 Difference]: Start difference. First operand 311 states and 454 transitions. Second operand 5 states. [2018-07-24 15:16:28,405 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:28,405 INFO L93 Difference]: Finished difference Result 660 states and 968 transitions. [2018-07-24 15:16:28,405 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 15:16:28,405 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-07-24 15:16:28,405 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:28,407 INFO L225 Difference]: With dead ends: 660 [2018-07-24 15:16:28,407 INFO L226 Difference]: Without dead ends: 418 [2018-07-24 15:16:28,408 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 222 SyntacticMatches, 0 SemanticMatches, 6 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.3s TimeCoverageRelationStatistics Valid=28, Invalid=28, Unknown=0, NotChecked=0, Total=56 [2018-07-24 15:16:28,409 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 418 states. [2018-07-24 15:16:28,419 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 418 to 389. [2018-07-24 15:16:28,420 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 389 states. [2018-07-24 15:16:28,421 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 389 states to 389 states and 573 transitions. [2018-07-24 15:16:28,421 INFO L78 Accepts]: Start accepts. Automaton has 389 states and 573 transitions. Word has length 56 [2018-07-24 15:16:28,421 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:28,421 INFO L471 AbstractCegarLoop]: Abstraction has 389 states and 573 transitions. [2018-07-24 15:16:28,421 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 15:16:28,422 INFO L276 IsEmpty]: Start isEmpty. Operand 389 states and 573 transitions. [2018-07-24 15:16:28,422 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 57 [2018-07-24 15:16:28,422 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:28,422 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:28,423 INFO L414 AbstractCegarLoop]: === Iteration 17 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:28,423 INFO L82 PathProgramCache]: Analyzing trace with hash 2119085052, now seen corresponding path program 1 times [2018-07-24 15:16:28,423 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:28,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:28,424 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:28,424 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:28,424 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:28,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:28,566 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:28,567 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:28,567 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 17 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:28,576 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:28,576 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:28,635 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:28,637 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:28,669 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:28,669 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:28,740 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 21 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:28,760 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:28,761 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 18 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:28,781 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:28,781 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:28,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:28,910 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:28,948 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 25 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:28,948 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:29,007 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 21 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:29,010 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:29,011 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [5, 5, 4, 5, 4] total 7 [2018-07-24 15:16:29,011 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:29,011 INFO L450 AbstractCegarLoop]: Interpolant automaton has 5 states [2018-07-24 15:16:29,012 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2018-07-24 15:16:29,012 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-07-24 15:16:29,012 INFO L87 Difference]: Start difference. First operand 389 states and 573 transitions. Second operand 5 states. [2018-07-24 15:16:29,226 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:29,226 INFO L93 Difference]: Finished difference Result 436 states and 639 transitions. [2018-07-24 15:16:29,227 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 5 states. [2018-07-24 15:16:29,227 INFO L78 Accepts]: Start accepts. Automaton has 5 states. Word has length 56 [2018-07-24 15:16:29,227 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:29,229 INFO L225 Difference]: With dead ends: 436 [2018-07-24 15:16:29,229 INFO L226 Difference]: Without dead ends: 430 [2018-07-24 15:16:29,232 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 228 GetRequests, 221 SyntacticMatches, 2 SemanticMatches, 5 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=14, Invalid=28, Unknown=0, NotChecked=0, Total=42 [2018-07-24 15:16:29,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 430 states. [2018-07-24 15:16:29,244 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 430 to 427. [2018-07-24 15:16:29,245 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 427 states. [2018-07-24 15:16:29,246 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 627 transitions. [2018-07-24 15:16:29,246 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 627 transitions. Word has length 56 [2018-07-24 15:16:29,247 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:29,247 INFO L471 AbstractCegarLoop]: Abstraction has 427 states and 627 transitions. [2018-07-24 15:16:29,247 INFO L472 AbstractCegarLoop]: Interpolant automaton has 5 states. [2018-07-24 15:16:29,247 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 627 transitions. [2018-07-24 15:16:29,247 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 61 [2018-07-24 15:16:29,248 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:29,248 INFO L353 BasicCegarLoop]: trace histogram [5, 5, 4, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:29,248 INFO L414 AbstractCegarLoop]: === Iteration 18 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:29,248 INFO L82 PathProgramCache]: Analyzing trace with hash 807144158, now seen corresponding path program 1 times [2018-07-24 15:16:29,248 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:29,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:29,249 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:29,249 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:29,250 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:29,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:29,487 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:29,488 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:29,488 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 19 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:29,496 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:29,496 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:29,546 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:29,548 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:29,850 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:29,850 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:30,360 WARN L169 SmtUtils]: Spent 320.00 ms on a formula simplification. DAG size of input: 21 DAG size of output: 13 [2018-07-24 15:16:30,466 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:30,487 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:30,487 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 20 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:30,503 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:30,503 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:30,630 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:30,636 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:30,685 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:30,686 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:30,934 INFO L134 CoverageAnalysis]: Checked inductivity of 43 backedges. 12 proven. 31 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:30,936 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:30,936 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 6, 6, 6, 7] total 19 [2018-07-24 15:16:30,936 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:30,936 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 15:16:30,937 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 15:16:30,937 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=61, Invalid=281, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:16:30,937 INFO L87 Difference]: Start difference. First operand 427 states and 627 transitions. Second operand 10 states. [2018-07-24 15:16:31,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:31,521 INFO L93 Difference]: Finished difference Result 430 states and 629 transitions. [2018-07-24 15:16:31,523 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 15:16:31,524 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 60 [2018-07-24 15:16:31,524 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:31,526 INFO L225 Difference]: With dead ends: 430 [2018-07-24 15:16:31,526 INFO L226 Difference]: Without dead ends: 428 [2018-07-24 15:16:31,527 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 247 GetRequests, 225 SyntacticMatches, 4 SemanticMatches, 18 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 102 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=68, Invalid=312, Unknown=0, NotChecked=0, Total=380 [2018-07-24 15:16:31,527 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 428 states. [2018-07-24 15:16:31,541 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 428 to 427. [2018-07-24 15:16:31,541 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 427 states. [2018-07-24 15:16:31,543 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 427 states to 427 states and 626 transitions. [2018-07-24 15:16:31,543 INFO L78 Accepts]: Start accepts. Automaton has 427 states and 626 transitions. Word has length 60 [2018-07-24 15:16:31,544 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:31,544 INFO L471 AbstractCegarLoop]: Abstraction has 427 states and 626 transitions. [2018-07-24 15:16:31,544 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 15:16:31,544 INFO L276 IsEmpty]: Start isEmpty. Operand 427 states and 626 transitions. [2018-07-24 15:16:31,545 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 68 [2018-07-24 15:16:31,545 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:31,545 INFO L353 BasicCegarLoop]: trace histogram [6, 6, 5, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:31,545 INFO L414 AbstractCegarLoop]: === Iteration 19 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:31,545 INFO L82 PathProgramCache]: Analyzing trace with hash -743255307, now seen corresponding path program 1 times [2018-07-24 15:16:31,546 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:31,546 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:31,546 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:31,547 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:31,547 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:31,634 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:31,879 WARN L169 SmtUtils]: Spent 103.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-07-24 15:16:32,058 WARN L169 SmtUtils]: Spent 127.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-07-24 15:16:32,312 WARN L169 SmtUtils]: Spent 175.00 ms on a formula simplification. DAG size of input: 16 DAG size of output: 14 [2018-07-24 15:16:32,402 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:32,402 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:32,402 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 21 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:32,411 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:32,411 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:32,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:32,480 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:32,651 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:32,652 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:33,182 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 44 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:33,213 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:33,213 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 22 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:33,240 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:33,241 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:33,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:33,421 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:33,531 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 50 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:33,531 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:33,678 INFO L134 CoverageAnalysis]: Checked inductivity of 65 backedges. 15 proven. 44 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2018-07-24 15:16:33,680 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:33,680 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 7, 8, 7] total 14 [2018-07-24 15:16:33,680 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:33,681 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 15:16:33,681 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 15:16:33,681 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=37, Invalid=145, Unknown=0, NotChecked=0, Total=182 [2018-07-24 15:16:33,682 INFO L87 Difference]: Start difference. First operand 427 states and 626 transitions. Second operand 9 states. [2018-07-24 15:16:34,074 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:34,074 INFO L93 Difference]: Finished difference Result 431 states and 630 transitions. [2018-07-24 15:16:34,075 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 15:16:34,075 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 67 [2018-07-24 15:16:34,075 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:34,077 INFO L225 Difference]: With dead ends: 431 [2018-07-24 15:16:34,078 INFO L226 Difference]: Without dead ends: 429 [2018-07-24 15:16:34,078 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 276 GetRequests, 251 SyntacticMatches, 12 SemanticMatches, 13 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 68 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=42, Invalid=168, Unknown=0, NotChecked=0, Total=210 [2018-07-24 15:16:34,079 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 429 states. [2018-07-24 15:16:34,090 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 429 to 428. [2018-07-24 15:16:34,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 428 states. [2018-07-24 15:16:34,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 428 states to 428 states and 627 transitions. [2018-07-24 15:16:34,091 INFO L78 Accepts]: Start accepts. Automaton has 428 states and 627 transitions. Word has length 67 [2018-07-24 15:16:34,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:34,092 INFO L471 AbstractCegarLoop]: Abstraction has 428 states and 627 transitions. [2018-07-24 15:16:34,092 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 15:16:34,092 INFO L276 IsEmpty]: Start isEmpty. Operand 428 states and 627 transitions. [2018-07-24 15:16:34,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 15:16:34,093 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:34,093 INFO L353 BasicCegarLoop]: trace histogram [7, 6, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:34,093 INFO L414 AbstractCegarLoop]: === Iteration 20 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:34,093 INFO L82 PathProgramCache]: Analyzing trace with hash -1746386041, now seen corresponding path program 1 times [2018-07-24 15:16:34,094 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:34,094 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:34,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:34,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:34,095 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:34,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:34,237 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:34,237 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:34,238 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 23 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:34,246 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:34,246 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:34,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:34,315 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:34,322 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:34,323 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:34,373 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:34,393 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:34,394 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 24 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:34,408 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:34,409 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:34,554 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:34,560 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:34,566 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:34,566 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:34,575 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 38 proven. 50 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:34,576 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:34,576 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [6, 6, 6, 6, 6] total 10 [2018-07-24 15:16:34,576 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:34,577 INFO L450 AbstractCegarLoop]: Interpolant automaton has 6 states [2018-07-24 15:16:34,577 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 6 interpolants. [2018-07-24 15:16:34,577 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 15:16:34,577 INFO L87 Difference]: Start difference. First operand 428 states and 627 transitions. Second operand 6 states. [2018-07-24 15:16:34,823 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:34,823 INFO L93 Difference]: Finished difference Result 865 states and 1269 transitions. [2018-07-24 15:16:34,825 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2018-07-24 15:16:34,825 INFO L78 Accepts]: Start accepts. Automaton has 6 states. Word has length 77 [2018-07-24 15:16:34,825 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:34,827 INFO L225 Difference]: With dead ends: 865 [2018-07-24 15:16:34,828 INFO L226 Difference]: Without dead ends: 545 [2018-07-24 15:16:34,828 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 314 GetRequests, 306 SyntacticMatches, 0 SemanticMatches, 8 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=45, Invalid=45, Unknown=0, NotChecked=0, Total=90 [2018-07-24 15:16:34,829 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545 states. [2018-07-24 15:16:34,842 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545 to 506. [2018-07-24 15:16:34,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 506 states. [2018-07-24 15:16:34,844 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 506 states to 506 states and 746 transitions. [2018-07-24 15:16:34,844 INFO L78 Accepts]: Start accepts. Automaton has 506 states and 746 transitions. Word has length 77 [2018-07-24 15:16:34,844 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:34,844 INFO L471 AbstractCegarLoop]: Abstraction has 506 states and 746 transitions. [2018-07-24 15:16:34,844 INFO L472 AbstractCegarLoop]: Interpolant automaton has 6 states. [2018-07-24 15:16:34,844 INFO L276 IsEmpty]: Start isEmpty. Operand 506 states and 746 transitions. [2018-07-24 15:16:34,845 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 78 [2018-07-24 15:16:34,845 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:34,845 INFO L353 BasicCegarLoop]: trace histogram [7, 7, 6, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:34,845 INFO L414 AbstractCegarLoop]: === Iteration 21 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:34,846 INFO L82 PathProgramCache]: Analyzing trace with hash -2139413051, now seen corresponding path program 1 times [2018-07-24 15:16:34,846 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:34,846 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:34,846 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:34,847 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:34,847 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:34,863 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:35,733 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:35,734 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:35,734 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 25 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:35,742 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:35,743 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:35,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:35,812 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:35,905 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 70 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:35,905 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:36,278 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 35 proven. 43 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:36,299 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:36,299 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 26 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:36,315 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:36,315 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:36,478 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:36,485 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:36,539 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 80 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:36,540 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:36,648 INFO L134 CoverageAnalysis]: Checked inductivity of 98 backedges. 18 proven. 73 refuted. 0 times theorem prover too weak. 7 trivial. 0 not checked. [2018-07-24 15:16:36,649 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:36,650 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 6, 8, 7] total 21 [2018-07-24 15:16:36,650 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:36,650 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 15:16:36,650 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 15:16:36,651 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=75, Invalid=345, Unknown=0, NotChecked=0, Total=420 [2018-07-24 15:16:36,651 INFO L87 Difference]: Start difference. First operand 506 states and 746 transitions. Second operand 12 states. [2018-07-24 15:16:37,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:37,150 INFO L93 Difference]: Finished difference Result 529 states and 778 transitions. [2018-07-24 15:16:37,151 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 15:16:37,151 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 77 [2018-07-24 15:16:37,152 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:37,154 INFO L225 Difference]: With dead ends: 529 [2018-07-24 15:16:37,154 INFO L226 Difference]: Without dead ends: 525 [2018-07-24 15:16:37,155 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 315 GetRequests, 293 SyntacticMatches, 2 SemanticMatches, 20 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 92 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=83, Invalid=379, Unknown=0, NotChecked=0, Total=462 [2018-07-24 15:16:37,155 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 525 states. [2018-07-24 15:16:37,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 525 to 525. [2018-07-24 15:16:37,170 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 525 states. [2018-07-24 15:16:37,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 525 states to 525 states and 772 transitions. [2018-07-24 15:16:37,171 INFO L78 Accepts]: Start accepts. Automaton has 525 states and 772 transitions. Word has length 77 [2018-07-24 15:16:37,172 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:37,172 INFO L471 AbstractCegarLoop]: Abstraction has 525 states and 772 transitions. [2018-07-24 15:16:37,172 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 15:16:37,172 INFO L276 IsEmpty]: Start isEmpty. Operand 525 states and 772 transitions. [2018-07-24 15:16:37,173 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 88 [2018-07-24 15:16:37,173 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:37,173 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:37,173 INFO L414 AbstractCegarLoop]: === Iteration 22 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:37,174 INFO L82 PathProgramCache]: Analyzing trace with hash -1314627048, now seen corresponding path program 1 times [2018-07-24 15:16:37,174 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:37,174 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:37,175 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:37,175 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:37,175 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:37,194 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:37,847 WARN L169 SmtUtils]: Spent 267.00 ms on a formula simplification. DAG size of input: 13 DAG size of output: 10 [2018-07-24 15:16:38,141 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 26 proven. 99 refuted. 0 times theorem prover too weak. 11 trivial. 0 not checked. [2018-07-24 15:16:38,141 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:38,141 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 27 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:38,153 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:38,153 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:38,229 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:38,232 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:38,293 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 99 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:38,293 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:38,630 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 58 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2018-07-24 15:16:38,651 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:38,651 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 28 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:38,667 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:38,667 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:38,878 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:38,886 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:38,906 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 99 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:38,906 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:39,767 INFO L134 CoverageAnalysis]: Checked inductivity of 136 backedges. 21 proven. 58 refuted. 0 times theorem prover too weak. 57 trivial. 0 not checked. [2018-07-24 15:16:39,769 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:39,769 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 7, 5, 7, 5] total 12 [2018-07-24 15:16:39,769 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:39,770 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 15:16:39,770 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 15:16:39,770 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=33, Invalid=99, Unknown=0, NotChecked=0, Total=132 [2018-07-24 15:16:39,770 INFO L87 Difference]: Start difference. First operand 525 states and 772 transitions. Second operand 9 states. [2018-07-24 15:16:40,066 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:40,067 INFO L93 Difference]: Finished difference Result 555 states and 810 transitions. [2018-07-24 15:16:40,069 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 15:16:40,069 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 87 [2018-07-24 15:16:40,069 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:40,072 INFO L225 Difference]: With dead ends: 555 [2018-07-24 15:16:40,072 INFO L226 Difference]: Without dead ends: 551 [2018-07-24 15:16:40,073 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 359 GetRequests, 339 SyntacticMatches, 9 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 54 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=38, Invalid=118, Unknown=0, NotChecked=0, Total=156 [2018-07-24 15:16:40,073 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 551 states. [2018-07-24 15:16:40,089 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 551 to 544. [2018-07-24 15:16:40,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 544 states. [2018-07-24 15:16:40,092 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 544 states to 544 states and 798 transitions. [2018-07-24 15:16:40,092 INFO L78 Accepts]: Start accepts. Automaton has 544 states and 798 transitions. Word has length 87 [2018-07-24 15:16:40,092 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:40,092 INFO L471 AbstractCegarLoop]: Abstraction has 544 states and 798 transitions. [2018-07-24 15:16:40,092 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 15:16:40,092 INFO L276 IsEmpty]: Start isEmpty. Operand 544 states and 798 transitions. [2018-07-24 15:16:40,093 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 91 [2018-07-24 15:16:40,094 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:40,094 INFO L353 BasicCegarLoop]: trace histogram [8, 8, 7, 5, 5, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:40,094 INFO L414 AbstractCegarLoop]: === Iteration 23 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:40,094 INFO L82 PathProgramCache]: Analyzing trace with hash 233904989, now seen corresponding path program 1 times [2018-07-24 15:16:40,094 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:40,095 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:40,095 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:40,096 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:40,096 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:40,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:40,642 WARN L169 SmtUtils]: Spent 119.00 ms on a formula simplification. DAG size of input: 14 DAG size of output: 9 [2018-07-24 15:16:40,700 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:40,701 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:40,701 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 29 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:40,712 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:40,712 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:40,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:40,807 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:40,993 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 110 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:40,993 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:41,886 WARN L169 SmtUtils]: Spent 573.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 11 [2018-07-24 15:16:42,121 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 67 proven. 64 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:42,141 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:42,141 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 30 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:42,157 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:42,157 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:42,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:42,412 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:42,463 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 21 proven. 120 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:42,463 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:42,681 INFO L134 CoverageAnalysis]: Checked inductivity of 141 backedges. 51 proven. 90 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:42,683 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:42,683 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 8, 8, 9, 9] total 25 [2018-07-24 15:16:42,683 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:42,683 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 15:16:42,683 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 15:16:42,684 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=100, Invalid=500, Unknown=0, NotChecked=0, Total=600 [2018-07-24 15:16:42,684 INFO L87 Difference]: Start difference. First operand 544 states and 798 transitions. Second operand 14 states. [2018-07-24 15:16:43,106 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:43,106 INFO L93 Difference]: Finished difference Result 549 states and 803 transitions. [2018-07-24 15:16:43,107 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 15:16:43,107 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 90 [2018-07-24 15:16:43,107 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:43,109 INFO L225 Difference]: With dead ends: 549 [2018-07-24 15:16:43,109 INFO L226 Difference]: Without dead ends: 547 [2018-07-24 15:16:43,110 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 373 GetRequests, 341 SyntacticMatches, 6 SemanticMatches, 26 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 154 ImplicationChecksByTransitivity, 1.9s TimeCoverageRelationStatistics Valid=125, Invalid=631, Unknown=0, NotChecked=0, Total=756 [2018-07-24 15:16:43,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 547 states. [2018-07-24 15:16:43,124 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 547 to 545. [2018-07-24 15:16:43,124 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 545 states. [2018-07-24 15:16:43,125 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 545 states to 545 states and 799 transitions. [2018-07-24 15:16:43,126 INFO L78 Accepts]: Start accepts. Automaton has 545 states and 799 transitions. Word has length 90 [2018-07-24 15:16:43,126 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:43,126 INFO L471 AbstractCegarLoop]: Abstraction has 545 states and 799 transitions. [2018-07-24 15:16:43,126 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 15:16:43,126 INFO L276 IsEmpty]: Start isEmpty. Operand 545 states and 799 transitions. [2018-07-24 15:16:43,127 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-07-24 15:16:43,127 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:43,127 INFO L353 BasicCegarLoop]: trace histogram [9, 8, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:43,128 INFO L414 AbstractCegarLoop]: === Iteration 24 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:43,128 INFO L82 PathProgramCache]: Analyzing trace with hash -1342705169, now seen corresponding path program 1 times [2018-07-24 15:16:43,128 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:43,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:43,129 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:43,129 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:43,129 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:43,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:43,658 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:43,658 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:43,658 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 31 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:43,670 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:43,671 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:43,750 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:43,754 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:43,766 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:43,766 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:43,836 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:43,857 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:43,857 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 32 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:43,872 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:43,872 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:44,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:44,061 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:44,071 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:44,071 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:44,132 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 54 proven. 118 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:44,134 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:44,134 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 7, 7, 7] total 12 [2018-07-24 15:16:44,135 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:44,135 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 15:16:44,135 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 15:16:44,135 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 15:16:44,136 INFO L87 Difference]: Start difference. First operand 545 states and 799 transitions. Second operand 7 states. [2018-07-24 15:16:44,411 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:44,412 INFO L93 Difference]: Finished difference Result 1070 states and 1569 transitions. [2018-07-24 15:16:44,412 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 15:16:44,412 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-07-24 15:16:44,413 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:44,416 INFO L225 Difference]: With dead ends: 1070 [2018-07-24 15:16:44,416 INFO L226 Difference]: Without dead ends: 672 [2018-07-24 15:16:44,418 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 406 SyntacticMatches, 0 SemanticMatches, 10 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=66, Invalid=66, Unknown=0, NotChecked=0, Total=132 [2018-07-24 15:16:44,418 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 672 states. [2018-07-24 15:16:44,432 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 672 to 623. [2018-07-24 15:16:44,433 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 623 states. [2018-07-24 15:16:44,434 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 623 states to 623 states and 918 transitions. [2018-07-24 15:16:44,434 INFO L78 Accepts]: Start accepts. Automaton has 623 states and 918 transitions. Word has length 102 [2018-07-24 15:16:44,435 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:44,435 INFO L471 AbstractCegarLoop]: Abstraction has 623 states and 918 transitions. [2018-07-24 15:16:44,435 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 15:16:44,435 INFO L276 IsEmpty]: Start isEmpty. Operand 623 states and 918 transitions. [2018-07-24 15:16:44,436 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 103 [2018-07-24 15:16:44,436 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:44,436 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:44,436 INFO L414 AbstractCegarLoop]: === Iteration 25 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:44,437 INFO L82 PathProgramCache]: Analyzing trace with hash -1084539731, now seen corresponding path program 1 times [2018-07-24 15:16:44,437 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:44,437 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:44,437 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:44,438 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:44,438 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:44,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:44,604 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:44,605 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:44,605 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 33 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:44,612 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:44,612 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:44,696 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:44,699 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:44,722 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:44,722 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:44,778 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 84 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-07-24 15:16:44,798 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:44,798 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 34 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:44,813 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:44,813 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:45,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:45,033 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:45,119 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 148 refuted. 0 times theorem prover too weak. 16 trivial. 0 not checked. [2018-07-24 15:16:45,120 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:45,166 INFO L134 CoverageAnalysis]: Checked inductivity of 188 backedges. 24 proven. 84 refuted. 0 times theorem prover too weak. 80 trivial. 0 not checked. [2018-07-24 15:16:45,168 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:45,168 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [7, 7, 4, 7, 4] total 9 [2018-07-24 15:16:45,168 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:45,168 INFO L450 AbstractCegarLoop]: Interpolant automaton has 7 states [2018-07-24 15:16:45,169 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 7 interpolants. [2018-07-24 15:16:45,169 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-07-24 15:16:45,169 INFO L87 Difference]: Start difference. First operand 623 states and 918 transitions. Second operand 7 states. [2018-07-24 15:16:45,332 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:45,332 INFO L93 Difference]: Finished difference Result 670 states and 984 transitions. [2018-07-24 15:16:45,333 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2018-07-24 15:16:45,333 INFO L78 Accepts]: Start accepts. Automaton has 7 states. Word has length 102 [2018-07-24 15:16:45,333 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:45,336 INFO L225 Difference]: With dead ends: 670 [2018-07-24 15:16:45,336 INFO L226 Difference]: Without dead ends: 664 [2018-07-24 15:16:45,336 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 416 GetRequests, 407 SyntacticMatches, 2 SemanticMatches, 7 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.1s TimeCoverageRelationStatistics Valid=20, Invalid=52, Unknown=0, NotChecked=0, Total=72 [2018-07-24 15:16:45,337 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 664 states. [2018-07-24 15:16:45,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 664 to 661. [2018-07-24 15:16:45,352 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-07-24 15:16:45,354 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 972 transitions. [2018-07-24 15:16:45,354 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 972 transitions. Word has length 102 [2018-07-24 15:16:45,354 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:45,355 INFO L471 AbstractCegarLoop]: Abstraction has 661 states and 972 transitions. [2018-07-24 15:16:45,355 INFO L472 AbstractCegarLoop]: Interpolant automaton has 7 states. [2018-07-24 15:16:45,355 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 972 transitions. [2018-07-24 15:16:45,356 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 107 [2018-07-24 15:16:45,356 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:45,356 INFO L353 BasicCegarLoop]: trace histogram [9, 9, 8, 6, 6, 4, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:45,356 INFO L414 AbstractCegarLoop]: === Iteration 26 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:45,357 INFO L82 PathProgramCache]: Analyzing trace with hash 35576591, now seen corresponding path program 1 times [2018-07-24 15:16:45,357 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:45,357 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:45,357 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:45,358 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:45,358 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:45,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:45,611 WARN L169 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-07-24 15:16:46,265 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 170 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:46,265 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:46,266 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 35 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:46,274 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:46,275 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:46,370 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:46,374 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:47,282 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 160 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:47,282 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:47,511 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 94 proven. 90 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:47,532 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:47,532 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 36 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:47,548 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:47,548 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:16:47,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:47,802 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:47,964 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 24 proven. 170 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:47,964 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:48,280 INFO L134 CoverageAnalysis]: Checked inductivity of 194 backedges. 54 proven. 140 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:48,282 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:48,283 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 9, 9, 10, 11] total 29 [2018-07-24 15:16:48,283 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:48,283 INFO L450 AbstractCegarLoop]: Interpolant automaton has 15 states [2018-07-24 15:16:48,284 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 15 interpolants. [2018-07-24 15:16:48,284 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=124, Invalid=688, Unknown=0, NotChecked=0, Total=812 [2018-07-24 15:16:48,284 INFO L87 Difference]: Start difference. First operand 661 states and 972 transitions. Second operand 15 states. [2018-07-24 15:16:48,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:48,695 INFO L93 Difference]: Finished difference Result 664 states and 974 transitions. [2018-07-24 15:16:48,695 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 15:16:48,696 INFO L78 Accepts]: Start accepts. Automaton has 15 states. Word has length 106 [2018-07-24 15:16:48,696 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:48,699 INFO L225 Difference]: With dead ends: 664 [2018-07-24 15:16:48,699 INFO L226 Difference]: Without dead ends: 662 [2018-07-24 15:16:48,700 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 436 GetRequests, 403 SyntacticMatches, 4 SemanticMatches, 29 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 203 ImplicationChecksByTransitivity, 2.2s TimeCoverageRelationStatistics Valid=142, Invalid=788, Unknown=0, NotChecked=0, Total=930 [2018-07-24 15:16:48,700 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 662 states. [2018-07-24 15:16:48,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 662 to 661. [2018-07-24 15:16:48,715 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-07-24 15:16:48,717 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 971 transitions. [2018-07-24 15:16:48,717 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 971 transitions. Word has length 106 [2018-07-24 15:16:48,718 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:48,718 INFO L471 AbstractCegarLoop]: Abstraction has 661 states and 971 transitions. [2018-07-24 15:16:48,718 INFO L472 AbstractCegarLoop]: Interpolant automaton has 15 states. [2018-07-24 15:16:48,718 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 971 transitions. [2018-07-24 15:16:48,719 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 114 [2018-07-24 15:16:48,719 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:48,719 INFO L353 BasicCegarLoop]: trace histogram [10, 10, 9, 6, 6, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:48,720 INFO L414 AbstractCegarLoop]: === Iteration 27 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:48,720 INFO L82 PathProgramCache]: Analyzing trace with hash -234907228, now seen corresponding path program 2 times [2018-07-24 15:16:48,720 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:48,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:48,721 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:16:48,721 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:48,721 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:48,805 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:49,012 WARN L169 SmtUtils]: Spent 100.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-07-24 15:16:49,175 WARN L169 SmtUtils]: Spent 112.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-07-24 15:16:49,396 WARN L169 SmtUtils]: Spent 143.00 ms on a formula simplification. DAG size of input: 15 DAG size of output: 13 [2018-07-24 15:16:49,587 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 208 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:49,588 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:49,588 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 37 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:49,599 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:49,600 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:49,699 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:49,700 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:49,703 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:49,877 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 198 refuted. 0 times theorem prover too weak. 10 trivial. 0 not checked. [2018-07-24 15:16:49,877 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:50,326 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 103 proven. 112 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:50,357 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:50,357 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 38 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:50,381 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:50,381 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:50,655 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:50,656 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:50,670 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:50,768 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 208 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:50,768 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:50,954 INFO L134 CoverageAnalysis]: Checked inductivity of 235 backedges. 27 proven. 150 refuted. 0 times theorem prover too weak. 58 trivial. 0 not checked. [2018-07-24 15:16:50,957 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:50,957 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 11, 10, 12, 7] total 25 [2018-07-24 15:16:50,957 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:50,958 INFO L450 AbstractCegarLoop]: Interpolant automaton has 17 states [2018-07-24 15:16:50,958 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 17 interpolants. [2018-07-24 15:16:50,959 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=509, Unknown=0, NotChecked=0, Total=600 [2018-07-24 15:16:50,959 INFO L87 Difference]: Start difference. First operand 661 states and 971 transitions. Second operand 17 states. [2018-07-24 15:16:51,720 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:51,720 INFO L93 Difference]: Finished difference Result 698 states and 1007 transitions. [2018-07-24 15:16:51,721 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 23 states. [2018-07-24 15:16:51,721 INFO L78 Accepts]: Start accepts. Automaton has 17 states. Word has length 113 [2018-07-24 15:16:51,721 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:51,723 INFO L225 Difference]: With dead ends: 698 [2018-07-24 15:16:51,723 INFO L226 Difference]: Without dead ends: 696 [2018-07-24 15:16:51,724 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 472 GetRequests, 424 SyntacticMatches, 16 SemanticMatches, 32 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 293 ImplicationChecksByTransitivity, 1.5s TimeCoverageRelationStatistics Valid=155, Invalid=967, Unknown=0, NotChecked=0, Total=1122 [2018-07-24 15:16:51,724 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 696 states. [2018-07-24 15:16:51,741 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 696 to 662. [2018-07-24 15:16:51,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 662 states. [2018-07-24 15:16:51,743 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 662 states to 662 states and 972 transitions. [2018-07-24 15:16:51,743 INFO L78 Accepts]: Start accepts. Automaton has 662 states and 972 transitions. Word has length 113 [2018-07-24 15:16:51,743 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:51,744 INFO L471 AbstractCegarLoop]: Abstraction has 662 states and 972 transitions. [2018-07-24 15:16:51,744 INFO L472 AbstractCegarLoop]: Interpolant automaton has 17 states. [2018-07-24 15:16:51,744 INFO L276 IsEmpty]: Start isEmpty. Operand 662 states and 972 transitions. [2018-07-24 15:16:51,745 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-07-24 15:16:51,745 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:51,745 INFO L353 BasicCegarLoop]: trace histogram [11, 10, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:51,745 INFO L414 AbstractCegarLoop]: === Iteration 28 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:51,746 INFO L82 PathProgramCache]: Analyzing trace with hash -238306442, now seen corresponding path program 2 times [2018-07-24 15:16:51,746 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:51,746 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:51,747 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:16:51,747 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:51,747 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:51,766 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:52,042 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:52,042 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:52,042 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 39 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:52,050 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:52,050 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:52,150 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:52,150 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:52,153 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:52,170 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:52,170 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:52,428 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:52,449 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:52,449 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 40 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:52,472 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:52,473 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:52,712 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:52,713 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:52,727 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:52,743 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:52,743 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:52,816 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 68 proven. 206 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:52,818 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:52,819 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [8, 8, 8, 8, 8] total 14 [2018-07-24 15:16:52,819 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:52,819 INFO L450 AbstractCegarLoop]: Interpolant automaton has 8 states [2018-07-24 15:16:52,819 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 8 interpolants. [2018-07-24 15:16:52,820 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 15:16:52,820 INFO L87 Difference]: Start difference. First operand 662 states and 972 transitions. Second operand 8 states. [2018-07-24 15:16:53,113 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:53,113 INFO L93 Difference]: Finished difference Result 1275 states and 1870 transitions. [2018-07-24 15:16:53,113 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 8 states. [2018-07-24 15:16:53,113 INFO L78 Accepts]: Start accepts. Automaton has 8 states. Word has length 123 [2018-07-24 15:16:53,114 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:53,118 INFO L225 Difference]: With dead ends: 1275 [2018-07-24 15:16:53,118 INFO L226 Difference]: Without dead ends: 799 [2018-07-24 15:16:53,119 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 502 GetRequests, 490 SyntacticMatches, 0 SemanticMatches, 12 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=91, Invalid=91, Unknown=0, NotChecked=0, Total=182 [2018-07-24 15:16:53,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 799 states. [2018-07-24 15:16:53,137 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 799 to 740. [2018-07-24 15:16:53,138 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 740 states. [2018-07-24 15:16:53,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 740 states to 740 states and 1091 transitions. [2018-07-24 15:16:53,140 INFO L78 Accepts]: Start accepts. Automaton has 740 states and 1091 transitions. Word has length 123 [2018-07-24 15:16:53,140 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:53,140 INFO L471 AbstractCegarLoop]: Abstraction has 740 states and 1091 transitions. [2018-07-24 15:16:53,140 INFO L472 AbstractCegarLoop]: Interpolant automaton has 8 states. [2018-07-24 15:16:53,140 INFO L276 IsEmpty]: Start isEmpty. Operand 740 states and 1091 transitions. [2018-07-24 15:16:53,141 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 124 [2018-07-24 15:16:53,141 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:53,142 INFO L353 BasicCegarLoop]: trace histogram [11, 11, 10, 7, 7, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:53,142 INFO L414 AbstractCegarLoop]: === Iteration 29 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:53,142 INFO L82 PathProgramCache]: Analyzing trace with hash -631333452, now seen corresponding path program 2 times [2018-07-24 15:16:53,142 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:53,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:53,143 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:16:53,143 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:53,143 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:53,167 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:53,655 WARN L169 SmtUtils]: Spent 156.00 ms on a formula simplification. DAG size of input: 13 DAG size of output: 10 [2018-07-24 15:16:53,773 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 35 proven. 254 refuted. 0 times theorem prover too weak. 5 trivial. 0 not checked. [2018-07-24 15:16:53,773 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:53,773 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 41 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:53,781 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:53,782 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:53,901 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:53,902 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:53,905 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:54,039 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 30 proven. 244 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:54,039 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:54,383 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 64 proven. 124 refuted. 0 times theorem prover too weak. 106 trivial. 0 not checked. [2018-07-24 15:16:54,404 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:54,404 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 42 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:54,419 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:54,419 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:54,702 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:54,703 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:54,718 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:54,999 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 30 proven. 264 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:54,999 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:55,118 INFO L134 CoverageAnalysis]: Checked inductivity of 294 backedges. 30 proven. 204 refuted. 0 times theorem prover too weak. 60 trivial. 0 not checked. [2018-07-24 15:16:55,119 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:55,120 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 9, 6, 12, 7] total 29 [2018-07-24 15:16:55,120 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:55,120 INFO L450 AbstractCegarLoop]: Interpolant automaton has 16 states [2018-07-24 15:16:55,121 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 16 interpolants. [2018-07-24 15:16:55,121 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=112, Invalid=700, Unknown=0, NotChecked=0, Total=812 [2018-07-24 15:16:55,122 INFO L87 Difference]: Start difference. First operand 740 states and 1091 transitions. Second operand 16 states. [2018-07-24 15:16:55,752 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:55,752 INFO L93 Difference]: Finished difference Result 801 states and 1160 transitions. [2018-07-24 15:16:55,753 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 20 states. [2018-07-24 15:16:55,753 INFO L78 Accepts]: Start accepts. Automaton has 16 states. Word has length 123 [2018-07-24 15:16:55,753 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:55,756 INFO L225 Difference]: With dead ends: 801 [2018-07-24 15:16:55,756 INFO L226 Difference]: Without dead ends: 797 [2018-07-24 15:16:55,756 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 513 GetRequests, 476 SyntacticMatches, 2 SemanticMatches, 35 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 304 ImplicationChecksByTransitivity, 1.4s TimeCoverageRelationStatistics Valid=167, Invalid=1165, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 15:16:55,757 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 797 states. [2018-07-24 15:16:55,773 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 797 to 759. [2018-07-24 15:16:55,773 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 759 states. [2018-07-24 15:16:55,774 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 759 states to 759 states and 1117 transitions. [2018-07-24 15:16:55,774 INFO L78 Accepts]: Start accepts. Automaton has 759 states and 1117 transitions. Word has length 123 [2018-07-24 15:16:55,775 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:55,775 INFO L471 AbstractCegarLoop]: Abstraction has 759 states and 1117 transitions. [2018-07-24 15:16:55,775 INFO L472 AbstractCegarLoop]: Interpolant automaton has 16 states. [2018-07-24 15:16:55,775 INFO L276 IsEmpty]: Start isEmpty. Operand 759 states and 1117 transitions. [2018-07-24 15:16:55,776 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 134 [2018-07-24 15:16:55,776 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:55,777 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:55,777 INFO L414 AbstractCegarLoop]: === Iteration 30 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:55,777 INFO L82 PathProgramCache]: Analyzing trace with hash -1671300281, now seen corresponding path program 2 times [2018-07-24 15:16:55,777 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:55,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:55,778 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:16:55,778 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:55,778 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:55,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:56,089 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:16:56,089 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:56,090 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 43 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:56,097 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:56,097 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:56,209 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:56,209 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:56,212 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:56,301 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:16:56,301 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:56,490 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 150 refuted. 0 times theorem prover too weak. 174 trivial. 0 not checked. [2018-07-24 15:16:56,509 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:56,510 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 44 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:56,525 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:56,525 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:56,878 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:56,878 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:56,892 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:56,986 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 298 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:16:56,986 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:57,187 INFO L134 CoverageAnalysis]: Checked inductivity of 357 backedges. 33 proven. 150 refuted. 0 times theorem prover too weak. 174 trivial. 0 not checked. [2018-07-24 15:16:57,189 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:57,189 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 5, 9, 5] total 13 [2018-07-24 15:16:57,189 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:57,189 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 15:16:57,190 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 15:16:57,190 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-07-24 15:16:57,190 INFO L87 Difference]: Start difference. First operand 759 states and 1117 transitions. Second operand 10 states. [2018-07-24 15:16:57,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:16:57,476 INFO L93 Difference]: Finished difference Result 788 states and 1154 transitions. [2018-07-24 15:16:57,477 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 15:16:57,477 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 133 [2018-07-24 15:16:57,477 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:16:57,480 INFO L225 Difference]: With dead ends: 788 [2018-07-24 15:16:57,480 INFO L226 Difference]: Without dead ends: 784 [2018-07-24 15:16:57,480 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 546 GetRequests, 531 SyntacticMatches, 4 SemanticMatches, 11 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 17 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=36, Invalid=120, Unknown=0, NotChecked=0, Total=156 [2018-07-24 15:16:57,481 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 784 states. [2018-07-24 15:16:57,500 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 784 to 778. [2018-07-24 15:16:57,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 778 states. [2018-07-24 15:16:57,502 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 778 states to 778 states and 1143 transitions. [2018-07-24 15:16:57,502 INFO L78 Accepts]: Start accepts. Automaton has 778 states and 1143 transitions. Word has length 133 [2018-07-24 15:16:57,502 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:16:57,502 INFO L471 AbstractCegarLoop]: Abstraction has 778 states and 1143 transitions. [2018-07-24 15:16:57,502 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 15:16:57,502 INFO L276 IsEmpty]: Start isEmpty. Operand 778 states and 1143 transitions. [2018-07-24 15:16:57,503 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 137 [2018-07-24 15:16:57,503 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:16:57,504 INFO L353 BasicCegarLoop]: trace histogram [12, 12, 11, 8, 8, 5, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:16:57,504 INFO L414 AbstractCegarLoop]: === Iteration 31 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:16:57,504 INFO L82 PathProgramCache]: Analyzing trace with hash 330710990, now seen corresponding path program 2 times [2018-07-24 15:16:57,504 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:16:57,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:57,505 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:16:57,505 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:16:57,505 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:16:57,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:16:58,060 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:58,060 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:58,060 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 45 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:16:58,067 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:58,068 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:58,183 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:58,183 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:58,187 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:58,327 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 314 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:58,327 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:58,791 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 191 proven. 156 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:16:58,812 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:16:58,812 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 46 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:16:58,828 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:16:58,828 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:16:59,215 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:16:59,215 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:16:59,225 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:16:59,391 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 33 proven. 334 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:59,391 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:16:59,873 INFO L134 CoverageAnalysis]: Checked inductivity of 367 backedges. 139 proven. 228 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:16:59,875 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:16:59,875 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 10, 10, 13, 13] total 37 [2018-07-24 15:16:59,875 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:16:59,876 INFO L450 AbstractCegarLoop]: Interpolant automaton has 20 states [2018-07-24 15:16:59,876 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 20 interpolants. [2018-07-24 15:16:59,877 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=197, Invalid=1135, Unknown=0, NotChecked=0, Total=1332 [2018-07-24 15:16:59,877 INFO L87 Difference]: Start difference. First operand 778 states and 1143 transitions. Second operand 20 states. [2018-07-24 15:17:02,547 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:02,548 INFO L93 Difference]: Finished difference Result 821 states and 1185 transitions. [2018-07-24 15:17:02,548 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 26 states. [2018-07-24 15:17:02,548 INFO L78 Accepts]: Start accepts. Automaton has 20 states. Word has length 136 [2018-07-24 15:17:02,548 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:02,552 INFO L225 Difference]: With dead ends: 821 [2018-07-24 15:17:02,552 INFO L226 Difference]: Without dead ends: 819 [2018-07-24 15:17:02,553 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 569 GetRequests, 517 SyntacticMatches, 6 SemanticMatches, 46 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 447 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=312, Invalid=1944, Unknown=0, NotChecked=0, Total=2256 [2018-07-24 15:17:02,554 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 819 states. [2018-07-24 15:17:02,574 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 819 to 779. [2018-07-24 15:17:02,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-07-24 15:17:02,576 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1144 transitions. [2018-07-24 15:17:02,576 INFO L78 Accepts]: Start accepts. Automaton has 779 states and 1144 transitions. Word has length 136 [2018-07-24 15:17:02,576 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:02,577 INFO L471 AbstractCegarLoop]: Abstraction has 779 states and 1144 transitions. [2018-07-24 15:17:02,577 INFO L472 AbstractCegarLoop]: Interpolant automaton has 20 states. [2018-07-24 15:17:02,577 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1144 transitions. [2018-07-24 15:17:02,578 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-07-24 15:17:02,578 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:02,578 INFO L353 BasicCegarLoop]: trace histogram [13, 12, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:02,578 INFO L414 AbstractCegarLoop]: === Iteration 32 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:02,579 INFO L82 PathProgramCache]: Analyzing trace with hash -352520992, now seen corresponding path program 2 times [2018-07-24 15:17:02,579 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:02,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:02,580 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:02,580 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:02,581 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:02,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:02,852 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 85 proven. 330 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:17:02,852 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:02,852 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 47 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:02,860 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:02,860 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:02,899 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 1 check-sat command(s) [2018-07-24 15:17:02,900 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:02,902 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:02,990 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 50 proven. 0 refuted. 0 times theorem prover too weak. 391 trivial. 0 not checked. [2018-07-24 15:17:02,991 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:03,239 WARN L169 SmtUtils]: Spent 125.00 ms on a formula simplification. DAG size of input: 16 DAG size of output: 8 [2018-07-24 15:17:03,303 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 50 proven. 0 refuted. 0 times theorem prover too weak. 391 trivial. 0 not checked. [2018-07-24 15:17:03,340 INFO L309 seRefinementStrategy]: Constructing automaton from 2 perfect and 1 imperfect interpolant sequences. [2018-07-24 15:17:03,340 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [3, 3] imperfect sequences [9] total 11 [2018-07-24 15:17:03,340 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:17:03,341 INFO L450 AbstractCegarLoop]: Interpolant automaton has 3 states [2018-07-24 15:17:03,341 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2018-07-24 15:17:03,341 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=48, Invalid=62, Unknown=0, NotChecked=0, Total=110 [2018-07-24 15:17:03,341 INFO L87 Difference]: Start difference. First operand 779 states and 1144 transitions. Second operand 3 states. [2018-07-24 15:17:03,666 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:03,666 INFO L93 Difference]: Finished difference Result 789 states and 1152 transitions. [2018-07-24 15:17:03,666 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2018-07-24 15:17:03,666 INFO L78 Accepts]: Start accepts. Automaton has 3 states. Word has length 148 [2018-07-24 15:17:03,666 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:03,669 INFO L225 Difference]: With dead ends: 789 [2018-07-24 15:17:03,669 INFO L226 Difference]: Without dead ends: 784 [2018-07-24 15:17:03,669 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 309 GetRequests, 300 SyntacticMatches, 0 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 19 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=48, Invalid=62, Unknown=0, NotChecked=0, Total=110 [2018-07-24 15:17:03,670 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 784 states. [2018-07-24 15:17:03,688 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 784 to 779. [2018-07-24 15:17:03,689 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 779 states. [2018-07-24 15:17:03,690 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 779 states to 779 states and 1141 transitions. [2018-07-24 15:17:03,690 INFO L78 Accepts]: Start accepts. Automaton has 779 states and 1141 transitions. Word has length 148 [2018-07-24 15:17:03,691 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:03,691 INFO L471 AbstractCegarLoop]: Abstraction has 779 states and 1141 transitions. [2018-07-24 15:17:03,691 INFO L472 AbstractCegarLoop]: Interpolant automaton has 3 states. [2018-07-24 15:17:03,691 INFO L276 IsEmpty]: Start isEmpty. Operand 779 states and 1141 transitions. [2018-07-24 15:17:03,692 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 149 [2018-07-24 15:17:03,692 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:03,692 INFO L353 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:03,693 INFO L414 AbstractCegarLoop]: === Iteration 33 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:03,693 INFO L82 PathProgramCache]: Analyzing trace with hash -94355554, now seen corresponding path program 2 times [2018-07-24 15:17:03,693 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:03,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:03,694 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:03,694 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:03,694 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:03,715 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:03,983 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:17:03,983 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:03,983 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 48 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:03,992 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:03,992 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:04,118 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:17:04,118 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:04,121 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:04,153 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:17:04,153 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:04,292 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 189 refuted. 0 times theorem prover too weak. 216 trivial. 0 not checked. [2018-07-24 15:17:04,322 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:04,322 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 49 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:04,346 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:04,346 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:04,674 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:17:04,674 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:04,683 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:04,717 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 379 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:17:04,717 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:04,750 INFO L134 CoverageAnalysis]: Checked inductivity of 441 backedges. 36 proven. 189 refuted. 0 times theorem prover too weak. 216 trivial. 0 not checked. [2018-07-24 15:17:04,751 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:04,752 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [9, 9, 4, 9, 4] total 11 [2018-07-24 15:17:04,752 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:04,752 INFO L450 AbstractCegarLoop]: Interpolant automaton has 9 states [2018-07-24 15:17:04,752 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 9 interpolants. [2018-07-24 15:17:04,752 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-07-24 15:17:04,753 INFO L87 Difference]: Start difference. First operand 779 states and 1141 transitions. Second operand 9 states. [2018-07-24 15:17:05,005 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:05,005 INFO L93 Difference]: Finished difference Result 1378 states and 2044 transitions. [2018-07-24 15:17:05,005 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2018-07-24 15:17:05,006 INFO L78 Accepts]: Start accepts. Automaton has 9 states. Word has length 148 [2018-07-24 15:17:05,006 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:05,009 INFO L225 Difference]: With dead ends: 1378 [2018-07-24 15:17:05,009 INFO L226 Difference]: Without dead ends: 820 [2018-07-24 15:17:05,010 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 604 GetRequests, 593 SyntacticMatches, 2 SemanticMatches, 9 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 2 ImplicationChecksByTransitivity, 0.2s TimeCoverageRelationStatistics Valid=26, Invalid=84, Unknown=0, NotChecked=0, Total=110 [2018-07-24 15:17:05,011 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 820 states. [2018-07-24 15:17:05,032 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 820 to 817. [2018-07-24 15:17:05,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 817 states. [2018-07-24 15:17:05,033 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 817 states to 817 states and 1195 transitions. [2018-07-24 15:17:05,033 INFO L78 Accepts]: Start accepts. Automaton has 817 states and 1195 transitions. Word has length 148 [2018-07-24 15:17:05,034 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:05,034 INFO L471 AbstractCegarLoop]: Abstraction has 817 states and 1195 transitions. [2018-07-24 15:17:05,034 INFO L472 AbstractCegarLoop]: Interpolant automaton has 9 states. [2018-07-24 15:17:05,034 INFO L276 IsEmpty]: Start isEmpty. Operand 817 states and 1195 transitions. [2018-07-24 15:17:05,034 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 153 [2018-07-24 15:17:05,034 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:05,035 INFO L353 BasicCegarLoop]: trace histogram [13, 13, 12, 9, 9, 6, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:05,035 INFO L414 AbstractCegarLoop]: === Iteration 34 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:05,035 INFO L82 PathProgramCache]: Analyzing trace with hash 1545010560, now seen corresponding path program 2 times [2018-07-24 15:17:05,035 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:05,035 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:05,036 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:05,036 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:05,036 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:05,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:05,818 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 417 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:05,818 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:05,818 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 50 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:05,826 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:05,826 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:05,949 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:17:05,949 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:05,953 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:06,156 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 397 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:17:06,156 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:06,590 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 238 proven. 195 refuted. 0 times theorem prover too weak. 20 trivial. 0 not checked. [2018-07-24 15:17:06,610 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:06,610 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 51 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:06,626 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:06,626 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:06,995 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:17:06,995 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:07,007 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:07,150 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 36 proven. 417 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:07,150 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:08,003 INFO L134 CoverageAnalysis]: Checked inductivity of 453 backedges. 142 proven. 311 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:08,004 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:08,005 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 11, 11, 14, 15] total 46 [2018-07-24 15:17:08,005 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:08,005 INFO L450 AbstractCegarLoop]: Interpolant automaton has 24 states [2018-07-24 15:17:08,006 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 24 interpolants. [2018-07-24 15:17:08,006 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=272, Invalid=1798, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 15:17:08,006 INFO L87 Difference]: Start difference. First operand 817 states and 1195 transitions. Second operand 24 states. [2018-07-24 15:17:09,259 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:09,260 INFO L93 Difference]: Finished difference Result 861 states and 1237 transitions. [2018-07-24 15:17:09,260 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 28 states. [2018-07-24 15:17:09,260 INFO L78 Accepts]: Start accepts. Automaton has 24 states. Word has length 152 [2018-07-24 15:17:09,260 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:09,263 INFO L225 Difference]: With dead ends: 861 [2018-07-24 15:17:09,264 INFO L226 Difference]: Without dead ends: 859 [2018-07-24 15:17:09,265 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 635 GetRequests, 575 SyntacticMatches, 4 SemanticMatches, 56 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 787 ImplicationChecksByTransitivity, 2.3s TimeCoverageRelationStatistics Valid=410, Invalid=2896, Unknown=0, NotChecked=0, Total=3306 [2018-07-24 15:17:09,265 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 859 states. [2018-07-24 15:17:09,285 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 859 to 817. [2018-07-24 15:17:09,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 817 states. [2018-07-24 15:17:09,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 817 states to 817 states and 1194 transitions. [2018-07-24 15:17:09,287 INFO L78 Accepts]: Start accepts. Automaton has 817 states and 1194 transitions. Word has length 152 [2018-07-24 15:17:09,287 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:09,287 INFO L471 AbstractCegarLoop]: Abstraction has 817 states and 1194 transitions. [2018-07-24 15:17:09,287 INFO L472 AbstractCegarLoop]: Interpolant automaton has 24 states. [2018-07-24 15:17:09,287 INFO L276 IsEmpty]: Start isEmpty. Operand 817 states and 1194 transitions. [2018-07-24 15:17:09,288 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 160 [2018-07-24 15:17:09,288 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:09,288 INFO L353 BasicCegarLoop]: trace histogram [14, 14, 13, 9, 9, 6, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:09,288 INFO L414 AbstractCegarLoop]: === Iteration 35 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:09,288 INFO L82 PathProgramCache]: Analyzing trace with hash -1285421549, now seen corresponding path program 3 times [2018-07-24 15:17:09,288 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:09,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:09,289 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:09,289 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:09,289 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:09,385 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:09,773 WARN L169 SmtUtils]: Spent 120.00 ms on a formula simplification that was a NOOP. DAG size: 9 [2018-07-24 15:17:10,237 WARN L169 SmtUtils]: Spent 398.00 ms on a formula simplification. DAG size of input: 16 DAG size of output: 14 [2018-07-24 15:17:10,647 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 39 proven. 474 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:10,648 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:10,648 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 52 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:10,659 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:10,660 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:10,737 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 15:17:10,737 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:10,739 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:11,014 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 249 proven. 31 refuted. 0 times theorem prover too weak. 233 trivial. 0 not checked. [2018-07-24 15:17:11,015 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:11,480 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 248 proven. 32 refuted. 0 times theorem prover too weak. 233 trivial. 0 not checked. [2018-07-24 15:17:11,499 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:11,499 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 53 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:11,514 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:11,515 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:11,833 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 6 check-sat command(s) [2018-07-24 15:17:11,834 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:11,840 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:11,915 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 249 proven. 31 refuted. 0 times theorem prover too weak. 233 trivial. 0 not checked. [2018-07-24 15:17:11,916 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:12,087 INFO L134 CoverageAnalysis]: Checked inductivity of 513 backedges. 248 proven. 32 refuted. 0 times theorem prover too weak. 233 trivial. 0 not checked. [2018-07-24 15:17:12,088 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:12,089 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [16, 8, 8, 8, 8] total 23 [2018-07-24 15:17:12,089 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:12,089 INFO L450 AbstractCegarLoop]: Interpolant automaton has 22 states [2018-07-24 15:17:12,089 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 22 interpolants. [2018-07-24 15:17:12,090 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=65, Invalid=441, Unknown=0, NotChecked=0, Total=506 [2018-07-24 15:17:12,090 INFO L87 Difference]: Start difference. First operand 817 states and 1194 transitions. Second operand 22 states. [2018-07-24 15:17:12,769 WARN L169 SmtUtils]: Spent 304.00 ms on a formula simplification. DAG size of input: 16 DAG size of output: 13 [2018-07-24 15:17:13,837 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:13,837 INFO L93 Difference]: Finished difference Result 1267 states and 1839 transitions. [2018-07-24 15:17:13,837 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 40 states. [2018-07-24 15:17:13,837 INFO L78 Accepts]: Start accepts. Automaton has 22 states. Word has length 159 [2018-07-24 15:17:13,838 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:13,840 INFO L225 Difference]: With dead ends: 1267 [2018-07-24 15:17:13,840 INFO L226 Difference]: Without dead ends: 706 [2018-07-24 15:17:13,842 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 679 GetRequests, 628 SyntacticMatches, 10 SemanticMatches, 41 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 297 ImplicationChecksByTransitivity, 2.7s TimeCoverageRelationStatistics Valid=182, Invalid=1624, Unknown=0, NotChecked=0, Total=1806 [2018-07-24 15:17:13,842 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 706 states. [2018-07-24 15:17:13,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 706 to 661. [2018-07-24 15:17:13,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 661 states. [2018-07-24 15:17:13,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 661 states to 661 states and 927 transitions. [2018-07-24 15:17:13,869 INFO L78 Accepts]: Start accepts. Automaton has 661 states and 927 transitions. Word has length 159 [2018-07-24 15:17:13,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:13,869 INFO L471 AbstractCegarLoop]: Abstraction has 661 states and 927 transitions. [2018-07-24 15:17:13,869 INFO L472 AbstractCegarLoop]: Interpolant automaton has 22 states. [2018-07-24 15:17:13,869 INFO L276 IsEmpty]: Start isEmpty. Operand 661 states and 927 transitions. [2018-07-24 15:17:13,870 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 170 [2018-07-24 15:17:13,871 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:13,871 INFO L353 BasicCegarLoop]: trace histogram [15, 14, 14, 10, 10, 6, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:13,871 INFO L414 AbstractCegarLoop]: === Iteration 36 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:13,871 INFO L82 PathProgramCache]: Analyzing trace with hash -348083931, now seen corresponding path program 3 times [2018-07-24 15:17:13,871 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:13,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:13,872 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:13,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:13,872 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:13,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:14,511 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:14,511 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:14,512 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 54 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:14,519 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:14,519 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:14,682 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 15:17:14,682 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:14,686 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:14,721 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:14,721 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:14,963 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:14,985 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:14,985 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 55 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:15,001 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:15,002 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:16,481 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 12 check-sat command(s) [2018-07-24 15:17:16,481 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:16,493 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:16,510 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:16,510 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:16,541 INFO L134 CoverageAnalysis]: Checked inductivity of 598 backedges. 98 proven. 470 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:16,543 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:16,543 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [10, 10, 10, 10, 10] total 18 [2018-07-24 15:17:16,543 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:16,544 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 15:17:16,544 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 15:17:16,544 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 15:17:16,544 INFO L87 Difference]: Start difference. First operand 661 states and 927 transitions. Second operand 10 states. [2018-07-24 15:17:16,708 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:16,709 INFO L93 Difference]: Finished difference Result 1162 states and 1629 transitions. [2018-07-24 15:17:16,709 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 15:17:16,709 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 169 [2018-07-24 15:17:16,709 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:16,712 INFO L225 Difference]: With dead ends: 1162 [2018-07-24 15:17:16,712 INFO L226 Difference]: Without dead ends: 764 [2018-07-24 15:17:16,713 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 690 GetRequests, 674 SyntacticMatches, 0 SemanticMatches, 16 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 0 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=153, Invalid=153, Unknown=0, NotChecked=0, Total=306 [2018-07-24 15:17:16,714 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 764 states. [2018-07-24 15:17:16,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 764 to 723. [2018-07-24 15:17:16,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 723 states. [2018-07-24 15:17:16,733 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 723 states to 723 states and 1015 transitions. [2018-07-24 15:17:16,733 INFO L78 Accepts]: Start accepts. Automaton has 723 states and 1015 transitions. Word has length 169 [2018-07-24 15:17:16,734 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:16,734 INFO L471 AbstractCegarLoop]: Abstraction has 723 states and 1015 transitions. [2018-07-24 15:17:16,734 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 15:17:16,734 INFO L276 IsEmpty]: Start isEmpty. Operand 723 states and 1015 transitions. [2018-07-24 15:17:16,735 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 182 [2018-07-24 15:17:16,735 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:16,736 INFO L353 BasicCegarLoop]: trace histogram [16, 16, 15, 11, 11, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:16,736 INFO L414 AbstractCegarLoop]: === Iteration 37 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:16,736 INFO L82 PathProgramCache]: Analyzing trace with hash -441432313, now seen corresponding path program 1 times [2018-07-24 15:17:16,736 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:16,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:16,737 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:16,737 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:16,737 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:16,818 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:17,412 WARN L169 SmtUtils]: Spent 159.00 ms on a formula simplification. DAG size of input: 9 DAG size of output: 5 [2018-07-24 15:17:17,904 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 45 proven. 611 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:17,905 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:17,905 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 56 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:17,912 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:17:17,912 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:17:18,057 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:18,061 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:18,205 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 656 proven. 0 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:18,205 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:18,466 INFO L134 CoverageAnalysis]: Checked inductivity of 692 backedges. 571 proven. 91 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:18,486 INFO L309 seRefinementStrategy]: Constructing automaton from 1 perfect and 2 imperfect interpolant sequences. [2018-07-24 15:17:18,486 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [10] imperfect sequences [10, 11] total 26 [2018-07-24 15:17:18,486 INFO L258 anRefinementStrategy]: Using the first perfect interpolant sequence [2018-07-24 15:17:18,486 INFO L450 AbstractCegarLoop]: Interpolant automaton has 10 states [2018-07-24 15:17:18,487 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 10 interpolants. [2018-07-24 15:17:18,487 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=262, Invalid=388, Unknown=0, NotChecked=0, Total=650 [2018-07-24 15:17:18,487 INFO L87 Difference]: Start difference. First operand 723 states and 1015 transitions. Second operand 10 states. [2018-07-24 15:17:18,626 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:18,626 INFO L93 Difference]: Finished difference Result 864 states and 1212 transitions. [2018-07-24 15:17:18,627 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 10 states. [2018-07-24 15:17:18,627 INFO L78 Accepts]: Start accepts. Automaton has 10 states. Word has length 181 [2018-07-24 15:17:18,627 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:18,630 INFO L225 Difference]: With dead ends: 864 [2018-07-24 15:17:18,630 INFO L226 Difference]: Without dead ends: 860 [2018-07-24 15:17:18,630 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 381 GetRequests, 352 SyntacticMatches, 5 SemanticMatches, 24 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 148 ImplicationChecksByTransitivity, 1.2s TimeCoverageRelationStatistics Valid=262, Invalid=388, Unknown=0, NotChecked=0, Total=650 [2018-07-24 15:17:18,631 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 860 states. [2018-07-24 15:17:18,653 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 860 to 856. [2018-07-24 15:17:18,654 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 856 states. [2018-07-24 15:17:18,655 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 856 states to 856 states and 1204 transitions. [2018-07-24 15:17:18,655 INFO L78 Accepts]: Start accepts. Automaton has 856 states and 1204 transitions. Word has length 181 [2018-07-24 15:17:18,655 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:18,655 INFO L471 AbstractCegarLoop]: Abstraction has 856 states and 1204 transitions. [2018-07-24 15:17:18,655 INFO L472 AbstractCegarLoop]: Interpolant automaton has 10 states. [2018-07-24 15:17:18,655 INFO L276 IsEmpty]: Start isEmpty. Operand 856 states and 1204 transitions. [2018-07-24 15:17:18,657 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 183 [2018-07-24 15:17:18,657 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:18,657 INFO L353 BasicCegarLoop]: trace histogram [16, 16, 15, 11, 11, 7, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:18,657 INFO L414 AbstractCegarLoop]: === Iteration 38 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:18,657 INFO L82 PathProgramCache]: Analyzing trace with hash -788052353, now seen corresponding path program 3 times [2018-07-24 15:17:18,657 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:18,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:18,658 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:17:18,658 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:18,658 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:18,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:19,288 WARN L169 SmtUtils]: Spent 117.00 ms on a formula simplification that was a NOOP. DAG size: 8 [2018-07-24 15:17:19,706 WARN L169 SmtUtils]: Spent 231.00 ms on a formula simplification. DAG size of input: 13 DAG size of output: 9 [2018-07-24 15:17:20,151 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 45 proven. 656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:20,151 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:20,152 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 57 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:20,159 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:20,159 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:20,346 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-07-24 15:17:20,346 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:20,350 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:21,185 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 665 proven. 6 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:21,185 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:21,414 WARN L169 SmtUtils]: Spent 110.00 ms on a formula simplification. DAG size of input: 115 DAG size of output: 20 [2018-07-24 15:17:21,740 WARN L169 SmtUtils]: Spent 135.00 ms on a formula simplification. DAG size of input: 114 DAG size of output: 14 [2018-07-24 15:17:22,275 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 612 proven. 63 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:17:22,297 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:22,297 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 58 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:22,312 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:22,312 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:25,356 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-07-24 15:17:25,357 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:25,378 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:25,552 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 45 proven. 656 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:25,552 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:26,400 WARN L169 SmtUtils]: Spent 102.00 ms on a formula simplification that was a NOOP. DAG size: 21 [2018-07-24 15:17:31,465 INFO L134 CoverageAnalysis]: Checked inductivity of 701 backedges. 273 proven. 428 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2018-07-24 15:17:31,467 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:31,468 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 12, 13, 17, 17] total 52 [2018-07-24 15:17:31,468 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:31,468 INFO L450 AbstractCegarLoop]: Interpolant automaton has 28 states [2018-07-24 15:17:31,469 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 28 interpolants. [2018-07-24 15:17:31,469 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=613, Invalid=2031, Unknown=8, NotChecked=0, Total=2652 [2018-07-24 15:17:31,470 INFO L87 Difference]: Start difference. First operand 856 states and 1204 transitions. Second operand 28 states. [2018-07-24 15:17:32,980 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:32,980 INFO L93 Difference]: Finished difference Result 874 states and 1220 transitions. [2018-07-24 15:17:32,981 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 35 states. [2018-07-24 15:17:32,981 INFO L78 Accepts]: Start accepts. Automaton has 28 states. Word has length 182 [2018-07-24 15:17:32,981 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:32,984 INFO L225 Difference]: With dead ends: 874 [2018-07-24 15:17:32,984 INFO L226 Difference]: Without dead ends: 872 [2018-07-24 15:17:32,985 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 758 GetRequests, 689 SyntacticMatches, 7 SemanticMatches, 62 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1104 ImplicationChecksByTransitivity, 9.1s TimeCoverageRelationStatistics Valid=892, Invalid=3132, Unknown=8, NotChecked=0, Total=4032 [2018-07-24 15:17:32,986 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 872 states. [2018-07-24 15:17:33,008 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 872 to 856. [2018-07-24 15:17:33,008 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 856 states. [2018-07-24 15:17:33,009 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 856 states to 856 states and 1203 transitions. [2018-07-24 15:17:33,009 INFO L78 Accepts]: Start accepts. Automaton has 856 states and 1203 transitions. Word has length 182 [2018-07-24 15:17:33,009 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:33,009 INFO L471 AbstractCegarLoop]: Abstraction has 856 states and 1203 transitions. [2018-07-24 15:17:33,010 INFO L472 AbstractCegarLoop]: Interpolant automaton has 28 states. [2018-07-24 15:17:33,010 INFO L276 IsEmpty]: Start isEmpty. Operand 856 states and 1203 transitions. [2018-07-24 15:17:33,011 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 198 [2018-07-24 15:17:33,011 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:33,011 INFO L353 BasicCegarLoop]: trace histogram [17, 16, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:33,011 INFO L414 AbstractCegarLoop]: === Iteration 39 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:33,011 INFO L82 PathProgramCache]: Analyzing trace with hash -1339885547, now seen corresponding path program 1 times [2018-07-24 15:17:33,012 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:33,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:33,012 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:33,012 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:33,012 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:33,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:33,337 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:33,338 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:33,338 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 59 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:33,347 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:17:33,347 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:17:33,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:33,506 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:33,542 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:33,543 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:33,690 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:33,711 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:33,711 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 60 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:33,726 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:17:33,726 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: FPandBP) [2018-07-24 15:17:34,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:34,086 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:34,113 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:34,113 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:34,281 INFO L134 CoverageAnalysis]: Checked inductivity of 811 backedges. 125 proven. 650 refuted. 0 times theorem prover too weak. 36 trivial. 0 not checked. [2018-07-24 15:17:34,283 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:34,283 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [11, 11, 11, 11, 11] total 19 [2018-07-24 15:17:34,283 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:34,283 INFO L450 AbstractCegarLoop]: Interpolant automaton has 11 states [2018-07-24 15:17:34,284 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 11 interpolants. [2018-07-24 15:17:34,284 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:34,284 INFO L87 Difference]: Start difference. First operand 856 states and 1203 transitions. Second operand 11 states. [2018-07-24 15:17:34,476 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:34,477 INFO L93 Difference]: Finished difference Result 1439 states and 2019 transitions. [2018-07-24 15:17:34,478 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 11 states. [2018-07-24 15:17:34,478 INFO L78 Accepts]: Start accepts. Automaton has 11 states. Word has length 197 [2018-07-24 15:17:34,478 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:34,481 INFO L225 Difference]: With dead ends: 1439 [2018-07-24 15:17:34,481 INFO L226 Difference]: Without dead ends: 963 [2018-07-24 15:17:34,482 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 804 GetRequests, 785 SyntacticMatches, 2 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 16 ImplicationChecksByTransitivity, 0.4s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:34,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 963 states. [2018-07-24 15:17:34,519 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 963 to 934. [2018-07-24 15:17:34,519 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-07-24 15:17:34,520 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1315 transitions. [2018-07-24 15:17:34,520 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 1315 transitions. Word has length 197 [2018-07-24 15:17:34,521 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:34,521 INFO L471 AbstractCegarLoop]: Abstraction has 934 states and 1315 transitions. [2018-07-24 15:17:34,521 INFO L472 AbstractCegarLoop]: Interpolant automaton has 11 states. [2018-07-24 15:17:34,521 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 1315 transitions. [2018-07-24 15:17:34,522 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 199 [2018-07-24 15:17:34,522 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:34,523 INFO L353 BasicCegarLoop]: trace histogram [17, 17, 16, 12, 12, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:34,523 INFO L414 AbstractCegarLoop]: === Iteration 40 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:34,523 INFO L82 PathProgramCache]: Analyzing trace with hash 403604017, now seen corresponding path program 3 times [2018-07-24 15:17:34,523 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:34,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:34,524 INFO L103 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2018-07-24 15:17:34,524 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:34,524 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:34,600 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:35,115 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 53 proven. 742 refuted. 0 times theorem prover too weak. 25 trivial. 0 not checked. [2018-07-24 15:17:35,115 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:35,115 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 61 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:35,123 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:35,123 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:35,320 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-07-24 15:17:35,320 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:35,324 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:35,643 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 771 proven. 19 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:35,643 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:36,336 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 718 proven. 76 refuted. 0 times theorem prover too weak. 26 trivial. 0 not checked. [2018-07-24 15:17:36,358 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:36,359 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 62 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:36,373 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:36,374 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:39,386 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 13 check-sat command(s) [2018-07-24 15:17:39,386 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:39,409 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:39,497 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 48 proven. 742 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:39,498 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:39,875 INFO L134 CoverageAnalysis]: Checked inductivity of 820 backedges. 448 proven. 342 refuted. 0 times theorem prover too weak. 30 trivial. 0 not checked. [2018-07-24 15:17:39,878 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:39,878 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 13, 14, 13, 13] total 47 [2018-07-24 15:17:39,878 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:39,879 INFO L450 AbstractCegarLoop]: Interpolant automaton has 25 states [2018-07-24 15:17:39,879 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 25 interpolants. [2018-07-24 15:17:39,880 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=591, Invalid=1571, Unknown=0, NotChecked=0, Total=2162 [2018-07-24 15:17:39,880 INFO L87 Difference]: Start difference. First operand 934 states and 1315 transitions. Second operand 25 states. [2018-07-24 15:17:41,226 WARN L169 SmtUtils]: Spent 190.00 ms on a formula simplification. DAG size of input: 18 DAG size of output: 13 [2018-07-24 15:17:41,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:41,372 INFO L93 Difference]: Finished difference Result 989 states and 1367 transitions. [2018-07-24 15:17:41,372 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 15:17:41,372 INFO L78 Accepts]: Start accepts. Automaton has 25 states. Word has length 198 [2018-07-24 15:17:41,373 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:41,376 INFO L225 Difference]: With dead ends: 989 [2018-07-24 15:17:41,376 INFO L226 Difference]: Without dead ends: 987 [2018-07-24 15:17:41,377 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 836 GetRequests, 768 SyntacticMatches, 2 SemanticMatches, 66 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 1230 ImplicationChecksByTransitivity, 2.1s TimeCoverageRelationStatistics Valid=1093, Invalid=3463, Unknown=0, NotChecked=0, Total=4556 [2018-07-24 15:17:41,378 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 987 states. [2018-07-24 15:17:41,404 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 987 to 934. [2018-07-24 15:17:41,404 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 934 states. [2018-07-24 15:17:41,405 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 934 states to 934 states and 1313 transitions. [2018-07-24 15:17:41,406 INFO L78 Accepts]: Start accepts. Automaton has 934 states and 1313 transitions. Word has length 198 [2018-07-24 15:17:41,406 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:41,406 INFO L471 AbstractCegarLoop]: Abstraction has 934 states and 1313 transitions. [2018-07-24 15:17:41,406 INFO L472 AbstractCegarLoop]: Interpolant automaton has 25 states. [2018-07-24 15:17:41,406 INFO L276 IsEmpty]: Start isEmpty. Operand 934 states and 1313 transitions. [2018-07-24 15:17:41,408 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 216 [2018-07-24 15:17:41,408 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:41,408 INFO L353 BasicCegarLoop]: trace histogram [19, 18, 18, 13, 13, 8, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:41,408 INFO L414 AbstractCegarLoop]: === Iteration 41 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:41,408 INFO L82 PathProgramCache]: Analyzing trace with hash -576783212, now seen corresponding path program 4 times [2018-07-24 15:17:41,408 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:41,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:41,409 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:41,409 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:41,409 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:41,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:42,448 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 15:17:42,448 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:42,448 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 63 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:42,463 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 15:17:42,463 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 15:17:42,636 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 15:17:42,636 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:42,640 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:42,671 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 15:17:42,671 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:42,863 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 15:17:42,883 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:42,883 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 64 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:42,898 INFO L103 rtionOrderModulation]: Keeping assertion order TERMS_WITH_SMALL_CONSTANTS_FIRST [2018-07-24 15:17:42,899 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder TERMS_WITH_SMALL_CONSTANTS_FIRST (IT: FPandBP) [2018-07-24 15:17:43,438 INFO L242 tOrderPrioritization]: Assert order TERMS_WITH_SMALL_CONSTANTS_FIRST issued 0 check-sat command(s) [2018-07-24 15:17:43,439 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:43,461 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:43,492 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 15:17:43,493 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:43,610 INFO L134 CoverageAnalysis]: Checked inductivity of 1010 backedges. 128 proven. 842 refuted. 0 times theorem prover too weak. 40 trivial. 0 not checked. [2018-07-24 15:17:43,612 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:43,613 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [12, 12, 12, 12, 12] total 19 [2018-07-24 15:17:43,613 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:43,613 INFO L450 AbstractCegarLoop]: Interpolant automaton has 12 states [2018-07-24 15:17:43,613 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 12 interpolants. [2018-07-24 15:17:43,614 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:43,614 INFO L87 Difference]: Start difference. First operand 934 states and 1313 transitions. Second operand 12 states. [2018-07-24 15:17:43,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:43,839 INFO L93 Difference]: Finished difference Result 1129 states and 1568 transitions. [2018-07-24 15:17:43,839 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 12 states. [2018-07-24 15:17:43,839 INFO L78 Accepts]: Start accepts. Automaton has 12 states. Word has length 215 [2018-07-24 15:17:43,840 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:43,843 INFO L225 Difference]: With dead ends: 1129 [2018-07-24 15:17:43,843 INFO L226 Difference]: Without dead ends: 1044 [2018-07-24 15:17:43,844 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 878 GetRequests, 851 SyntacticMatches, 10 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 78 ImplicationChecksByTransitivity, 1.1s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:43,844 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1044 states. [2018-07-24 15:17:43,883 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1044 to 1012. [2018-07-24 15:17:43,883 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1012 states. [2018-07-24 15:17:43,885 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1012 states to 1012 states and 1420 transitions. [2018-07-24 15:17:43,885 INFO L78 Accepts]: Start accepts. Automaton has 1012 states and 1420 transitions. Word has length 215 [2018-07-24 15:17:43,885 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:43,885 INFO L471 AbstractCegarLoop]: Abstraction has 1012 states and 1420 transitions. [2018-07-24 15:17:43,885 INFO L472 AbstractCegarLoop]: Interpolant automaton has 12 states. [2018-07-24 15:17:43,886 INFO L276 IsEmpty]: Start isEmpty. Operand 1012 states and 1420 transitions. [2018-07-24 15:17:43,887 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 244 [2018-07-24 15:17:43,887 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:43,887 INFO L353 BasicCegarLoop]: trace histogram [21, 20, 20, 15, 15, 10, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:43,888 INFO L414 AbstractCegarLoop]: === Iteration 42 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:43,888 INFO L82 PathProgramCache]: Analyzing trace with hash 1513807620, now seen corresponding path program 2 times [2018-07-24 15:17:43,917 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:43,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:43,918 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:43,918 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:43,918 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:43,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:44,248 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-07-24 15:17:44,248 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:44,248 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 65 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:44,255 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:44,255 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:44,442 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:17:44,443 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:44,447 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:44,487 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-07-24 15:17:44,488 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:44,758 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-07-24 15:17:44,779 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:44,780 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 66 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 66 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:44,795 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST1 [2018-07-24 15:17:44,795 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:45,242 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST1 issued 2 check-sat command(s) [2018-07-24 15:17:45,243 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:45,265 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:45,298 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-07-24 15:17:45,298 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:45,560 INFO L134 CoverageAnalysis]: Checked inductivity of 1283 backedges. 159 proven. 1078 refuted. 0 times theorem prover too weak. 46 trivial. 0 not checked. [2018-07-24 15:17:45,562 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:45,563 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [13, 13, 13, 13, 13] total 19 [2018-07-24 15:17:45,563 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:45,564 INFO L450 AbstractCegarLoop]: Interpolant automaton has 13 states [2018-07-24 15:17:45,564 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 13 interpolants. [2018-07-24 15:17:45,565 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:45,565 INFO L87 Difference]: Start difference. First operand 1012 states and 1420 transitions. Second operand 13 states. [2018-07-24 15:17:45,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:45,813 INFO L93 Difference]: Finished difference Result 1679 states and 2350 transitions. [2018-07-24 15:17:45,814 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 13 states. [2018-07-24 15:17:45,814 INFO L78 Accepts]: Start accepts. Automaton has 13 states. Word has length 243 [2018-07-24 15:17:45,814 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:45,819 INFO L225 Difference]: With dead ends: 1679 [2018-07-24 15:17:45,819 INFO L226 Difference]: Without dead ends: 1125 [2018-07-24 15:17:45,820 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 992 GetRequests, 957 SyntacticMatches, 18 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 140 ImplicationChecksByTransitivity, 0.6s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:45,821 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1125 states. [2018-07-24 15:17:45,867 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1125 to 1090. [2018-07-24 15:17:45,867 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1090 states. [2018-07-24 15:17:45,869 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1090 states to 1090 states and 1531 transitions. [2018-07-24 15:17:45,869 INFO L78 Accepts]: Start accepts. Automaton has 1090 states and 1531 transitions. Word has length 243 [2018-07-24 15:17:45,869 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:45,869 INFO L471 AbstractCegarLoop]: Abstraction has 1090 states and 1531 transitions. [2018-07-24 15:17:45,869 INFO L472 AbstractCegarLoop]: Interpolant automaton has 13 states. [2018-07-24 15:17:45,869 INFO L276 IsEmpty]: Start isEmpty. Operand 1090 states and 1531 transitions. [2018-07-24 15:17:45,871 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 262 [2018-07-24 15:17:45,871 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:45,871 INFO L353 BasicCegarLoop]: trace histogram [23, 22, 22, 16, 16, 10, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:45,872 INFO L414 AbstractCegarLoop]: === Iteration 43 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:45,872 INFO L82 PathProgramCache]: Analyzing trace with hash -438655549, now seen corresponding path program 5 times [2018-07-24 15:17:45,872 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:45,872 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:45,873 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:45,873 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:45,873 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:45,902 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:46,226 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-07-24 15:17:46,226 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:46,226 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 67 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:46,235 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 15:17:46,236 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:46,552 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2018-07-24 15:17:46,552 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:46,558 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:46,619 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-07-24 15:17:46,619 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:46,893 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-07-24 15:17:46,914 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:46,914 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 68 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:46,929 INFO L103 rtionOrderModulation]: Keeping assertion order INSIDE_LOOP_FIRST1 [2018-07-24 15:17:46,930 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder INSIDE_LOOP_FIRST1 (IT: FPandBP) [2018-07-24 15:17:55,920 INFO L242 tOrderPrioritization]: Assert order INSIDE_LOOP_FIRST1 issued 14 check-sat command(s) [2018-07-24 15:17:55,920 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:55,949 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:55,993 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-07-24 15:17:55,994 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:56,182 INFO L134 CoverageAnalysis]: Checked inductivity of 1530 backedges. 158 proven. 1322 refuted. 0 times theorem prover too weak. 50 trivial. 0 not checked. [2018-07-24 15:17:56,185 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:56,186 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [14, 14, 14, 14, 14] total 19 [2018-07-24 15:17:56,186 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:56,186 INFO L450 AbstractCegarLoop]: Interpolant automaton has 14 states [2018-07-24 15:17:56,187 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 14 interpolants. [2018-07-24 15:17:56,187 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:56,187 INFO L87 Difference]: Start difference. First operand 1090 states and 1531 transitions. Second operand 14 states. [2018-07-24 15:17:56,502 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:56,503 INFO L93 Difference]: Finished difference Result 1291 states and 1790 transitions. [2018-07-24 15:17:56,503 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 14 states. [2018-07-24 15:17:56,503 INFO L78 Accepts]: Start accepts. Automaton has 14 states. Word has length 261 [2018-07-24 15:17:56,503 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:56,507 INFO L225 Difference]: With dead ends: 1291 [2018-07-24 15:17:56,507 INFO L226 Difference]: Without dead ends: 1206 [2018-07-24 15:17:56,508 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1066 GetRequests, 1023 SyntacticMatches, 26 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 202 ImplicationChecksByTransitivity, 0.5s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:17:56,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1206 states. [2018-07-24 15:17:56,554 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1206 to 1168. [2018-07-24 15:17:56,554 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 1168 states. [2018-07-24 15:17:56,555 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1168 states to 1168 states and 1638 transitions. [2018-07-24 15:17:56,556 INFO L78 Accepts]: Start accepts. Automaton has 1168 states and 1638 transitions. Word has length 261 [2018-07-24 15:17:56,556 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:56,556 INFO L471 AbstractCegarLoop]: Abstraction has 1168 states and 1638 transitions. [2018-07-24 15:17:56,556 INFO L472 AbstractCegarLoop]: Interpolant automaton has 14 states. [2018-07-24 15:17:56,556 INFO L276 IsEmpty]: Start isEmpty. Operand 1168 states and 1638 transitions. [2018-07-24 15:17:56,558 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 290 [2018-07-24 15:17:56,558 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:56,558 INFO L353 BasicCegarLoop]: trace histogram [25, 24, 24, 18, 18, 12, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:56,558 INFO L414 AbstractCegarLoop]: === Iteration 44 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:56,559 INFO L82 PathProgramCache]: Analyzing trace with hash 1601829811, now seen corresponding path program 3 times [2018-07-24 15:17:56,559 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:56,559 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:56,559 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:56,560 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:56,560 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:56,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:17:57,018 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 193 proven. 1614 refuted. 0 times theorem prover too weak. 56 trivial. 0 not checked. [2018-07-24 15:17:57,019 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:57,019 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 69 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:17:57,027 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:57,027 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:57,109 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-07-24 15:17:57,109 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:57,112 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:57,447 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 469 proven. 4 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-07-24 15:17:57,447 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:57,581 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 469 proven. 4 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-07-24 15:17:57,601 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:17:57,601 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 70 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:17:57,617 INFO L103 rtionOrderModulation]: Keeping assertion order OUTSIDE_LOOP_FIRST2 [2018-07-24 15:17:57,617 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder OUTSIDE_LOOP_FIRST2 (IT: FPandBP) [2018-07-24 15:17:57,903 INFO L242 tOrderPrioritization]: Assert order OUTSIDE_LOOP_FIRST2 issued 5 check-sat command(s) [2018-07-24 15:17:57,904 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:17:57,912 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:17:58,027 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 469 proven. 4 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-07-24 15:17:58,028 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:17:58,099 INFO L134 CoverageAnalysis]: Checked inductivity of 1863 backedges. 469 proven. 4 refuted. 0 times theorem prover too weak. 1390 trivial. 0 not checked. [2018-07-24 15:17:58,101 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:17:58,101 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [15, 6, 6, 6, 6] total 22 [2018-07-24 15:17:58,101 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:17:58,102 INFO L450 AbstractCegarLoop]: Interpolant automaton has 19 states [2018-07-24 15:17:58,102 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 19 interpolants. [2018-07-24 15:17:58,102 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=182, Invalid=280, Unknown=0, NotChecked=0, Total=462 [2018-07-24 15:17:58,102 INFO L87 Difference]: Start difference. First operand 1168 states and 1638 transitions. Second operand 19 states. [2018-07-24 15:17:58,643 WARN L169 SmtUtils]: Spent 200.00 ms on a formula simplification. DAG size of input: 18 DAG size of output: 16 [2018-07-24 15:17:58,920 WARN L169 SmtUtils]: Spent 150.00 ms on a formula simplification. DAG size of input: 18 DAG size of output: 16 [2018-07-24 15:17:59,668 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:17:59,668 INFO L93 Difference]: Finished difference Result 1322 states and 1840 transitions. [2018-07-24 15:17:59,668 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 37 states. [2018-07-24 15:17:59,669 INFO L78 Accepts]: Start accepts. Automaton has 19 states. Word has length 289 [2018-07-24 15:17:59,669 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:17:59,671 INFO L225 Difference]: With dead ends: 1322 [2018-07-24 15:17:59,671 INFO L226 Difference]: Without dead ends: 690 [2018-07-24 15:17:59,673 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1213 GetRequests, 1166 SyntacticMatches, 3 SemanticMatches, 44 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 368 ImplicationChecksByTransitivity, 1.7s TimeCoverageRelationStatistics Valid=660, Invalid=1410, Unknown=0, NotChecked=0, Total=2070 [2018-07-24 15:17:59,673 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 690 states. [2018-07-24 15:17:59,697 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 690 to 663. [2018-07-24 15:17:59,698 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 663 states. [2018-07-24 15:17:59,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 663 states to 663 states and 911 transitions. [2018-07-24 15:17:59,698 INFO L78 Accepts]: Start accepts. Automaton has 663 states and 911 transitions. Word has length 289 [2018-07-24 15:17:59,699 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:17:59,699 INFO L471 AbstractCegarLoop]: Abstraction has 663 states and 911 transitions. [2018-07-24 15:17:59,699 INFO L472 AbstractCegarLoop]: Interpolant automaton has 19 states. [2018-07-24 15:17:59,699 INFO L276 IsEmpty]: Start isEmpty. Operand 663 states and 911 transitions. [2018-07-24 15:17:59,701 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 354 [2018-07-24 15:17:59,701 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:17:59,701 INFO L353 BasicCegarLoop]: trace histogram [31, 30, 30, 22, 22, 14, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:17:59,702 INFO L414 AbstractCegarLoop]: === Iteration 45 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:17:59,702 INFO L82 PathProgramCache]: Analyzing trace with hash -1748649631, now seen corresponding path program 6 times [2018-07-24 15:17:59,702 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:17:59,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:59,703 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:17:59,703 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:17:59,703 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:17:59,744 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2018-07-24 15:18:00,220 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-07-24 15:18:00,221 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:18:00,221 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode Z3_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/z3 Starting monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 71 with z3 -smt2 -in SMTLIB2_COMPLIANT=true -t:12000 [2018-07-24 15:18:00,228 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 15:18:00,228 INFO L288 anRefinementStrategy]: Using traceCheck mode Z3_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 15:18:00,630 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-07-24 15:18:00,630 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:18:00,638 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:18:00,761 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-07-24 15:18:00,761 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:18:01,097 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-07-24 15:18:01,119 INFO L297 seRefinementStrategy]: The current sequences of interpolants are not accepted, trying to find more. [2018-07-24 15:18:01,119 INFO L191 anRefinementStrategy]: Switched to InterpolantGenerator mode CVC4_IG No working directory specified, using /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/cvc4nyu Starting monitored process 72 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 (exit command is (exit), workingDir is null) Waiting until toolchain timeout for monitored process 72 with cvc4nyu --tear-down-incremental --print-success --lang smt --rewrite-divk --tlimit-per=12000 [2018-07-24 15:18:01,134 INFO L103 rtionOrderModulation]: Keeping assertion order MIX_INSIDE_OUTSIDE [2018-07-24 15:18:01,134 INFO L288 anRefinementStrategy]: Using traceCheck mode CVC4_IG with AssertCodeBlockOrder MIX_INSIDE_OUTSIDE (IT: FPandBP) [2018-07-24 15:18:10,855 INFO L242 tOrderPrioritization]: Assert order MIX_INSIDE_OUTSIDE issued 21 check-sat command(s) [2018-07-24 15:18:10,856 INFO L243 tOrderPrioritization]: Conjunction of SSA is unsat [2018-07-24 15:18:10,895 INFO L273 TraceCheckSpWp]: Computing forward predicates... [2018-07-24 15:18:10,965 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-07-24 15:18:10,965 INFO L316 TraceCheckSpWp]: Computing backward predicates... [2018-07-24 15:18:11,288 INFO L134 CoverageAnalysis]: Checked inductivity of 2894 backedges. 218 proven. 2606 refuted. 0 times theorem prover too weak. 70 trivial. 0 not checked. [2018-07-24 15:18:11,292 INFO L309 seRefinementStrategy]: Constructing automaton from 0 perfect and 5 imperfect interpolant sequences. [2018-07-24 15:18:11,292 INFO L324 seRefinementStrategy]: Number of different interpolants: perfect sequences [] imperfect sequences [18, 18, 18, 18, 18] total 19 [2018-07-24 15:18:11,292 INFO L251 anRefinementStrategy]: Using the first two imperfect interpolant sequences [2018-07-24 15:18:11,293 INFO L450 AbstractCegarLoop]: Interpolant automaton has 18 states [2018-07-24 15:18:11,293 INFO L132 InterpolantAutomaton]: Constructing interpolant automaton starting with 18 interpolants. [2018-07-24 15:18:11,293 INFO L133 InterpolantAutomaton]: CoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:18:11,293 INFO L87 Difference]: Start difference. First operand 663 states and 911 transitions. Second operand 18 states. [2018-07-24 15:18:11,507 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2018-07-24 15:18:11,507 INFO L93 Difference]: Finished difference Result 869 states and 1196 transitions. [2018-07-24 15:18:11,508 INFO L142 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 18 states. [2018-07-24 15:18:11,508 INFO L78 Accepts]: Start accepts. Automaton has 18 states. Word has length 353 [2018-07-24 15:18:11,509 INFO L84 Accepts]: Finished accepts. some prefix is accepted. [2018-07-24 15:18:11,511 INFO L225 Difference]: With dead ends: 869 [2018-07-24 15:18:11,511 INFO L226 Difference]: Without dead ends: 784 [2018-07-24 15:18:11,512 INFO L573 BasicCegarLoop]: 0 DeclaredPredicates, 1442 GetRequests, 1367 SyntacticMatches, 58 SemanticMatches, 17 ConstructedPredicates, 0 IntricatePredicates, 0 DeprecatedPredicates, 450 ImplicationChecksByTransitivity, 0.7s TimeCoverageRelationStatistics Valid=171, Invalid=171, Unknown=0, NotChecked=0, Total=342 [2018-07-24 15:18:11,512 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 784 states. [2018-07-24 15:18:11,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 784 to 741. [2018-07-24 15:18:11,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand 741 states. [2018-07-24 15:18:11,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 741 states to 741 states and 1018 transitions. [2018-07-24 15:18:11,537 INFO L78 Accepts]: Start accepts. Automaton has 741 states and 1018 transitions. Word has length 353 [2018-07-24 15:18:11,538 INFO L84 Accepts]: Finished accepts. word is rejected. [2018-07-24 15:18:11,538 INFO L471 AbstractCegarLoop]: Abstraction has 741 states and 1018 transitions. [2018-07-24 15:18:11,538 INFO L472 AbstractCegarLoop]: Interpolant automaton has 18 states. [2018-07-24 15:18:11,538 INFO L276 IsEmpty]: Start isEmpty. Operand 741 states and 1018 transitions. [2018-07-24 15:18:11,540 INFO L282 IsEmpty]: Finished isEmpty. Found accepting run of length 400 [2018-07-24 15:18:11,540 INFO L345 BasicCegarLoop]: Found error trace [2018-07-24 15:18:11,541 INFO L353 BasicCegarLoop]: trace histogram [35, 34, 34, 25, 25, 16, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2018-07-24 15:18:11,541 INFO L414 AbstractCegarLoop]: === Iteration 46 === [mainErr0AssertViolationERROR_FUNCTION]=== [2018-07-24 15:18:11,541 INFO L82 PathProgramCache]: Analyzing trace with hash -1805057072, now seen corresponding path program 7 times [2018-07-24 15:18:11,541 INFO L69 tionRefinementEngine]: Using refinement strategy RubberTaipanRefinementStrategy [2018-07-24 15:18:11,542 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:18:11,542 INFO L101 rtionOrderModulation]: Changing assertion order to NOT_INCREMENTALLY [2018-07-24 15:18:11,542 INFO L119 rtionOrderModulation]: Craig_TreeInterpolation forces the order to NOT_INCREMENTALLY [2018-07-24 15:18:11,542 INFO L288 anRefinementStrategy]: Using traceCheck mode SMTINTERPOL with AssertCodeBlockOrder NOT_INCREMENTALLY (IT: Craig_TreeInterpolation) [2018-07-24 15:18:12,254 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-07-24 15:18:13,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2018-07-24 15:18:13,207 INFO L419 BasicCegarLoop]: Counterexample might be feasible [2018-07-24 15:18:13,427 INFO L202 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction CFG 24.07 03:18:13 BoogieIcfgContainer [2018-07-24 15:18:13,429 INFO L132 PluginConnector]: ------------------------ END TraceAbstraction---------------------------- [2018-07-24 15:18:13,430 INFO L168 Benchmark]: Toolchain (without parser) took 122609.83 ms. Allocated memory was 1.5 GB in the beginning and 3.1 GB in the end (delta: 1.5 GB). Free memory was 1.4 GB in the beginning and 1.8 GB in the end (delta: -411.3 MB). Peak memory consumption was 1.1 GB. Max. memory is 7.1 GB. [2018-07-24 15:18:13,430 INFO L168 Benchmark]: CDTParser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 15:18:13,431 INFO L168 Benchmark]: CACSL2BoogieTranslator took 539.20 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. [2018-07-24 15:18:13,431 INFO L168 Benchmark]: Boogie Procedure Inliner took 34.84 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. [2018-07-24 15:18:13,432 INFO L168 Benchmark]: Boogie Preprocessor took 54.25 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. [2018-07-24 15:18:13,432 INFO L168 Benchmark]: RCFGBuilder took 1720.58 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 755.0 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -778.0 MB). Peak memory consumption was 19.5 MB. Max. memory is 7.1 GB. [2018-07-24 15:18:13,433 INFO L168 Benchmark]: TraceAbstraction took 120255.97 ms. Allocated memory was 2.3 GB in the beginning and 3.1 GB in the end (delta: 783.8 MB). Free memory was 2.2 GB in the beginning and 1.8 GB in the end (delta: 335.1 MB). Peak memory consumption was 1.1 GB. Max. memory is 7.1 GB. [2018-07-24 15:18:13,442 INFO L336 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.24 ms. Allocated memory is still 1.5 GB. Free memory is still 1.5 GB. There was no memory consumed. Max. memory is 7.1 GB. * CACSL2BoogieTranslator took 539.20 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 21.1 MB). Peak memory consumption was 21.1 MB. Max. memory is 7.1 GB. * Boogie Procedure Inliner took 34.84 ms. Allocated memory is still 1.5 GB. Free memory is still 1.4 GB. There was no memory consumed. Max. memory is 7.1 GB. * Boogie Preprocessor took 54.25 ms. Allocated memory is still 1.5 GB. Free memory was 1.4 GB in the beginning and 1.4 GB in the end (delta: 10.6 MB). Peak memory consumption was 10.6 MB. Max. memory is 7.1 GB. * RCFGBuilder took 1720.58 ms. Allocated memory was 1.5 GB in the beginning and 2.3 GB in the end (delta: 755.0 MB). Free memory was 1.4 GB in the beginning and 2.2 GB in the end (delta: -778.0 MB). Peak memory consumption was 19.5 MB. Max. memory is 7.1 GB. * TraceAbstraction took 120255.97 ms. Allocated memory was 2.3 GB in the beginning and 3.1 GB in the end (delta: 783.8 MB). Free memory was 2.2 GB in the beginning and 1.8 GB in the end (delta: 335.1 MB). Peak memory consumption was 1.1 GB. Max. memory is 7.1 GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - CounterExampleResult [Line: 569]: a call of __VERIFIER_error() is reachable a call of __VERIFIER_error() is reachable We found a FailurePath: [L5] int m_Protocol = 1; [L6] int m_msg_2 = 2; [L7] int m_recv_ack_2 = 3; [L8] int m_msg_1_1 = 4; [L9] int m_msg_1_2 = 5; [L10] int m_recv_ack_1_1 = 6; [L11] int m_recv_ack_1_2 = 7; VAL [\old(m_msg_1_1)=20, \old(m_msg_1_2)=23, \old(m_msg_2)=24, \old(m_Protocol)=25, \old(m_recv_ack_1_1)=21, \old(m_recv_ack_1_2)=22, \old(m_recv_ack_2)=26, m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3] [L16] int q = 0; [L17] int method_id; [L20] int this_expect = 0; [L21] int this_buffer_empty = 0; VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, q=0, this_buffer_empty=0, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=0, this_buffer_empty=0, this_expect=0] [L43] COND TRUE q == 0 [L44] COND TRUE __VERIFIER_nondet_int() [L46] COND TRUE 1 [L48] method_id = 1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=0, this_buffer_empty=0, this_expect=0] [L50] COND FALSE !(0) [L54] q = 1 [L56] this_expect=0 [L56] this_buffer_empty=1 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=3, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=1, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=1, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=1, this_buffer_empty=1, this_expect=0] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=18, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=3, q=3, this_buffer_empty=0, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=3, this_buffer_empty=0, this_expect=1] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=3, P3=0, P4=3, P5=0, P6=0, P7=0, P8=3, P9=0, q=4, this_buffer_empty=1, this_expect=1] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=1] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=7, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=5, this_buffer_empty=0, this_expect=2] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-3, q=1, this_buffer_empty=1, this_expect=2] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=2] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=3] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=3] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=19, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=5, this_buffer_empty=0, this_expect=4] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=0, q=1, this_buffer_empty=1, this_expect=4] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=4] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-10, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=5] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=5] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=5, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=6] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=6] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=6] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-4, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=7] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=7] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=9, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=8] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=8] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=8] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=2, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=9] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=9] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=11, P2=-1, P3=0, P4=-1, P5=0, P6=-2, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=5, this_buffer_empty=0, this_expect=10] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=4, q=1, this_buffer_empty=1, this_expect=10] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=10] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-12, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=11] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=11] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=13, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=12] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=12] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=12] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-6, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=13] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=13] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=15, P2=-1, P3=0, P4=-1, P5=0, P6=1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=14] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=14] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=14] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-8, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=15] [L286] COND FALSE !((((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2))))) [L290] q = 4 [L292] this_expect=this_expect [L292] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=1, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L363] COND TRUE q == 4 [L364] COND FALSE !(__VERIFIER_nondet_int()) [L380] COND FALSE !(__VERIFIER_nondet_int()) [L396] COND FALSE !(__VERIFIER_nondet_int()) [L412] COND TRUE __VERIFIER_nondet_int() [L414] COND TRUE (((P1 % 2) != (0 % 2)) && !(((P1 % 2) != ((0 + 1) % 2)) && ((P1 % 2) != (0 % 2)))) [L416] method_id = 5 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=4, this_buffer_empty=1, this_expect=15] [L418] COND FALSE !(((((((P6 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))) || (((this_buffer_empty != 1) && ((P6 % 2) != (0 % 2))) && (((P6 % 2) != (0 % 2)) && !(((P6 % 2) != ((0 + 1) % 2)) && ((P6 % 2) != (0 % 2))))))) [L422] q = 5 [L424] this_expect=(this_expect + 1) [L424] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=17, P2=-1, P3=0, P4=-1, P5=0, P6=-1, P7=0, P8=-1, P9=-1, q=5, this_buffer_empty=0, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L263] COND FALSE !(q == 3) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L363] COND FALSE !(q == 4) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=5, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L463] COND TRUE q == 5 [L464] COND FALSE !(__VERIFIER_nondet_int()) [L480] COND FALSE !(__VERIFIER_nondet_int()) [L496] COND FALSE !(__VERIFIER_nondet_int()) [L512] COND FALSE !(__VERIFIER_nondet_int()) [L528] COND FALSE !(__VERIFIER_nondet_int()) [L544] COND TRUE __VERIFIER_nondet_int() [L546] COND TRUE ((P1 != (((0 + 1) - 1) % 2)) && !((P1 != ((((0 + 1) + 1) - 1) % 2)) && (P1 != (((0 + 1) - 1) % 2)))) [L548] method_id = 7 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=5, this_buffer_empty=0, this_expect=16] [L550] COND FALSE !(((((this_buffer_empty == 1) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))) || ((((P9 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && (P9 != (((0 + 1) - 1) % 2))) && ((P9 != (((0 + 1) - 1) % 2)) && !((P9 != ((((0 + 1) + 1) - 1) % 2)) && (P9 != (((0 + 1) - 1) % 2))))))) [L554] q = 1 [L556] this_expect=this_expect [L556] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=1, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=1, q=1, this_buffer_empty=1, this_expect=16] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND FALSE !(this_expect > 16) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=7, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L63] COND TRUE q == 1 [L64] COND TRUE __VERIFIER_nondet_int() [L66] COND TRUE !((P1 % 2) != (0 % 2)) [L68] method_id = 2 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=1, this_buffer_empty=1, this_expect=16] [L70] COND FALSE !((((((P1 % 2) != (this_expect % 2)) && (this_buffer_empty == 1)) && !((P1 % 2) != (0 % 2))) || ((this_buffer_empty != 1) && !((P1 % 2) != (0 % 2))))) [L74] q = 3 [L76] this_expect=(this_expect + 1) [L76] this_buffer_empty=(1 - this_buffer_empty) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=-14, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=17] [L24] COND TRUE 1 [L27] int P1=__VERIFIER_nondet_int(); [L28] int P2=__VERIFIER_nondet_int(); [L29] int P3=__VERIFIER_nondet_int(); [L30] int P4=__VERIFIER_nondet_int(); [L31] int P5=__VERIFIER_nondet_int(); [L32] int P6=__VERIFIER_nondet_int(); [L33] int P7=__VERIFIER_nondet_int(); [L34] int P8=__VERIFIER_nondet_int(); [L35] int P9=__VERIFIER_nondet_int(); [L38] COND TRUE this_expect > 16 [L39] this_expect = -16 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L43] COND FALSE !(q == 0) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L63] COND FALSE !(q == 1) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L163] COND FALSE !(q == 2) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=2, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L263] COND TRUE q == 3 [L264] COND FALSE !(__VERIFIER_nondet_int()) [L280] COND TRUE __VERIFIER_nondet_int() [L282] COND TRUE !(P1 != (((0 + 1) - 1) % 2)) [L284] method_id = 3 VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L286] COND TRUE (((this_buffer_empty == 1) && !(P3 != (((0 + 1) - 1) % 2))) || (((P3 != ((this_expect - 1) % 2)) && (this_buffer_empty != 1)) && !(P3 != (((0 + 1) - 1) % 2)))) VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] [L569] __VERIFIER_error() VAL [m_msg_1_1=4, m_msg_1_2=5, m_msg_2=2, m_Protocol=1, m_recv_ack_1_1=6, m_recv_ack_1_2=7, m_recv_ack_2=3, method_id=3, P1=0, P2=-1, P3=0, P4=-1, P5=0, P6=0, P7=0, P8=-1, P9=-1, q=3, this_buffer_empty=0, this_expect=-16] - StatisticsResult: Ultimate Automizer benchmark data CFG has 3 procedures, 115 locations, 1 error locations. UNSAFE Result, 120.1s OverallTime, 46 OverallIterations, 35 TraceHistogramMax, 24.9s AutomataDifference, 0.0s DeadEndRemovalTime, 0.0s HoareAnnotationTime, HoareTripleCheckerStatistics: 9748 SDtfs, 16736 SDslu, 50186 SDs, 0 SdLazy, 9078 SolverSat, 1209 SolverUnsat, 0 SolverUnknown, 0 SolverNotchecked, 16.4s Time, PredicateUnifierStatistics: 0 DeclaredPredicates, 18472 GetRequests, 17486 SyntacticMatches, 242 SemanticMatches, 744 ConstructedPredicates, 0 IntricatePredicates, 1 DeprecatedPredicates, 6636 ImplicationChecksByTransitivity, 45.7s Time, 0.0s BasicInterpolantAutomatonTime, BiggestAbstraction: size=1168occurred in iteration=43, traceCheckStatistics: No data available, InterpolantConsolidationStatistics: No data available, PathInvariantsStatistics: No data available, 0/0 InterpolantCoveringCapability, TotalInterpolationStatistics: No data available, 0.0s AbstIntTime, 0 AbstIntIterations, 0 AbstIntStrong, NaN AbsIntWeakeningRatio, NaN AbsIntAvgWeakeningVarsNumRemoved, NaN AbsIntAvgWeakenedConjuncts, 0.0s DumpTime, AutomataMinimizationStatistics: 0.9s AutomataMinimizationTime, 45 MinimizatonAttempts, 872 StatesRemovedByMinimization, 43 NontrivialMinimizations, HoareAnnotationStatistics: No data available, RefinementEngineStatistics: TraceCheckStatistics: 1.8s SsaConstructionTime, 37.3s SatisfiabilityAnalysisTime, 50.7s InterpolantComputationTime, 14233 NumberOfCodeBlocks, 13461 NumberOfCodeBlocksAsserted, 289 NumberOfCheckSat, 22588 ConstructedInterpolants, 1048 QuantifiedInterpolants, 20213604 SizeOfPredicates, 212 NumberOfNonLiveVariables, 49534 ConjunctsInSsa, 1360 ConjunctsInUnsatCore, 187 InterpolantComputations, 13 PerfectInterpolantSequences, 27665/82546 InterpolantCoveringCapability, InvariantSynthesisStatistics: No data available, InterpolantConsolidationStatistics: No data available, ReuseStatistics: No data available RESULT: Ultimate proved your program to be incorrect! Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-Benchmark-0-2018-07-24_15-18-13-464.csv Written .csv to /storage/repos/ultimate/releaseScripts/default/UAutomizer-linux/csv/psyco_abp_1_false-unreach-call_false-termination_true-no-overflow.c_svcomp-Reach-64bit-RubberTaipan_Default-OldIcfg.epf_AutomizerCInline.xml/Csv-TraceAbstractionBenchmarks-0-2018-07-24_15-18-13-464.csv Received shutdown request...